1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; We compute exact length on each instruction for most of the time.
26 ;; In some case, most notably bit operations that may involve memory
27 ;; operands, the lengths in this file are "worst case".
29 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
30 ;; registers. Right now GCC doesn't expose the "e" half to the
31 ;; compiler, so using add/subs for addhi and subhi is safe. Long
32 ;; term, we want to expose the "e" half to the compiler (gives us 8
33 ;; more 16bit registers). At that point addhi and subhi can't use
36 ;; There's currently no way to have an insv/extzv expander for the H8/300H
37 ;; because word_mode is different for the H8/300 and H8/300H.
39 ;; Shifts/rotates by small constants should be handled by special
40 ;; patterns so we get the length and cc status correct.
42 ;; Bitfield operations no longer accept memory operands. We need
43 ;; to add variants which operate on memory back to the MD.
45 ;; ??? Implement remaining bit ops available on the h8300
47 ;; ----------------------------------------------------------------------
49 ;; ----------------------------------------------------------------------
65 ;; ----------------------------------------------------------------------
67 ;; ----------------------------------------------------------------------
69 (define_attr "cpu" "h8300,h8300h"
70 (const (symbol_ref "cpu_type")))
72 (define_attr "type" "branch,arith"
73 (const_string "arith"))
75 ;; The size of instructions in bytes.
77 (define_attr "length" ""
78 (cond [(eq_attr "type" "branch")
79 (if_then_else (and (ge (minus (match_dup 0) (pc))
81 (le (minus (match_dup 0) (pc))
84 (if_then_else (and (eq_attr "cpu" "h8300h")
85 (and (ge (minus (pc) (match_dup 0))
87 (le (minus (pc) (match_dup 0))
93 ;; Condition code settings.
95 ;; none - insn does not affect cc
96 ;; none_0hit - insn does not affect cc but it does modify operand 0
97 ;; This attribute is used to keep track of when operand 0 changes.
98 ;; See the description of NOTICE_UPDATE_CC for more info.
99 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
100 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
101 ;; compare - compare instruction
102 ;; clobber - value of cc is unknown
104 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
105 (const_string "clobber"))
107 ;; Provide the maximum length of an assembly instruction in an asm
108 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
110 (define_asm_attributes
111 [(set (attr "length")
112 (cond [(ne (symbol_ref "TARGET_H8300") (const_int 0)) (const_int 4)
113 (ne (symbol_ref "TARGET_H8300H") (const_int 0)) (const_int 10)
114 (ne (symbol_ref "TARGET_H8300S") (const_int 0)) (const_int 10)]
117 ;; ----------------------------------------------------------------------
119 ;; ----------------------------------------------------------------------
123 (define_insn "pushqi1_h8300"
124 [(parallel [(set (reg:HI SP_REG)
125 (plus:HI (reg:HI SP_REG) (const_int -2)))
126 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
127 (match_operand:QI 0 "register_operand" "r"))])]
129 && operands[0] != stack_pointer_rtx"
131 [(set_attr "length" "2")
132 (set_attr "cc" "clobber")])
134 (define_insn "pushqi1_h8300hs"
135 [(parallel [(set (reg:SI SP_REG)
136 (plus:SI (reg:SI SP_REG) (const_int -4)))
137 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
138 (match_operand:QI 0 "register_operand" "r"))])]
139 "(TARGET_H8300H || TARGET_H8300S)
140 && operands[0] != stack_pointer_rtx"
142 [(set_attr "length" "4")
143 (set_attr "cc" "clobber")])
145 (define_insn "pushqi1_h8300hs_normal"
146 [(parallel [(set (reg:HI SP_REG)
147 (plus:HI (reg:HI SP_REG) (const_int -4)))
148 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
149 (match_operand:QI 0 "register_operand" "r"))])]
150 "(TARGET_H8300H || TARGET_H8300S)
151 && operands[0] != stack_pointer_rtx"
153 [(set_attr "length" "4")
154 (set_attr "cc" "clobber")])
156 (define_expand "pushqi1"
157 [(match_operand:QI 0 "register_operand" "")]
162 emit_insn (gen_pushqi1_h8300 (operands[0]));
163 else if (!TARGET_NORMAL_MODE)
164 emit_insn (gen_pushqi1_h8300hs (operands[0]));
166 emit_insn (gen_pushqi1_h8300hs_normal (operands[0]));
170 (define_insn "*movqi_h8300"
171 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
172 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
174 && (register_operand (operands[0], QImode)
175 || register_operand (operands[1], QImode))"
183 [(set_attr "length" "2,2,2,2,4,4")
184 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
186 (define_insn "*movqi_h8300hs"
187 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
188 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
189 "(TARGET_H8300H || TARGET_H8300S)
190 && (register_operand (operands[0], QImode)
191 || register_operand (operands[1], QImode))"
199 [(set (attr "length")
200 (symbol_ref "compute_mov_length (operands)"))
201 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
203 (define_expand "movqi"
204 [(set (match_operand:QI 0 "general_operand_dst" "")
205 (match_operand:QI 1 "general_operand_src" ""))]
209 /* One of the ops has to be in a register. */
210 if (!register_operand (operand0, QImode)
211 && !register_operand (operand1, QImode))
213 operands[1] = copy_to_mode_reg (QImode, operand1);
217 (define_insn "movstrictqi"
218 [(set (strict_low_part
219 (match_operand:QI 0 "register_operand" "+r,r,r,r,r"))
220 (match_operand:QI 1 "general_operand_src" " I,r,n,>,m"))]
228 [(set (attr "length")
229 (symbol_ref "compute_mov_length (operands)"))
230 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
234 (define_expand "pushhi1_h8300"
235 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
236 (match_operand:HI 0 "register_operand" ""))]
238 && operands[0] != stack_pointer_rtx"
241 (define_insn "pushhi1_h8300hs"
242 [(parallel [(set (reg:SI SP_REG)
243 (plus:SI (reg:SI SP_REG) (const_int -4)))
244 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
245 (match_operand:HI 0 "register_operand" "r"))])]
246 "(TARGET_H8300H || TARGET_H8300S)
247 && operands[0] != stack_pointer_rtx"
249 [(set_attr "length" "4")
250 (set_attr "cc" "clobber")])
252 (define_insn "pushhi1_h8300hs_normal"
253 [(parallel [(set (reg:HI SP_REG)
254 (plus:HI (reg:HI SP_REG) (const_int -4)))
255 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
256 (match_operand:HI 0 "register_operand" "r"))])]
257 "(TARGET_H8300H || TARGET_H8300S)
258 && operands[0] != stack_pointer_rtx"
260 [(set_attr "length" "4")
261 (set_attr "cc" "clobber")])
263 (define_expand "pushhi1"
264 [(match_operand:HI 0 "register_operand" "")]
269 emit_insn (gen_pushhi1_h8300 (operands[0]));
270 else if (!TARGET_NORMAL_MODE)
271 emit_insn (gen_pushhi1_h8300hs (operands[0]));
273 emit_insn (gen_pushhi1_h8300hs_normal (operands[0]));
277 (define_insn "*movhi_h8300"
278 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
279 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
281 && (register_operand (operands[0], HImode)
282 || register_operand (operands[1], HImode))
283 && !(GET_CODE (operands[0]) == MEM
284 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
285 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
286 && GET_CODE (operands[1]) == REG
287 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
295 [(set (attr "length")
296 (symbol_ref "compute_mov_length (operands)"))
297 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
299 (define_insn "*movhi_h8300hs"
300 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
301 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
302 "(TARGET_H8300H || TARGET_H8300S)
303 && (register_operand (operands[0], HImode)
304 || register_operand (operands[1], HImode))"
312 [(set (attr "length")
313 (symbol_ref "compute_mov_length (operands)"))
314 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
316 (define_expand "movhi"
317 [(set (match_operand:HI 0 "general_operand_dst" "")
318 (match_operand:HI 1 "general_operand_src" ""))]
322 /* One of the ops has to be in a register. */
323 if (!register_operand (operand1, HImode)
324 && !register_operand (operand0, HImode))
326 operands[1] = copy_to_mode_reg (HImode, operand1);
330 (define_insn "movstricthi"
331 [(set (strict_low_part
332 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
333 (match_operand:HI 1 "general_operand_src" " I,r,i,>,m"))]
341 [(set (attr "length")
342 (symbol_ref "compute_mov_length (operands)"))
343 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
347 (define_expand "movsi"
348 [(set (match_operand:SI 0 "general_operand_dst" "")
349 (match_operand:SI 1 "general_operand_src" ""))]
355 if (h8300_expand_movsi (operands))
360 /* One of the ops has to be in a register. */
361 if (!register_operand (operand1, SImode)
362 && !register_operand (operand0, SImode))
364 operands[1] = copy_to_mode_reg (SImode, operand1);
369 (define_expand "movsf"
370 [(set (match_operand:SF 0 "general_operand_dst" "")
371 (match_operand:SF 1 "general_operand_src" ""))]
377 if (h8300_expand_movsi (operands))
382 /* One of the ops has to be in a register. */
383 if (!register_operand (operand1, SFmode)
384 && !register_operand (operand0, SFmode))
386 operands[1] = copy_to_mode_reg (SFmode, operand1);
391 (define_insn "*movsi_h8300"
392 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
393 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
395 && (register_operand (operands[0], SImode)
396 || register_operand (operands[1], SImode))"
399 unsigned int rn = -1;
400 switch (which_alternative)
403 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
405 if (REGNO (operands[0]) < REGNO (operands[1]))
406 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
408 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
410 /* Make sure we don't trample the register we index with. */
411 if (GET_CODE (operands[1]) == MEM)
413 rtx inside = XEXP (operands[1], 0);
418 else if (GET_CODE (inside) == PLUS)
420 rtx lhs = XEXP (inside, 0);
421 rtx rhs = XEXP (inside, 1);
422 if (REG_P (lhs)) rn = REGNO (lhs);
423 if (REG_P (rhs)) rn = REGNO (rhs);
426 if (rn == REGNO (operands[0]))
428 /* Move the second word first. */
429 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
433 if (GET_CODE (operands[1]) == CONST_INT)
435 /* If either half is zero, use sub.w to clear that
437 if ((INTVAL (operands[1]) & 0xffff) == 0)
438 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
439 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
440 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
441 /* If the upper half and the lower half are the same,
442 copy one half to the other. */
443 if ((INTVAL (operands[1]) & 0xffff)
444 == ((INTVAL (operands[1]) >> 16) & 0xffff))
445 return \"mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0\";
447 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
450 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
452 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
454 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
459 [(set (attr "length")
460 (symbol_ref "compute_mov_length (operands)"))
461 (set_attr "cc" "clobber")])
463 (define_insn "*movsf_h8300"
464 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
465 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
467 && (register_operand (operands[0], SFmode)
468 || register_operand (operands[1], SFmode))"
471 /* Copy of the movsi stuff. */
472 unsigned int rn = -1;
473 switch (which_alternative)
476 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
478 if (REGNO (operands[0]) < REGNO (operands[1]))
479 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
481 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
483 /* Make sure we don't trample the register we index with. */
484 if (GET_CODE (operands[1]) == MEM)
486 rtx inside = XEXP (operands[1], 0);
491 else if (GET_CODE (inside) == PLUS)
493 rtx lhs = XEXP (inside, 0);
494 rtx rhs = XEXP (inside, 1);
495 if (REG_P (lhs)) rn = REGNO (lhs);
496 if (REG_P (rhs)) rn = REGNO (rhs);
499 if (rn == REGNO (operands[0]))
500 /* Move the second word first. */
501 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
503 /* Move the first word first. */
504 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
507 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
509 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
511 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
516 [(set (attr "length")
517 (symbol_ref "compute_mov_length (operands)"))
518 (set_attr "cc" "clobber")])
520 (define_insn "*movsi_h8300hs"
521 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
522 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
523 "(TARGET_H8300S || TARGET_H8300H)
524 && (register_operand (operands[0], SImode)
525 || register_operand (operands[1], SImode))
526 && !(GET_CODE (operands[0]) == MEM
527 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
528 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
529 && GET_CODE (operands[1]) == REG
530 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
533 switch (which_alternative)
536 return \"sub.l %S0,%S0\";
540 return \"clrmac\;ldmac %1,macl\";
542 return \"stmac macl,%0\";
544 if (GET_CODE (operands[1]) == CONST_INT)
546 int val = INTVAL (operands[1]);
548 /* Look for constants which can be made by adding an 8-bit
549 number to zero in one of the two low bytes. */
550 if (val == (val & 0xff))
552 operands[1] = GEN_INT ((char) val & 0xff);
553 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
556 if (val == (val & 0xff00))
558 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
559 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
562 /* Look for constants that can be obtained by subs, inc, and
564 switch (val & 0xffffffff)
567 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
569 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
571 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
574 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
576 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
579 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
581 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
584 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
586 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
590 return \"mov.l %S1,%S0\";
592 [(set (attr "length")
593 (symbol_ref "compute_mov_length (operands)"))
594 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
596 (define_insn "*movsf_h8300hs"
597 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
598 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
599 "(TARGET_H8300H || TARGET_H8300S)
600 && (register_operand (operands[0], SFmode)
601 || register_operand (operands[1], SFmode))"
609 [(set (attr "length")
610 (symbol_ref "compute_mov_length (operands)"))
611 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
613 ;; ----------------------------------------------------------------------
615 ;; ----------------------------------------------------------------------
618 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
620 (match_operand 1 "const_int_operand" "n,n")))]
623 [(set_attr "length" "2,4")
624 (set_attr "cc" "set_zn,set_zn")])
627 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
629 (match_operand 1 "const_int_operand" "n")))]
632 [(set_attr "length" "2")
633 (set_attr "cc" "set_zn")])
635 (define_insn_and_split "*tst_extzv_1_n"
637 (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
639 (match_operand 1 "const_int_operand" "n,n,n")))
640 (clobber (match_scratch:QI 2 "=X,X,&r"))]
641 "(TARGET_H8300H || TARGET_H8300S)"
647 && !EXTRA_CONSTRAINT (operands[0], 'U')"
650 (parallel [(set (cc0) (zero_extract:SI (match_dup 2)
653 (clobber (scratch:QI))])]
655 [(set_attr "length" "2,8,10")
656 (set_attr "cc" "set_zn,set_zn,set_zn")])
659 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
661 (match_operand 1 "const_int_operand" "n")))]
662 "(TARGET_H8300H || TARGET_H8300S)
663 && INTVAL (operands[1]) <= 15"
665 [(set_attr "length" "2")
666 (set_attr "cc" "set_zn")])
668 (define_insn_and_split "*tstsi_upper_bit"
670 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
672 (match_operand 1 "const_int_operand" "n")))
673 (clobber (match_scratch:SI 2 "=&r"))]
674 "(TARGET_H8300H || TARGET_H8300S)
675 && INTVAL (operands[1]) >= 16"
677 "&& reload_completed"
679 (ior:SI (and:SI (match_dup 2)
681 (lshiftrt:SI (match_dup 0)
684 (zero_extract:SI (match_dup 2)
687 "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
689 (define_insn "*tstsi_variable_bit"
691 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
693 (and:SI (match_operand:SI 1 "register_operand" "r")
695 "TARGET_H8300H || TARGET_H8300S"
697 [(set_attr "length" "2")
698 (set_attr "cc" "set_zn")])
700 (define_insn_and_split "*tstsi_variable_bit_qi"
702 (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
704 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
706 (clobber (match_scratch:QI 2 "=X,X,&r"))]
707 "(TARGET_H8300H || TARGET_H8300S)"
713 && !EXTRA_CONSTRAINT (operands[0], 'U')"
716 (parallel [(set (cc0) (zero_extract:SI (zero_extend:SI (match_dup 2))
718 (and:SI (match_dup 1)
720 (clobber (scratch:QI))])]
722 [(set_attr "length" "2,8,10")
723 (set_attr "cc" "set_zn,set_zn,set_zn")])
726 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
729 [(set_attr "length" "2")
730 (set_attr "cc" "set_znv")])
733 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
736 [(set_attr "length" "2")
737 (set_attr "cc" "set_znv")])
739 (define_insn "*tsthi_upper"
741 (and:HI (match_operand:HI 0 "register_operand" "r")
745 [(set_attr "length" "2")
746 (set_attr "cc" "set_znv")])
749 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
750 "TARGET_H8300H || TARGET_H8300S"
752 [(set_attr "length" "2")
753 (set_attr "cc" "set_znv")])
755 (define_insn "*tstsi_upper"
757 (and:SI (match_operand:SI 0 "register_operand" "r")
758 (const_int -65536)))]
761 [(set_attr "length" "2")
762 (set_attr "cc" "set_znv")])
766 (compare (match_operand:QI 0 "register_operand" "r")
767 (match_operand:QI 1 "nonmemory_operand" "rn")))]
770 [(set_attr "length" "2")
771 (set_attr "cc" "compare")])
773 (define_expand "cmphi"
775 (compare (match_operand:HI 0 "register_operand" "")
776 (match_operand:HI 1 "nonmemory_operand" "")))]
780 /* Force operand1 into a register if we're compiling
782 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
783 operands[1] = force_reg (HImode, operands[1]);
786 (define_insn "*cmphi_h8300"
788 (compare (match_operand:HI 0 "register_operand" "r")
789 (match_operand:HI 1 "register_operand" "r")))]
792 [(set_attr "length" "2")
793 (set_attr "cc" "compare")])
795 (define_insn "*cmphi_h8300hs"
797 (compare (match_operand:HI 0 "register_operand" "r,r")
798 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
799 "TARGET_H8300H || TARGET_H8300S"
801 [(set_attr "length" "2,4")
802 (set_attr "cc" "compare,compare")])
806 (compare (match_operand:SI 0 "register_operand" "r,r")
807 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
808 "TARGET_H8300H || TARGET_H8300S"
810 [(set_attr "length" "2,6")
811 (set_attr "cc" "compare,compare")])
813 ;; ----------------------------------------------------------------------
815 ;; ----------------------------------------------------------------------
817 (define_insn "addqi3"
818 [(set (match_operand:QI 0 "register_operand" "=r")
819 (plus:QI (match_operand:QI 1 "register_operand" "%0")
820 (match_operand:QI 2 "nonmemory_operand" "rn")))]
823 [(set_attr "length" "2")
824 (set_attr "cc" "set_zn")])
826 (define_expand "addhi3"
827 [(set (match_operand:HI 0 "register_operand" "")
828 (plus:HI (match_operand:HI 1 "register_operand" "")
829 (match_operand:HI 2 "nonmemory_operand" "")))]
833 (define_insn "*addhi3_h8300"
834 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
835 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
836 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
842 add.b %s2,%s0\;addx %t2,%t0
844 [(set_attr "length" "2,2,2,4,2")
845 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
847 ;; This splitter is very important to make the stack adjustment
848 ;; interrupt-safe. The combination of add.b and addx is unsafe!
850 ;; We apply this split after the peephole2 pass so that we won't end
851 ;; up creating too many adds/subs when a scratch register is
852 ;; available, which is actually a common case because stack unrolling
853 ;; tends to happen immediately after a function call.
856 [(set (match_operand:HI 0 "stack_pointer_operand" "")
857 (plus:HI (match_dup 0)
858 (match_operand 1 "const_int_gt_2_operand" "")))]
859 "TARGET_H8300 && flow2_completed"
861 "split_adds_subs (HImode, operands); DONE;")
864 [(match_scratch:HI 2 "r")
865 (set (match_operand:HI 0 "stack_pointer_operand" "")
866 (plus:HI (match_dup 0)
867 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
872 (plus:HI (match_dup 0)
876 (define_insn "*addhi3_h8300hs"
877 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
878 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
879 (match_operand:HI 2 "nonmemory_operand" "L,N,J,n,r")))]
880 "TARGET_H8300H || TARGET_H8300S"
887 [(set_attr "length" "2,2,2,4,2")
888 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
890 (define_insn "*addhi3_incdec"
891 [(set (match_operand:HI 0 "register_operand" "=r,r")
892 (unspec:HI [(match_operand:HI 1 "register_operand" "0,0")
893 (match_operand:HI 2 "incdec_operand" "M,O")]
895 "TARGET_H8300H || TARGET_H8300S"
899 [(set_attr "length" "2,2")
900 (set_attr "cc" "set_zn,set_zn")])
903 [(set (match_operand:HI 0 "register_operand" "")
904 (plus:HI (match_dup 0)
905 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
908 "split_adds_subs (HImode, operands); DONE;")
910 (define_expand "addsi3"
911 [(set (match_operand:SI 0 "register_operand" "")
912 (plus:SI (match_operand:SI 1 "register_operand" "")
913 (match_operand:SI 2 "nonmemory_operand" "")))]
917 (define_insn "*addsi_h8300"
918 [(set (match_operand:SI 0 "register_operand" "=r,r")
919 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
920 (match_operand:SI 2 "nonmemory_operand" "n,r")))]
922 "* return output_plussi (operands);"
923 [(set (attr "length")
924 (symbol_ref "compute_plussi_length (operands)"))
926 (symbol_ref "compute_plussi_cc (operands)"))])
928 (define_insn "*addsi_h8300hs"
929 [(set (match_operand:SI 0 "register_operand" "=r,r")
930 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
931 (match_operand:SI 2 "nonmemory_operand" "i,r")))]
932 "TARGET_H8300H || TARGET_H8300S"
933 "* return output_plussi (operands);"
934 [(set (attr "length")
935 (symbol_ref "compute_plussi_length (operands)"))
937 (symbol_ref "compute_plussi_cc (operands)"))])
939 (define_insn "*addsi3_incdec"
940 [(set (match_operand:SI 0 "register_operand" "=r,r")
941 (unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
942 (match_operand:SI 2 "incdec_operand" "M,O")]
944 "TARGET_H8300H || TARGET_H8300S"
948 [(set_attr "length" "2,2")
949 (set_attr "cc" "set_zn,set_zn")])
952 [(set (match_operand:SI 0 "register_operand" "")
953 (plus:SI (match_dup 0)
954 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
955 "TARGET_H8300H || TARGET_H8300S"
957 "split_adds_subs (SImode, operands); DONE;")
959 ;; ----------------------------------------------------------------------
960 ;; SUBTRACT INSTRUCTIONS
961 ;; ----------------------------------------------------------------------
963 (define_insn "subqi3"
964 [(set (match_operand:QI 0 "register_operand" "=r")
965 (minus:QI (match_operand:QI 1 "register_operand" "0")
966 (match_operand:QI 2 "register_operand" "r")))]
969 [(set_attr "length" "2")
970 (set_attr "cc" "set_zn")])
972 (define_expand "subhi3"
973 [(set (match_operand:HI 0 "register_operand" "")
974 (minus:HI (match_operand:HI 1 "general_operand" "")
975 (match_operand:HI 2 "nonmemory_operand" "")))]
979 (define_insn "*subhi3_h8300"
980 [(set (match_operand:HI 0 "register_operand" "=r,r")
981 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
982 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
986 add.b %E2,%s0\;addx %F2,%t0"
987 [(set_attr "length" "2,4")
988 (set_attr "cc" "set_zn,clobber")])
990 (define_insn "*subhi3_h8300hs"
991 [(set (match_operand:HI 0 "register_operand" "=r,r")
992 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
993 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
994 "TARGET_H8300H || TARGET_H8300S"
998 [(set_attr "length" "2,4")
999 (set_attr "cc" "set_zn,set_zn")])
1001 (define_expand "subsi3"
1002 [(set (match_operand:SI 0 "register_operand" "")
1003 (minus:SI (match_operand:SI 1 "register_operand" "")
1004 (match_operand:SI 2 "nonmemory_operand" "")))]
1008 (define_insn "*subsi3_h8300"
1009 [(set (match_operand:SI 0 "register_operand" "=r")
1010 (minus:SI (match_operand:SI 1 "register_operand" "0")
1011 (match_operand:SI 2 "register_operand" "r")))]
1013 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1014 [(set_attr "length" "6")
1015 (set_attr "cc" "clobber")])
1017 (define_insn "*subsi3_h8300hs"
1018 [(set (match_operand:SI 0 "register_operand" "=r,r")
1019 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
1020 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
1021 "TARGET_H8300H || TARGET_H8300S"
1025 [(set_attr "length" "2,6")
1026 (set_attr "cc" "set_zn,set_zn")])
1028 ;; ----------------------------------------------------------------------
1029 ;; MULTIPLY INSTRUCTIONS
1030 ;; ----------------------------------------------------------------------
1032 ;; Note that the H8/300 can only handle umulqihi3.
1034 (define_insn "mulqihi3"
1035 [(set (match_operand:HI 0 "register_operand" "=r")
1036 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1037 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1038 "TARGET_H8300H || TARGET_H8300S"
1040 [(set_attr "length" "4")
1041 (set_attr "cc" "set_zn")])
1043 (define_insn "mulhisi3"
1044 [(set (match_operand:SI 0 "register_operand" "=r")
1045 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1046 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1047 "TARGET_H8300H || TARGET_H8300S"
1049 [(set_attr "length" "4")
1050 (set_attr "cc" "set_zn")])
1052 (define_insn "umulqihi3"
1053 [(set (match_operand:HI 0 "register_operand" "=r")
1054 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1055 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1058 [(set_attr "length" "2")
1059 (set_attr "cc" "none_0hit")])
1061 (define_insn "umulhisi3"
1062 [(set (match_operand:SI 0 "register_operand" "=r")
1063 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1064 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1065 "TARGET_H8300H || TARGET_H8300S"
1067 [(set_attr "length" "2")
1068 (set_attr "cc" "none_0hit")])
1070 ;; This is a "bridge" instruction. Combine can't cram enough insns
1071 ;; together to crate a MAC instruction directly, but it can create
1072 ;; this instruction, which then allows combine to create the real
1075 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1076 ;; insn must generate reasonably correct code. Egad.
1078 [(set (match_operand:SI 0 "register_operand" "=a")
1081 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1083 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1085 "clrmac\;mac @%2+,@%1+"
1086 [(set_attr "length" "6")
1087 (set_attr "cc" "none_0hit")])
1090 [(set (match_operand:SI 0 "register_operand" "=a")
1092 (sign_extend:SI (mem:HI
1093 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1094 (sign_extend:SI (mem:HI
1095 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1096 (match_operand:SI 3 "register_operand" "0")))]
1099 [(set_attr "length" "4")
1100 (set_attr "cc" "none_0hit")])
1102 ;; ----------------------------------------------------------------------
1103 ;; DIVIDE/MOD INSTRUCTIONS
1104 ;; ----------------------------------------------------------------------
1106 (define_insn "udivmodqi4"
1107 [(set (match_operand:QI 0 "register_operand" "=r")
1110 (match_operand:HI 1 "register_operand" "0")
1111 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1112 (set (match_operand:QI 3 "register_operand" "=r")
1116 (zero_extend:HI (match_dup 2)))))]
1120 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1121 return \"divxu.b\\t%X2,%T0\";
1123 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1125 [(set_attr "length" "4")
1126 (set_attr "cc" "clobber")])
1128 (define_insn "divmodqi4"
1129 [(set (match_operand:QI 0 "register_operand" "=r")
1132 (match_operand:HI 1 "register_operand" "0")
1133 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1134 (set (match_operand:QI 3 "register_operand" "=r")
1138 (sign_extend:HI (match_dup 2)))))]
1139 "TARGET_H8300H || TARGET_H8300S"
1142 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1143 return \"divxs.b\\t%X2,%T0\";
1145 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
1147 [(set_attr "length" "6")
1148 (set_attr "cc" "clobber")])
1150 (define_insn "udivmodhi4"
1151 [(set (match_operand:HI 0 "register_operand" "=r")
1154 (match_operand:SI 1 "register_operand" "0")
1155 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1156 (set (match_operand:HI 3 "register_operand" "=r")
1160 (zero_extend:SI (match_dup 2)))))]
1161 "TARGET_H8300H || TARGET_H8300S"
1164 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1165 return \"divxu.w\\t%T2,%S0\";
1167 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1169 [(set_attr "length" "4")
1170 (set_attr "cc" "clobber")])
1172 (define_insn "divmodhi4"
1173 [(set (match_operand:HI 0 "register_operand" "=r")
1176 (match_operand:SI 1 "register_operand" "0")
1177 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1178 (set (match_operand:HI 3 "register_operand" "=r")
1182 (sign_extend:SI (match_dup 2)))))]
1183 "TARGET_H8300H || TARGET_H8300S"
1186 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1187 return \"divxs.w\\t%T2,%S0\";
1189 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
1191 [(set_attr "length" "6")
1192 (set_attr "cc" "clobber")])
1194 ;; ----------------------------------------------------------------------
1196 ;; ----------------------------------------------------------------------
1198 (define_insn "*andqi3_1"
1199 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1200 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1201 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1202 "register_operand (operands[0], QImode)
1203 || single_zero_operand (operands[2], QImode)"
1207 [(set_attr "length" "2,8")
1208 (set_attr "cc" "set_znv,none_0hit")])
1210 (define_expand "andqi3"
1211 [(set (match_operand:QI 0 "bit_operand" "")
1212 (and:QI (match_operand:QI 1 "bit_operand" "")
1213 (match_operand:QI 2 "nonmemory_operand" "")))]
1217 if (fix_bit_operand (operands, 0, AND))
1221 (define_expand "andhi3"
1222 [(set (match_operand:HI 0 "register_operand" "")
1223 (and:HI (match_operand:HI 1 "register_operand" "")
1224 (match_operand:HI 2 "nonmemory_operand" "")))]
1228 (define_insn "*andorqi3"
1229 [(set (match_operand:QI 0 "register_operand" "=r")
1230 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1231 (match_operand:QI 3 "single_one_operand" "n"))
1232 (match_operand:QI 1 "register_operand" "0")))]
1234 "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
1235 [(set_attr "length" "6")
1236 (set_attr "cc" "clobber")])
1238 (define_insn "*andorhi3"
1239 [(set (match_operand:HI 0 "register_operand" "=r")
1240 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1241 (match_operand:HI 3 "single_one_operand" "n"))
1242 (match_operand:HI 1 "register_operand" "0")))]
1246 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1247 if (INTVAL (operands[3]) > 128)
1249 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1250 return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
1252 return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
1254 [(set_attr "length" "6")
1255 (set_attr "cc" "clobber")])
1257 (define_insn "*andorsi3"
1258 [(set (match_operand:SI 0 "register_operand" "=r")
1259 (ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
1260 (match_operand:SI 3 "single_one_operand" "n"))
1261 (match_operand:SI 1 "register_operand" "0")))]
1262 "(INTVAL (operands[3]) & 0xffff) != 0"
1265 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1266 if (INTVAL (operands[3]) > 128)
1268 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1269 return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
1271 return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
1273 [(set_attr "length" "6")
1274 (set_attr "cc" "clobber")])
1276 (define_insn "*andorsi3_shift_8"
1277 [(set (match_operand:SI 0 "register_operand" "=r")
1278 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1281 (match_operand:SI 1 "register_operand" "0")))]
1284 [(set_attr "length" "2")
1285 (set_attr "cc" "clobber")])
1287 (define_expand "andsi3"
1288 [(set (match_operand:SI 0 "register_operand" "")
1289 (and:SI (match_operand:SI 1 "register_operand" "")
1290 (match_operand:SI 2 "nonmemory_operand" "")))]
1294 ;; ----------------------------------------------------------------------
1296 ;; ----------------------------------------------------------------------
1298 (define_insn "*iorqi3_1"
1299 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1300 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1301 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1302 "register_operand (operands[0], QImode)
1303 || single_one_operand (operands[2], QImode)"
1307 [(set_attr "length" "2,8")
1308 (set_attr "cc" "set_znv,none_0hit")])
1310 (define_expand "iorqi3"
1311 [(set (match_operand:QI 0 "bit_operand" "")
1312 (ior:QI (match_operand:QI 1 "bit_operand" "")
1313 (match_operand:QI 2 "nonmemory_operand" "")))]
1317 if (fix_bit_operand (operands, 1, IOR))
1321 (define_expand "iorhi3"
1322 [(set (match_operand:HI 0 "register_operand" "")
1323 (ior:HI (match_operand:HI 1 "register_operand" "")
1324 (match_operand:HI 2 "nonmemory_operand" "")))]
1328 (define_expand "iorsi3"
1329 [(set (match_operand:SI 0 "register_operand" "")
1330 (ior:SI (match_operand:SI 1 "register_operand" "")
1331 (match_operand:SI 2 "nonmemory_operand" "")))]
1335 ;; ----------------------------------------------------------------------
1337 ;; ----------------------------------------------------------------------
1339 (define_insn "*xorqi3_1"
1340 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1341 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1342 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1343 "register_operand (operands[0], QImode)
1344 || single_one_operand (operands[2], QImode)"
1348 [(set_attr "length" "2,8")
1349 (set_attr "cc" "set_znv,none_0hit")])
1351 (define_expand "xorqi3"
1352 [(set (match_operand:QI 0 "bit_operand" "")
1353 (xor:QI (match_operand:QI 1 "bit_operand" "")
1354 (match_operand:QI 2 "nonmemory_operand" "")))]
1358 if (fix_bit_operand (operands, 1, XOR))
1362 (define_expand "xorhi3"
1363 [(set (match_operand:HI 0 "register_operand" "")
1364 (xor:HI (match_operand:HI 1 "register_operand" "")
1365 (match_operand:HI 2 "nonmemory_operand" "")))]
1369 (define_expand "xorsi3"
1370 [(set (match_operand:SI 0 "register_operand" "")
1371 (xor:SI (match_operand:SI 1 "register_operand" "")
1372 (match_operand:SI 2 "nonmemory_operand" "")))]
1376 ;; ----------------------------------------------------------------------
1377 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1378 ;; ----------------------------------------------------------------------
1380 (define_insn "*logicalhi3"
1381 [(set (match_operand:HI 0 "register_operand" "=r")
1382 (match_operator:HI 3 "bit_operator"
1383 [(match_operand:HI 1 "register_operand" "%0")
1384 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1386 "* return output_logical_op (HImode, operands);"
1387 [(set (attr "length")
1388 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1390 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1392 (define_insn "*logicalsi3"
1393 [(set (match_operand:SI 0 "register_operand" "=r")
1394 (match_operator:SI 3 "bit_operator"
1395 [(match_operand:SI 1 "register_operand" "%0")
1396 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1398 "* return output_logical_op (SImode, operands);"
1399 [(set (attr "length")
1400 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1402 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1404 ;; ----------------------------------------------------------------------
1405 ;; NEGATION INSTRUCTIONS
1406 ;; ----------------------------------------------------------------------
1408 (define_insn "negqi2"
1409 [(set (match_operand:QI 0 "register_operand" "=r")
1410 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1413 [(set_attr "length" "2")
1414 (set_attr "cc" "set_zn")])
1416 (define_expand "neghi2"
1417 [(set (match_operand:HI 0 "register_operand" "")
1418 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1424 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1429 (define_expand "neghi2_h8300"
1431 (not:HI (match_operand:HI 1 "register_operand" "")))
1432 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1433 (set (match_operand:HI 0 "register_operand" "")
1436 "operands[2] = gen_reg_rtx (HImode);")
1438 (define_insn "*neghi2_h8300hs"
1439 [(set (match_operand:HI 0 "register_operand" "=r")
1440 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1441 "TARGET_H8300H || TARGET_H8300S"
1443 [(set_attr "length" "2")
1444 (set_attr "cc" "set_zn")])
1446 (define_expand "negsi2"
1447 [(set (match_operand:SI 0 "register_operand" "")
1448 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1454 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1459 (define_expand "negsi2_h8300"
1461 (not:SI (match_operand:SI 1 "register_operand" "")))
1462 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1463 (set (match_operand:SI 0 "register_operand" "")
1466 "operands[2] = gen_reg_rtx (SImode);")
1468 (define_insn "*negsi2_h8300hs"
1469 [(set (match_operand:SI 0 "register_operand" "=r")
1470 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1471 "TARGET_H8300H || TARGET_H8300S"
1473 [(set_attr "length" "2")
1474 (set_attr "cc" "set_zn")])
1476 (define_expand "negsf2"
1477 [(set (match_operand:SF 0 "register_operand" "")
1478 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1482 (define_insn "*negsf2_h8300"
1483 [(set (match_operand:SF 0 "register_operand" "=r")
1484 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1487 [(set_attr "cc" "clobber")
1488 (set_attr "length" "2")])
1490 (define_insn "*negsf2_h8300hs"
1491 [(set (match_operand:SF 0 "register_operand" "=r")
1492 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1493 "TARGET_H8300H || TARGET_H8300S"
1494 "xor.w\\t#32768,%e0"
1495 [(set_attr "cc" "clobber")
1496 (set_attr "length" "4")])
1498 ;; ----------------------------------------------------------------------
1499 ;; ABSOLUTE VALUE INSTRUCTIONS
1500 ;; ----------------------------------------------------------------------
1502 (define_expand "abssf2"
1503 [(set (match_operand:SF 0 "register_operand" "")
1504 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1508 (define_insn "*abssf2_h8300"
1509 [(set (match_operand:SF 0 "register_operand" "=r")
1510 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1513 [(set_attr "cc" "clobber")
1514 (set_attr "length" "2")])
1516 (define_insn "*abssf2_h8300hs"
1517 [(set (match_operand:SF 0 "register_operand" "=r")
1518 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1519 "TARGET_H8300H || TARGET_H8300S"
1520 "and.w\\t#32767,%e0"
1521 [(set_attr "cc" "clobber")
1522 (set_attr "length" "4")])
1524 ;; ----------------------------------------------------------------------
1526 ;; ----------------------------------------------------------------------
1528 (define_insn "one_cmplqi2"
1529 [(set (match_operand:QI 0 "register_operand" "=r")
1530 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1533 [(set_attr "length" "2")
1534 (set_attr "cc" "set_znv")])
1536 (define_expand "one_cmplhi2"
1537 [(set (match_operand:HI 0 "register_operand" "=r")
1538 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1542 (define_insn "*one_cmplhi2_h8300"
1543 [(set (match_operand:HI 0 "register_operand" "=r")
1544 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1547 [(set_attr "cc" "clobber")
1548 (set_attr "length" "4")])
1550 (define_insn "*one_cmplhi2_h8300hs"
1551 [(set (match_operand:HI 0 "register_operand" "=r")
1552 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1553 "TARGET_H8300H || TARGET_H8300S"
1555 [(set_attr "cc" "set_znv")
1556 (set_attr "length" "2")])
1558 (define_expand "one_cmplsi2"
1559 [(set (match_operand:SI 0 "register_operand" "=r")
1560 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1564 (define_insn "*one_complsi2_h8300"
1565 [(set (match_operand:SI 0 "register_operand" "=r")
1566 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1568 "not %w0\;not %x0\;not %y0\;not %z0"
1569 [(set_attr "cc" "clobber")
1570 (set_attr "length" "8")])
1572 (define_insn "*one_complsi2_h8300hs"
1573 [(set (match_operand:SI 0 "register_operand" "=r")
1574 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1575 "TARGET_H8300H || TARGET_H8300S"
1577 [(set_attr "cc" "set_znv")
1578 (set_attr "length" "2")])
1580 ;; ----------------------------------------------------------------------
1581 ;; JUMP INSTRUCTIONS
1582 ;; ----------------------------------------------------------------------
1584 ;; Conditional jump instructions
1586 (define_expand "ble"
1588 (if_then_else (le (cc0)
1590 (label_ref (match_operand 0 "" ""))
1595 (define_expand "bleu"
1597 (if_then_else (leu (cc0)
1599 (label_ref (match_operand 0 "" ""))
1604 (define_expand "bge"
1606 (if_then_else (ge (cc0)
1608 (label_ref (match_operand 0 "" ""))
1613 (define_expand "bgeu"
1615 (if_then_else (geu (cc0)
1617 (label_ref (match_operand 0 "" ""))
1622 (define_expand "blt"
1624 (if_then_else (lt (cc0)
1626 (label_ref (match_operand 0 "" ""))
1631 (define_expand "bltu"
1633 (if_then_else (ltu (cc0)
1635 (label_ref (match_operand 0 "" ""))
1640 (define_expand "bgt"
1642 (if_then_else (gt (cc0)
1644 (label_ref (match_operand 0 "" ""))
1649 (define_expand "bgtu"
1651 (if_then_else (gtu (cc0)
1653 (label_ref (match_operand 0 "" ""))
1658 (define_expand "beq"
1660 (if_then_else (eq (cc0)
1662 (label_ref (match_operand 0 "" ""))
1667 (define_expand "bne"
1669 (if_then_else (ne (cc0)
1671 (label_ref (match_operand 0 "" ""))
1676 (define_insn "branch_true"
1678 (if_then_else (match_operator 1 "comparison_operator"
1679 [(cc0) (const_int 0)])
1680 (label_ref (match_operand 0 "" ""))
1685 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1686 && (GET_CODE (operands[1]) == GT
1687 || GET_CODE (operands[1]) == GE
1688 || GET_CODE (operands[1]) == LE
1689 || GET_CODE (operands[1]) == LT))
1691 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1695 if (get_attr_length (insn) == 2)
1696 return \"b%j1 %l0\";
1697 else if (get_attr_length (insn) == 4)
1698 return \"b%j1 %l0:16\";
1700 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1702 [(set_attr "type" "branch")
1703 (set_attr "cc" "none")])
1705 (define_insn "branch_false"
1707 (if_then_else (match_operator 1 "comparison_operator"
1708 [(cc0) (const_int 0)])
1710 (label_ref (match_operand 0 "" ""))))]
1714 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1715 && (GET_CODE (operands[1]) == GT
1716 || GET_CODE (operands[1]) == GE
1717 || GET_CODE (operands[1]) == LE
1718 || GET_CODE (operands[1]) == LT))
1720 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1724 if (get_attr_length (insn) == 2)
1725 return \"b%k1 %l0\";
1726 else if (get_attr_length (insn) == 4)
1727 return \"b%k1 %l0:16\";
1729 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1731 [(set_attr "type" "branch")
1732 (set_attr "cc" "none")])
1734 ;; Unconditional and other jump instructions.
1738 (label_ref (match_operand 0 "" "")))]
1742 if (get_attr_length (insn) == 2)
1744 else if (get_attr_length (insn) == 4)
1745 return \"bra %l0:16\";
1747 return \"jmp @%l0\";
1749 [(set_attr "type" "branch")
1750 (set_attr "cc" "none")])
1752 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1754 (define_expand "tablejump"
1755 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1756 (use (label_ref (match_operand 1 "" "")))])]
1760 (define_insn "*tablejump_h8300"
1761 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1762 (use (label_ref (match_operand 1 "" "")))]
1765 [(set_attr "cc" "none")
1766 (set_attr "length" "2")])
1768 (define_insn "*tablejump_h8300hs_advanced"
1769 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1770 (use (label_ref (match_operand 1 "" "")))]
1771 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1773 [(set_attr "cc" "none")
1774 (set_attr "length" "2")])
1776 (define_insn "*tablejump_h8300hs_normal"
1777 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1778 (use (label_ref (match_operand 1 "" "")))]
1779 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1781 [(set_attr "cc" "none")
1782 (set_attr "length" "2")])
1784 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1786 (define_expand "indirect_jump"
1787 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1791 (define_insn "*indirect_jump_h8300"
1792 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1795 [(set_attr "cc" "none")
1796 (set_attr "length" "2")])
1798 (define_insn "*indirect_jump_h8300hs_advanced"
1799 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1800 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
1802 [(set_attr "cc" "none")
1803 (set_attr "length" "2")])
1805 (define_insn "*indirect_jump_h8300hs_normal"
1806 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1807 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
1809 [(set_attr "cc" "none")
1810 (set_attr "length" "2")])
1812 ;; Call subroutine with no return value.
1814 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1817 [(call (match_operand:QI 0 "call_insn_operand" "or")
1818 (match_operand:HI 1 "general_operand" "g"))]
1822 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1823 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1824 return \"jsr\\t@%0:8\";
1826 return \"jsr\\t%0\";
1828 [(set_attr "cc" "clobber")
1829 (set (attr "length")
1830 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1834 ;; Call subroutine, returning value in operand 0
1835 ;; (which must be a hard register).
1837 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1839 (define_insn "call_value"
1840 [(set (match_operand 0 "" "=r")
1841 (call (match_operand:QI 1 "call_insn_operand" "or")
1842 (match_operand:HI 2 "general_operand" "g")))]
1846 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1847 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1848 return \"jsr\\t@%1:8\";
1850 return \"jsr\\t%1\";
1852 [(set_attr "cc" "clobber")
1853 (set (attr "length")
1854 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1862 [(set_attr "cc" "none")
1863 (set_attr "length" "2")])
1865 ;; ----------------------------------------------------------------------
1866 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
1867 ;; ----------------------------------------------------------------------
1869 (define_expand "push_h8300"
1870 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
1871 (match_operand:HI 0 "register_operand" ""))]
1875 (define_expand "push_h8300hs_advanced"
1876 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
1877 (match_operand:SI 0 "register_operand" ""))]
1878 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1881 (define_expand "push_h8300hs_normal"
1882 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
1883 (match_operand:SI 0 "register_operand" ""))]
1884 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1887 (define_expand "pop_h8300"
1888 [(set (match_operand:HI 0 "register_operand" "")
1889 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
1893 (define_expand "pop_h8300hs_advanced"
1894 [(set (match_operand:SI 0 "register_operand" "")
1895 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
1896 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
1899 (define_expand "pop_h8300hs_normal"
1900 [(set (match_operand:SI 0 "register_operand" "")
1901 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
1902 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
1905 (define_insn "stm_h8300s_2_advanced"
1907 [(set (reg:SI SP_REG)
1908 (plus:SI (reg:SI SP_REG) (const_int -8)))
1909 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1910 (match_operand:SI 0 "register_operand" ""))
1911 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1912 (match_operand:SI 1 "register_operand" ""))])]
1913 "TARGET_H8300S && !TARGET_NORMAL_MODE
1914 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1915 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1916 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1917 "stm.l\\t%S0-%S1,@-er7"
1918 [(set_attr "cc" "none")
1919 (set_attr "length" "4")])
1921 (define_insn "stm_h8300s_2_normal"
1923 [(set (reg:HI SP_REG)
1924 (plus:HI (reg:HI SP_REG) (const_int -8)))
1925 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1926 (match_operand:SI 0 "register_operand" ""))
1927 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1928 (match_operand:SI 1 "register_operand" ""))])]
1929 "TARGET_H8300S && TARGET_NORMAL_MODE
1930 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1931 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1932 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1933 "stm.l\\t%S0-%S1,@-er7"
1934 [(set_attr "cc" "none")
1935 (set_attr "length" "4")])
1937 (define_expand "stm_h8300s_2"
1938 [(match_operand:SI 0 "register_operand" "")
1939 (match_operand:SI 1 "register_operand" "")]
1941 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
1942 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
1943 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
1946 if (!TARGET_NORMAL_MODE)
1947 emit_insn (gen_stm_h8300s_2_advanced (operands[0], operands[1]));
1949 emit_insn (gen_stm_h8300s_2_normal (operands[0], operands[1]));
1953 (define_insn "stm_h8300s_3_advanced"
1955 [(set (reg:SI SP_REG)
1956 (plus:SI (reg:SI SP_REG) (const_int -12)))
1957 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
1958 (match_operand:SI 0 "register_operand" ""))
1959 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
1960 (match_operand:SI 1 "register_operand" ""))
1961 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
1962 (match_operand:SI 2 "register_operand" ""))])]
1963 "TARGET_H8300S && !TARGET_NORMAL_MODE
1964 && ((REGNO (operands[0]) == 0
1965 && REGNO (operands[1]) == 1
1966 && REGNO (operands[2]) == 2)
1967 || (REGNO (operands[0]) == 4
1968 && REGNO (operands[1]) == 5
1969 && REGNO (operands[2]) == 6))"
1970 "stm.l\\t%S0-%S2,@-er7"
1971 [(set_attr "cc" "none")
1972 (set_attr "length" "4")])
1974 (define_insn "stm_h8300s_3_normal"
1976 [(set (reg:HI SP_REG)
1977 (plus:HI (reg:HI SP_REG) (const_int -12)))
1978 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
1979 (match_operand:SI 0 "register_operand" ""))
1980 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
1981 (match_operand:SI 1 "register_operand" ""))
1982 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
1983 (match_operand:SI 2 "register_operand" ""))])]
1984 "TARGET_H8300S && TARGET_NORMAL_MODE
1985 && ((REGNO (operands[0]) == 0
1986 && REGNO (operands[1]) == 1
1987 && REGNO (operands[2]) == 2)
1988 || (REGNO (operands[0]) == 4
1989 && REGNO (operands[1]) == 5
1990 && REGNO (operands[2]) == 6))"
1991 "stm.l\\t%S0-%S2,@-er7"
1992 [(set_attr "cc" "none")
1993 (set_attr "length" "4")])
1995 (define_expand "stm_h8300s_3"
1996 [(match_operand:SI 0 "register_operand" "")
1997 (match_operand:SI 1 "register_operand" "")
1998 (match_operand:SI 2 "register_operand" "")]
2000 && ((REGNO (operands[0]) == 0
2001 && REGNO (operands[1]) == 1
2002 && REGNO (operands[2]) == 2)
2003 || (REGNO (operands[0]) == 4
2004 && REGNO (operands[1]) == 5
2005 && REGNO (operands[2]) == 6))"
2008 if (!TARGET_NORMAL_MODE)
2009 emit_insn (gen_stm_h8300s_3_advanced (operands[0], operands[1],
2012 emit_insn (gen_stm_h8300s_3_normal (operands[0], operands[1],
2017 (define_insn "stm_h8300s_4_advanced"
2019 [(set (reg:SI SP_REG)
2020 (plus:SI (reg:SI SP_REG) (const_int -16)))
2021 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
2022 (match_operand:SI 0 "register_operand" ""))
2023 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
2024 (match_operand:SI 1 "register_operand" ""))
2025 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
2026 (match_operand:SI 2 "register_operand" ""))
2027 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
2028 (match_operand:SI 3 "register_operand" ""))])]
2029 "TARGET_H8300S && !TARGET_NORMAL_MODE
2030 && REGNO (operands[0]) == 0
2031 && REGNO (operands[1]) == 1
2032 && REGNO (operands[2]) == 2
2033 && REGNO (operands[3]) == 3"
2034 "stm.l\\t%S0-%S3,@-er7"
2035 [(set_attr "cc" "none")
2036 (set_attr "length" "4")])
2038 (define_insn "stm_h8300s_4_normal"
2040 [(set (reg:HI SP_REG)
2041 (plus:HI (reg:HI SP_REG) (const_int -16)))
2042 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
2043 (match_operand:SI 0 "register_operand" ""))
2044 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
2045 (match_operand:SI 1 "register_operand" ""))
2046 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
2047 (match_operand:SI 2 "register_operand" ""))
2048 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
2049 (match_operand:SI 3 "register_operand" ""))])]
2050 "TARGET_H8300S && TARGET_NORMAL_MODE
2051 && REGNO (operands[0]) == 0
2052 && REGNO (operands[1]) == 1
2053 && REGNO (operands[2]) == 2
2054 && REGNO (operands[3]) == 3"
2055 "stm.l\\t%S0-%S3,@-er7"
2056 [(set_attr "cc" "none")
2057 (set_attr "length" "4")])
2059 (define_expand "stm_h8300s_4"
2060 [(match_operand:SI 0 "register_operand" "")
2061 (match_operand:SI 1 "register_operand" "")
2062 (match_operand:SI 2 "register_operand" "")
2063 (match_operand:SI 3 "register_operand" "")]
2065 && REGNO (operands[0]) == 0
2066 && REGNO (operands[1]) == 1
2067 && REGNO (operands[2]) == 2
2068 && REGNO (operands[3]) == 3"
2071 if (!TARGET_NORMAL_MODE)
2072 emit_insn (gen_stm_h8300s_4_advanced (operands[0], operands[1],
2073 operands[2], operands[3]));
2075 emit_insn (gen_stm_h8300s_4_normal (operands[0], operands[1],
2076 operands[2], operands[3]));
2080 (define_insn "ldm_h8300s_2_advanced"
2082 [(set (reg:SI SP_REG)
2083 (plus:SI (reg:SI SP_REG) (const_int 8)))
2084 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2085 (match_operand:SI 0 "register_operand" ""))
2086 (set (mem:SI (reg:SI SP_REG))
2087 (match_operand:SI 1 "register_operand" ""))])]
2088 "TARGET_H8300S && !TARGET_NORMAL_MODE
2089 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2090 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2091 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2092 "ldm.l\\t@er7+,%S0-%S1"
2093 [(set_attr "cc" "none")
2094 (set_attr "length" "4")])
2096 (define_insn "ldm_h8300s_2_normal"
2098 [(set (reg:HI SP_REG)
2099 (plus:HI (reg:HI SP_REG) (const_int 8)))
2100 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2101 (match_operand:SI 0 "register_operand" ""))
2102 (set (mem:SI (reg:HI SP_REG))
2103 (match_operand:SI 1 "register_operand" ""))])]
2104 "TARGET_H8300S && TARGET_NORMAL_MODE
2105 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2106 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2107 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2108 "ldm.l\\t@er7+,%S0-%S1"
2109 [(set_attr "cc" "none")
2110 (set_attr "length" "4")])
2112 (define_expand "ldm_h8300s_2"
2113 [(match_operand:SI 0 "register_operand" "")
2114 (match_operand:SI 1 "register_operand" "")]
2116 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
2117 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
2118 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
2121 if (!TARGET_NORMAL_MODE)
2122 emit_insn (gen_ldm_h8300s_2_advanced (operands[0], operands[1]));
2124 emit_insn (gen_ldm_h8300s_2_normal (operands[0], operands[1]));
2128 (define_insn "ldm_h8300s_3_advanced"
2130 [(set (reg:SI SP_REG)
2131 (plus:SI (reg:SI SP_REG) (const_int 12)))
2132 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2133 (match_operand:SI 0 "register_operand" ""))
2134 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2135 (match_operand:SI 1 "register_operand" ""))
2136 (set (mem:SI (reg:SI SP_REG))
2137 (match_operand:SI 2 "register_operand" ""))])]
2138 "TARGET_H8300S && !TARGET_NORMAL_MODE
2139 && ((REGNO (operands[0]) == 0
2140 && REGNO (operands[1]) == 1
2141 && REGNO (operands[2]) == 2)
2142 || (REGNO (operands[0]) == 4
2143 && REGNO (operands[1]) == 5
2144 && REGNO (operands[2]) == 6))"
2145 "ldm.l\\t@er7+,%S0-%S2"
2146 [(set_attr "cc" "none")
2147 (set_attr "length" "4")])
2149 (define_insn "ldm_h8300s_3_normal"
2151 [(set (reg:HI SP_REG)
2152 (plus:HI (reg:HI SP_REG) (const_int 12)))
2153 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2154 (match_operand:SI 0 "register_operand" ""))
2155 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2156 (match_operand:SI 1 "register_operand" ""))
2157 (set (mem:SI (reg:HI SP_REG))
2158 (match_operand:SI 2 "register_operand" ""))])]
2159 "TARGET_H8300S && TARGET_NORMAL_MODE
2160 && ((REGNO (operands[0]) == 0
2161 && REGNO (operands[1]) == 1
2162 && REGNO (operands[2]) == 2)
2163 || (REGNO (operands[0]) == 4
2164 && REGNO (operands[1]) == 5
2165 && REGNO (operands[2]) == 6))"
2166 "ldm.l\\t@er7+,%S0-%S2"
2167 [(set_attr "cc" "none")
2168 (set_attr "length" "4")])
2170 (define_expand "ldm_h8300s_3"
2171 [(match_operand:SI 0 "register_operand" "")
2172 (match_operand:SI 1 "register_operand" "")
2173 (match_operand:SI 2 "register_operand" "")]
2175 && ((REGNO (operands[0]) == 0
2176 && REGNO (operands[1]) == 1
2177 && REGNO (operands[2]) == 2)
2178 || (REGNO (operands[0]) == 4
2179 && REGNO (operands[1]) == 5
2180 && REGNO (operands[2]) == 6))"
2183 if (!TARGET_NORMAL_MODE)
2184 emit_insn (gen_ldm_h8300s_3_advanced (operands[0], operands[1],
2187 emit_insn (gen_ldm_h8300s_3_normal (operands[0], operands[1],
2192 (define_insn "ldm_h8300s_4_advanced"
2194 [(set (reg:SI SP_REG)
2195 (plus:SI (reg:SI SP_REG) (const_int 16)))
2196 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 12)))
2197 (match_operand:SI 0 "register_operand" ""))
2198 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 8)))
2199 (match_operand:SI 1 "register_operand" ""))
2200 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int 4)))
2201 (match_operand:SI 2 "register_operand" ""))
2202 (set (mem:SI (reg:SI SP_REG))
2203 (match_operand:SI 3 "register_operand" ""))])]
2204 "TARGET_H8300S && !TARGET_NORMAL_MODE
2205 && REGNO (operands[0]) == 0
2206 && REGNO (operands[1]) == 1
2207 && REGNO (operands[2]) == 2
2208 && REGNO (operands[3]) == 3"
2209 "ldm.l\\t@er7+,%S0-%S3"
2210 [(set_attr "cc" "none")
2211 (set_attr "length" "4")])
2213 (define_insn "ldm_h8300s_4_normal"
2215 [(set (reg:HI SP_REG)
2216 (plus:HI (reg:HI SP_REG) (const_int 16)))
2217 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 12)))
2218 (match_operand:SI 0 "register_operand" ""))
2219 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 8)))
2220 (match_operand:SI 1 "register_operand" ""))
2221 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int 4)))
2222 (match_operand:SI 2 "register_operand" ""))
2223 (set (mem:SI (reg:HI SP_REG))
2224 (match_operand:SI 3 "register_operand" ""))])]
2225 "TARGET_H8300S && !TARGET_NORMAL_MODE
2226 && REGNO (operands[0]) == 0
2227 && REGNO (operands[1]) == 1
2228 && REGNO (operands[2]) == 2
2229 && REGNO (operands[3]) == 3"
2230 "ldm.l\\t@er7+,%S0-%S3"
2231 [(set_attr "cc" "none")
2232 (set_attr "length" "4")])
2234 (define_expand "ldm_h8300s_4"
2235 [(match_operand:SI 0 "register_operand" "")
2236 (match_operand:SI 1 "register_operand" "")
2237 (match_operand:SI 2 "register_operand" "")
2238 (match_operand:SI 3 "register_operand" "")]
2239 "TARGET_H8300S && !TARGET_NORMAL_MODE
2240 && REGNO (operands[0]) == 0
2241 && REGNO (operands[1]) == 1
2242 && REGNO (operands[2]) == 2
2243 && REGNO (operands[3]) == 3"
2246 if (!TARGET_NORMAL_MODE)
2247 emit_insn (gen_ldm_h8300s_4_advanced (operands[0], operands[1],
2248 operands[2], operands[3]));
2250 emit_insn (gen_ldm_h8300s_4_normal (operands[0], operands[1],
2251 operands[2], operands[3]));
2255 (define_expand "return"
2257 "h8300_can_use_return_insn_p ()"
2260 (define_insn "*return_1"
2265 if (h8300_current_function_interrupt_function_p ())
2270 [(set_attr "cc" "none")
2271 (set_attr "length" "2")])
2273 (define_expand "prologue"
2276 "h8300_expand_prologue (); DONE;")
2278 (define_expand "epilogue"
2281 "h8300_expand_epilogue ();")
2283 (define_insn "monitor_prologue"
2284 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2289 return \"subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr\";
2290 else if (TARGET_H8300H)
2291 return \"mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr\";
2292 else if (TARGET_H8300S)
2293 return \"stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr\";
2296 [(set_attr "length" "20")
2297 (set_attr "cc" "clobber")])
2299 ;; ----------------------------------------------------------------------
2300 ;; EXTEND INSTRUCTIONS
2301 ;; ----------------------------------------------------------------------
2303 (define_expand "zero_extendqihi2"
2304 [(set (match_operand:HI 0 "register_operand" "")
2305 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2309 (define_insn "*zero_extendqihi2_h8300"
2310 [(set (match_operand:HI 0 "register_operand" "=r,r")
2311 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2316 [(set_attr "length" "2,10")
2317 (set_attr "cc" "clobber,clobber")])
2319 (define_insn "*zero_extendqihi2_h8300hs"
2320 [(set (match_operand:HI 0 "register_operand" "=r,r")
2321 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2322 "TARGET_H8300H || TARGET_H8300S"
2326 [(set_attr "length" "2,10")
2327 (set_attr "cc" "set_znv,set_znv")])
2329 ;; Split the zero extension of a general operand (actually a memory
2330 ;; operand) into a load of the operand and the actual zero extension
2331 ;; so that 1) the length will be accurate, and 2) the zero extensions
2332 ;; appearing at the end of basic blocks may be merged.
2335 [(set (match_operand:HI 0 "register_operand" "")
2336 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2341 (zero_extend:HI (match_dup 2)))]
2342 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2344 (define_expand "zero_extendqisi2"
2345 [(set (match_operand:SI 0 "register_operand" "")
2346 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2350 (define_insn "*zero_extendqisi2_h8300"
2351 [(set (match_operand:SI 0 "register_operand" "=r,r")
2352 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2355 mov.b #0,%x0\;sub.w %e0,%e0
2356 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2357 [(set_attr "length" "4,8")
2358 (set_attr "cc" "clobber,clobber")])
2360 (define_insn "*zero_extendqisi2_h8300hs"
2361 [(set (match_operand:SI 0 "register_operand" "=r,r")
2362 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2363 "TARGET_H8300H || TARGET_H8300S"
2367 [(set (match_operand:SI 0 "register_operand" "")
2368 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2369 "(TARGET_H8300H || TARGET_H8300S)
2370 && reg_overlap_mentioned_p (operands[0], operands[1])
2371 && reload_completed"
2375 (zero_extend:HI (match_dup 2)))
2377 (zero_extend:SI (match_dup 3)))]
2378 "operands[2] = gen_lowpart (QImode, operands[0]);
2379 operands[3] = gen_lowpart (HImode, operands[0]);")
2382 [(set (match_operand:SI 0 "register_operand" "")
2383 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2384 "(TARGET_H8300H || TARGET_H8300S)
2385 && !reg_overlap_mentioned_p (operands[0], operands[1])
2386 && reload_completed"
2389 (set (strict_low_part (match_dup 2))
2391 "operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));")
2393 (define_expand "zero_extendhisi2"
2394 [(set (match_operand:SI 0 "register_operand" "")
2395 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2399 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2400 (define_insn "*zero_extendhisi2_h8300"
2401 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2402 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2406 mov.w %f1,%f0\;sub.w %e0,%e0
2407 mov.w %e1,%f0\;sub.w %e0,%e0"
2408 [(set_attr "length" "2,4,6")
2409 (set_attr "cc" "clobber,clobber,clobber")])
2411 (define_insn "*zero_extendhisi2_h8300hs"
2412 [(set (match_operand:SI 0 "register_operand" "=r")
2413 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2414 "TARGET_H8300H || TARGET_H8300S"
2416 [(set_attr "length" "2")
2417 (set_attr "cc" "set_znv")])
2419 (define_expand "extendqihi2"
2420 [(set (match_operand:HI 0 "register_operand" "")
2421 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
2425 (define_insn "*extendqihi2_h8300"
2426 [(set (match_operand:HI 0 "register_operand" "=r,r")
2427 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2430 bld #7,%s0\;subx %t0,%t0
2431 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2432 [(set_attr "length" "4,8")
2433 (set_attr "cc" "clobber,clobber")])
2435 (define_insn "*extendqihi2_h8300hs"
2436 [(set (match_operand:HI 0 "register_operand" "=r")
2437 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2438 "TARGET_H8300H || TARGET_H8300S"
2440 [(set_attr "length" "2")
2441 (set_attr "cc" "set_znv")])
2443 (define_expand "extendqisi2"
2444 [(set (match_operand:SI 0 "register_operand" "")
2445 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2449 (define_insn "*extendqisi2_h8300"
2450 [(set (match_operand:SI 0 "register_operand" "")
2451 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2454 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2455 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2456 [(set_attr "length" "8,12")
2457 (set_attr "cc" "clobber,clobber")])
2459 ;; The following pattern is needed because without the pattern, the
2460 ;; combiner would split (sign_extend:SI (reg:QI)) into into two 24-bit
2461 ;; shifts, one ashift and one ashiftrt.
2463 (define_insn_and_split "*extendqisi2_h8300hs"
2464 [(set (match_operand:SI 0 "register_operand" "=r")
2465 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2466 "(TARGET_H8300H || TARGET_H8300S)"
2468 "&& reload_completed"
2470 (sign_extend:HI (match_dup 1)))
2472 (sign_extend:SI (match_dup 2)))]
2473 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
2475 (define_expand "extendhisi2"
2476 [(set (match_operand:SI 0 "register_operand" "")
2477 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2481 (define_insn "*extendhisi2_h8300"
2482 [(set (match_operand:SI 0 "register_operand" "=r,r")
2483 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2486 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2487 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2488 [(set_attr "length" "6,10")
2489 (set_attr "cc" "clobber,clobber")])
2491 (define_insn "*extendhisi2_h8300hs"
2492 [(set (match_operand:SI 0 "register_operand" "=r")
2493 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2494 "TARGET_H8300H || TARGET_H8300S"
2496 [(set_attr "length" "2")
2497 (set_attr "cc" "set_znv")])
2499 ;; ----------------------------------------------------------------------
2501 ;; ----------------------------------------------------------------------
2503 ;; We make some attempt to provide real efficient shifting. One example is
2504 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
2505 ;; reg and moving 0 into the former reg.
2507 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2508 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2509 ;; give the optimizer more cracks at the code. However, we wish to do things
2510 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2511 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2512 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
2513 ;; to detect cases it can optimize.
2515 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2516 ;; easier "do it at insn emit time" route.
2520 (define_expand "ashlqi3"
2521 [(set (match_operand:QI 0 "register_operand" "")
2522 (ashift:QI (match_operand:QI 1 "register_operand" "")
2523 (match_operand:QI 2 "nonmemory_operand" "")))]
2525 "expand_a_shift (QImode, ASHIFT, operands); DONE;")
2527 (define_expand "ashrqi3"
2528 [(set (match_operand:QI 0 "register_operand" "")
2529 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2530 (match_operand:QI 2 "nonmemory_operand" "")))]
2532 "expand_a_shift (QImode, ASHIFTRT, operands); DONE;")
2534 (define_expand "lshrqi3"
2535 [(set (match_operand:QI 0 "register_operand" "")
2536 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2537 (match_operand:QI 2 "nonmemory_operand" "")))]
2539 "expand_a_shift (QImode, LSHIFTRT, operands); DONE;")
2541 (define_insn "*shiftqi"
2542 [(set (match_operand:QI 0 "register_operand" "=r,r")
2543 (match_operator:QI 3 "nshift_operator"
2544 [ (match_operand:QI 1 "register_operand" "0,0")
2545 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2546 (clobber (match_scratch:QI 4 "=X,&r"))]
2548 "* return output_a_shift (operands);"
2549 [(set (attr "length")
2550 (symbol_ref "compute_a_shift_length (insn, operands)"))
2552 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2556 (define_expand "ashlhi3"
2557 [(set (match_operand:HI 0 "register_operand" "")
2558 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
2559 (match_operand:QI 2 "nonmemory_operand" "")))]
2561 "expand_a_shift (HImode, ASHIFT, operands); DONE;")
2563 (define_expand "lshrhi3"
2564 [(set (match_operand:HI 0 "register_operand" "")
2565 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
2566 (match_operand:QI 2 "nonmemory_operand" "")))]
2568 "expand_a_shift (HImode, LSHIFTRT, operands); DONE;")
2570 (define_expand "ashrhi3"
2571 [(set (match_operand:HI 0 "register_operand" "")
2572 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2573 (match_operand:QI 2 "nonmemory_operand" "")))]
2575 "expand_a_shift (HImode, ASHIFTRT, operands); DONE;")
2577 (define_insn "*shifthi"
2578 [(set (match_operand:HI 0 "register_operand" "=r,r")
2579 (match_operator:HI 3 "nshift_operator"
2580 [ (match_operand:HI 1 "register_operand" "0,0")
2581 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2582 (clobber (match_scratch:QI 4 "=X,&r"))]
2584 "* return output_a_shift (operands);"
2585 [(set (attr "length")
2586 (symbol_ref "compute_a_shift_length (insn, operands)"))
2588 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2592 (define_expand "ashlsi3"
2593 [(set (match_operand:SI 0 "register_operand" "")
2594 (ashift:SI (match_operand:SI 1 "general_operand" "")
2595 (match_operand:QI 2 "nonmemory_operand" "")))]
2597 "expand_a_shift (SImode, ASHIFT, operands); DONE;")
2599 (define_expand "lshrsi3"
2600 [(set (match_operand:SI 0 "register_operand" "")
2601 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
2602 (match_operand:QI 2 "nonmemory_operand" "")))]
2604 "expand_a_shift (SImode, LSHIFTRT, operands); DONE;")
2606 (define_expand "ashrsi3"
2607 [(set (match_operand:SI 0 "register_operand" "")
2608 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
2609 (match_operand:QI 2 "nonmemory_operand" "")))]
2611 "expand_a_shift (SImode, ASHIFTRT, operands); DONE;")
2613 (define_insn "*shiftsi"
2614 [(set (match_operand:SI 0 "register_operand" "=r,r")
2615 (match_operator:SI 3 "nshift_operator"
2616 [ (match_operand:SI 1 "register_operand" "0,0")
2617 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2618 (clobber (match_scratch:QI 4 "=X,&r"))]
2620 "* return output_a_shift (operands);"
2621 [(set (attr "length")
2622 (symbol_ref "compute_a_shift_length (insn, operands)"))
2624 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2626 ;; Split a variable shift into a loop. If the register containing
2627 ;; the shift count dies, then we just use that register.
2631 [(set (match_operand 0 "register_operand" "")
2632 (match_operator 2 "nshift_operator"
2634 (match_operand:QI 1 "register_operand" "")]))
2635 (clobber (match_operand:QI 3 "register_operand" ""))])]
2637 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2641 (if_then_else (le (cc0) (const_int 0))
2642 (label_ref (match_dup 5))
2647 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2648 (clobber (scratch:QI))])
2650 (plus:QI (match_dup 1) (const_int -1)))
2654 (if_then_else (ne (cc0) (const_int 0))
2655 (label_ref (match_dup 4))
2658 "operands[4] = gen_label_rtx ();
2659 operands[5] = gen_label_rtx ();")
2663 [(set (match_operand 0 "register_operand" "")
2664 (match_operator 2 "nshift_operator"
2666 (match_operand:QI 1 "register_operand" "")]))
2667 (clobber (match_operand:QI 3 "register_operand" ""))])]
2669 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2675 (if_then_else (le (cc0) (const_int 0))
2676 (label_ref (match_dup 5))
2681 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2682 (clobber (scratch:QI))])
2684 (plus:QI (match_dup 3) (const_int -1)))
2688 (if_then_else (ne (cc0) (const_int 0))
2689 (label_ref (match_dup 4))
2692 "operands[4] = gen_label_rtx ();
2693 operands[5] = gen_label_rtx ();")
2695 ;; ----------------------------------------------------------------------
2697 ;; ----------------------------------------------------------------------
2699 (define_expand "rotlqi3"
2700 [(set (match_operand:QI 0 "register_operand" "")
2701 (rotate:QI (match_operand:QI 1 "register_operand" "")
2702 (match_operand:QI 2 "nonmemory_operand" "")))]
2704 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2706 (define_insn "*rotlqi3_1"
2707 [(set (match_operand:QI 0 "register_operand" "=r")
2708 (rotate:QI (match_operand:QI 1 "register_operand" "0")
2709 (match_operand:QI 2 "immediate_operand" "")))]
2711 "* return output_a_rotate (ROTATE, operands);"
2712 [(set (attr "length")
2713 (symbol_ref "compute_a_rotate_length (operands)"))
2714 (set_attr "cc" "clobber")])
2716 (define_expand "rotlhi3"
2717 [(set (match_operand:HI 0 "register_operand" "")
2718 (rotate:HI (match_operand:HI 1 "register_operand" "")
2719 (match_operand:QI 2 "nonmemory_operand" "")))]
2721 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2723 (define_insn "*rotlhi3_1"
2724 [(set (match_operand:HI 0 "register_operand" "=r")
2725 (rotate:HI (match_operand:HI 1 "register_operand" "0")
2726 (match_operand:QI 2 "immediate_operand" "")))]
2728 "* return output_a_rotate (ROTATE, operands);"
2729 [(set (attr "length")
2730 (symbol_ref "compute_a_rotate_length (operands)"))
2731 (set_attr "cc" "clobber")])
2733 (define_expand "rotlsi3"
2734 [(set (match_operand:SI 0 "register_operand" "")
2735 (rotate:SI (match_operand:SI 1 "register_operand" "")
2736 (match_operand:QI 2 "nonmemory_operand" "")))]
2737 "TARGET_H8300H || TARGET_H8300S"
2738 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
2740 (define_insn "*rotlsi3_1"
2741 [(set (match_operand:SI 0 "register_operand" "=r")
2742 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2743 (match_operand:QI 2 "immediate_operand" "")))]
2744 "TARGET_H8300H || TARGET_H8300S"
2745 "* return output_a_rotate (ROTATE, operands);"
2746 [(set (attr "length")
2747 (symbol_ref "compute_a_rotate_length (operands)"))
2748 (set_attr "cc" "clobber")])
2750 ;; -----------------------------------------------------------------
2752 ;; -----------------------------------------------------------------
2753 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2754 ;; instructions so let's use them as well as we can.
2756 ;; You'll never believe all these patterns perform one basic action --
2757 ;; load a bit from the source, optionally invert the bit, then store it
2758 ;; in the destination (which is known to be zero).
2760 ;; Combine obviously need some work to better identify this situation and
2761 ;; canonicalize the form better.
2764 ;; Normal loads with a 16bit destination.
2768 [(set (match_operand:HI 0 "register_operand" "=&r")
2769 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2771 (match_operand:HI 2 "immediate_operand" "n")))]
2773 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2774 [(set_attr "cc" "clobber")
2775 (set_attr "length" "6")])
2778 ;; Inverted loads with a 16bit destination.
2782 [(set (match_operand:HI 0 "register_operand" "=&r")
2783 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2784 (match_operand:HI 3 "const_int_operand" "n"))
2786 (match_operand:HI 2 "const_int_operand" "n")))]
2788 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2789 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2790 [(set_attr "cc" "clobber")
2791 (set_attr "length" "8")])
2794 ;; Normal loads with a 32bit destination.
2797 (define_insn "*extzv_1_r_h8300"
2798 [(set (match_operand:SI 0 "register_operand" "=&r")
2799 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2801 (match_operand 2 "const_int_operand" "n")))]
2803 && INTVAL (operands[2]) < 16"
2804 "* return output_simode_bld (0, operands);"
2805 [(set_attr "cc" "clobber")
2806 (set_attr "length" "8")])
2808 (define_insn "*extzv_1_r_h8300hs"
2809 [(set (match_operand:SI 0 "register_operand" "=r,r")
2810 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2812 (match_operand 2 "const_int_operand" "n,n")))]
2813 "(TARGET_H8300H || TARGET_H8300S)
2814 && INTVAL (operands[2]) < 16"
2815 "* return output_simode_bld (0, operands);"
2816 [(set_attr "cc" "set_znv,set_znv")
2817 (set_attr "length" "8,6")])
2820 ;; Inverted loads with a 32bit destination.
2823 (define_insn "*extzv_1_r_inv_h8300"
2824 [(set (match_operand:SI 0 "register_operand" "=&r")
2825 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2826 (match_operand:HI 3 "const_int_operand" "n"))
2828 (match_operand 2 "const_int_operand" "n")))]
2830 && INTVAL (operands[2]) < 16
2831 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2832 "* return output_simode_bld (1, operands);"
2833 [(set_attr "cc" "clobber")
2834 (set_attr "length" "8")])
2836 (define_insn "*extzv_1_r_inv_h8300hs"
2837 [(set (match_operand:SI 0 "register_operand" "=r,r")
2838 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2839 (match_operand 3 "const_int_operand" "n,n"))
2841 (match_operand 2 "const_int_operand" "n,n")))]
2842 "(TARGET_H8300H || TARGET_H8300S)
2843 && INTVAL (operands[2]) < 16
2844 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2845 "* return output_simode_bld (1, operands);"
2846 [(set_attr "cc" "set_znv,set_znv")
2847 (set_attr "length" "8,6")])
2849 (define_expand "insv"
2850 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2851 (match_operand:HI 1 "general_operand" "")
2852 (match_operand:HI 2 "general_operand" ""))
2853 (match_operand:HI 3 "general_operand" ""))]
2857 /* We only have single bit bit-field instructions. */
2858 if (INTVAL (operands[1]) != 1)
2861 /* For now, we don't allow memory operands. */
2862 if (GET_CODE (operands[0]) == MEM
2863 || GET_CODE (operands[3]) == MEM)
2868 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2870 (match_operand:HI 1 "immediate_operand" "n"))
2871 (match_operand:HI 2 "register_operand" "r"))]
2873 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2874 [(set_attr "cc" "clobber")
2875 (set_attr "length" "4")])
2877 (define_expand "extzv"
2878 [(set (match_operand:HI 0 "register_operand" "")
2879 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2880 (match_operand:HI 2 "general_operand" "")
2881 (match_operand:HI 3 "general_operand" "")))]
2885 /* We only have single bit bit-field instructions. */
2886 if (INTVAL (operands[2]) != 1)
2889 /* For now, we don't allow memory operands. */
2890 if (GET_CODE (operands[1]) == MEM)
2894 ;; BAND, BOR, and BXOR patterns
2897 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2898 (match_operator:HI 4 "bit_operator"
2899 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2901 (match_operand:HI 2 "immediate_operand" "n"))
2902 (match_operand:HI 3 "bit_operand" "0")]))]
2904 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
2905 [(set_attr "cc" "clobber")
2906 (set_attr "length" "6")])
2909 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2910 (match_operator:HI 5 "bit_operator"
2911 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2913 (match_operand:HI 2 "immediate_operand" "n"))
2914 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2916 (match_operand:HI 4 "immediate_operand" "n"))]))]
2918 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
2919 [(set_attr "cc" "clobber")
2920 (set_attr "length" "6")])
2922 ;; -----------------------------------------------------------------
2924 ;; -----------------------------------------------------------------
2928 (define_insn "*insv_si_1_n"
2929 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2931 (match_operand:SI 1 "const_int_operand" "n"))
2932 (match_operand:SI 2 "register_operand" "r"))]
2933 "(TARGET_H8300H || TARGET_H8300S)
2934 && INTVAL (operands[1]) < 16"
2935 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
2936 [(set_attr "cc" "clobber")
2937 (set_attr "length" "4")])
2939 (define_insn "*insv_si_1_n_lshiftrt"
2940 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2942 (match_operand:SI 1 "const_int_operand" "n"))
2943 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2944 (match_operand:SI 3 "const_int_operand" "n")))]
2945 "(TARGET_H8300H || TARGET_H8300S)
2946 && INTVAL (operands[1]) < 16
2947 && INTVAL (operands[3]) < 16"
2948 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
2949 [(set_attr "cc" "clobber")
2950 (set_attr "length" "4")])
2952 (define_insn "*insv_si_1_n_lshiftrt_16"
2953 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2955 (match_operand:SI 1 "const_int_operand" "n"))
2956 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
2958 "(TARGET_H8300H || TARGET_H8300S)
2959 && INTVAL (operands[1]) < 16"
2960 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
2961 [(set_attr "cc" "clobber")
2962 (set_attr "length" "6")])
2964 (define_insn "*insv_si_8_8"
2965 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2968 (match_operand:SI 1 "register_operand" "r"))]
2969 "TARGET_H8300H || TARGET_H8300S"
2971 [(set_attr "cc" "clobber")
2972 (set_attr "length" "2")])
2974 (define_insn "*insv_si_8_8_lshiftrt_8"
2975 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2978 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
2980 "TARGET_H8300H || TARGET_H8300S"
2982 [(set_attr "cc" "clobber")
2983 (set_attr "length" "2")])
2987 (define_insn "*extzv_8_8"
2988 [(set (match_operand:SI 0 "register_operand" "=r,r")
2989 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2992 "TARGET_H8300H || TARGET_H8300S"
2994 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
2995 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
2996 [(set_attr "cc" "set_znv,clobber")
2997 (set_attr "length" "6,4")])
2999 (define_insn "*extzv_8_16"
3000 [(set (match_operand:SI 0 "register_operand" "=r")
3001 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3004 "TARGET_H8300H || TARGET_H8300S"
3005 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3006 [(set_attr "cc" "set_znv")
3007 (set_attr "length" "6")])
3009 (define_insn "*extzv_16_8"
3010 [(set (match_operand:SI 0 "register_operand" "=r")
3011 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3014 (clobber (match_scratch:SI 2 "=&r"))]
3016 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3017 [(set_attr "length" "8")
3018 (set_attr "cc" "set_znv")])
3020 ;; Extract the exponent of a float.
3022 (define_insn_and_split "*extzv_8_23"
3023 [(set (match_operand:SI 0 "register_operand" "=r")
3024 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3027 "(TARGET_H8300H || TARGET_H8300S)"
3029 "&& reload_completed"
3030 [(parallel [(set (match_dup 0)
3031 (ashift:SI (match_dup 0)
3033 (clobber (scratch:QI))])
3034 (parallel [(set (match_dup 0)
3035 (lshiftrt:SI (match_dup 0)
3037 (clobber (scratch:QI))])]
3042 ;; ((SImode) HImode) << 15
3044 (define_insn_and_split "*twoshifts_l16_r1"
3045 [(set (match_operand:SI 0 "register_operand" "=r")
3046 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3048 (const_int 2147450880)))]
3049 "(TARGET_H8300H || TARGET_H8300S)"
3051 "&& reload_completed"
3052 [(parallel [(set (match_dup 0)
3053 (ashift:SI (match_dup 0)
3055 (clobber (scratch:QI))])
3056 (parallel [(set (match_dup 0)
3057 (lshiftrt:SI (match_dup 0)
3059 (clobber (scratch:QI))])]
3062 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3064 (define_insn_and_split "*andsi3_ashift_n_lower"
3065 [(set (match_operand:SI 0 "register_operand" "=r,r")
3066 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3067 (match_operand:QI 2 "const_int_operand" "S,n"))
3068 (match_operand:SI 3 "const_int_operand" "n,n")))
3069 (clobber (match_scratch:QI 4 "=X,&r"))]
3070 "(TARGET_H8300H || TARGET_H8300S)
3071 && INTVAL (operands[2]) <= 15
3072 && INTVAL (operands[3]) == ((-1 << INTVAL (operands[2])) & 0xffff)"
3074 "&& reload_completed"
3075 [(parallel [(set (match_dup 5)
3076 (ashift:HI (match_dup 5)
3078 (clobber (match_dup 4))])
3080 (zero_extend:SI (match_dup 5)))]
3081 "operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3083 ;; Accept (A >> 30) & 2 and the like.
3085 (define_insn "*andsi3_lshiftrt_n_sb"
3086 [(set (match_operand:SI 0 "register_operand" "=r")
3087 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3088 (match_operand:SI 2 "const_int_operand" "n"))
3089 (match_operand:SI 3 "single_one_operand" "n")))]
3090 "(TARGET_H8300H || TARGET_H8300S)
3091 && exact_log2 (INTVAL (operands[3])) < 16
3092 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3095 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3096 return \"shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0\";
3098 [(set_attr "length" "8")
3099 (set_attr "cc" "clobber")])
3101 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3102 [(set (match_operand:SI 0 "register_operand" "=r")
3103 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3105 (const_int 4194304)))]
3106 "(TARGET_H8300H || TARGET_H8300S)"
3108 "&& reload_completed"
3110 (and:SI (lshiftrt:SI (match_dup 0)
3113 (parallel [(set (match_dup 0)
3114 (ashift:SI (match_dup 0)
3116 (clobber (scratch:QI))])]
3121 (define_insn "*addsi3_upper"
3122 [(set (match_operand:SI 0 "register_operand" "=r")
3123 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3125 (match_operand:SI 2 "register_operand" "0")))]
3126 "TARGET_H8300H || TARGET_H8300S"
3128 [(set_attr "length" "2")
3129 (set_attr "cc" "clobber")])
3131 (define_insn "*addsi3_lshiftrt_16_zexthi"
3132 [(set (match_operand:SI 0 "register_operand" "=r")
3133 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3135 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3136 "TARGET_H8300H || TARGET_H8300S"
3137 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3138 [(set_attr "cc" "clobber")
3139 (set_attr "length" "6")])
3141 (define_insn_and_split "*addsi3_and_r_1"
3142 [(set (match_operand:SI 0 "register_operand" "=r")
3143 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3145 (match_operand:SI 2 "register_operand" "0")))]
3146 "(TARGET_H8300H || TARGET_H8300S)"
3148 "&& reload_completed"
3150 (zero_extract:SI (match_dup 1)
3154 (if_then_else (eq (cc0)
3156 (label_ref (match_dup 3))
3159 (plus:SI (match_dup 2)
3162 "operands[3] = gen_label_rtx ();")
3164 (define_insn_and_split "*addsi3_and_not_r_1"
3165 [(set (match_operand:SI 0 "register_operand" "=r")
3166 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3168 (match_operand:SI 2 "register_operand" "0")))]
3169 "(TARGET_H8300H || TARGET_H8300S)"
3171 "&& reload_completed"
3173 (zero_extract:SI (match_dup 1)
3177 (if_then_else (ne (cc0)
3179 (label_ref (match_dup 3))
3182 (plus:SI (match_dup 2)
3185 "operands[3] = gen_label_rtx ();")
3189 (define_insn "*ixorhi3_zext"
3190 [(set (match_operand:HI 0 "register_operand" "=r")
3191 (match_operator:HI 1 "iorxor_operator"
3192 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3193 (match_operand:HI 3 "register_operand" "0")]))]
3196 [(set_attr "cc" "clobber")
3197 (set_attr "length" "2")])
3201 (define_insn "*ixorsi3_zext_qi"
3202 [(set (match_operand:SI 0 "register_operand" "=r")
3203 (match_operator:SI 1 "iorxor_operator"
3204 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3205 (match_operand:SI 3 "register_operand" "0")]))]
3208 [(set_attr "cc" "clobber")
3209 (set_attr "length" "2")])
3211 (define_insn "*ixorsi3_zext_hi"
3212 [(set (match_operand:SI 0 "register_operand" "=r")
3213 (match_operator:SI 1 "iorxor_operator"
3214 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3215 (match_operand:SI 3 "register_operand" "0")]))]
3216 "TARGET_H8300H || TARGET_H8300S"
3218 [(set_attr "cc" "clobber")
3219 (set_attr "length" "2")])
3221 (define_insn "*ixorsi3_ashift_16"
3222 [(set (match_operand:SI 0 "register_operand" "=r")
3223 (match_operator:SI 1 "iorxor_operator"
3224 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3226 (match_operand:SI 3 "register_operand" "0")]))]
3227 "TARGET_H8300H || TARGET_H8300S"
3229 [(set_attr "cc" "clobber")
3230 (set_attr "length" "2")])
3232 (define_insn "*ixorsi3_lshiftrt_16"
3233 [(set (match_operand:SI 0 "register_operand" "=r")
3234 (match_operator:SI 1 "iorxor_operator"
3235 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3237 (match_operand:SI 3 "register_operand" "0")]))]
3238 "TARGET_H8300H || TARGET_H8300S"
3240 [(set_attr "cc" "clobber")
3241 (set_attr "length" "2")])
3245 (define_insn "*iorhi3_ashift_8"
3246 [(set (match_operand:HI 0 "register_operand" "=r")
3247 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3249 (match_operand:HI 2 "register_operand" "0")))]
3252 [(set_attr "cc" "clobber")
3253 (set_attr "length" "2")])
3255 (define_insn "*iorhi3_lshiftrt_8"
3256 [(set (match_operand:HI 0 "register_operand" "=r")
3257 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3259 (match_operand:HI 2 "register_operand" "0")))]
3262 [(set_attr "cc" "clobber")
3263 (set_attr "length" "2")])
3265 (define_insn "*iorhi3_two_qi"
3266 [(set (match_operand:HI 0 "register_operand" "=r")
3267 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3268 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3272 [(set_attr "cc" "clobber")
3273 (set_attr "length" "2")])
3275 (define_insn "*iorhi3_two_qi_mem"
3276 [(set (match_operand:HI 0 "register_operand" "=&r")
3277 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3278 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3281 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3282 [(set_attr "cc" "clobber")
3283 (set_attr "length" "16")])
3286 [(set (match_operand:HI 0 "register_operand" "")
3287 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3288 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3290 "(TARGET_H8300H || TARGET_H8300S)
3292 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3295 "operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));")
3299 (define_insn "*iorsi3_two_hi"
3300 [(set (match_operand:SI 0 "register_operand" "=r")
3301 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3302 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3304 "TARGET_H8300H || TARGET_H8300S"
3306 [(set_attr "cc" "clobber")
3307 (set_attr "length" "2")])
3309 (define_insn_and_split "*iorsi3_two_qi_zext"
3310 [(set (match_operand:SI 0 "register_operand" "=&r")
3311 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3313 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3315 (const_int 65280))))]
3316 "(TARGET_H8300H || TARGET_H8300S)"
3318 "&& reload_completed"
3320 (ior:HI (zero_extend:HI (match_dup 1))
3321 (ashift:HI (subreg:HI (match_dup 2) 0)
3324 (zero_extend:SI (match_dup 3)))]
3325 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3327 (define_insn "*iorsi3_e2f"
3328 [(set (match_operand:SI 0 "register_operand" "=r")
3329 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3331 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3333 "TARGET_H8300H || TARGET_H8300S"
3335 [(set_attr "length" "2")
3336 (set_attr "cc" "clobber")])
3338 (define_insn_and_split "*iorsi3_two_qi_sext"
3339 [(set (match_operand:SI 0 "register_operand" "=r")
3340 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3341 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3343 "(TARGET_H8300H || TARGET_H8300S)"
3345 "&& reload_completed"
3347 (ior:HI (zero_extend:HI (match_dup 1))
3348 (ashift:HI (match_dup 4)
3351 (sign_extend:SI (match_dup 3)))]
3352 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3353 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3355 (define_insn "*iorsi3_w"
3356 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3357 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3359 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3360 "TARGET_H8300H || TARGET_H8300S"
3362 [(set_attr "length" "2,8")
3363 (set_attr "cc" "clobber,clobber")])
3365 (define_insn "*iorsi3_ashift_31"
3366 [(set (match_operand:SI 0 "register_operand" "=&r")
3367 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3369 (match_operand:SI 2 "register_operand" "0")))]
3370 "TARGET_H8300H || TARGET_H8300S"
3371 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3372 [(set_attr "length" "6")
3373 (set_attr "cc" "set_znv")])
3375 (define_insn "*iorsi3_and_ashift"
3376 [(set (match_operand:SI 0 "register_operand" "=r")
3377 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3378 (match_operand:SI 2 "const_int_operand" "n"))
3379 (match_operand:SI 3 "single_one_operand" "n"))
3380 (match_operand:SI 4 "register_operand" "0")))]
3381 "(TARGET_H8300H || TARGET_H8300S)
3382 && (INTVAL (operands[3]) & ~0xffff) == 0"
3385 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3386 - INTVAL (operands[2]));
3387 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3388 operands[2] = srcpos;
3389 operands[3] = dstpos;
3390 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3392 [(set_attr "length" "6")
3393 (set_attr "cc" "clobber")])
3395 (define_insn "*iorsi3_and_lshiftrt"
3396 [(set (match_operand:SI 0 "register_operand" "=r")
3397 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3398 (match_operand:SI 2 "const_int_operand" "n"))
3399 (match_operand:SI 3 "single_one_operand" "n"))
3400 (match_operand:SI 4 "register_operand" "0")))]
3401 "(TARGET_H8300H || TARGET_H8300S)
3402 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3405 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3406 + INTVAL (operands[2]));
3407 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3408 operands[2] = srcpos;
3409 operands[3] = dstpos;
3410 return \"bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0\";
3412 [(set_attr "length" "6")
3413 (set_attr "cc" "clobber")])
3415 (define_insn "*iorsi3_zero_extract"
3416 [(set (match_operand:SI 0 "register_operand" "=r")
3417 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3419 (match_operand:SI 2 "const_int_operand" "n"))
3420 (match_operand:SI 3 "register_operand" "0")))]
3421 "(TARGET_H8300H || TARGET_H8300S)
3422 && INTVAL (operands[2]) < 16"
3423 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3424 [(set_attr "length" "6")
3425 (set_attr "cc" "clobber")])
3427 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3428 [(set (match_operand:SI 0 "register_operand" "=r")
3429 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3432 (match_operand:SI 2 "register_operand" "0")))]
3433 "(TARGET_H8300H || TARGET_H8300S)"
3434 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3435 [(set_attr "length" "8")
3436 (set_attr "cc" "clobber")])
3438 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3439 [(set (match_operand:SI 0 "register_operand" "=r")
3440 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3442 (const_int 4194304))
3443 (match_operand:SI 2 "register_operand" "0")))
3444 (clobber (match_scratch:HI 3 "=&r"))]
3445 "(TARGET_H8300H || TARGET_H8300S)"
3448 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3449 return \"shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3451 return \"rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0\";
3453 [(set_attr "length" "10")
3454 (set_attr "cc" "clobber")])
3456 ;; Used to OR the exponent of a float.
3458 (define_insn "*iorsi3_shift"
3459 [(set (match_operand:SI 0 "register_operand" "=r")
3460 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3462 (match_operand:SI 2 "register_operand" "0")))
3463 (clobber (match_scratch:SI 3 "=&r"))]
3464 "TARGET_H8300H || TARGET_H8300S"
3469 [(set (match_operand:SI 0 "register_operand" "")
3470 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3473 (clobber (match_operand:SI 2 "register_operand" ""))])]
3474 "(TARGET_H8300H || TARGET_H8300S)
3476 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3477 && REGNO (operands[0]) != REGNO (operands[1])"
3478 [(parallel [(set (match_dup 3)
3479 (ashift:HI (match_dup 3)
3481 (clobber (scratch:QI))])
3483 (ior:SI (ashift:SI (match_dup 1)
3486 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3490 [(set (match_operand:SI 0 "register_operand" "")
3491 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3494 (clobber (match_operand:SI 2 "register_operand" ""))])]
3495 "(TARGET_H8300H || TARGET_H8300S)
3497 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3498 && REGNO (operands[0]) != REGNO (operands[1]))"
3501 (parallel [(set (match_dup 3)
3502 (ashift:HI (match_dup 3)
3504 (clobber (scratch:QI))])
3506 (ior:SI (ashift:SI (match_dup 2)
3509 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3511 (define_insn "*iorsi2_and_1_lshiftrt_1"
3512 [(set (match_operand:SI 0 "register_operand" "=r")
3513 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3515 (lshiftrt:SI (match_dup 1)
3517 "TARGET_H8300H || TARGET_H8300S"
3518 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3519 [(set_attr "length" "6")
3520 (set_attr "cc" "clobber")])
3522 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3523 [(set (match_operand:SI 0 "register_operand" "=r")
3524 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3526 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3528 "(TARGET_H8300H || TARGET_H8300S)"
3530 "&& reload_completed"
3532 (ior:HI (ashift:HI (match_dup 4)
3535 (parallel [(set (match_dup 0)
3536 (ashift:SI (match_dup 0)
3538 (clobber (scratch:QI))])]
3539 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3540 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3542 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3543 [(set (match_operand:SI 0 "register_operand" "=&r")
3544 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3546 (const_int 16711680))
3547 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3549 "(TARGET_H8300H || TARGET_H8300S)"
3551 "&& reload_completed"
3553 (ior:HI (zero_extend:HI (match_dup 1))
3554 (ashift:HI (subreg:HI (match_dup 2) 0)
3556 (parallel [(set (match_dup 0)
3557 (ashift:SI (match_dup 0)
3559 (clobber (scratch:QI))])]
3560 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3562 ;; Used to add the exponent of a float.
3564 (define_insn "*addsi3_shift"
3565 [(set (match_operand:SI 0 "register_operand" "=r")
3566 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3567 (const_int 8388608))
3568 (match_operand:SI 2 "register_operand" "0")))
3569 (clobber (match_scratch:SI 3 "=&r"))]
3570 "TARGET_H8300H || TARGET_H8300S"
3575 [(set (match_operand:SI 0 "register_operand" "")
3576 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3577 (const_int 8388608))
3579 (clobber (match_operand:SI 2 "register_operand" ""))])]
3580 "(TARGET_H8300H || TARGET_H8300S)
3582 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3583 && REGNO (operands[0]) != REGNO (operands[1])"
3584 [(parallel [(set (match_dup 3)
3585 (ashift:HI (match_dup 3)
3587 (clobber (scratch:QI))])
3589 (plus:SI (mult:SI (match_dup 1)
3592 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));")
3596 [(set (match_operand:SI 0 "register_operand" "")
3597 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3598 (const_int 8388608))
3600 (clobber (match_operand:SI 2 "register_operand" ""))])]
3601 "(TARGET_H8300H || TARGET_H8300S)
3603 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3604 && REGNO (operands[0]) != REGNO (operands[1]))"
3607 (parallel [(set (match_dup 3)
3608 (ashift:HI (match_dup 3)
3610 (clobber (scratch:QI))])
3612 (plus:SI (mult:SI (match_dup 2)
3615 "operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));")
3619 (define_insn_and_split "*ashiftsi_sextqi_7"
3620 [(set (match_operand:SI 0 "register_operand" "=r")
3621 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
3623 "(TARGET_H8300H || TARGET_H8300S)"
3625 "&& reload_completed"
3626 [(parallel [(set (match_dup 2)
3627 (ashift:HI (match_dup 2)
3629 (clobber (scratch:QI))])
3631 (sign_extend:SI (match_dup 2)))
3632 (parallel [(set (match_dup 0)
3633 (ashiftrt:SI (match_dup 0)
3635 (clobber (scratch:QI))])]
3636 "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
3638 ;; Storing a part of HImode to QImode.
3641 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3642 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3646 [(set_attr "cc" "set_znv")
3647 (set_attr "length" "8")])
3649 ;; Storing a part of SImode to QImode.
3652 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3653 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3657 [(set_attr "cc" "set_znv")
3658 (set_attr "length" "8")])
3661 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3662 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3664 (clobber (match_scratch:SI 2 "=&r"))]
3665 "TARGET_H8300H || TARGET_H8300S"
3666 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
3667 [(set_attr "cc" "set_znv")
3668 (set_attr "length" "10")])
3671 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
3672 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3674 (clobber (match_scratch:SI 2 "=&r"))]
3675 "TARGET_H8300H || TARGET_H8300S"
3676 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
3677 [(set_attr "cc" "set_znv")
3678 (set_attr "length" "10")])
3680 (define_insn_and_split ""
3682 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3686 (label_ref (match_operand 1 "" ""))
3694 (if_then_else (ge (cc0)
3696 (label_ref (match_dup 1))
3700 (define_insn_and_split ""
3702 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
3706 (label_ref (match_operand 1 "" ""))
3714 (if_then_else (lt (cc0)
3716 (label_ref (match_dup 1))
3720 ;; -----------------------------------------------------------------
3721 ;; PEEPHOLE PATTERNS
3722 ;; -----------------------------------------------------------------
3724 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3728 [(set (match_operand:HI 0 "register_operand" "")
3729 (lshiftrt:HI (match_dup 0)
3730 (match_operand:HI 1 "const_int_operand" "")))
3731 (clobber (match_operand:HI 2 "" ""))])
3733 (and:HI (match_dup 0)
3734 (match_operand:HI 3 "const_int_operand" "")))]
3735 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3737 (and:HI (match_dup 0)
3741 (lshiftrt:HI (match_dup 0)
3743 (clobber (match_dup 2))])]
3746 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3750 [(set (match_operand:HI 0 "register_operand" "")
3751 (ashift:HI (match_dup 0)
3752 (match_operand:HI 1 "const_int_operand" "")))
3753 (clobber (match_operand:HI 2 "" ""))])
3755 (and:HI (match_dup 0)
3756 (match_operand:HI 3 "const_int_operand" "")))]
3757 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3759 (and:HI (match_dup 0)
3763 (ashift:HI (match_dup 0)
3765 (clobber (match_dup 2))])]
3768 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
3772 [(set (match_operand:SI 0 "register_operand" "")
3773 (lshiftrt:SI (match_dup 0)
3774 (match_operand:SI 1 "const_int_operand" "")))
3775 (clobber (match_operand:SI 2 "" ""))])
3777 (and:SI (match_dup 0)
3778 (match_operand:SI 3 "const_int_operand" "")))]
3779 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
3781 (and:SI (match_dup 0)
3785 (lshiftrt:SI (match_dup 0)
3787 (clobber (match_dup 2))])]
3790 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
3794 [(set (match_operand:SI 0 "register_operand" "")
3795 (ashift:SI (match_dup 0)
3796 (match_operand:SI 1 "const_int_operand" "")))
3797 (clobber (match_operand:SI 2 "" ""))])
3799 (and:SI (match_dup 0)
3800 (match_operand:SI 3 "const_int_operand" "")))]
3801 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
3803 (and:SI (match_dup 0)
3807 (ashift:SI (match_dup 0)
3809 (clobber (match_dup 2))])]
3812 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
3816 [(set (match_operand:SI 0 "register_operand" "")
3817 (lshiftrt:SI (match_dup 0)
3818 (match_operand:SI 1 "const_int_operand" "")))
3819 (clobber (match_operand:SI 2 "" ""))])
3821 (and:SI (match_dup 0)
3822 (match_operand:SI 3 "const_int_operand" "")))]
3823 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
3825 (and:SI (match_dup 0)
3829 (lshiftrt:SI (match_dup 0)
3831 (clobber (match_dup 2))])]
3834 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
3838 [(set (match_operand:SI 0 "register_operand" "")
3839 (ashift:SI (match_dup 0)
3840 (match_operand:SI 1 "const_int_operand" "")))
3841 (clobber (match_operand:SI 2 "" ""))])
3843 (and:SI (match_dup 0)
3844 (match_operand:SI 3 "const_int_operand" "")))]
3845 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
3847 (and:SI (match_dup 0)
3851 (ashift:SI (match_dup 0)
3853 (clobber (match_dup 2))])]
3856 ;; Convert a QImode push into an SImode push so that the
3857 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3860 [(parallel [(set (reg:SI SP_REG)
3861 (plus:SI (reg:SI SP_REG) (const_int -4)))
3862 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
3863 (match_operand:QI 0 "register_operand" ""))])]
3864 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3865 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3867 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3870 [(parallel [(set (reg:HI SP_REG)
3871 (plus:HI (reg:HI SP_REG) (const_int -4)))
3872 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
3873 (match_operand:QI 0 "register_operand" ""))])]
3874 "TARGET_H8300S && TARGET_NORMAL_MODE"
3875 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3877 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3879 ;; Convert a HImode push into an SImode push so that the
3880 ;; define_peephole2 below can cram multiple pushes into one stm.l.
3883 [(parallel [(set (reg:SI SP_REG)
3884 (plus:SI (reg:SI SP_REG) (const_int -4)))
3885 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
3886 (match_operand:HI 0 "register_operand" ""))])]
3887 "TARGET_H8300S && !TARGET_NORMAL_MODE"
3888 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3890 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3893 [(parallel [(set (reg:HI SP_REG)
3894 (plus:HI (reg:HI SP_REG) (const_int -4)))
3895 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
3896 (match_operand:HI 0 "register_operand" ""))])]
3897 "TARGET_H8300S && TARGET_NORMAL_MODE"
3898 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3900 "operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
3902 ;; Cram four pushes into stm.l.
3905 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3906 (match_operand:SI 0 "register_operand" ""))
3907 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3908 (match_operand:SI 1 "register_operand" ""))
3909 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3910 (match_operand:SI 2 "register_operand" ""))
3911 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3912 (match_operand:SI 3 "register_operand" ""))]
3913 "TARGET_H8300S && !TARGET_NORMAL_MODE
3914 && REGNO (operands[0]) == 0
3915 && REGNO (operands[1]) == 1
3916 && REGNO (operands[2]) == 2
3917 && REGNO (operands[3]) == 3"
3918 [(parallel [(set (reg:SI SP_REG)
3919 (plus:SI (reg:SI SP_REG)
3921 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3923 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3925 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3927 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
3932 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3933 (match_operand:SI 0 "register_operand" ""))
3934 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3935 (match_operand:SI 1 "register_operand" ""))
3936 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3937 (match_operand:SI 2 "register_operand" ""))
3938 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3939 (match_operand:SI 3 "register_operand" ""))]
3940 "TARGET_H8300S && TARGET_NORMAL_MODE
3941 && REGNO (operands[0]) == 0
3942 && REGNO (operands[1]) == 1
3943 && REGNO (operands[2]) == 2
3944 && REGNO (operands[3]) == 3"
3945 [(parallel [(set (reg:HI SP_REG)
3946 (plus:HI (reg:HI SP_REG)
3948 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
3950 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
3952 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
3954 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
3958 ;; Cram three pushes into stm.l.
3961 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3962 (match_operand:SI 0 "register_operand" ""))
3963 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3964 (match_operand:SI 1 "register_operand" ""))
3965 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
3966 (match_operand:SI 2 "register_operand" ""))]
3967 "TARGET_H8300S && !TARGET_NORMAL_MODE
3968 && ((REGNO (operands[0]) == 0
3969 && REGNO (operands[1]) == 1
3970 && REGNO (operands[2]) == 2)
3971 || (REGNO (operands[0]) == 4
3972 && REGNO (operands[1]) == 5
3973 && REGNO (operands[2]) == 6))"
3974 [(parallel [(set (reg:SI SP_REG)
3975 (plus:SI (reg:SI SP_REG)
3977 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
3979 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
3981 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
3986 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3987 (match_operand:SI 0 "register_operand" ""))
3988 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3989 (match_operand:SI 1 "register_operand" ""))
3990 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
3991 (match_operand:SI 2 "register_operand" ""))]
3992 "TARGET_H8300S && TARGET_NORMAL_MODE
3993 && ((REGNO (operands[0]) == 0
3994 && REGNO (operands[1]) == 1
3995 && REGNO (operands[2]) == 2)
3996 || (REGNO (operands[0]) == 4
3997 && REGNO (operands[1]) == 5
3998 && REGNO (operands[2]) == 6))"
3999 [(parallel [(set (reg:HI SP_REG)
4000 (plus:HI (reg:HI SP_REG)
4002 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4004 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4006 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4010 ;; Cram two pushes into stm.l.
4013 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4014 (match_operand:SI 0 "register_operand" ""))
4015 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4016 (match_operand:SI 1 "register_operand" ""))]
4017 "TARGET_H8300S && !TARGET_NORMAL_MODE
4018 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4019 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4020 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4021 [(parallel [(set (reg:SI SP_REG)
4022 (plus:SI (reg:SI SP_REG)
4024 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4026 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4031 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4032 (match_operand:SI 0 "register_operand" ""))
4033 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4034 (match_operand:SI 1 "register_operand" ""))]
4035 "TARGET_H8300S && TARGET_NORMAL_MODE
4036 && ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1)
4037 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3)
4038 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5))"
4039 [(parallel [(set (reg:HI SP_REG)
4040 (plus:HI (reg:HI SP_REG)
4042 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4044 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4051 ;; add.w r7,r0 (6 bytes)
4056 ;; adds #2,r0 (4 bytes)
4059 [(set (match_operand:HI 0 "register_operand" "")
4060 (match_operand:HI 1 "const_int_operand" ""))
4062 (plus:HI (match_dup 0)
4063 (match_operand:HI 2 "register_operand" "")))]
4064 "REG_P (operands[0]) && REG_P (operands[2])
4065 && REGNO (operands[0]) != REGNO (operands[2])
4066 && (CONST_OK_FOR_J (INTVAL (operands[1]))
4067 || CONST_OK_FOR_L (INTVAL (operands[1]))
4068 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4072 (plus:HI (match_dup 0)
4080 ;; add.l er7,er0 (6 bytes)
4085 ;; adds #4,er0 (4 bytes)
4088 [(set (match_operand:SI 0 "register_operand" "")
4089 (match_operand:SI 1 "const_int_operand" ""))
4091 (plus:SI (match_dup 0)
4092 (match_operand:SI 2 "register_operand" "")))]
4093 "(TARGET_H8300H || TARGET_H8300S)
4094 && REG_P (operands[0]) && REG_P (operands[2])
4095 && REGNO (operands[0]) != REGNO (operands[2])
4096 && (CONST_OK_FOR_L (INTVAL (operands[1]))
4097 || CONST_OK_FOR_N (INTVAL (operands[1])))"
4101 (plus:SI (match_dup 0)
4108 ;; add.l #10,er0 (takes 8 bytes)
4114 ;; add.l er7,er0 (takes 6 bytes)
4117 [(set (match_operand:SI 0 "register_operand" "")
4118 (match_operand:SI 1 "register_operand" ""))
4120 (plus:SI (match_dup 0)
4121 (match_operand:SI 2 "const_int_operand" "")))]
4122 "(TARGET_H8300H || TARGET_H8300S)
4123 && REG_P (operands[0]) && REG_P (operands[1])
4124 && REGNO (operands[0]) != REGNO (operands[1])
4125 && !CONST_OK_FOR_L (INTVAL (operands[2]))
4126 && !CONST_OK_FOR_N (INTVAL (operands[2]))
4127 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4128 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4129 || INTVAL (operands[2]) == 0xffff
4130 || INTVAL (operands[2]) == 0xfffe)"
4134 (plus:SI (match_dup 0)
4150 [(set (match_operand:HI 0 "register_operand" "")
4151 (plus:HI (match_dup 0)
4152 (match_operand 1 "incdec_operand" "")))
4156 (if_then_else (match_operator 3 "eqne_operator"
4157 [(cc0) (const_int 0)])
4158 (label_ref (match_operand 2 "" ""))
4160 "TARGET_H8300H || TARGET_H8300S"
4161 [(set (match_operand:HI 0 "register_operand" "")
4162 (unspec:HI [(match_dup 0)
4168 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4169 (label_ref (match_dup 2))
4173 ;; The SImode version of the previous pattern.
4176 [(set (match_operand:SI 0 "register_operand" "")
4177 (plus:SI (match_dup 0)
4178 (match_operand 1 "incdec_operand" "")))
4182 (if_then_else (match_operator 3 "eqne_operator"
4183 [(cc0) (const_int 0)])
4184 (label_ref (match_operand 2 "" ""))
4186 "TARGET_H8300H || TARGET_H8300S"
4187 [(set (match_operand:SI 0 "register_operand" "")
4188 (unspec:SI [(match_dup 0)
4194 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4195 (label_ref (match_dup 2))
4200 [(parallel [(set (cc0)
4201 (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4204 (clobber (scratch:QI))])
4206 (if_then_else (match_operator 1 "eqne_operator"
4207 [(cc0) (const_int 0)])
4208 (label_ref (match_operand 2 "" ""))
4210 "(TARGET_H8300H || TARGET_H8300S)"
4214 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4215 (label_ref (match_dup 2))
4217 "operands[3] = ((GET_CODE (operands[1]) == EQ)
4218 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4219 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));")
4221 ;; The next three peephole2's will try to transform
4223 ;; mov.b A,r0l (or mov.l A,er0)
4230 ;; and.b #CST,r0l (if CST is not 255)
4233 [(set (match_operand:QI 0 "register_operand" "")
4234 (match_operand:QI 1 "general_operand" ""))
4235 (set (match_operand:SI 2 "register_operand" "")
4236 (and:SI (match_dup 2)
4238 "(TARGET_H8300H || TARGET_H8300S)
4239 && !reg_overlap_mentioned_p (operands[2], operands[1])
4240 && REGNO (operands[0]) == REGNO (operands[2])"
4243 (set (strict_low_part (match_dup 0))
4248 [(set (match_operand:SI 0 "register_operand" "")
4249 (match_operand:SI 1 "general_operand" ""))
4251 (and:SI (match_dup 0)
4253 "(TARGET_H8300H || TARGET_H8300S)
4254 && !reg_overlap_mentioned_p (operands[0], operands[1])
4255 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4258 (set (strict_low_part (match_dup 2))
4260 "operands[2] = gen_lowpart (QImode, operands[0]);
4261 operands[3] = gen_lowpart (QImode, operands[1]);")
4264 [(set (match_operand 0 "register_operand" "")
4265 (match_operand 1 "general_operand" ""))
4266 (set (match_operand:SI 2 "register_operand" "")
4267 (and:SI (match_dup 2)
4268 (match_operand:SI 3 "const_int_qi_operand" "")))]
4269 "(TARGET_H8300H || TARGET_H8300S)
4270 && (GET_MODE (operands[0]) == QImode
4271 || GET_MODE (operands[0]) == HImode
4272 || GET_MODE (operands[0]) == SImode)
4273 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4274 && REGNO (operands[0]) == REGNO (operands[2])
4275 && !reg_overlap_mentioned_p (operands[2], operands[1])
4276 && !(GET_MODE (operands[1]) != QImode
4277 && GET_CODE (operands[1]) == MEM
4278 && MEM_VOLATILE_P (operands[1]))"
4281 (set (strict_low_part (match_dup 4))
4284 (and:SI (match_dup 2)
4286 "operands[4] = gen_lowpart (QImode, operands[0]);
4287 operands[5] = gen_lowpart (QImode, operands[1]);
4288 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));")
4291 [(set (match_operand:SI 0 "register_operand" "")
4292 (match_operand:SI 1 "register_operand" ""))
4294 (and:SI (match_dup 0)
4295 (const_int 65280)))]
4296 "(TARGET_H8300H || TARGET_H8300S)
4297 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4300 (set (zero_extract:SI (match_dup 0)
4303 (lshiftrt:SI (match_dup 1)
4307 ;; If a load of mem:SI is followed by an AND that turns off the upper
4308 ;; half, then we can load mem:HI instead.
4311 [(set (match_operand:SI 0 "register_operand" "")
4312 (match_operand:SI 1 "memory_operand" ""))
4314 (and:SI (match_dup 0)
4315 (match_operand:SI 2 "const_int_operand" "")))]
4316 "(TARGET_H8300H || TARGET_H8300S)
4317 && !MEM_VOLATILE_P (operands[1])
4318 && (INTVAL (operands[2]) & ~0xffff) == 0
4319 && INTVAL (operands[2]) != 255"
4323 (and:SI (match_dup 0)
4325 "operands[3] = gen_lowpart (HImode, operands[0]);
4326 operands[4] = gen_lowpart (HImode, operands[1]);")
4328 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4329 ;; the equivalent with shorter sequences. Here is the summary. Cases
4330 ;; are grouped for each define_peephole2.
4332 ;; reg const_int use insn
4333 ;; --------------------------------------------------------
4334 ;; dead -2 eq/ne inc.l
4335 ;; dead -1 eq/ne inc.l
4336 ;; dead 1 eq/ne dec.l
4337 ;; dead 2 eq/ne dec.l
4339 ;; dead 1 geu/ltu shar.l
4340 ;; dead 3 (H8S) geu/ltu shar.l
4342 ;; ---- 255 geu/ltu mov.b
4356 (compare (match_operand:HI 0 "register_operand" "")
4357 (match_operand:HI 1 "incdec_operand" "")))
4359 (if_then_else (match_operator 3 "eqne_operator"
4360 [(cc0) (const_int 0)])
4361 (label_ref (match_operand 2 "" ""))
4363 "(TARGET_H8300H || TARGET_H8300S)
4364 && peep2_reg_dead_p (1, operands[0])"
4366 (unspec:HI [(match_dup 0)
4372 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4373 (label_ref (match_dup 2))
4375 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4389 (compare (match_operand:HI 0 "register_operand" "")
4390 (match_operand:HI 1 "const_int_operand" "")))
4392 (if_then_else (match_operator 2 "gtle_operator"
4393 [(cc0) (const_int 0)])
4394 (label_ref (match_operand 3 "" ""))
4396 "(TARGET_H8300H || TARGET_H8300S)
4397 && peep2_reg_dead_p (1, operands[0])
4398 && (INTVAL (operands[1]) == 1
4399 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4400 [(parallel [(set (match_dup 0)
4401 (ashiftrt:HI (match_dup 0)
4403 (clobber (scratch:QI))])
4407 (if_then_else (match_dup 4)
4408 (label_ref (match_dup 3))
4410 "switch (GET_CODE (operands[2]))
4413 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4416 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4419 operands[4] = operands[2];
4422 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4436 (compare (match_operand:HI 0 "register_operand" "")
4439 (if_then_else (match_operator 1 "gtle_operator"
4440 [(cc0) (const_int 0)])
4441 (label_ref (match_operand 2 "" ""))
4443 "TARGET_H8300H || TARGET_H8300S"
4445 (and:HI (match_dup 0)
4448 (if_then_else (match_dup 3)
4449 (label_ref (match_dup 2))
4451 "switch (GET_CODE (operands[1]))
4454 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4457 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4460 operands[3] = operands[1];
4464 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4465 ;; the equivalent with shorter sequences. Here is the summary. Cases
4466 ;; are grouped for each define_peephole2.
4468 ;; reg const_int use insn
4469 ;; --------------------------------------------------------
4470 ;; live -2 eq/ne copy and inc.l
4471 ;; live -1 eq/ne copy and inc.l
4472 ;; live 1 eq/ne copy and dec.l
4473 ;; live 2 eq/ne copy and dec.l
4475 ;; dead -2 eq/ne inc.l
4476 ;; dead -1 eq/ne inc.l
4477 ;; dead 1 eq/ne dec.l
4478 ;; dead 2 eq/ne dec.l
4480 ;; dead -131072 eq/ne inc.w and test
4481 ;; dead -65536 eq/ne inc.w and test
4482 ;; dead 65536 eq/ne dec.w and test
4483 ;; dead 131072 eq/ne dec.w and test
4485 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4486 ;; dead 0x0000??00 eq/ne xor.b and test
4487 ;; dead 0x0000ffff eq/ne not.w and test
4489 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4490 ;; dead 0xffff??ff eq/ne xor.b and not.l
4491 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4492 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4494 ;; live 1 geu/ltu copy and shar.l
4495 ;; live 3 (H8S) geu/ltu copy and shar.l
4497 ;; dead 1 geu/ltu shar.l
4498 ;; dead 3 (H8S) geu/ltu shar.l
4500 ;; dead 3 (H8/300H) geu/ltu and.b and test
4501 ;; dead 7 geu/ltu and.b and test
4502 ;; dead 15 geu/ltu and.b and test
4503 ;; dead 31 geu/ltu and.b and test
4504 ;; dead 63 geu/ltu and.b and test
4505 ;; dead 127 geu/ltu and.b and test
4506 ;; dead 255 geu/ltu and.b and test
4508 ;; ---- 65535 geu/ltu mov.w
4510 ;; For a small constant, it is cheaper to actually do the subtraction
4511 ;; and then test the register.
4515 (compare (match_operand:SI 0 "register_operand" "")
4516 (match_operand:SI 1 "incdec_operand" "")))
4518 (if_then_else (match_operator 3 "eqne_operator"
4519 [(cc0) (const_int 0)])
4520 (label_ref (match_operand 2 "" ""))
4522 "(TARGET_H8300H || TARGET_H8300S)
4523 && peep2_reg_dead_p (1, operands[0])"
4525 (unspec:SI [(match_dup 0)
4531 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4532 (label_ref (match_dup 2))
4534 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4538 (compare (match_operand:SI 0 "register_operand" "")
4539 (match_operand:SI 1 "const_int_operand" "")))
4541 (if_then_else (match_operator 3 "eqne_operator"
4542 [(cc0) (const_int 0)])
4543 (label_ref (match_operand 2 "" ""))
4545 "(TARGET_H8300H || TARGET_H8300S)
4546 && peep2_reg_dead_p (1, operands[0])
4547 && (INTVAL (operands[1]) == -131072
4548 || INTVAL (operands[1]) == -65536
4549 || INTVAL (operands[1]) == 65536
4550 || INTVAL (operands[1]) == 131072)"
4552 (plus:SI (match_dup 0)
4557 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4558 (label_ref (match_dup 2))
4560 "operands[4] = GEN_INT (- INTVAL (operands[1]));")
4562 ;; For certain (in)equality comparisons against a constant, we can
4563 ;; XOR the register with the constant, and test the register against
4568 (compare (match_operand:SI 0 "register_operand" "")
4569 (match_operand:SI 1 "const_int_operand" "")))
4571 (if_then_else (match_operator 3 "eqne_operator"
4572 [(cc0) (const_int 0)])
4573 (label_ref (match_operand 2 "" ""))
4575 "(TARGET_H8300H || TARGET_H8300S)
4576 && peep2_reg_dead_p (1, operands[0])
4577 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
4578 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
4579 || INTVAL (operands[1]) == 0x0000ffff)
4580 && INTVAL (operands[1]) != 1
4581 && INTVAL (operands[1]) != 2"
4583 (xor:SI (match_dup 0)
4588 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4589 (label_ref (match_dup 2))
4595 (compare (match_operand:SI 0 "register_operand" "")
4596 (match_operand:SI 1 "const_int_operand" "")))
4598 (if_then_else (match_operator 3 "eqne_operator"
4599 [(cc0) (const_int 0)])
4600 (label_ref (match_operand 2 "" ""))
4602 "(TARGET_H8300H || TARGET_H8300S)
4603 && peep2_reg_dead_p (1, operands[0])
4604 && ((INTVAL (operands[1]) | 0x00ff) == -1
4605 || (INTVAL (operands[1]) | 0xff00) == -1)
4606 && INTVAL (operands[1]) != -1
4607 && INTVAL (operands[1]) != -2"
4609 (xor:SI (match_dup 0)
4612 (not:SI (match_dup 0)))
4616 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4617 (label_ref (match_dup 2))
4619 "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
4623 (compare (match_operand:SI 0 "register_operand" "")
4624 (match_operand:SI 1 "const_int_operand" "")))
4626 (if_then_else (match_operator 3 "eqne_operator"
4627 [(cc0) (const_int 0)])
4628 (label_ref (match_operand 2 "" ""))
4630 "(TARGET_H8300H || TARGET_H8300S)
4631 && peep2_reg_dead_p (1, operands[0])
4632 && (INTVAL (operands[1]) == -2147483647 - 1
4633 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
4635 (rotate:SI (match_dup 0)
4638 (unspec:SI [(match_dup 0)
4644 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4645 (label_ref (match_dup 2))
4647 "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);")
4660 ;; We avoid this transformation if we see more than one copy of the
4661 ;; same compare insn immediately before this one.
4664 [(match_scratch:SI 4 "r")
4666 (compare (match_operand:SI 0 "register_operand" "")
4667 (match_operand:SI 1 "const_int_operand" "")))
4669 (if_then_else (match_operator 2 "gtle_operator"
4670 [(cc0) (const_int 0)])
4671 (label_ref (match_operand 3 "" ""))
4673 "(TARGET_H8300H || TARGET_H8300S)
4674 && !peep2_reg_dead_p (1, operands[0])
4675 && (INTVAL (operands[1]) == 1
4676 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
4677 && !same_cmp_preceding_p (insn)"
4680 (parallel [(set (match_dup 4)
4681 (ashiftrt:SI (match_dup 4)
4683 (clobber (scratch:QI))])
4687 (if_then_else (match_dup 5)
4688 (label_ref (match_dup 3))
4690 "switch (GET_CODE (operands[2]))
4693 operands[5] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4696 operands[5] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4699 operands[5] = operands[2];
4702 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4716 (compare (match_operand:SI 0 "register_operand" "")
4717 (match_operand:SI 1 "const_int_operand" "")))
4719 (if_then_else (match_operator 2 "gtle_operator"
4720 [(cc0) (const_int 0)])
4721 (label_ref (match_operand 3 "" ""))
4723 "(TARGET_H8300H || TARGET_H8300S)
4724 && peep2_reg_dead_p (1, operands[0])
4725 && (INTVAL (operands[1]) == 1
4726 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4727 [(parallel [(set (match_dup 0)
4728 (ashiftrt:SI (match_dup 0)
4730 (clobber (scratch:QI))])
4734 (if_then_else (match_dup 4)
4735 (label_ref (match_dup 3))
4737 "switch (GET_CODE (operands[2]))
4740 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4743 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4746 operands[4] = operands[2];
4749 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));")
4764 (compare (match_operand:SI 0 "register_operand" "")
4765 (match_operand:SI 1 "const_int_operand" "")))
4767 (if_then_else (match_operator 2 "gtle_operator"
4768 [(cc0) (const_int 0)])
4769 (label_ref (match_operand 3 "" ""))
4771 "(TARGET_H8300H || TARGET_H8300S)
4772 && peep2_reg_dead_p (1, operands[0])
4773 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
4774 || INTVAL (operands[1]) == 7
4775 || INTVAL (operands[1]) == 15
4776 || INTVAL (operands[1]) == 31
4777 || INTVAL (operands[1]) == 63
4778 || INTVAL (operands[1]) == 127
4779 || INTVAL (operands[1]) == 255)"
4781 (and:SI (match_dup 0)
4786 (if_then_else (match_dup 4)
4787 (label_ref (match_dup 3))
4789 "switch (GET_CODE (operands[2]))
4792 operands[4] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4795 operands[4] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4798 operands[4] = operands[2];
4801 operands[5] = GEN_INT (~INTVAL (operands[1]));")
4803 ;; Transform A <= 65535 to (A & 0xffff0000) == 0.
4807 (compare (match_operand:SI 0 "register_operand" "")
4810 (if_then_else (match_operator 1 "gtle_operator"
4811 [(cc0) (const_int 0)])
4812 (label_ref (match_operand 2 "" ""))
4814 "TARGET_H8300H || TARGET_H8300S"
4816 (and:SI (match_dup 0)
4817 (const_int -65536)))
4819 (if_then_else (match_dup 3)
4820 (label_ref (match_dup 2))
4822 "switch (GET_CODE (operands[1]))
4825 operands[3] = gen_rtx_NE (VOIDmode, cc0_rtx, const0_rtx);
4828 operands[3] = gen_rtx_EQ (VOIDmode, cc0_rtx, const0_rtx);
4831 operands[3] = operands[1];
4835 ;; For constants like -1, -2, 1, 2, it is still cheaper to make a copy
4836 ;; of the register being tested, do the subtraction on the copy, and
4837 ;; then test the copy. We avoid this transformation if we see more
4838 ;; than one copy of the same compare insn.
4841 [(match_scratch:SI 4 "r")
4843 (compare (match_operand:SI 0 "register_operand" "")
4844 (match_operand:SI 1 "incdec_operand" "")))
4846 (if_then_else (match_operator 3 "eqne_operator"
4847 [(cc0) (const_int 0)])
4848 (label_ref (match_operand 2 "" ""))
4850 "(TARGET_H8300H || TARGET_H8300S)
4851 && !peep2_reg_dead_p (1, operands[0])
4852 && !same_cmp_following_p (insn)"
4856 (unspec:SI [(match_dup 4)
4862 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4863 (label_ref (match_dup 2))
4865 "operands[5] = GEN_INT (- INTVAL (operands[1]));")
4867 ;; Narrow the mode of testing if possible.
4870 [(set (match_operand:HI 0 "register_operand" "")
4871 (and:HI (match_dup 0)
4872 (match_operand:HI 1 "const_int_qi_operand" "")))
4876 (if_then_else (match_operator 3 "eqne_operator"
4877 [(cc0) (const_int 0)])
4878 (label_ref (match_operand 2 "" ""))
4880 "peep2_reg_dead_p (2, operands[0])"
4882 (and:QI (match_dup 4)
4887 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4888 (label_ref (match_dup 2))
4890 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4891 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4894 [(set (match_operand:SI 0 "register_operand" "")
4895 (and:SI (match_dup 0)
4896 (match_operand:SI 1 "const_int_qi_operand" "")))
4900 (if_then_else (match_operator 3 "eqne_operator"
4901 [(cc0) (const_int 0)])
4902 (label_ref (match_operand 2 "" ""))
4904 "peep2_reg_dead_p (2, operands[0])"
4906 (and:QI (match_dup 4)
4911 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4912 (label_ref (match_dup 2))
4914 "operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
4915 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);")
4918 [(set (match_operand:SI 0 "register_operand" "")
4919 (and:SI (match_dup 0)
4920 (match_operand:SI 1 "const_int_hi_operand" "")))
4924 (if_then_else (match_operator 3 "eqne_operator"
4925 [(cc0) (const_int 0)])
4926 (label_ref (match_operand 2 "" ""))
4928 "peep2_reg_dead_p (2, operands[0])"
4930 (and:HI (match_dup 4)
4935 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4936 (label_ref (match_dup 2))
4938 "operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
4939 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);")
4942 [(set (match_operand:SI 0 "register_operand" "")
4943 (and:SI (match_dup 0)
4944 (match_operand:SI 1 "const_int_qi_operand" "")))
4946 (xor:SI (match_dup 0)
4947 (match_operand:SI 2 "const_int_qi_operand" "")))
4951 (if_then_else (match_operator 4 "eqne_operator"
4952 [(cc0) (const_int 0)])
4953 (label_ref (match_operand 3 "" ""))
4955 "peep2_reg_dead_p (3, operands[0])
4956 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
4958 (and:QI (match_dup 5)
4961 (xor:QI (match_dup 5)
4966 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
4967 (label_ref (match_dup 3))
4969 "operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
4970 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
4971 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);")
4973 ;; These triggers right at the end of allocation of locals in the
4974 ;; prologue. The only profitable cases are when we have stack
4975 ;; adjustment of -4 or -12. That of -8 won't happen because it is
4976 ;; always split into two consecutive subtractions of -4.
4979 [(set (reg:SI SP_REG)
4980 (plus:SI (reg:SI SP_REG)
4982 (set (mem:SI (reg:SI SP_REG))
4983 (match_operand:SI 0 "register_operand" ""))]
4984 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4985 && REGNO (operands[0]) != SP_REG"
4986 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4991 [(set (reg:SI SP_REG)
4992 (plus:SI (reg:SI SP_REG)
4994 (set (mem:SI (reg:SI SP_REG))
4995 (match_operand:SI 0 "register_operand" ""))]
4996 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
4997 && REGNO (operands[0]) != SP_REG"
4998 [(set (reg:SI SP_REG)
4999 (plus:SI (reg:SI SP_REG)
5001 (set (reg:SI SP_REG)
5002 (plus:SI (reg:SI SP_REG)
5004 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))