1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992-2018 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; We compute exact length on each instruction for most of the time.
24 ;; In some case, most notably bit operations that may involve memory
25 ;; operands, the lengths in this file are "worst case".
27 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
28 ;; registers. Right now GCC doesn't expose the "e" half to the
29 ;; compiler, so using add/subs for addhi and subhi is safe. Long
30 ;; term, we want to expose the "e" half to the compiler (gives us 8
31 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; There's currently no way to have an insv/extzv expander for the H8/300H
35 ;; because word_mode is different for the H8/300 and H8/300H.
37 ;; Shifts/rotates by small constants should be handled by special
38 ;; patterns so we get the length and cc status correct.
40 ;; Bitfield operations no longer accept memory operands. We need
41 ;; to add variants which operate on memory back to the MD.
43 ;; ??? Implement remaining bit ops available on the h8300
45 ;; ----------------------------------------------------------------------
47 ;; ----------------------------------------------------------------------
70 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 (define_attr "cpu" "h8300,h8300h"
75 (const (symbol_ref "cpu_type")))
77 (define_attr "type" "branch,arith,bitbranch,call"
78 (const_string "arith"))
80 (define_attr "length_table" "none,add,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
81 (const_string "none"))
83 ;; The size of instructions in bytes.
85 (define_attr "length" ""
86 (cond [(eq_attr "type" "branch")
87 ;; In a forward delayed branch, (pc) represents the end of the
88 ;; delay sequence, not the end of the branch itself.
89 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (le (plus (minus (match_dup 0) (pc))
92 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (if_then_else (and (eq_attr "cpu" "h8300h")
96 (and (ge (minus (pc) (match_dup 0))
98 (le (minus (pc) (match_dup 0))
102 (eq_attr "type" "bitbranch")
103 (if_then_else (and (ge (minus (match_dup 0) (pc))
105 (le (minus (match_dup 0) (pc))
107 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
109 (if_then_else (and (eq_attr "cpu" "h8300h")
110 (and (ge (minus (pc) (match_dup 0))
112 (le (minus (pc) (match_dup 0))
114 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
116 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
118 (eq_attr "length_table" "!none")
119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
122 ;; Condition code settings.
124 ;; none - insn does not affect cc
125 ;; none_0hit - insn does not affect cc but it does modify operand 0
126 ;; This attribute is used to keep track of when operand 0 changes.
127 ;; See the description of NOTICE_UPDATE_CC for more info.
128 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
129 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
130 ;; compare - compare instruction
131 ;; clobber - value of cc is unknown
133 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
134 (const_string "clobber"))
136 ;; Type of delay slot. NONE means the instruction has no delay slot.
137 ;; JUMP means it is an unconditional jump that (if short enough)
138 ;; could be implemented using bra/s.
140 (define_attr "delay_slot" "none,jump"
141 (const_string "none"))
143 ;; "yes" if the instruction can be put into a delay slot. It's not
144 ;; entirely clear that jsr is not valid in delay slots, but it
145 ;; definitely doesn't have the effect of causing the called function
146 ;; to return to the target of the delayed branch.
148 (define_attr "can_delay" "no,yes"
149 (cond [(eq_attr "type" "branch,bitbranch,call")
151 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
153 (const_string "yes")))
155 ;; Only allow jumps to have a delay slot if we think they might
156 ;; be short enough. This is just an optimization: we don't know
157 ;; for certain whether they will be or not.
159 (define_delay (and (eq_attr "delay_slot" "jump")
160 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
161 [(eq_attr "can_delay" "yes")
165 ;; Provide the maximum length of an assembly instruction in an asm
166 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
168 (define_asm_attributes
169 [(set (attr "length")
170 (cond [(match_test "TARGET_H8300") (const_int 4)
171 (match_test "TARGET_H8300H") (const_int 10)
172 (match_test "TARGET_H8300S") (const_int 10)]
175 (include "predicates.md")
176 (include "constraints.md")
178 ;; ----------------------------------------------------------------------
180 ;; ----------------------------------------------------------------------
182 ;; This mode iterator allows :P to be used for patterns that operate on
183 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
185 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
187 (define_mode_iterator QHI [QI HI])
189 (define_mode_iterator HSI [HI SI])
191 (define_mode_iterator QHSI [QI HI SI])
193 (define_mode_iterator QHSIF [QI HI SI SF])
195 (define_code_iterator shifts [ashift ashiftrt lshiftrt])
197 (define_code_iterator ors [ior xor])
199 ;; ----------------------------------------------------------------------
201 ;; ----------------------------------------------------------------------
205 (define_insn "*movqi_h8nosx"
206 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
207 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
208 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
209 && h8300_move_ok (operands[0], operands[1])"
217 [(set (attr "length")
218 (symbol_ref "compute_mov_length (operands)"))
219 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
221 (define_insn "*movqi_h8sx"
222 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
223 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
228 [(set_attr "length_table" "mov_imm4,movb")
229 (set_attr "cc" "set_znv")])
231 (define_expand "mov<mode>"
232 [(set (match_operand:QHSIF 0 "general_operand_dst" "")
233 (match_operand:QHSIF 1 "general_operand_src" ""))]
236 enum machine_mode mode = <MODE>mode;
237 if (TARGET_H8300 && (mode == SImode || mode == SFmode))
239 /* The original H8/300 needs to split up 32 bit moves. */
240 if (h8300_expand_movsi (operands))
243 else if (!TARGET_H8300SX)
245 /* Other H8 chips, except the H8/SX family can only handle a
246 single memory operand, which is checked by h8300_move_ok.
248 We could perhaps have h8300_move_ok handle the H8/SX better
249 and just remove the !TARGET_H8300SX conditional. */
250 if (!h8300_move_ok (operands[0], operands[1]))
251 operands[1] = copy_to_mode_reg (mode, operand1);
255 (define_insn "movstrictqi"
256 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
257 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
262 [(set_attr "length" "2,*")
263 (set_attr "length_table" "*,movb")
264 (set_attr "cc" "set_zn,set_znv")])
268 (define_insn "*movhi_h8nosx"
269 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
270 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
271 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
272 && h8300_move_ok (operands[0], operands[1])"
280 [(set (attr "length")
281 (symbol_ref "compute_mov_length (operands)"))
282 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
284 (define_insn "*movhi_h8sx"
285 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
286 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
294 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
295 (set_attr "length" "2,2,*,*,*")
296 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
298 (define_insn "movstricthi"
299 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
300 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
306 [(set_attr "length" "2,2,*")
307 (set_attr "length_table" "*,*,movw")
308 (set_attr "cc" "set_zn,set_znv,set_znv")])
312 (define_insn "*movsi_h8300"
313 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
314 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
316 && h8300_move_ok (operands[0], operands[1])"
318 unsigned int rn = -1;
319 switch (which_alternative)
322 return "sub.w %e0,%e0\;sub.w %f0,%f0";
324 if (REGNO (operands[0]) < REGNO (operands[1]))
325 return "mov.w %e1,%e0\;mov.w %f1,%f0";
327 return "mov.w %f1,%f0\;mov.w %e1,%e0";
329 /* Make sure we don't trample the register we index with. */
330 if (GET_CODE (operands[1]) == MEM)
332 rtx inside = XEXP (operands[1], 0);
337 else if (GET_CODE (inside) == PLUS)
339 rtx lhs = XEXP (inside, 0);
340 rtx rhs = XEXP (inside, 1);
341 if (REG_P (lhs)) rn = REGNO (lhs);
342 if (REG_P (rhs)) rn = REGNO (rhs);
345 if (rn == REGNO (operands[0]))
347 /* Move the second word first. */
348 return "mov.w %f1,%f0\;mov.w %e1,%e0";
352 if (GET_CODE (operands[1]) == CONST_INT)
354 /* If either half is zero, use sub.w to clear that
356 if ((INTVAL (operands[1]) & 0xffff) == 0)
357 return "mov.w %e1,%e0\;sub.w %f0,%f0";
358 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
359 return "sub.w %e0,%e0\;mov.w %f1,%f0";
360 /* If the upper half and the lower half are the same,
361 copy one half to the other. */
362 if ((INTVAL (operands[1]) & 0xffff)
363 == ((INTVAL (operands[1]) >> 16) & 0xffff))
364 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
366 return "mov.w %e1,%e0\;mov.w %f1,%f0";
369 return "mov.w %e1,%e0\;mov.w %f1,%f0";
371 return "mov.w %f1,%T0\;mov.w %e1,%T0";
373 return "mov.w %T1,%e0\;mov.w %T1,%f0";
378 [(set (attr "length")
379 (symbol_ref "compute_mov_length (operands)"))])
381 (define_insn "*movsi_h8300hs"
382 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
383 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
384 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
385 && h8300_move_ok (operands[0], operands[1])"
387 switch (which_alternative)
390 return "sub.l %S0,%S0";
394 return "clrmac\;ldmac %1,macl";
396 return "stmac macl,%0";
398 if (GET_CODE (operands[1]) == CONST_INT)
400 int val = INTVAL (operands[1]);
402 /* Look for constants which can be made by adding an 8-bit
403 number to zero in one of the two low bytes. */
404 if (val == (val & 0xff))
406 operands[1] = GEN_INT ((char) val & 0xff);
407 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
410 if (val == (val & 0xff00))
412 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
413 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
416 /* Look for constants that can be obtained by subs, inc, and
418 switch (val & 0xffffffff)
421 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
423 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
425 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
428 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
430 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
433 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
435 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
438 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
440 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
444 return "mov.l %S1,%S0";
446 [(set (attr "length")
447 (symbol_ref "compute_mov_length (operands)"))
448 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
450 (define_insn "*movsi_h8sx"
451 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
452 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
460 clrmac\;ldmac %1,macl
462 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
463 (set_attr "length" "2,2,*,*,2,6,4")
464 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
466 (define_insn "*movsf_h8sx"
467 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
468 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
473 [(set_attr "length" "2,*")
474 (set_attr "length_table" "*,movl")
475 (set_attr "cc" "set_zn,set_znv")])
477 ;; Implement block moves using movmd. Defining movmemsi allows the full
478 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
479 ;; See h8sx_emit_movmd for details.
481 (define_expand "movmemsi"
482 [(use (match_operand:BLK 0 "memory_operand" ""))
483 (use (match_operand:BLK 1 "memory_operand" ""))
484 (use (match_operand:SI 2 "" ""))
485 (use (match_operand:SI 3 "const_int_operand" ""))]
488 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3])))
494 ;; Expander for generating movmd insns. Operand 0 is the destination
495 ;; memory region, operand 1 is the source, operand 2 is the counter
496 ;; register and operand 3 is the chunk size (1, 2 or 4).
498 (define_expand "movmd"
500 [(set (match_operand:BLK 0 "memory_operand" "")
501 (match_operand:BLK 1 "memory_operand" ""))
502 (unspec [(match_operand:HI 2 "register_operand" "")
503 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
504 (clobber (match_dup 4))
505 (clobber (match_dup 5))
510 operands[4] = copy_rtx (XEXP (operands[0], 0));
511 operands[5] = copy_rtx (XEXP (operands[1], 0));
514 ;; This is a difficult instruction to reload since operand 0 must be the
515 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
517 (define_insn "movmd_internal_<mode>"
518 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
519 (mem:BLK (match_operand:P 4 "register_operand" "1,1")))
520 (unspec [(match_operand:HI 5 "register_operand" "2,2")
521 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
522 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
523 (clobber (match_operand:P 1 "register_operand" "=f,f"))
524 (set (match_operand:HI 2 "register_operand" "=c,c")
530 [(set_attr "length" "2,14")
531 (set_attr "can_delay" "no")
532 (set_attr "cc" "none,clobber")])
534 ;; Split the above instruction if the destination register isn't er6.
535 ;; We need a sequence like:
543 ;; where <dest> is the current destination register (operand 4).
544 ;; The fourth instruction will be deleted if <dest> dies here.
547 [(set (match_operand:BLK 0 "memory_operand" "")
548 (match_operand:BLK 1 "memory_operand" ""))
549 (unspec [(match_operand:HI 2 "register_operand" "")
550 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
551 (clobber (match_operand:P 4 "register_operand" ""))
552 (clobber (match_operand:P 5 "register_operand" ""))
555 "TARGET_H8300SX && reload_completed
556 && REGNO (operands[4]) != DESTINATION_REG"
561 h8300_swap_into_er6 (XEXP (operands[0], 0));
562 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
563 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
564 h8300_swap_out_of_er6 (operands[4]);
568 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
569 ;; the final character, but movsd leaves it pointing to the character
572 (define_expand "movstr"
573 [(use (match_operand 0 "register_operand" ""))
574 (use (match_operand:BLK 1 "memory_operand" ""))
575 (use (match_operand:BLK 2 "memory_operand" ""))]
578 operands[1] = replace_equiv_address
579 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
580 operands[2] = replace_equiv_address
581 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
582 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
583 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx));
587 ;; Expander for generating a movsd instruction. Operand 0 is the
588 ;; destination string, operand 1 is the source string and operand 2
589 ;; is a scratch register.
591 (define_expand "movsd"
593 [(set (match_operand:BLK 0 "memory_operand" "")
594 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
596 (clobber (match_dup 3))
597 (clobber (match_dup 4))
598 (clobber (match_operand 2 "register_operand" ""))])]
601 operands[3] = copy_rtx (XEXP (operands[0], 0));
602 operands[4] = copy_rtx (XEXP (operands[1], 0));
605 ;; See comments above memcpy_internal().
607 (define_insn "stpcpy_internal_<mode>"
608 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
609 (unspec:BLK [(mem:BLK (match_operand:P 4 "register_operand" "1,1"))]
611 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
612 (clobber (match_operand:P 1 "register_operand" "=f,f"))
613 (clobber (match_operand:P 2 "register_operand" "=c,c"))]
616 \n1:\tmovsd\t2f\;bra\t1b\n2:
618 [(set_attr "length" "6,18")
619 (set_attr "cc" "none,clobber")])
621 ;; Split the above instruction if the destination isn't er6. This works
622 ;; in the same way as the movmd splitter.
625 [(set (match_operand:BLK 0 "memory_operand" "")
626 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
627 (clobber (match_operand:P 2 "register_operand" ""))
628 (clobber (match_operand:P 3 "register_operand" ""))
629 (clobber (match_operand:P 4 "register_operand" ""))]
630 "TARGET_H8300SX && reload_completed
631 && REGNO (operands[2]) != DESTINATION_REG"
636 h8300_swap_into_er6 (XEXP (operands[0], 0));
637 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
638 emit_insn (gen_movsd (dest, operands[1], operands[4]));
639 h8300_swap_out_of_er6 (operands[2]);
645 (define_insn "*movsf_h8300"
646 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
647 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
649 && (register_operand (operands[0], SFmode)
650 || register_operand (operands[1], SFmode))"
652 /* Copy of the movsi stuff. */
653 unsigned int rn = -1;
654 switch (which_alternative)
657 return "sub.w %e0,%e0\;sub.w %f0,%f0";
659 if (REGNO (operands[0]) < REGNO (operands[1]))
660 return "mov.w %e1,%e0\;mov.w %f1,%f0";
662 return "mov.w %f1,%f0\;mov.w %e1,%e0";
664 /* Make sure we don't trample the register we index with. */
665 if (GET_CODE (operands[1]) == MEM)
667 rtx inside = XEXP (operands[1], 0);
672 else if (GET_CODE (inside) == PLUS)
674 rtx lhs = XEXP (inside, 0);
675 rtx rhs = XEXP (inside, 1);
676 if (REG_P (lhs)) rn = REGNO (lhs);
677 if (REG_P (rhs)) rn = REGNO (rhs);
680 if (rn == REGNO (operands[0]))
681 /* Move the second word first. */
682 return "mov.w %f1,%f0\;mov.w %e1,%e0";
684 /* Move the first word first. */
685 return "mov.w %e1,%e0\;mov.w %f1,%f0";
688 return "mov.w %e1,%e0\;mov.w %f1,%f0";
690 return "mov.w %f1,%T0\;mov.w %e1,%T0";
692 return "mov.w %T1,%e0\;mov.w %T1,%f0";
697 [(set (attr "length")
698 (symbol_ref "compute_mov_length (operands)"))])
700 (define_insn "*movsf_h8300hs"
701 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
702 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
703 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
704 && (register_operand (operands[0], SFmode)
705 || register_operand (operands[1], SFmode))"
713 [(set (attr "length")
714 (symbol_ref "compute_mov_length (operands)"))
715 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
717 ;; ----------------------------------------------------------------------
719 ;; ----------------------------------------------------------------------
721 (define_insn "*pushqi1_h8300"
725 (plus:HI (reg:HI SP_REG) (const_int -2))))
726 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
729 [(set_attr "length" "2")])
731 (define_insn "*push1_h8300hs_<mode>"
735 (plus:P (reg:P SP_REG) (const_int -4))))
736 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
737 "TARGET_H8300H || TARGET_H8300S"
739 [(set_attr "length" "4")])
742 ;; ----------------------------------------------------------------------
744 ;; ----------------------------------------------------------------------
748 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
750 (match_operand 1 "const_int_operand" "n,n"))
754 [(set_attr "length" "2,4")
755 (set_attr "cc" "set_zn,set_zn")])
757 (define_insn_and_split "*tst_extzv_1_n"
759 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
761 (match_operand 1 "const_int_operand" "n,n,n"))
763 (clobber (match_scratch:QI 2 "=X,X,&r"))]
764 "TARGET_H8300H || TARGET_H8300S"
770 && !satisfies_constraint_U (operands[0])"
773 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
777 (clobber (scratch:QI))])]
779 [(set_attr "length" "2,8,10")
780 (set_attr "cc" "set_zn,set_zn,set_zn")])
784 (compare (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
786 (match_operand 1 "const_int_operand" "n"))
788 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
789 && INTVAL (operands[1]) <= 15"
791 [(set_attr "length" "2")
792 (set_attr "cc" "set_zn")])
794 (define_insn_and_split "*tstsi_upper_bit"
796 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
798 (match_operand 1 "const_int_operand" "n"))
800 (clobber (match_scratch:SI 2 "=&r"))]
801 "(TARGET_H8300H || TARGET_H8300S)
802 && INTVAL (operands[1]) >= 16"
804 "&& reload_completed"
806 (ior:SI (and:SI (match_dup 2)
808 (lshiftrt:SI (match_dup 0)
811 (compare (zero_extract:SI (match_dup 2)
816 operands[3] = GEN_INT (INTVAL (operands[1]) - 16);
819 (define_insn "*tstsi_variable_bit"
821 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
823 (and:SI (match_operand:SI 1 "register_operand" "r")
826 "TARGET_H8300H || TARGET_H8300S"
828 [(set_attr "length" "2")
829 (set_attr "cc" "set_zn")])
831 (define_insn_and_split "*tstsi_variable_bit_qi"
833 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
835 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
838 (clobber (match_scratch:QI 2 "=X,X,&r"))]
839 "TARGET_H8300H || TARGET_H8300S"
845 && !satisfies_constraint_U (operands[0])"
848 (parallel [(set (cc0)
849 (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
851 (and:SI (match_dup 1)
854 (clobber (scratch:QI))])]
856 [(set_attr "length" "2,8,10")
857 (set_attr "cc" "set_zn,set_zn,set_zn")])
859 (define_insn "*tst<mode>"
861 (compare (match_operand:QHI 0 "register_operand" "r")
865 if (<MODE>mode == QImode)
866 return "mov.b %X0,%X0";
867 else if (<MODE>mode == HImode)
868 return "mov.w %T0,%T0";
871 [(set_attr "length" "2")
872 (set_attr "cc" "set_znv")])
874 (define_insn "*tsthi_upper"
876 (compare (and:HI (match_operand:HI 0 "register_operand" "r")
881 [(set_attr "length" "2")
882 (set_attr "cc" "set_znv")])
884 (define_insn "*tstsi"
886 (compare (match_operand:SI 0 "register_operand" "r")
888 "TARGET_H8300H || TARGET_H8300S"
890 [(set_attr "length" "2")
891 (set_attr "cc" "set_znv")])
893 (define_insn "*tstsi_upper"
895 (compare (and:SI (match_operand:SI 0 "register_operand" "r")
900 [(set_attr "length" "2")
901 (set_attr "cc" "set_znv")])
903 (define_insn "*cmpqi"
905 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
906 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
909 [(set_attr "length_table" "add")
910 (set_attr "cc" "compare")])
912 (define_insn "*cmphi_h8300_znvc"
914 (compare (match_operand:HI 0 "register_operand" "r")
915 (match_operand:HI 1 "register_operand" "r")))]
918 [(set_attr "length" "2")
919 (set_attr "cc" "compare")])
921 (define_insn "*cmphi_h8300hs_znvc"
923 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
924 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
925 "TARGET_H8300H || TARGET_H8300S"
927 switch (which_alternative)
931 return "cmp.w %T1,%T0";
933 return "cmp.w %T1:3,%T0";
935 return "cmp.w %T1,%T0";
940 [(set_attr "length_table" "short_immediate,add")
941 (set_attr "cc" "compare,compare")])
945 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
946 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
947 "TARGET_H8300H || TARGET_H8300S"
949 switch (which_alternative)
953 return "cmp.l %S1,%S0";
955 return "cmp.l %S1:3,%S0";
957 return "cmp.l %S1,%S0";
962 [(set_attr "length" "2,*")
963 (set_attr "length_table" "*,add")
964 (set_attr "cc" "compare,compare")])
966 ;; ----------------------------------------------------------------------
968 ;; ----------------------------------------------------------------------
970 (define_expand "add<mode>3"
971 [(set (match_operand:QHSI 0 "register_operand" "")
972 (plus:QHSI (match_operand:QHSI 1 "register_operand" "")
973 (match_operand:QHSI 2 "h8300_src_operand" "")))]
977 (define_insn "*addqi3"
978 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
979 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
980 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
981 "h8300_operands_match_p (operands)"
983 [(set_attr "length_table" "add")
984 (set_attr "cc" "set_zn")])
986 (define_insn "*addhi3_h8300"
987 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
988 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
989 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
995 add.b %s2,%s0\;addx %t2,%t0
997 [(set_attr "length" "2,2,2,4,2")
998 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
1000 ;; This splitter is very important to make the stack adjustment
1001 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1003 ;; We apply this split after the peephole2 pass so that we won't end
1004 ;; up creating too many adds/subs when a scratch register is
1005 ;; available, which is actually a common case because stack unrolling
1006 ;; tends to happen immediately after a function call.
1009 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1010 (plus:HI (match_dup 0)
1011 (match_operand 1 "const_int_gt_2_operand" "")))]
1012 "TARGET_H8300 && epilogue_completed"
1015 split_adds_subs (HImode, operands);
1020 [(match_scratch:HI 2 "r")
1021 (set (match_operand:HI 0 "stack_pointer_operand" "")
1022 (plus:HI (match_dup 0)
1023 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1028 (plus:HI (match_dup 0)
1032 (define_insn "*addhi3_h8300hs"
1033 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1034 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1035 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1036 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1043 [(set_attr "length" "2,2,2,4,2")
1044 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1046 (define_insn "*add<mode>3_incdec"
1047 [(set (match_operand:HSI 0 "register_operand" "=r,r")
1048 (unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0")
1049 (match_operand:HSI 2 "incdec_operand" "M,O")]
1051 "TARGET_H8300H || TARGET_H8300S"
1053 if (which_alternative == 0)
1054 return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0";
1055 else if (which_alternative == 1)
1056 return <MODE>mode == HImode ? "dec.w\t%G2,%T0" : "dec.l\t%G2,%S0";
1059 [(set_attr "length" "2,2")
1060 (set_attr "cc" "set_zn,set_zn")])
1062 (define_insn "*addhi3_h8sx"
1063 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1064 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1065 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1066 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1072 [(set_attr "length_table" "short_immediate,short_immediate,*,add")
1073 (set_attr "length" "*,*,2,*")
1074 (set_attr "cc" "set_zn")])
1077 [(set (match_operand:HI 0 "register_operand" "")
1078 (plus:HI (match_dup 0)
1079 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1083 split_adds_subs (HImode, operands);
1088 (define_insn "*addsi_h8300"
1089 [(set (match_operand:SI 0 "register_operand" "=r,r")
1090 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1091 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1094 return output_plussi (operands);
1096 [(set (attr "length")
1097 (symbol_ref "compute_plussi_length (operands)"))
1099 (symbol_ref "compute_plussi_cc (operands)"))])
1101 (define_insn "*addsi_h8300hs"
1102 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1103 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1104 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1105 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1107 return output_plussi (operands);
1109 [(set (attr "length")
1110 (symbol_ref "compute_plussi_length (operands)"))
1112 (symbol_ref "compute_plussi_cc (operands)"))])
1115 [(set (match_operand:SI 0 "register_operand" "")
1116 (plus:SI (match_dup 0)
1117 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1118 "TARGET_H8300H || TARGET_H8300S"
1121 split_adds_subs (SImode, operands);
1125 ;; ----------------------------------------------------------------------
1126 ;; SUBTRACT INSTRUCTIONS
1127 ;; ----------------------------------------------------------------------
1129 (define_expand "sub<mode>3"
1130 [(set (match_operand:QHSI 0 "register_operand" "")
1131 (minus:QHSI (match_operand:QHSI 1 "register_operand" "")
1132 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1135 if (TARGET_H8300 && <MODE>mode == SImode)
1136 operands[2] = force_reg (SImode, operands[2]);
1139 (define_insn "*subqi3"
1140 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1141 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1142 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1143 "h8300_operands_match_p (operands)"
1145 [(set_attr "length_table" "add")
1146 (set_attr "cc" "set_zn")])
1148 (define_insn "*subhi3_h8300"
1149 [(set (match_operand:HI 0 "register_operand" "=r,r")
1150 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1151 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1155 add.b %E2,%s0\;addx %F2,%t0"
1156 [(set_attr "length" "2,4")
1157 (set_attr "cc" "set_zn,clobber")])
1159 (define_insn "*sub<mode>3_h8300hs"
1160 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ")
1161 (minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0")
1162 (match_operand:HSI 2 "h8300_src_operand" "rQ,i")))]
1163 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1165 if (<MODE>mode == HImode)
1166 return "sub.w %T2,%T0";
1167 else if (<MODE>mode == SImode)
1168 return "sub.l %S2,%S0";
1171 [(set_attr "length_table" "add")
1172 (set_attr "cc" "set_zn")])
1174 (define_insn "*subsi3_h8300"
1175 [(set (match_operand:SI 0 "register_operand" "=r")
1176 (minus:SI (match_operand:SI 1 "register_operand" "0")
1177 (match_operand:SI 2 "register_operand" "r")))]
1179 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1180 [(set_attr "length" "6")])
1183 ;; ----------------------------------------------------------------------
1184 ;; MULTIPLY INSTRUCTIONS
1185 ;; ----------------------------------------------------------------------
1187 ;; Note that the H8/300 can only handle umulqihi3.
1189 (define_expand "mulqihi3"
1190 [(set (match_operand:HI 0 "register_operand" "")
1191 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1192 ;; intentionally-mismatched modes
1193 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1194 "TARGET_H8300H || TARGET_H8300S"
1196 if (GET_MODE (operands[2]) != VOIDmode)
1197 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1200 (define_insn "*mulqihi3_const"
1201 [(set (match_operand:HI 0 "register_operand" "=r")
1202 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1203 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1206 [(set_attr "length" "4")
1207 (set_attr "cc" "set_zn")])
1209 (define_insn "*mulqihi3"
1210 [(set (match_operand:HI 0 "register_operand" "=r")
1211 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1212 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1213 "TARGET_H8300H || TARGET_H8300S"
1215 [(set_attr "length" "4")
1216 (set_attr "cc" "set_zn")])
1218 (define_expand "mulhisi3"
1219 [(set (match_operand:SI 0 "register_operand" "")
1220 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1221 ;; intentionally-mismatched modes
1222 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1223 "TARGET_H8300H || TARGET_H8300S"
1225 if (GET_MODE (operands[2]) != VOIDmode)
1226 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1229 (define_insn "*mulhisi3_const"
1230 [(set (match_operand:SI 0 "register_operand" "=r")
1231 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1232 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1235 [(set_attr "length" "4")
1236 (set_attr "cc" "set_zn")])
1238 (define_insn "*mulhisi3"
1239 [(set (match_operand:SI 0 "register_operand" "=r")
1240 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1241 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1242 "TARGET_H8300H || TARGET_H8300S"
1244 [(set_attr "length" "4")
1245 (set_attr "cc" "set_zn")])
1247 (define_expand "umulqihi3"
1248 [(set (match_operand:HI 0 "register_operand" "")
1249 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1250 ;; intentionally-mismatched modes
1251 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1252 "TARGET_H8300H || TARGET_H8300S"
1254 if (GET_MODE (operands[2]) != VOIDmode)
1255 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1258 (define_insn "*umulqihi3_const"
1259 [(set (match_operand:HI 0 "register_operand" "=r")
1260 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1261 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1264 [(set_attr "length" "4")
1265 (set_attr "cc" "set_zn")])
1267 (define_insn "*umulqihi3"
1268 [(set (match_operand:HI 0 "register_operand" "=r")
1269 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1270 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1273 [(set_attr "length" "2")
1274 (set_attr "cc" "none_0hit")])
1276 (define_expand "umulhisi3"
1277 [(set (match_operand:SI 0 "register_operand" "")
1278 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1279 ;; intentionally-mismatched modes
1280 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1281 "TARGET_H8300H || TARGET_H8300S"
1283 if (GET_MODE (operands[2]) != VOIDmode)
1284 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1287 (define_insn "*umulhisi3_const"
1288 [(set (match_operand:SI 0 "register_operand" "=r")
1289 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1290 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1293 [(set_attr "length" "4")
1294 (set_attr "cc" "set_zn")])
1296 (define_insn "*umulhisi3"
1297 [(set (match_operand:SI 0 "register_operand" "=r")
1298 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1299 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1300 "TARGET_H8300H || TARGET_H8300S"
1302 [(set_attr "length" "2")
1303 (set_attr "cc" "none_0hit")])
1305 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1306 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1307 ;; on all H8SX variants.
1309 (define_insn "mul<mode>3"
1310 [(set (match_operand:HSI 0 "register_operand" "=r")
1311 (mult:HSI (match_operand:HSI 1 "register_operand" "%0")
1312 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1314 { return <MODE>mode == HImode ? "muls.w\\t%T2,%T0" : "muls.l\\t%S2,%S0"; }
1315 [(set_attr "length" "2")
1316 (set_attr "cc" "set_zn")])
1318 (define_insn "smulsi3_highpart"
1319 [(set (match_operand:SI 0 "register_operand" "=r")
1323 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1324 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1327 "muls/u.l\\t%S2,%S0"
1328 [(set_attr "length" "2")
1329 (set_attr "cc" "set_zn")])
1331 (define_insn "umulsi3_highpart"
1332 [(set (match_operand:SI 0 "register_operand" "=r")
1336 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1337 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1340 "mulu/u.l\\t%S2,%S0"
1341 [(set_attr "length" "2")
1342 (set_attr "cc" "none_0hit")])
1344 ;; This is a "bridge" instruction. Combine can't cram enough insns
1345 ;; together to crate a MAC instruction directly, but it can create
1346 ;; this instruction, which then allows combine to create the real
1349 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1350 ;; insn must generate reasonably correct code. Egad.
1353 [(set (match_operand:SI 0 "register_operand" "=a")
1356 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1358 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1360 "clrmac\;mac @%2+,@%1+"
1361 [(set_attr "length" "6")
1362 (set_attr "cc" "none_0hit")])
1365 [(set (match_operand:SI 0 "register_operand" "=a")
1367 (sign_extend:SI (mem:HI
1368 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1369 (sign_extend:SI (mem:HI
1370 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1371 (match_operand:SI 3 "register_operand" "0")))]
1374 [(set_attr "length" "4")
1375 (set_attr "cc" "none_0hit")])
1377 ;; ----------------------------------------------------------------------
1378 ;; DIVIDE/MOD INSTRUCTIONS
1379 ;; ----------------------------------------------------------------------
1381 (define_insn "udiv<mode>3"
1382 [(set (match_operand:HSI 0 "register_operand" "=r")
1383 (udiv:HSI (match_operand:HSI 1 "register_operand" "0")
1384 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1386 { return <MODE>mode == HImode ? "divu.w\\t%T2,%T0" : "divu.l\\t%S2,%S0"; }
1387 [(set_attr "length" "2")])
1389 (define_insn "div<mode>3"
1390 [(set (match_operand:HSI 0 "register_operand" "=r")
1391 (div:HSI (match_operand:HSI 1 "register_operand" "0")
1392 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1394 { return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
1395 [(set_attr "length" "2")])
1397 (define_insn "udivmodqi4"
1398 [(set (match_operand:QI 0 "register_operand" "=r")
1401 (match_operand:HI 1 "register_operand" "0")
1402 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1403 (set (match_operand:QI 3 "register_operand" "=r")
1407 (zero_extend:HI (match_dup 2)))))]
1410 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1411 return "divxu.b\\t%X2,%T0";
1413 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1415 [(set_attr "length" "4")])
1417 (define_insn "divmodqi4"
1418 [(set (match_operand:QI 0 "register_operand" "=r")
1421 (match_operand:HI 1 "register_operand" "0")
1422 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1423 (set (match_operand:QI 3 "register_operand" "=r")
1427 (sign_extend:HI (match_dup 2)))))]
1428 "TARGET_H8300H || TARGET_H8300S"
1430 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1431 return "divxs.b\\t%X2,%T0";
1433 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1435 [(set_attr "length" "6")])
1437 (define_insn "udivmodhi4"
1438 [(set (match_operand:HI 0 "register_operand" "=r")
1441 (match_operand:SI 1 "register_operand" "0")
1442 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1443 (set (match_operand:HI 3 "register_operand" "=r")
1447 (zero_extend:SI (match_dup 2)))))]
1448 "TARGET_H8300H || TARGET_H8300S"
1450 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1451 return "divxu.w\\t%T2,%S0";
1453 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1455 [(set_attr "length" "4")])
1457 (define_insn "divmodhi4"
1458 [(set (match_operand:HI 0 "register_operand" "=r")
1461 (match_operand:SI 1 "register_operand" "0")
1462 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1463 (set (match_operand:HI 3 "register_operand" "=r")
1467 (sign_extend:SI (match_dup 2)))))]
1468 "TARGET_H8300H || TARGET_H8300S"
1470 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1471 return "divxs.w\\t%T2,%S0";
1473 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1475 [(set_attr "length" "6")])
1477 ;; ----------------------------------------------------------------------
1479 ;; ----------------------------------------------------------------------
1481 (define_insn "bclrqi_msx"
1482 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1483 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1484 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1485 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1487 [(set_attr "length" "8")])
1490 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1491 (and:HI (match_operand:HI 1 "bit_register_indirect_operand")
1492 (match_operand:HI 2 "single_zero_operand")))]
1495 (and:QI (match_dup 1)
1498 if (abs (INTVAL (operands[2])) > 0xFF)
1500 operands[0] = adjust_address (operands[0], QImode, 0);
1501 operands[1] = adjust_address (operands[1], QImode, 0);
1502 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1506 operands[0] = adjust_address (operands[0], QImode, 1);
1507 operands[1] = adjust_address (operands[1], QImode, 1);
1511 (define_insn "bclrhi_msx"
1512 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1513 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1514 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1517 [(set_attr "length" "8")])
1519 (define_insn "*andqi3_2"
1520 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1521 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1522 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1528 [(set_attr "length" "8,*,8")
1529 (set_attr "length_table" "*,logicb,*")
1530 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1532 (define_insn "andqi3_1"
1533 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1534 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1535 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1536 "register_operand (operands[0], QImode)
1537 || single_zero_operand (operands[2], QImode)"
1541 [(set_attr "length" "2,8")
1542 (set_attr "cc" "none_0hit,set_znv")])
1544 (define_expand "and<mode>3"
1545 [(set (match_operand:QHSI 0 "register_operand" "")
1546 (and:QHSI (match_operand:QHSI 1 "register_operand" "")
1547 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1551 (define_insn "*andor<mode>3"
1552 [(set (match_operand:QHSI 0 "register_operand" "=r")
1553 (ior:QHSI (and:QHSI (match_operand:QHSI 2 "register_operand" "r")
1554 (match_operand:QHSI 3 "single_one_operand" "n"))
1555 (match_operand:QHSI 1 "register_operand" "0")))]
1556 "(<MODE>mode == QImode
1557 || <MODE>mode == HImode
1558 || (<MODE>mode == SImode
1559 && (INTVAL (operands[3]) & 0xffff) != 0))"
1561 if (<MODE>mode == QImode)
1562 return "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0";
1564 if (<MODE>mode == HImode)
1566 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1567 if (INTVAL (operands[3]) > 128)
1569 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1570 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
1572 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
1575 if (<MODE>mode == SImode)
1577 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1578 if (INTVAL (operands[3]) > 128)
1580 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1581 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
1583 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
1589 [(set_attr "length" "6")])
1591 (define_insn "*andorsi3_shift_8"
1592 [(set (match_operand:SI 0 "register_operand" "=r")
1593 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1596 (match_operand:SI 1 "register_operand" "0")))]
1599 [(set_attr "length" "2")])
1601 ;; ----------------------------------------------------------------------
1602 ;; OR/XOR INSTRUCTIONS
1603 ;; ----------------------------------------------------------------------
1605 (define_insn "b<code>qi_msx"
1606 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1607 (ors:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1608 (match_operand:QI 2 "single_one_operand" "Y2")))]
1609 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1610 { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
1611 [(set_attr "length" "8")])
1613 (define_insn "b<code>hi_msx"
1614 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1615 (ors:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1616 (match_operand:HI 2 "single_one_operand" "Y2")))]
1618 { return <CODE> == IOR ? "bset\\t%V2,%0" : "bnot\\t%V2,%0"; }
1619 [(set_attr "length" "8")])
1621 (define_insn "<code>qi3_1"
1622 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1623 (ors:QI (match_operand:QI 1 "bit_operand" "%0,0")
1624 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1625 "TARGET_H8300SX || register_operand (operands[0], QImode)
1626 || single_one_operand (operands[2], QImode)"
1628 if (which_alternative == 0)
1629 return <CODE> == IOR ? "bset\\t%V2,%R0" : "bnot\\t%V2,%R0";
1630 else if (which_alternative == 1)
1631 return <CODE> == IOR ? "or\\t%X2,%X0" : "xor\\t%X2,%X0";
1633 [(set_attr "length" "8,*")
1634 (set_attr "length_table" "*,logicb")
1635 (set_attr "cc" "none_0hit,set_znv")])
1637 (define_expand "<code><mode>3"
1638 [(set (match_operand:QHSI 0 "register_operand" "")
1639 (ors:QHSI (match_operand:QHSI 1 "register_operand" "")
1640 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1644 ;; ----------------------------------------------------------------------
1645 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1646 ;; ----------------------------------------------------------------------
1648 ;; We need a separate pattern here because machines other than the
1649 ;; original H8300 don't have to split the 16-bit operand into a pair
1650 ;; of high/low instructions, so we can accept literal addresses, that
1651 ;; have to be loaded into a register on H8300.
1653 (define_insn "*logical<mode>3_sn"
1654 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
1655 (match_operator:HSI 3 "bit_operator"
1656 [(match_operand:HSI 1 "h8300_dst_operand" "%0")
1657 (match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
1658 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1660 return output_logical_op (<MODE>mode, operands);
1662 [(set (attr "length")
1663 (symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))
1665 (symbol_ref "compute_logical_op_cc (<MODE>mode, operands)"))])
1667 (define_insn "*logical<mode>3"
1668 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
1669 (match_operator:HSI 3 "bit_operator"
1670 [(match_operand:HSI 1 "h8300_dst_operand" "%0")
1671 (match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
1672 "h8300_operands_match_p (operands)"
1674 return output_logical_op (<MODE>mode, operands);
1676 [(set (attr "length")
1677 (symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))
1679 (symbol_ref "compute_logical_op_cc (<MODE>mode, operands)"))])
1681 ;; ----------------------------------------------------------------------
1682 ;; NEGATION INSTRUCTIONS
1683 ;; ----------------------------------------------------------------------
1685 (define_expand "neg<mode>2"
1686 [(set (match_operand:QHSIF 0 "register_operand" "")
1687 (neg:QHSIF (match_operand:QHSIF 1 "register_operand" "")))]
1690 enum machine_mode mode = <MODE>mode;
1693 if (mode == QImode || mode == SFmode)
1695 else if (mode == HImode)
1697 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1700 else if (mode == SImode)
1702 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1708 (define_insn "*negqi2"
1709 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1710 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1713 [(set_attr "length_table" "unary")
1714 (set_attr "cc" "set_zn")])
1716 (define_expand "neg<mode>2_h8300"
1718 (not:HSI (match_operand:HSI 1 "register_operand" "")))
1719 (set (match_dup 2) (plus:HSI (match_dup 2) (const_int 1)))
1720 (set (match_operand:HSI 0 "register_operand" "")
1724 operands[2] = gen_reg_rtx (<MODE>mode);
1727 (define_insn "*neghi2_h8300hs"
1728 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1729 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1730 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1732 [(set_attr "length_table" "unary")
1733 (set_attr "cc" "set_zn")])
1735 (define_insn "*negsi2_h8300hs"
1736 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1737 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1738 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1740 [(set_attr "length_table" "unary")
1741 (set_attr "cc" "set_zn")])
1743 (define_insn "*negsf2_h8300"
1744 [(set (match_operand:SF 0 "register_operand" "=r")
1745 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1748 [(set_attr "length" "2")])
1750 (define_insn "*negsf2_h8300hs"
1751 [(set (match_operand:SF 0 "register_operand" "=r")
1752 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1753 "TARGET_H8300H || TARGET_H8300S"
1754 "xor.w\\t#32768,%e0"
1755 [(set_attr "length" "4")])
1757 ;; ----------------------------------------------------------------------
1758 ;; ABSOLUTE VALUE INSTRUCTIONS
1759 ;; ----------------------------------------------------------------------
1761 (define_expand "abssf2"
1762 [(set (match_operand:SF 0 "register_operand" "")
1763 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1767 (define_insn "*abssf2_h8300"
1768 [(set (match_operand:SF 0 "register_operand" "=r")
1769 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1772 [(set_attr "length" "2")])
1774 (define_insn "*abssf2_h8300hs"
1775 [(set (match_operand:SF 0 "register_operand" "=r")
1776 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1777 "TARGET_H8300H || TARGET_H8300S"
1778 "and.w\\t#32767,%e0"
1779 [(set_attr "length" "4")])
1781 ;; ----------------------------------------------------------------------
1783 ;; ----------------------------------------------------------------------
1785 (define_expand "one_cmpl<mode>2"
1786 [(set (match_operand:QHSI 0 "register_operand" "")
1787 (not:QHSI (match_operand:QHSI 1 "register_operand" "")))]
1791 (define_insn "*one_cmplqi2"
1792 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1793 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1796 [(set_attr "length_table" "unary")
1797 (set_attr "cc" "set_znv")])
1799 (define_insn "*one_cmplhi2_h8300"
1800 [(set (match_operand:HI 0 "register_operand" "=r")
1801 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1804 [(set_attr "length" "4")])
1806 (define_insn "*one_cmplhi2_h8300hs"
1807 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1808 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1809 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1811 [(set_attr "cc" "set_znv")
1812 (set_attr "length_table" "unary")])
1814 (define_insn "*one_cmplsi2_h8300"
1815 [(set (match_operand:SI 0 "register_operand" "=r")
1816 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1818 "not %w0\;not %x0\;not %y0\;not %z0"
1819 [(set_attr "length" "8")])
1821 (define_insn "*one_cmplsi2_h8300hs"
1822 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1823 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1824 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1826 [(set_attr "cc" "set_znv")
1827 (set_attr "length_table" "unary")])
1829 ;; ----------------------------------------------------------------------
1830 ;; JUMP INSTRUCTIONS
1831 ;; ----------------------------------------------------------------------
1833 ;; Conditional jump instructions
1835 (define_expand "cbranchqi4"
1836 [(use (match_operator 0 "ordered_comparison_operator"
1837 [(match_operand:QI 1 "h8300_dst_operand" "")
1838 (match_operand:QI 2 "h8300_src_operand" "")]))
1839 (use (match_operand 3 ""))]
1842 h8300_expand_branch (operands);
1846 (define_expand "cbranchhi4"
1847 [(use (match_operator 0 "ordered_comparison_operator"
1848 [(match_operand:HI 1 "h8300_dst_operand" "")
1849 (match_operand:HI 2 "h8300_src_operand" "")]))
1850 (use (match_operand 3 ""))]
1853 /* Force operand1 into a register if we're compiling
1855 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
1857 operands[2] = force_reg (HImode, operands[2]);
1858 h8300_expand_branch (operands);
1862 (define_expand "cbranchsi4"
1863 [(use (match_operator 0 "ordered_comparison_operator"
1864 [(match_operand:SI 1 "h8300_dst_operand" "")
1865 (match_operand:SI 2 "h8300_src_operand" "")]))
1866 (use (match_operand 3 ""))]
1867 "TARGET_H8300H || TARGET_H8300S"
1869 h8300_expand_branch (operands);
1873 (define_insn "branch_true"
1875 (if_then_else (match_operator 1 "comparison_operator"
1876 [(cc0) (const_int 0)])
1877 (label_ref (match_operand 0 "" ""))
1881 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1882 && (GET_CODE (operands[1]) == GT
1883 || GET_CODE (operands[1]) == GE
1884 || GET_CODE (operands[1]) == LE
1885 || GET_CODE (operands[1]) == LT))
1887 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1891 if (get_attr_length (insn) == 2)
1893 else if (get_attr_length (insn) == 4)
1894 return "b%j1 %l0:16";
1896 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1898 [(set_attr "type" "branch")
1899 (set_attr "cc" "none")])
1901 (define_insn "branch_false"
1903 (if_then_else (match_operator 1 "comparison_operator"
1904 [(cc0) (const_int 0)])
1906 (label_ref (match_operand 0 "" ""))))]
1909 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1910 && (GET_CODE (operands[1]) == GT
1911 || GET_CODE (operands[1]) == GE
1912 || GET_CODE (operands[1]) == LE
1913 || GET_CODE (operands[1]) == LT))
1915 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1919 if (get_attr_length (insn) == 2)
1921 else if (get_attr_length (insn) == 4)
1922 return "b%k1 %l0:16";
1924 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1926 [(set_attr "type" "branch")
1927 (set_attr "cc" "none")])
1929 (define_insn "*brabc"
1931 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
1933 (match_operand:QI 2 "immediate_operand" "n"))
1935 (label_ref (match_operand 0 "" ""))
1939 switch (get_attr_length (insn)
1940 - h8300_insn_length_from_table (insn, operands))
1943 return "bra/bc %2,%R1,%l0";
1945 return "bra/bc %2,%R1,%l0:16";
1947 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1950 [(set_attr "type" "bitbranch")
1951 (set_attr "length_table" "bitbranch")
1952 (set_attr "cc" "none")])
1954 (define_insn "*brabs"
1956 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
1958 (match_operand:QI 2 "immediate_operand" "n"))
1960 (label_ref (match_operand 0 "" ""))
1964 switch (get_attr_length (insn)
1965 - h8300_insn_length_from_table (insn, operands))
1968 return "bra/bs %2,%R1,%l0";
1970 return "bra/bs %2,%R1,%l0:16";
1972 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1975 [(set_attr "type" "bitbranch")
1976 (set_attr "length_table" "bitbranch")
1977 (set_attr "cc" "none")])
1979 ;; Unconditional and other jump instructions.
1983 (label_ref (match_operand 0 "" "")))]
1986 if (final_sequence != 0)
1988 if (get_attr_length (insn) == 2)
1992 /* The branch isn't short enough to use bra/s. Output the
1993 branch and delay slot in their normal order.
1995 If this is a backward branch, it will now be branching two
1996 bytes further than previously thought. The length-based
1997 test for bra vs. jump is very conservative though, so the
1998 branch will still be within range. */
2002 seq = final_sequence;
2004 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, & seen);
2005 final_scan_insn (seq->insn (0), asm_out_file, optimize, 1, & seen);
2006 seq->insn (1)->set_deleted ();
2010 else if (get_attr_length (insn) == 2)
2012 else if (get_attr_length (insn) == 4)
2013 return "bra %l0:16";
2017 [(set_attr "type" "branch")
2018 (set (attr "delay_slot")
2019 (if_then_else (match_test "TARGET_H8300SX")
2020 (const_string "jump")
2021 (const_string "none")))
2022 (set_attr "cc" "none")])
2024 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2026 (define_expand "tablejump"
2027 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2028 (use (label_ref (match_operand 1 "" "")))])]
2032 (define_insn "*tablejump_h8300"
2033 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2034 (use (label_ref (match_operand 1 "" "")))]
2037 [(set_attr "cc" "none")
2038 (set_attr "length" "2")])
2040 (define_insn "*tablejump_h8300hs_advanced"
2041 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2042 (use (label_ref (match_operand 1 "" "")))]
2043 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2045 [(set_attr "cc" "none")
2046 (set_attr "length" "2")])
2048 (define_insn "*tablejump_h8300hs_normal"
2049 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2050 (use (label_ref (match_operand 1 "" "")))]
2051 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2053 [(set_attr "cc" "none")
2054 (set_attr "length" "2")])
2056 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2058 (define_expand "indirect_jump"
2059 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2063 (define_insn "*indirect_jump_h8300"
2064 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2067 [(set_attr "cc" "none")
2068 (set_attr "length" "2")])
2070 (define_insn "*indirect_jump_h8300hs_advanced"
2071 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2072 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2074 [(set_attr "cc" "none")
2075 (set_attr "length" "2")])
2077 (define_insn "*indirect_jump_h8300hs_normal"
2078 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2079 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2081 [(set_attr "cc" "none")
2082 (set_attr "length" "2")])
2084 ;; Call subroutine with no return value.
2086 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2089 [(call (match_operand:QI 0 "call_insn_operand" "or")
2090 (match_operand:HI 1 "general_operand" "g"))]
2093 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2094 && (SYMBOL_REF_FLAGS (XEXP (operands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2095 return "jsr\\t@%0:8";
2099 [(set_attr "type" "call")
2100 (set (attr "length")
2101 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2105 ;; Call subroutine, returning value in operand 0
2106 ;; (which must be a hard register).
2108 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2110 (define_insn "call_value"
2111 [(set (match_operand 0 "" "=r")
2112 (call (match_operand:QI 1 "call_insn_operand" "or")
2113 (match_operand:HI 2 "general_operand" "g")))]
2116 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2117 && (SYMBOL_REF_FLAGS (XEXP (operands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2118 return "jsr\\t@%1:8";
2122 [(set_attr "type" "call")
2123 (set (attr "length")
2124 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2132 [(set_attr "cc" "none")
2133 (set_attr "length" "2")])
2135 ;; ----------------------------------------------------------------------
2136 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2137 ;; ----------------------------------------------------------------------
2139 (define_expand "push_h8300"
2140 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2141 (match_operand:HI 0 "register_operand" ""))]
2145 (define_expand "push_h8300hs_advanced"
2146 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2147 (match_operand:SI 0 "register_operand" ""))]
2148 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2151 (define_expand "push_h8300hs_normal"
2152 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2153 (match_operand:SI 0 "register_operand" ""))]
2154 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2157 (define_expand "pop_h8300"
2158 [(set (match_operand:HI 0 "register_operand" "")
2159 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2163 (define_expand "pop_h8300hs_advanced"
2164 [(set (match_operand:SI 0 "register_operand" "")
2165 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2166 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2169 (define_expand "pop_h8300hs_normal"
2170 [(set (match_operand:SI 0 "register_operand" "")
2171 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2172 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2175 (define_insn "ldm_h8300sx"
2176 [(match_parallel 0 "h8300_ldm_parallel"
2177 [(set (match_operand:SI 1 "register_operand" "")
2178 (match_operand:SI 2 "memory_operand" ""))])]
2181 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2182 XVECLEN (operands[0], 0) - 2));
2183 return "ldm.l\t@er7+,%S1-%S3";
2185 [(set_attr "cc" "none")
2186 (set_attr "length" "4")])
2188 (define_insn "stm_h8300sx"
2189 [(match_parallel 0 "h8300_stm_parallel"
2190 [(set (match_operand:SI 1 "memory_operand" "")
2191 (match_operand:SI 2 "register_operand" ""))])]
2194 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2195 XVECLEN (operands[0], 0) - 2));
2196 return "stm.l\t%S2-%S3,@-er7";
2198 [(set_attr "cc" "none")
2199 (set_attr "length" "4")])
2201 (define_insn "return_h8sx"
2202 [(match_parallel 0 "h8300_return_parallel"
2204 (set (match_operand:SI 1 "register_operand" "")
2205 (match_operand:SI 2 "memory_operand" ""))])]
2208 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2209 XVECLEN (operands[0], 0) - 2));
2210 if (h8300_current_function_interrupt_function_p ()
2211 || h8300_current_function_monitor_function_p ())
2212 return "rte/l\t%S1-%S3";
2214 return "rts/l\t%S1-%S3";
2216 [(set_attr "cc" "none")
2217 (set_attr "can_delay" "no")
2218 (set_attr "length" "2")])
2220 (define_expand "return"
2222 "h8300_can_use_return_insn_p ()"
2225 (define_insn "*return_1"
2229 if (h8300_current_function_interrupt_function_p ()
2230 || h8300_current_function_monitor_function_p ())
2235 [(set_attr "cc" "none")
2236 (set_attr "can_delay" "no")
2237 (set_attr "length" "2")])
2239 (define_expand "prologue"
2243 h8300_expand_prologue ();
2247 (define_expand "epilogue"
2251 h8300_expand_epilogue ();
2255 (define_insn "monitor_prologue"
2256 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2260 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
2261 else if (TARGET_H8300H && TARGET_NORMAL_MODE)
2262 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2263 else if (TARGET_H8300H)
2264 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2265 else if (TARGET_H8300S && TARGET_NEXR )
2266 return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2267 else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE)
2268 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2269 else if (TARGET_H8300S && TARGET_NORMAL_MODE)
2270 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2271 else if (TARGET_H8300S)
2272 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2275 [(set_attr "length" "20")])
2277 ;; ----------------------------------------------------------------------
2278 ;; EXTEND INSTRUCTIONS
2279 ;; ----------------------------------------------------------------------
2281 (define_expand "zero_extendqi<mode>2"
2282 [(set (match_operand:HSI 0 "register_operand" "")
2283 (zero_extend:HSI (match_operand:QI 1 "general_operand_src" "")))]
2287 operands[1] = force_reg (QImode, operands[1]);
2290 (define_insn "*zero_extendqihi2_h8300"
2291 [(set (match_operand:HI 0 "register_operand" "=r,r")
2292 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2297 [(set_attr "length" "2,10")])
2299 (define_insn "*zero_extendqihi2_h8300hs"
2300 [(set (match_operand:HI 0 "register_operand" "=r,r")
2301 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2302 "TARGET_H8300H || TARGET_H8300S"
2306 [(set_attr "length" "2,10")
2307 (set_attr "cc" "set_znv,set_znv")])
2309 ;; Split the zero extension of a general operand (actually a memory
2310 ;; operand) into a load of the operand and the actual zero extension
2311 ;; so that 1) the length will be accurate, and 2) the zero extensions
2312 ;; appearing at the end of basic blocks may be merged.
2315 [(set (match_operand:HI 0 "register_operand" "")
2316 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2321 (zero_extend:HI (match_dup 2)))]
2323 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2327 (define_insn "*zero_extendqisi2_h8300"
2328 [(set (match_operand:SI 0 "register_operand" "=r,r")
2329 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2332 mov.b #0,%x0\;sub.w %e0,%e0
2333 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2334 [(set_attr "length" "4,8")])
2336 (define_insn "*zero_extendqisi2_h8300hs"
2337 [(set (match_operand:SI 0 "register_operand" "=r,r")
2338 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2339 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2343 [(set (match_operand:SI 0 "register_operand" "")
2344 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2345 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2346 && reg_overlap_mentioned_p (operands[0], operands[1])
2347 && reload_completed"
2351 (zero_extend:HI (match_dup 2)))
2353 (zero_extend:SI (match_dup 3)))]
2355 operands[2] = gen_lowpart (QImode, operands[0]);
2356 operands[3] = gen_lowpart (HImode, operands[0]);
2360 [(set (match_operand:SI 0 "register_operand" "")
2361 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2362 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2363 && !reg_overlap_mentioned_p (operands[0], operands[1])
2364 && reload_completed"
2367 (set (strict_low_part (match_dup 2))
2370 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2373 (define_insn "*zero_extendqisi2_h8sx"
2374 [(set (match_operand:SI 0 "register_operand" "=r")
2375 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2378 [(set_attr "length" "2")
2379 (set_attr "cc" "set_znv")])
2381 (define_expand "zero_extendhisi2"
2382 [(set (match_operand:SI 0 "register_operand" "")
2383 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2387 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2388 (define_insn "*zero_extendhisi2_h8300"
2389 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2390 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2394 mov.w %f1,%f0\;sub.w %e0,%e0
2395 mov.w %e1,%f0\;sub.w %e0,%e0"
2396 [(set_attr "length" "2,4,6")])
2398 (define_insn "*zero_extendhisi2_h8300hs"
2399 [(set (match_operand:SI 0 "register_operand" "=r")
2400 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2401 "TARGET_H8300H || TARGET_H8300S"
2403 [(set_attr "length" "2")
2404 (set_attr "cc" "set_znv")])
2406 (define_expand "extendqi<mode>2"
2407 [(set (match_operand:HSI 0 "register_operand" "")
2408 (sign_extend:HSI (match_operand:QI 1 "register_operand" "")))]
2412 (define_insn "*extendqihi2_h8300"
2413 [(set (match_operand:HI 0 "register_operand" "=r,r")
2414 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2417 bld #7,%s0\;subx %t0,%t0
2418 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2419 [(set_attr "length" "4,8")])
2421 (define_insn "*extendqihi2_h8300hs"
2422 [(set (match_operand:HI 0 "register_operand" "=r")
2423 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2424 "TARGET_H8300H || TARGET_H8300S"
2426 [(set_attr "length" "2")
2427 (set_attr "cc" "set_znv")])
2429 (define_insn "*extendqisi2_h8300"
2430 [(set (match_operand:SI 0 "register_operand" "=r,r")
2431 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2434 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2435 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2436 [(set_attr "length" "8,12")])
2438 ;; The following pattern is needed because without the pattern, the
2439 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2440 ;; shifts, one ashift and one ashiftrt.
2442 (define_insn_and_split "*extendqisi2_h8300hs"
2443 [(set (match_operand:SI 0 "register_operand" "=r")
2444 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2445 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2447 "&& reload_completed"
2449 (sign_extend:HI (match_dup 1)))
2451 (sign_extend:SI (match_dup 2)))]
2453 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
2456 (define_insn "*extendqisi2_h8sx"
2457 [(set (match_operand:SI 0 "register_operand" "=r")
2458 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2461 [(set_attr "length" "2")
2462 (set_attr "cc" "set_znv")])
2464 (define_expand "extendhisi2"
2465 [(set (match_operand:SI 0 "register_operand" "")
2466 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2470 (define_insn "*extendhisi2_h8300"
2471 [(set (match_operand:SI 0 "register_operand" "=r,r")
2472 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2475 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2476 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2477 [(set_attr "length" "6,10")])
2479 (define_insn "*extendhisi2_h8300hs"
2480 [(set (match_operand:SI 0 "register_operand" "=r")
2481 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2482 "TARGET_H8300H || TARGET_H8300S"
2484 [(set_attr "length" "2")
2485 (set_attr "cc" "set_znv")])
2487 ;; ----------------------------------------------------------------------
2489 ;; ----------------------------------------------------------------------
2491 ;; We make some attempt to provide real efficient shifting. One example is
2492 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2493 ;; reg and moving 0 into the former reg.
2495 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2496 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2497 ;; give the optimizer more cracks at the code. However, we wish to do things
2498 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2499 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2500 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2501 ;; to detect cases it can optimize.
2503 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2504 ;; easier "do it at insn emit time" route.
2508 (define_expand "ashlqi3"
2509 [(set (match_operand:QI 0 "register_operand" "")
2510 (ashift:QI (match_operand:QI 1 "register_operand" "")
2511 (match_operand:QI 2 "nonmemory_operand" "")))]
2514 if (expand_a_shift (QImode, ASHIFT, operands))
2518 (define_expand "ashrqi3"
2519 [(set (match_operand:QI 0 "register_operand" "")
2520 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2521 (match_operand:QI 2 "nonmemory_operand" "")))]
2524 if (expand_a_shift (QImode, ASHIFTRT, operands))
2528 (define_expand "lshrqi3"
2529 [(set (match_operand:QI 0 "register_operand" "")
2530 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2531 (match_operand:QI 2 "nonmemory_operand" "")))]
2534 if (expand_a_shift (QImode, LSHIFTRT, operands))
2539 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2540 (match_operator:QI 3 "h8sx_unary_shift_operator"
2541 [(match_operand:QI 1 "h8300_dst_operand" "0")
2542 (match_operand:QI 2 "const_int_operand" "")]))]
2543 "h8300_operands_match_p (operands)"
2545 return output_h8sx_shift (operands, 'b', 'X');
2547 [(set_attr "length_table" "unary")
2548 (set_attr "cc" "set_znv")])
2551 [(set (match_operand:QI 0 "register_operand" "=r")
2552 (match_operator:QI 3 "h8sx_binary_shift_operator"
2553 [(match_operand:QI 1 "register_operand" "0")
2554 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2557 return output_h8sx_shift (operands, 'b', 'X');
2559 [(set_attr "length" "4")
2560 (set_attr "cc" "set_znv")])
2562 (define_insn "*shiftqi"
2563 [(set (match_operand:QI 0 "register_operand" "=r,r")
2564 (match_operator:QI 3 "nshift_operator"
2565 [(match_operand:QI 1 "register_operand" "0,0")
2566 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2567 (clobber (match_scratch:QI 4 "=X,&r"))]
2570 return output_a_shift (operands);
2572 [(set (attr "length")
2573 (symbol_ref "compute_a_shift_length (insn, operands)"))
2575 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2579 (define_expand "ashlhi3"
2580 [(set (match_operand:HI 0 "register_operand" "")
2581 (ashift:HI (match_operand:HI 1 "register_operand" "")
2582 (match_operand:QI 2 "nonmemory_operand" "")))]
2585 if (expand_a_shift (HImode, ASHIFT, operands))
2589 (define_expand "lshrhi3"
2590 [(set (match_operand:HI 0 "register_operand" "")
2591 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2592 (match_operand:QI 2 "nonmemory_operand" "")))]
2595 if (expand_a_shift (HImode, LSHIFTRT, operands))
2599 (define_expand "ashrhi3"
2600 [(set (match_operand:HI 0 "register_operand" "")
2601 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2602 (match_operand:QI 2 "nonmemory_operand" "")))]
2605 if (expand_a_shift (HImode, ASHIFTRT, operands))
2610 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2611 (match_operator:HI 3 "h8sx_unary_shift_operator"
2612 [(match_operand:HI 1 "h8300_dst_operand" "0")
2613 (match_operand:QI 2 "const_int_operand" "")]))]
2614 "h8300_operands_match_p (operands)"
2616 return output_h8sx_shift (operands, 'w', 'T');
2618 [(set_attr "length_table" "unary")
2619 (set_attr "cc" "set_znv")])
2622 [(set (match_operand:HI 0 "register_operand" "=r")
2623 (match_operator:HI 3 "h8sx_binary_shift_operator"
2624 [(match_operand:HI 1 "register_operand" "0")
2625 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2628 return output_h8sx_shift (operands, 'w', 'T');
2630 [(set_attr "length" "4")
2631 (set_attr "cc" "set_znv")])
2633 (define_insn "*shifthi"
2634 [(set (match_operand:HI 0 "register_operand" "=r,r")
2635 (match_operator:HI 3 "nshift_operator"
2636 [(match_operand:HI 1 "register_operand" "0,0")
2637 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2638 (clobber (match_scratch:QI 4 "=X,&r"))]
2641 return output_a_shift (operands);
2643 [(set (attr "length")
2644 (symbol_ref "compute_a_shift_length (insn, operands)"))
2646 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2650 (define_expand "ashlsi3"
2651 [(set (match_operand:SI 0 "register_operand" "")
2652 (ashift:SI (match_operand:SI 1 "register_operand" "")
2653 (match_operand:QI 2 "nonmemory_operand" "")))]
2656 if (expand_a_shift (SImode, ASHIFT, operands))
2660 (define_expand "lshrsi3"
2661 [(set (match_operand:SI 0 "register_operand" "")
2662 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2663 (match_operand:QI 2 "nonmemory_operand" "")))]
2666 if (expand_a_shift (SImode, LSHIFTRT, operands))
2670 (define_expand "ashrsi3"
2671 [(set (match_operand:SI 0 "register_operand" "")
2672 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2673 (match_operand:QI 2 "nonmemory_operand" "")))]
2676 if (expand_a_shift (SImode, ASHIFTRT, operands))
2681 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2682 (match_operator:SI 3 "h8sx_unary_shift_operator"
2683 [(match_operand:SI 1 "h8300_dst_operand" "0")
2684 (match_operand:QI 2 "const_int_operand" "")]))]
2685 "h8300_operands_match_p (operands)"
2687 return output_h8sx_shift (operands, 'l', 'S');
2689 [(set_attr "length_table" "unary")
2690 (set_attr "cc" "set_znv")])
2693 [(set (match_operand:SI 0 "register_operand" "=r")
2694 (match_operator:SI 3 "h8sx_binary_shift_operator"
2695 [(match_operand:SI 1 "register_operand" "0")
2696 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2699 return output_h8sx_shift (operands, 'l', 'S');
2701 [(set_attr "length" "4")
2702 (set_attr "cc" "set_znv")])
2704 (define_insn "*shiftsi"
2705 [(set (match_operand:SI 0 "register_operand" "=r,r")
2706 (match_operator:SI 3 "nshift_operator"
2707 [(match_operand:SI 1 "register_operand" "0,0")
2708 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2709 (clobber (match_scratch:QI 4 "=X,&r"))]
2712 return output_a_shift (operands);
2714 [(set (attr "length")
2715 (symbol_ref "compute_a_shift_length (insn, operands)"))
2717 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2719 ;; Split a variable shift into a loop. If the register containing
2720 ;; the shift count dies, then we just use that register.
2723 [(set (match_operand 0 "register_operand" "")
2724 (match_operator 2 "nshift_operator"
2726 (match_operand:QI 1 "register_operand" "")]))
2727 (clobber (match_operand:QI 3 "register_operand" ""))]
2729 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2730 [(set (cc0) (compare (match_dup 1) (const_int 0)))
2732 (if_then_else (le (cc0) (const_int 0))
2733 (label_ref (match_dup 5))
2738 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2739 (clobber (scratch:QI))])
2740 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
2741 (set (cc0) (compare (match_dup 1) (const_int 0)))
2743 (if_then_else (ne (cc0) (const_int 0))
2744 (label_ref (match_dup 4))
2748 operands[4] = gen_label_rtx ();
2749 operands[5] = gen_label_rtx ();
2753 [(set (match_operand 0 "register_operand" "")
2754 (match_operator 2 "nshift_operator"
2756 (match_operand:QI 1 "register_operand" "")]))
2757 (clobber (match_operand:QI 3 "register_operand" ""))]
2759 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2762 (set (cc0) (compare (match_dup 3) (const_int 0)))
2764 (if_then_else (le (cc0) (const_int 0))
2765 (label_ref (match_dup 5))
2770 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2771 (clobber (scratch:QI))])
2772 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
2773 (set (cc0) (compare (match_dup 3) (const_int 0)))
2775 (if_then_else (ne (cc0) (const_int 0))
2776 (label_ref (match_dup 4))
2780 operands[4] = gen_label_rtx ();
2781 operands[5] = gen_label_rtx ();
2784 ;; ----------------------------------------------------------------------
2786 ;; ----------------------------------------------------------------------
2788 (define_expand "rotl<mode>3"
2789 [(set (match_operand:QHI 0 "register_operand" "")
2790 (rotate:QHI (match_operand:QHI 1 "register_operand" "")
2791 (match_operand:QI 2 "nonmemory_operand" "")))]
2794 if (expand_a_rotate (operands))
2798 (define_insn "rotl<mode>3_1"
2799 [(set (match_operand:QHI 0 "register_operand" "=r")
2800 (rotate:QHI (match_operand:QHI 1 "register_operand" "0")
2801 (match_operand:QI 2 "immediate_operand" "")))]
2804 return output_a_rotate (ROTATE, operands);
2806 [(set (attr "length")
2807 (symbol_ref "compute_a_rotate_length (operands)"))])
2809 (define_expand "rotlsi3"
2810 [(set (match_operand:SI 0 "register_operand" "")
2811 (rotate:SI (match_operand:SI 1 "register_operand" "")
2812 (match_operand:QI 2 "nonmemory_operand" "")))]
2813 "TARGET_H8300H || TARGET_H8300S"
2815 if (expand_a_rotate (operands))
2819 (define_insn "rotlsi3_1"
2820 [(set (match_operand:SI 0 "register_operand" "=r")
2821 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2822 (match_operand:QI 2 "immediate_operand" "")))]
2823 "TARGET_H8300H || TARGET_H8300S"
2825 return output_a_rotate (ROTATE, operands);
2827 [(set (attr "length")
2828 (symbol_ref "compute_a_rotate_length (operands)"))])
2830 ;; -----------------------------------------------------------------
2832 ;; -----------------------------------------------------------------
2833 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2834 ;; instructions so let's use them as well as we can.
2836 ;; You'll never believe all these patterns perform one basic action --
2837 ;; load a bit from the source, optionally invert the bit, then store it
2838 ;; in the destination (which is known to be zero).
2840 ;; Combine obviously need some work to better identify this situation and
2841 ;; canonicalize the form better.
2844 ;; Normal loads with a 16bit destination.
2848 [(set (match_operand:HI 0 "register_operand" "=&r")
2849 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2851 (match_operand:HI 2 "immediate_operand" "n")))]
2853 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2854 [(set_attr "length" "6")])
2857 ;; Inverted loads with a 16bit destination.
2861 [(set (match_operand:HI 0 "register_operand" "=&r")
2862 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2863 (match_operand:HI 3 "const_int_operand" "n"))
2865 (match_operand:HI 2 "const_int_operand" "n")))]
2866 "(TARGET_H8300 || TARGET_H8300SX)
2867 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2868 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2869 [(set_attr "length" "8")])
2872 ;; Normal loads with a 32bit destination.
2875 (define_insn "*extzv_1_r_h8300"
2876 [(set (match_operand:SI 0 "register_operand" "=&r")
2877 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2879 (match_operand 2 "const_int_operand" "n")))]
2880 "TARGET_H8300 && INTVAL (operands[2]) < 16"
2882 return output_simode_bld (0, operands);
2884 [(set_attr "length" "8")])
2886 (define_insn "*extzv_1_r_h8300hs"
2887 [(set (match_operand:SI 0 "register_operand" "=r,r")
2888 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2890 (match_operand 2 "const_int_operand" "n,n")))]
2891 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
2893 return output_simode_bld (0, operands);
2895 [(set_attr "cc" "set_znv,set_znv")
2896 (set_attr "length" "8,6")])
2899 ;; Inverted loads with a 32bit destination.
2902 (define_insn "*extzv_1_r_inv_h8300"
2903 [(set (match_operand:SI 0 "register_operand" "=&r")
2904 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2905 (match_operand:HI 3 "const_int_operand" "n"))
2907 (match_operand 2 "const_int_operand" "n")))]
2908 "TARGET_H8300 && INTVAL (operands[2]) < 16
2909 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2911 return output_simode_bld (1, operands);
2913 [(set_attr "length" "8")])
2915 (define_insn "*extzv_1_r_inv_h8300hs"
2916 [(set (match_operand:SI 0 "register_operand" "=r,r")
2917 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2918 (match_operand 3 "const_int_operand" "n,n"))
2920 (match_operand 2 "const_int_operand" "n,n")))]
2921 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
2922 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2924 return output_simode_bld (1, operands);
2926 [(set_attr "cc" "set_znv,set_znv")
2927 (set_attr "length" "8,6")])
2929 (define_expand "insv"
2930 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
2931 (match_operand:HI 1 "general_operand" "")
2932 (match_operand:HI 2 "general_operand" ""))
2933 (match_operand:HI 3 "general_operand" ""))]
2934 "TARGET_H8300 || TARGET_H8300SX"
2938 if (GET_CODE (operands[1]) == CONST_INT
2939 && GET_CODE (operands[2]) == CONST_INT
2940 && INTVAL (operands[1]) <= 8
2941 && INTVAL (operands[2]) >= 0
2942 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
2943 && memory_operand (operands[0], GET_MODE (operands[0])))
2945 /* If the source operand is zero, it's better to use AND rather
2946 than BFST. Likewise OR if the operand is all ones. */
2947 if (GET_CODE (operands[3]) == CONST_INT)
2949 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
2950 if ((INTVAL (operands[3]) & mask) == 0)
2952 if ((INTVAL (operands[3]) & mask) == mask)
2955 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
2957 if (!can_create_pseudo_p ())
2959 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode,
2960 XEXP (operands[0], 0)));
2962 operands[3] = gen_lowpart (QImode, operands[3]);
2965 if (! register_operand (operands[3], QImode))
2967 if (!can_create_pseudo_p ())
2969 operands[3] = force_reg (QImode, operands[3]);
2971 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
2972 operands[3], operands[1], operands[2]));
2978 /* We only have single bit bit-field instructions. */
2979 if (INTVAL (operands[1]) != 1)
2982 /* For now, we don't allow memory operands. */
2983 if (GET_CODE (operands[0]) == MEM
2984 || GET_CODE (operands[3]) == MEM)
2987 if (GET_CODE (operands[3]) != REG)
2988 operands[3] = force_reg (HImode, operands[3]);
2992 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2994 (match_operand:HI 1 "immediate_operand" "n"))
2995 (match_operand:HI 2 "register_operand" "r"))]
2997 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2998 [(set_attr "length" "4")])
3000 (define_expand "extzv"
3001 [(set (match_operand:HI 0 "register_operand" "")
3002 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3003 (match_operand:HI 2 "general_operand" "")
3004 (match_operand:HI 3 "general_operand" "")))]
3005 "TARGET_H8300 || TARGET_H8300SX"
3009 if (GET_CODE (operands[2]) == CONST_INT
3010 && GET_CODE (operands[3]) == CONST_INT
3011 && INTVAL (operands[2]) <= 8
3012 && INTVAL (operands[3]) >= 0
3013 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3014 && memory_operand (operands[1], QImode))
3018 /* Optimize the case where we're extracting into a paradoxical
3019 subreg. It's only necessary to extend to the inner reg. */
3020 if (GET_CODE (operands[0]) == SUBREG
3021 && subreg_lowpart_p (operands[0])
3022 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3023 < GET_MODE_SIZE (GET_MODE (operands[0])))
3024 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3026 operands[0] = SUBREG_REG (operands[0]);
3028 if (!can_create_pseudo_p ())
3029 temp = gen_lowpart (QImode, operands[0]);
3031 temp = gen_reg_rtx (QImode);
3034 if (! bit_memory_operand (operands[1], QImode))
3036 if (!can_create_pseudo_p ())
3038 operands[1] = replace_equiv_address (operands[1],
3039 force_reg (Pmode, XEXP (operands[1], 0)));
3041 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3042 convert_move (operands[0], temp, 1);
3048 /* We only have single bit bit-field instructions. */
3049 if (INTVAL (operands[2]) != 1)
3052 /* For now, we don't allow memory operands. */
3053 if (GET_CODE (operands[1]) == MEM)
3057 ;; BAND, BOR, and BXOR patterns
3060 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3061 (match_operator:HI 4 "bit_operator"
3062 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3064 (match_operand:HI 2 "immediate_operand" "n"))
3065 (match_operand:HI 3 "bit_operand" "0")]))]
3067 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3068 [(set_attr "length" "6")])
3071 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3072 (match_operator:HI 5 "bit_operator"
3073 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3075 (match_operand:HI 2 "immediate_operand" "n"))
3076 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3078 (match_operand:HI 4 "immediate_operand" "n"))]))]
3080 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3081 [(set_attr "length" "6")])
3084 [(set (match_operand:QI 0 "register_operand" "=r")
3085 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3086 (match_operand:QI 2 "immediate_operand" "n")
3087 (match_operand:QI 3 "immediate_operand" "n")))]
3088 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3090 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3091 - (1 << INTVAL (operands[3])));
3092 return "bfld %2,%1,%R0";
3094 [(set_attr "cc" "none_0hit")
3095 (set_attr "length_table" "bitfield")])
3098 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3099 (match_operand:QI 2 "immediate_operand" "n")
3100 (match_operand:QI 3 "immediate_operand" "n"))
3101 (match_operand:QI 1 "register_operand" "r"))]
3102 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3104 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3105 - (1 << INTVAL (operands[3])));
3106 return "bfst %R1,%2,%0";
3108 [(set_attr "cc" "none_0hit")
3109 (set_attr "length_table" "bitfield")])
3111 (define_expand "cstoreqi4"
3112 [(use (match_operator 1 "eqne_operator"
3113 [(match_operand:QI 2 "h8300_dst_operand" "")
3114 (match_operand:QI 3 "h8300_src_operand" "")]))
3115 (clobber (match_operand:HI 0 "register_operand"))]
3118 h8300_expand_store (operands);
3122 (define_expand "cstorehi4"
3123 [(use (match_operator 1 "eqne_operator"
3124 [(match_operand:HI 2 "h8300_dst_operand" "")
3125 (match_operand:HI 3 "h8300_src_operand" "")]))
3126 (clobber (match_operand:HI 0 "register_operand"))]
3129 h8300_expand_store (operands);
3133 (define_expand "cstoresi4"
3134 [(use (match_operator 1 "eqne_operator"
3135 [(match_operand:SI 2 "h8300_dst_operand" "")
3136 (match_operand:SI 3 "h8300_src_operand" "")]))
3137 (clobber (match_operand:HI 0 "register_operand"))]
3140 h8300_expand_store (operands);
3144 (define_insn "*bstzhireg"
3145 [(set (match_operand:HI 0 "register_operand" "=r")
3146 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3148 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3149 [(set_attr "cc" "clobber")])
3151 (define_insn_and_split "*cmpstz"
3152 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
3154 (match_operand:QI 1 "immediate_operand" "n,n"))
3155 (match_operator:QI 2 "eqne_operator"
3156 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3157 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3159 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3160 || GET_CODE (operands[4]) == CONST_INT)
3161 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3162 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3165 [(set (cc0) (match_dup 5))
3166 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3167 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3169 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3171 [(set_attr "cc" "set_znv,compare")])
3173 (define_insn "*bstz"
3174 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3176 (match_operand:QI 1 "immediate_operand" "n"))
3177 (eq:QI (cc0) (const_int 0)))]
3178 "TARGET_H8300SX && reload_completed"
3180 [(set_attr "cc" "none_0hit")
3181 (set_attr "length_table" "unary")])
3183 (define_insn "*bistz"
3184 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3186 (match_operand:QI 1 "immediate_operand" "n"))
3187 (ne:QI (cc0) (const_int 0)))]
3188 "TARGET_H8300SX && reload_completed"
3190 [(set_attr "cc" "none_0hit")
3191 (set_attr "length_table" "unary")])
3193 (define_insn_and_split "*cmpcondbset"
3194 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3195 (if_then_else:QI (match_operator 1 "eqne_operator"
3196 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3197 (match_operand 3 "h8300_src_operand" "I,rQi")])
3198 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3199 (match_operand:QI 5 "single_one_operand" "n,n"))
3204 [(set (cc0) (match_dup 6))
3206 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3207 (ior:QI (match_dup 4) (match_dup 5))
3210 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3212 [(set_attr "cc" "set_znv,compare")])
3214 (define_insn "*condbset"
3215 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3216 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3217 [(cc0) (const_int 0)])
3218 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3219 (match_operand:QI 1 "single_one_operand" "n"))
3221 "TARGET_H8300SX && reload_completed"
3223 [(set_attr "cc" "none_0hit")
3224 (set_attr "length_table" "logicb")])
3226 (define_insn_and_split "*cmpcondbclr"
3227 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3228 (if_then_else:QI (match_operator 1 "eqne_operator"
3229 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3230 (match_operand 3 "h8300_src_operand" "I,rQi")])
3231 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3232 (match_operand:QI 5 "single_zero_operand" "n,n"))
3237 [(set (cc0) (match_dup 6))
3239 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3240 (and:QI (match_dup 4) (match_dup 5))
3243 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3245 [(set_attr "cc" "set_znv,compare")])
3247 (define_insn "*condbclr"
3248 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3249 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3250 [(cc0) (const_int 0)])
3251 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3252 (match_operand:QI 1 "single_zero_operand" "n"))
3254 "TARGET_H8300SX && reload_completed"
3256 [(set_attr "cc" "none_0hit")
3257 (set_attr "length_table" "logicb")])
3259 (define_insn_and_split "*cmpcondbsetreg"
3260 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3261 (if_then_else:QI (match_operator 1 "eqne_operator"
3262 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3263 (match_operand 3 "h8300_src_operand" "I,rQi")])
3264 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3265 (ashift:QI (const_int 1)
3266 (match_operand:QI 5 "register_operand" "r,r")))
3271 [(set (cc0) (match_dup 6))
3273 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3274 (ior:QI (match_dup 4)
3275 (ashift:QI (const_int 1)
3276 (match_operand:QI 5 "register_operand" "r,r")))
3279 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3281 [(set_attr "cc" "set_znv,compare")])
3283 (define_insn "*condbsetreg"
3284 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3285 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3286 [(cc0) (const_int 0)])
3287 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3288 (ashift:QI (const_int 1)
3289 (match_operand:QI 1 "register_operand" "r")))
3291 "TARGET_H8300SX && reload_completed"
3293 [(set_attr "cc" "none_0hit")
3294 (set_attr "length_table" "logicb")])
3296 (define_insn_and_split "*cmpcondbclrreg"
3297 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3298 (if_then_else:QI (match_operator 1 "eqne_operator"
3299 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3300 (match_operand 3 "h8300_src_operand" "I,rQi")])
3301 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3302 (ashift:QI (const_int 1)
3303 (match_operand:QI 5 "register_operand" "r,r")))
3308 [(set (cc0) (match_dup 6))
3310 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3311 (and:QI (match_dup 4)
3312 (ashift:QI (const_int 1)
3313 (match_operand:QI 5 "register_operand" "r,r")))
3316 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3318 [(set_attr "cc" "set_znv,compare")])
3320 (define_insn "*condbclrreg"
3321 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3322 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3323 [(cc0) (const_int 0)])
3324 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3325 (ashift:QI (const_int 1)
3326 (match_operand:QI 1 "register_operand" "r")))
3328 "TARGET_H8300SX && reload_completed"
3330 [(set_attr "cc" "none_0hit")
3331 (set_attr "length_table" "logicb")])
3334 ;; -----------------------------------------------------------------
3336 ;; -----------------------------------------------------------------
3340 (define_insn "*insv_si_1_n"
3341 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3343 (match_operand:SI 1 "const_int_operand" "n"))
3344 (match_operand:SI 2 "register_operand" "r"))]
3345 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3346 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3347 [(set_attr "length" "4")])
3349 (define_insn "*insv_si_1_n_lshiftrt"
3350 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3352 (match_operand:SI 1 "const_int_operand" "n"))
3353 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3354 (match_operand:SI 3 "const_int_operand" "n")))]
3355 "(TARGET_H8300H || TARGET_H8300S)
3356 && INTVAL (operands[1]) < 16
3357 && INTVAL (operands[3]) < 16"
3358 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3359 [(set_attr "length" "4")])
3361 (define_insn "*insv_si_1_n_lshiftrt_16"
3362 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3364 (match_operand:SI 1 "const_int_operand" "n"))
3365 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3367 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3368 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3369 [(set_attr "length" "6")])
3371 (define_insn "*insv_si_8_8"
3372 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3375 (match_operand:SI 1 "register_operand" "r"))]
3376 "TARGET_H8300H || TARGET_H8300S"
3378 [(set_attr "length" "2")])
3380 (define_insn "*insv_si_8_8_lshiftrt_8"
3381 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3384 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3386 "TARGET_H8300H || TARGET_H8300S"
3388 [(set_attr "length" "2")])
3392 (define_insn "*extzv_8_8"
3393 [(set (match_operand:SI 0 "register_operand" "=r,r")
3394 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3397 "TARGET_H8300H || TARGET_H8300S"
3399 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3400 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3401 [(set_attr "cc" "set_znv,clobber")
3402 (set_attr "length" "6,4")])
3404 (define_insn "*extzv_8_16"
3405 [(set (match_operand:SI 0 "register_operand" "=r")
3406 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3409 "TARGET_H8300H || TARGET_H8300S"
3410 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3411 [(set_attr "cc" "set_znv")
3412 (set_attr "length" "6")])
3414 (define_insn "*extzv_16_8"
3415 [(set (match_operand:SI 0 "register_operand" "=r")
3416 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3419 (clobber (match_scratch:SI 2 "=&r"))]
3421 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3422 [(set_attr "length" "8")
3423 (set_attr "cc" "set_znv")])
3425 ;; Extract the exponent of a float.
3427 (define_insn_and_split "*extzv_8_23"
3428 [(set (match_operand:SI 0 "register_operand" "=r")
3429 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3432 "(TARGET_H8300H || TARGET_H8300S)"
3434 "&& reload_completed"
3435 [(parallel [(set (match_dup 0)
3436 (ashift:SI (match_dup 0)
3438 (clobber (scratch:QI))])
3439 (parallel [(set (match_dup 0)
3440 (lshiftrt:SI (match_dup 0)
3442 (clobber (scratch:QI))])]
3447 ;; ((SImode) HImode) << 15
3449 (define_insn_and_split "*twoshifts_l16_r1"
3450 [(set (match_operand:SI 0 "register_operand" "=r")
3451 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3453 (const_int 2147450880)))]
3454 "(TARGET_H8300H || TARGET_H8300S)"
3456 "&& reload_completed"
3457 [(parallel [(set (match_dup 0)
3458 (ashift:SI (match_dup 0)
3460 (clobber (scratch:QI))])
3461 (parallel [(set (match_dup 0)
3462 (lshiftrt:SI (match_dup 0)
3464 (clobber (scratch:QI))])]
3467 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3469 (define_insn_and_split "*andsi3_ashift_n_lower"
3470 [(set (match_operand:SI 0 "register_operand" "=r,r")
3471 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3472 (match_operand:QI 2 "const_int_operand" "S,n"))
3473 (match_operand:SI 3 "const_int_operand" "n,n")))
3474 (clobber (match_scratch:QI 4 "=X,&r"))]
3475 "(TARGET_H8300H || TARGET_H8300S)
3476 && INTVAL (operands[2]) <= 15
3477 && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
3480 "&& reload_completed"
3481 [(parallel [(set (match_dup 5)
3482 (ashift:HI (match_dup 5)
3484 (clobber (match_dup 4))])
3486 (zero_extend:SI (match_dup 5)))]
3488 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));
3491 ;; Accept (A >> 30) & 2 and the like.
3493 (define_insn "*andsi3_lshiftrt_n_sb"
3494 [(set (match_operand:SI 0 "register_operand" "=r")
3495 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3496 (match_operand:SI 2 "const_int_operand" "n"))
3497 (match_operand:SI 3 "single_one_operand" "n")))]
3498 "(TARGET_H8300H || TARGET_H8300S)
3499 && exact_log2 (INTVAL (operands[3])) < 16
3500 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3502 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3503 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
3505 [(set_attr "length" "8")])
3507 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3508 [(set (match_operand:SI 0 "register_operand" "=r")
3509 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3511 (const_int 4194304)))]
3512 "TARGET_H8300H || TARGET_H8300S"
3514 "&& reload_completed"
3516 (and:SI (lshiftrt:SI (match_dup 0)
3519 (parallel [(set (match_dup 0)
3520 (ashift:SI (match_dup 0)
3522 (clobber (scratch:QI))])]
3527 (define_insn "*addsi3_upper"
3528 [(set (match_operand:SI 0 "register_operand" "=r")
3529 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3531 (match_operand:SI 2 "register_operand" "0")))]
3532 "TARGET_H8300H || TARGET_H8300S"
3534 [(set_attr "length" "2")])
3536 (define_insn "*addsi3_lshiftrt_16_zexthi"
3537 [(set (match_operand:SI 0 "register_operand" "=r")
3538 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3540 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3541 "TARGET_H8300H || TARGET_H8300S"
3542 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3543 [(set_attr "length" "6")])
3545 (define_insn_and_split "*addsi3_and_r_1"
3546 [(set (match_operand:SI 0 "register_operand" "=r")
3547 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3549 (match_operand:SI 2 "register_operand" "0")))]
3550 "TARGET_H8300H || TARGET_H8300S"
3552 "&& reload_completed"
3553 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3558 (if_then_else (eq (cc0)
3560 (label_ref (match_dup 3))
3563 (plus:SI (match_dup 2)
3567 operands[3] = gen_label_rtx ();
3570 (define_insn_and_split "*addsi3_and_not_r_1"
3571 [(set (match_operand:SI 0 "register_operand" "=r")
3572 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3574 (match_operand:SI 2 "register_operand" "0")))]
3575 "TARGET_H8300H || TARGET_H8300S"
3577 "&& reload_completed"
3578 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3583 (if_then_else (ne (cc0)
3585 (label_ref (match_dup 3))
3588 (plus:SI (match_dup 2)
3592 operands[3] = gen_label_rtx ();
3597 (define_insn "*ixorhi3_zext"
3598 [(set (match_operand:HI 0 "register_operand" "=r")
3599 (match_operator:HI 1 "iorxor_operator"
3600 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3601 (match_operand:HI 3 "register_operand" "0")]))]
3604 [(set_attr "length" "2")])
3608 (define_insn "*ixorsi3_zext_qi"
3609 [(set (match_operand:SI 0 "register_operand" "=r")
3610 (match_operator:SI 1 "iorxor_operator"
3611 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3612 (match_operand:SI 3 "register_operand" "0")]))]
3615 [(set_attr "length" "2")])
3617 (define_insn "*ixorsi3_zext_hi"
3618 [(set (match_operand:SI 0 "register_operand" "=r")
3619 (match_operator:SI 1 "iorxor_operator"
3620 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3621 (match_operand:SI 3 "register_operand" "0")]))]
3622 "TARGET_H8300H || TARGET_H8300S"
3624 [(set_attr "length" "2")])
3626 (define_insn "*ixorsi3_ashift_16"
3627 [(set (match_operand:SI 0 "register_operand" "=r")
3628 (match_operator:SI 1 "iorxor_operator"
3629 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3631 (match_operand:SI 3 "register_operand" "0")]))]
3632 "TARGET_H8300H || TARGET_H8300S"
3634 [(set_attr "length" "2")])
3636 (define_insn "*ixorsi3_lshiftrt_16"
3637 [(set (match_operand:SI 0 "register_operand" "=r")
3638 (match_operator:SI 1 "iorxor_operator"
3639 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3641 (match_operand:SI 3 "register_operand" "0")]))]
3642 "TARGET_H8300H || TARGET_H8300S"
3644 [(set_attr "length" "2")])
3648 (define_insn "*iorhi3_ashift_8"
3649 [(set (match_operand:HI 0 "register_operand" "=r")
3650 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3652 (match_operand:HI 2 "register_operand" "0")))]
3655 [(set_attr "length" "2")])
3657 (define_insn "*iorhi3_lshiftrt_8"
3658 [(set (match_operand:HI 0 "register_operand" "=r")
3659 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3661 (match_operand:HI 2 "register_operand" "0")))]
3664 [(set_attr "length" "2")])
3666 (define_insn "*iorhi3_two_qi"
3667 [(set (match_operand:HI 0 "register_operand" "=r")
3668 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3669 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3673 [(set_attr "length" "2")])
3675 (define_insn "*iorhi3_two_qi_mem"
3676 [(set (match_operand:HI 0 "register_operand" "=&r")
3677 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3678 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3681 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3682 [(set_attr "length" "16")])
3685 [(set (match_operand:HI 0 "register_operand" "")
3686 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3687 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3689 "(TARGET_H8300H || TARGET_H8300S)
3691 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3695 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));
3700 (define_insn "*iorsi3_two_hi"
3701 [(set (match_operand:SI 0 "register_operand" "=r")
3702 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3703 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3705 "TARGET_H8300H || TARGET_H8300S"
3707 [(set_attr "length" "2")])
3709 (define_insn_and_split "*iorsi3_two_qi_zext"
3710 [(set (match_operand:SI 0 "register_operand" "=&r")
3711 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3712 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3714 (const_int 65280))))]
3715 "TARGET_H8300H || TARGET_H8300S"
3717 "&& reload_completed"
3719 (ior:HI (zero_extend:HI (match_dup 1))
3720 (ashift:HI (subreg:HI (match_dup 2) 0)
3723 (zero_extend:SI (match_dup 3)))]
3725 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3728 (define_insn "*iorsi3_e2f"
3729 [(set (match_operand:SI 0 "register_operand" "=r")
3730 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3732 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3734 "TARGET_H8300H || TARGET_H8300S"
3736 [(set_attr "length" "2")])
3738 (define_insn_and_split "*iorsi3_two_qi_sext"
3739 [(set (match_operand:SI 0 "register_operand" "=r")
3740 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3741 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3743 "TARGET_H8300H || TARGET_H8300S"
3745 "&& reload_completed"
3747 (ior:HI (zero_extend:HI (match_dup 1))
3748 (ashift:HI (match_dup 4)
3751 (sign_extend:SI (match_dup 3)))]
3753 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3754 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
3757 (define_insn "*iorsi3_w"
3758 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3759 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3761 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3762 "TARGET_H8300H || TARGET_H8300S"
3764 [(set_attr "length" "2,8")])
3766 (define_insn "*iorsi3_ashift_31"
3767 [(set (match_operand:SI 0 "register_operand" "=&r")
3768 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3770 (match_operand:SI 2 "register_operand" "0")))]
3771 "TARGET_H8300H || TARGET_H8300S"
3772 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3773 [(set_attr "length" "6")
3774 (set_attr "cc" "set_znv")])
3776 (define_insn "*iorsi3_and_ashift"
3777 [(set (match_operand:SI 0 "register_operand" "=r")
3778 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3779 (match_operand:SI 2 "const_int_operand" "n"))
3780 (match_operand:SI 3 "single_one_operand" "n"))
3781 (match_operand:SI 4 "register_operand" "0")))]
3782 "(TARGET_H8300H || TARGET_H8300S)
3783 && (INTVAL (operands[3]) & ~0xffff) == 0"
3785 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3786 - INTVAL (operands[2]));
3787 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3788 operands[2] = srcpos;
3789 operands[3] = dstpos;
3790 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3792 [(set_attr "length" "6")])
3794 (define_insn "*iorsi3_and_lshiftrt"
3795 [(set (match_operand:SI 0 "register_operand" "=r")
3796 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3797 (match_operand:SI 2 "const_int_operand" "n"))
3798 (match_operand:SI 3 "single_one_operand" "n"))
3799 (match_operand:SI 4 "register_operand" "0")))]
3800 "(TARGET_H8300H || TARGET_H8300S)
3801 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3803 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3804 + INTVAL (operands[2]));
3805 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3806 operands[2] = srcpos;
3807 operands[3] = dstpos;
3808 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3810 [(set_attr "length" "6")])
3812 (define_insn "*iorsi3_zero_extract"
3813 [(set (match_operand:SI 0 "register_operand" "=r")
3814 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3816 (match_operand:SI 2 "const_int_operand" "n"))
3817 (match_operand:SI 3 "register_operand" "0")))]
3818 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
3819 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3820 [(set_attr "length" "6")])
3822 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3823 [(set (match_operand:SI 0 "register_operand" "=r")
3824 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3827 (match_operand:SI 2 "register_operand" "0")))]
3828 "TARGET_H8300H || TARGET_H8300S"
3829 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3830 [(set_attr "length" "8")])
3832 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3833 [(set (match_operand:SI 0 "register_operand" "=r")
3834 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3836 (const_int 4194304))
3837 (match_operand:SI 2 "register_operand" "0")))
3838 (clobber (match_scratch:HI 3 "=&r"))]
3839 "TARGET_H8300H || TARGET_H8300S"
3841 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3842 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3844 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3846 [(set_attr "length" "10")])
3848 ;; Used to OR the exponent of a float.
3850 (define_insn "*iorsi3_shift"
3851 [(set (match_operand:SI 0 "register_operand" "=r")
3852 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3854 (match_operand:SI 2 "register_operand" "0")))
3855 (clobber (match_scratch:SI 3 "=&r"))]
3856 "TARGET_H8300H || TARGET_H8300S"
3860 [(set (match_operand:SI 0 "register_operand" "")
3861 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3864 (clobber (match_operand:SI 2 "register_operand" ""))]
3865 "(TARGET_H8300H || TARGET_H8300S)
3866 && epilogue_completed
3867 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3868 && REGNO (operands[0]) != REGNO (operands[1])"
3869 [(parallel [(set (match_dup 3)
3870 (ashift:HI (match_dup 3)
3872 (clobber (scratch:QI))])
3874 (ior:SI (ashift:SI (match_dup 1)
3878 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
3882 [(set (match_operand:SI 0 "register_operand" "")
3883 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3886 (clobber (match_operand:SI 2 "register_operand" ""))]
3887 "(TARGET_H8300H || TARGET_H8300S)
3888 && epilogue_completed
3889 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3890 && REGNO (operands[0]) != REGNO (operands[1]))"
3893 (parallel [(set (match_dup 3)
3894 (ashift:HI (match_dup 3)
3896 (clobber (scratch:QI))])
3898 (ior:SI (ashift:SI (match_dup 2)
3902 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
3905 (define_insn "*iorsi2_and_1_lshiftrt_1"
3906 [(set (match_operand:SI 0 "register_operand" "=r")
3907 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3909 (lshiftrt:SI (match_dup 1)
3911 "TARGET_H8300H || TARGET_H8300S"
3912 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3913 [(set_attr "length" "6")])
3915 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3916 [(set (match_operand:SI 0 "register_operand" "=r")
3917 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3919 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3921 "TARGET_H8300H || TARGET_H8300S"
3923 "&& reload_completed"
3925 (ior:HI (ashift:HI (match_dup 4)
3928 (parallel [(set (match_dup 0)
3929 (ashift:SI (match_dup 0)
3931 (clobber (scratch:QI))])]
3933 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3934 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
3937 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
3938 [(set (match_operand:SI 0 "register_operand" "=&r")
3939 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
3941 (const_int 16711680))
3942 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3944 "TARGET_H8300H || TARGET_H8300S"
3946 "&& reload_completed"
3948 (ior:HI (zero_extend:HI (match_dup 1))
3949 (ashift:HI (subreg:HI (match_dup 2) 0)
3951 (parallel [(set (match_dup 0)
3952 (ashift:SI (match_dup 0)
3954 (clobber (scratch:QI))])]
3956 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3959 ;; Used to add the exponent of a float.
3961 (define_insn "*addsi3_shift"
3962 [(set (match_operand:SI 0 "register_operand" "=r")
3963 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3964 (const_int 8388608))
3965 (match_operand:SI 2 "register_operand" "0")))
3966 (clobber (match_scratch:SI 3 "=&r"))]
3967 "TARGET_H8300H || TARGET_H8300S"
3971 [(set (match_operand:SI 0 "register_operand" "")
3972 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3973 (const_int 8388608))
3975 (clobber (match_operand:SI 2 "register_operand" ""))]
3976 "(TARGET_H8300H || TARGET_H8300S)
3977 && epilogue_completed
3978 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3979 && REGNO (operands[0]) != REGNO (operands[1])"
3980 [(parallel [(set (match_dup 3)
3981 (ashift:HI (match_dup 3)
3983 (clobber (scratch:QI))])
3985 (plus:SI (mult:SI (match_dup 1)
3989 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
3993 [(set (match_operand:SI 0 "register_operand" "")
3994 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3995 (const_int 8388608))
3997 (clobber (match_operand:SI 2 "register_operand" ""))]
3998 "(TARGET_H8300H || TARGET_H8300S)
3999 && epilogue_completed
4000 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4001 && REGNO (operands[0]) != REGNO (operands[1]))"
4004 (parallel [(set (match_dup 3)
4005 (ashift:HI (match_dup 3)
4007 (clobber (scratch:QI))])
4009 (plus:SI (mult:SI (match_dup 2)
4013 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4018 (define_insn_and_split "*ashiftsi_sextqi_7"
4019 [(set (match_operand:SI 0 "register_operand" "=r")
4020 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4022 "TARGET_H8300H || TARGET_H8300S"
4024 "&& reload_completed"
4025 [(parallel [(set (match_dup 2)
4026 (ashift:HI (match_dup 2)
4028 (clobber (scratch:QI))])
4030 (sign_extend:SI (match_dup 2)))
4031 (parallel [(set (match_dup 0)
4032 (ashiftrt:SI (match_dup 0)
4034 (clobber (scratch:QI))])]
4036 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
4039 ;; Storing a part of HImode to QImode.
4042 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4043 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4047 [(set_attr "cc" "set_znv")
4048 (set_attr "length" "8")])
4050 ;; Storing a part of SImode to QImode.
4053 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4054 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4058 [(set_attr "cc" "set_znv")
4059 (set_attr "length" "8")])
4062 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4063 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4065 (clobber (match_scratch:SI 2 "=&r"))]
4066 "TARGET_H8300H || TARGET_H8300S"
4067 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4068 [(set_attr "cc" "set_znv")
4069 (set_attr "length" "10")])
4072 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4073 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4075 (clobber (match_scratch:SI 2 "=&r"))]
4076 "TARGET_H8300H || TARGET_H8300S"
4077 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4078 [(set_attr "cc" "set_znv")
4079 (set_attr "length" "10")])
4081 (define_insn_and_split ""
4083 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4087 (label_ref (match_operand 1 "" ""))
4092 [(set (cc0) (compare (match_dup 0)
4095 (if_then_else (ge (cc0)
4097 (label_ref (match_dup 1))
4101 (define_insn_and_split ""
4103 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4107 (label_ref (match_operand 1 "" ""))
4112 [(set (cc0) (compare (match_dup 0)
4115 (if_then_else (lt (cc0)
4117 (label_ref (match_dup 1))
4121 ;; -----------------------------------------------------------------
4122 ;; PEEPHOLE PATTERNS
4123 ;; -----------------------------------------------------------------
4125 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4128 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4129 (lshiftrt:HI (match_dup 0)
4130 (match_operand:HI 1 "const_int_operand" "")))
4131 (clobber (match_operand:HI 2 "" ""))])
4133 (and:HI (match_dup 0)
4134 (match_operand:HI 3 "const_int_operand" "")))]
4135 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4137 (and:HI (match_dup 0)
4139 (parallel [(set (match_dup 0)
4140 (lshiftrt:HI (match_dup 0) (match_dup 1)))
4141 (clobber (match_dup 2))])]
4144 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4147 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4148 (ashift:HI (match_dup 0)
4149 (match_operand:HI 1 "const_int_operand" "")))
4150 (clobber (match_operand:HI 2 "" ""))])
4152 (and:HI (match_dup 0)
4153 (match_operand:HI 3 "const_int_operand" "")))]
4154 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4156 (and:HI (match_dup 0)
4158 (parallel [(set (match_dup 0)
4159 (ashift:HI (match_dup 0) (match_dup 1)))
4160 (clobber (match_dup 2))])]
4163 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4166 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4167 (lshiftrt:SI (match_dup 0)
4168 (match_operand:SI 1 "const_int_operand" "")))
4169 (clobber (match_operand:SI 2 "" ""))])
4171 (and:SI (match_dup 0)
4172 (match_operand:SI 3 "const_int_operand" "")))]
4173 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4175 (and:SI (match_dup 0)
4177 (parallel [(set (match_dup 0)
4178 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4179 (clobber (match_dup 2))])]
4182 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4185 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4186 (ashift:SI (match_dup 0)
4187 (match_operand:SI 1 "const_int_operand" "")))
4188 (clobber (match_operand:SI 2 "" ""))])
4190 (and:SI (match_dup 0)
4191 (match_operand:SI 3 "const_int_operand" "")))]
4192 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4194 (and:SI (match_dup 0)
4196 (parallel [(set (match_dup 0)
4197 (ashift:SI (match_dup 0) (match_dup 1)))
4198 (clobber (match_dup 2))])]
4201 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4204 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4205 (lshiftrt:SI (match_dup 0)
4206 (match_operand:SI 1 "const_int_operand" "")))
4207 (clobber (match_operand:SI 2 "" ""))])
4209 (and:SI (match_dup 0)
4210 (match_operand:SI 3 "const_int_operand" "")))]
4211 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4213 (and:SI (match_dup 0)
4215 (parallel [(set (match_dup 0)
4216 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4217 (clobber (match_dup 2))])]
4220 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4223 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4224 (ashift:SI (match_dup 0)
4225 (match_operand:SI 1 "const_int_operand" "")))
4226 (clobber (match_operand:SI 2 "" ""))])
4228 (and:SI (match_dup 0)
4229 (match_operand:SI 3 "const_int_operand" "")))]
4230 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4232 (and:SI (match_dup 0)
4234 (parallel [(set (match_dup 0)
4235 (ashift:SI (match_dup 0) (match_dup 1)))
4236 (clobber (match_dup 2))])]
4239 ;; Convert a QImode push into an SImode push so that the
4240 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4243 [(parallel [(set (reg:SI SP_REG)
4244 (plus:SI (reg:SI SP_REG) (const_int -4)))
4245 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4246 (match_operand:QI 0 "register_operand" ""))])]
4247 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4248 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4251 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4255 [(parallel [(set (reg:HI SP_REG)
4256 (plus:HI (reg:HI SP_REG) (const_int -4)))
4257 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4258 (match_operand:QI 0 "register_operand" ""))])]
4259 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4260 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4263 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4266 ;; Convert a HImode push into an SImode push so that the
4267 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4270 [(parallel [(set (reg:SI SP_REG)
4271 (plus:SI (reg:SI SP_REG) (const_int -4)))
4272 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4273 (match_operand:HI 0 "register_operand" ""))])]
4274 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4275 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4278 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4282 [(parallel [(set (reg:HI SP_REG)
4283 (plus:HI (reg:HI SP_REG) (const_int -4)))
4284 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4285 (match_operand:HI 0 "register_operand" ""))])]
4286 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4287 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4290 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4293 ;; Cram four pushes into stm.l.
4296 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4297 (match_operand:SI 0 "register_operand" ""))
4298 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4299 (match_operand:SI 1 "register_operand" ""))
4300 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4301 (match_operand:SI 2 "register_operand" ""))
4302 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4303 (match_operand:SI 3 "register_operand" ""))]
4304 "TARGET_H8300S && !TARGET_NORMAL_MODE
4305 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4306 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4307 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4308 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4309 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4310 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4312 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4314 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4316 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4318 (set (reg:SI SP_REG)
4319 (plus:SI (reg:SI SP_REG)
4320 (const_int -16)))])]
4324 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4325 (match_operand:SI 0 "register_operand" ""))
4326 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4327 (match_operand:SI 1 "register_operand" ""))
4328 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4329 (match_operand:SI 2 "register_operand" ""))
4330 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4331 (match_operand:SI 3 "register_operand" ""))]
4332 "TARGET_H8300S && TARGET_NORMAL_MODE
4333 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4334 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4335 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4336 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4337 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4338 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4340 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4342 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4344 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4346 (set (reg:HI SP_REG)
4347 (plus:HI (reg:HI SP_REG)
4348 (const_int -16)))])]
4351 ;; Cram three pushes into stm.l.
4354 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4355 (match_operand:SI 0 "register_operand" ""))
4356 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4357 (match_operand:SI 1 "register_operand" ""))
4358 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4359 (match_operand:SI 2 "register_operand" ""))]
4360 "TARGET_H8300S && !TARGET_NORMAL_MODE
4361 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4362 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4363 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4364 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4365 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4367 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4369 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4371 (set (reg:SI SP_REG)
4372 (plus:SI (reg:SI SP_REG)
4373 (const_int -12)))])]
4377 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4378 (match_operand:SI 0 "register_operand" ""))
4379 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4380 (match_operand:SI 1 "register_operand" ""))
4381 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4382 (match_operand:SI 2 "register_operand" ""))]
4383 "TARGET_H8300S && TARGET_NORMAL_MODE
4384 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4385 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4386 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4387 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4388 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4390 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4392 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4394 (set (reg:HI SP_REG)
4395 (plus:HI (reg:HI SP_REG)
4396 (const_int -12)))])]
4399 ;; Cram two pushes into stm.l.
4402 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4403 (match_operand:SI 0 "register_operand" ""))
4404 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4405 (match_operand:SI 1 "register_operand" ""))]
4406 "TARGET_H8300S && !TARGET_NORMAL_MODE
4407 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4408 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4409 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4410 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4412 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4414 (set (reg:SI SP_REG)
4415 (plus:SI (reg:SI SP_REG)
4420 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4421 (match_operand:SI 0 "register_operand" ""))
4422 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4423 (match_operand:SI 1 "register_operand" ""))]
4424 "TARGET_H8300S && TARGET_NORMAL_MODE
4425 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4426 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4427 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4428 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4430 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4432 (set (reg:HI SP_REG)
4433 (plus:HI (reg:HI SP_REG)
4440 ;; add.w r7,r0 (6 bytes)
4445 ;; adds #2,r0 (4 bytes)
4448 [(set (match_operand:HI 0 "register_operand" "")
4449 (match_operand:HI 1 "const_int_operand" ""))
4451 (plus:HI (match_dup 0)
4452 (match_operand:HI 2 "register_operand" "")))]
4453 "REG_P (operands[0]) && REG_P (operands[2])
4454 && REGNO (operands[0]) != REGNO (operands[2])
4455 && (satisfies_constraint_J (operands[1])
4456 || satisfies_constraint_L (operands[1])
4457 || satisfies_constraint_N (operands[1]))"
4461 (plus:HI (match_dup 0)
4469 ;; add.l er7,er0 (6 bytes)
4474 ;; adds #4,er0 (4 bytes)
4477 [(set (match_operand:SI 0 "register_operand" "")
4478 (match_operand:SI 1 "const_int_operand" ""))
4480 (plus:SI (match_dup 0)
4481 (match_operand:SI 2 "register_operand" "")))]
4482 "(TARGET_H8300H || TARGET_H8300S)
4483 && REG_P (operands[0]) && REG_P (operands[2])
4484 && REGNO (operands[0]) != REGNO (operands[2])
4485 && (satisfies_constraint_L (operands[1])
4486 || satisfies_constraint_N (operands[1]))"
4490 (plus:SI (match_dup 0)
4497 ;; add.l #10,er0 (takes 8 bytes)
4503 ;; add.l er7,er0 (takes 6 bytes)
4506 [(set (match_operand:SI 0 "register_operand" "")
4507 (match_operand:SI 1 "register_operand" ""))
4509 (plus:SI (match_dup 0)
4510 (match_operand:SI 2 "const_int_operand" "")))]
4511 "(TARGET_H8300H || TARGET_H8300S)
4512 && REG_P (operands[0]) && REG_P (operands[1])
4513 && REGNO (operands[0]) != REGNO (operands[1])
4514 && !satisfies_constraint_L (operands[2])
4515 && !satisfies_constraint_N (operands[2])
4516 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4517 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4518 || INTVAL (operands[2]) == 0xffff
4519 || INTVAL (operands[2]) == 0xfffe)"
4523 (plus:SI (match_dup 0)
4539 [(set (match_operand:HI 0 "register_operand" "")
4540 (plus:HI (match_dup 0)
4541 (match_operand 1 "incdec_operand" "")))
4542 (set (cc0) (compare (match_dup 0)
4545 (if_then_else (match_operator 3 "eqne_operator"
4546 [(cc0) (const_int 0)])
4547 (label_ref (match_operand 2 "" ""))
4549 "TARGET_H8300H || TARGET_H8300S"
4550 [(set (match_operand:HI 0 "register_operand" "")
4551 (unspec:HI [(match_dup 0)
4554 (set (cc0) (compare (match_dup 0)
4557 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4558 (label_ref (match_dup 2))
4562 ;; The SImode version of the previous pattern.
4565 [(set (match_operand:SI 0 "register_operand" "")
4566 (plus:SI (match_dup 0)
4567 (match_operand 1 "incdec_operand" "")))
4568 (set (cc0) (compare (match_dup 0)
4571 (if_then_else (match_operator 3 "eqne_operator"
4572 [(cc0) (const_int 0)])
4573 (label_ref (match_operand 2 "" ""))
4575 "TARGET_H8300H || TARGET_H8300S"
4576 [(set (match_operand:SI 0 "register_operand" "")
4577 (unspec:SI [(match_dup 0)
4580 (set (cc0) (compare (match_dup 0)
4583 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4584 (label_ref (match_dup 2))
4589 [(parallel [(set (cc0)
4590 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4594 (clobber (scratch:QI))])
4596 (if_then_else (match_operator 1 "eqne_operator"
4597 [(cc0) (const_int 0)])
4598 (label_ref (match_operand 2 "" ""))
4600 "TARGET_H8300H || TARGET_H8300S"
4601 [(set (cc0) (compare (match_dup 0)
4604 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4605 (label_ref (match_dup 2))
4608 operands[3] = ((GET_CODE (operands[1]) == EQ)
4609 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4610 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
4613 ;; The next three peephole2's will try to transform
4615 ;; mov.b A,r0l (or mov.l A,er0)
4622 ;; and.b #CST,r0l (if CST is not 255)
4625 [(set (match_operand:QI 0 "register_operand" "")
4626 (match_operand:QI 1 "general_operand" ""))
4627 (set (match_operand:SI 2 "register_operand" "")
4628 (and:SI (match_dup 2)
4630 "(TARGET_H8300H || TARGET_H8300S)
4631 && !reg_overlap_mentioned_p (operands[2], operands[1])
4632 && REGNO (operands[0]) == REGNO (operands[2])"
4635 (set (strict_low_part (match_dup 0))
4640 [(set (match_operand:SI 0 "register_operand" "")
4641 (match_operand:SI 1 "general_operand" ""))
4643 (and:SI (match_dup 0)
4645 "(TARGET_H8300H || TARGET_H8300S)
4646 && !reg_overlap_mentioned_p (operands[0], operands[1])
4647 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4648 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4651 (set (strict_low_part (match_dup 2))
4654 operands[2] = gen_lowpart (QImode, operands[0]);
4655 operands[3] = gen_lowpart (QImode, operands[1]);
4659 [(set (match_operand 0 "register_operand" "")
4660 (match_operand 1 "general_operand" ""))
4661 (set (match_operand:SI 2 "register_operand" "")
4662 (and:SI (match_dup 2)
4663 (match_operand:SI 3 "const_int_qi_operand" "")))]
4664 "(TARGET_H8300H || TARGET_H8300S)
4665 && (GET_MODE (operands[0]) == QImode
4666 || GET_MODE (operands[0]) == HImode
4667 || GET_MODE (operands[0]) == SImode)
4668 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4669 && REGNO (operands[0]) == REGNO (operands[2])
4670 && !reg_overlap_mentioned_p (operands[2], operands[1])
4671 && !(GET_MODE (operands[1]) != QImode
4672 && GET_CODE (operands[1]) == MEM
4673 && !offsettable_memref_p (operands[1]))
4674 && !(GET_MODE (operands[1]) != QImode
4675 && GET_CODE (operands[1]) == MEM
4676 && MEM_VOLATILE_P (operands[1]))"
4679 (set (strict_low_part (match_dup 4))
4682 (and:SI (match_dup 2)
4685 operands[4] = gen_lowpart (QImode, operands[0]);
4686 operands[5] = gen_lowpart (QImode, operands[1]);
4687 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
4691 [(set (match_operand:SI 0 "register_operand" "")
4692 (match_operand:SI 1 "register_operand" ""))
4694 (and:SI (match_dup 0)
4695 (const_int 65280)))]
4696 "(TARGET_H8300H || TARGET_H8300S)
4697 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4700 (set (zero_extract:SI (match_dup 0)
4703 (lshiftrt:SI (match_dup 1)
4707 ;; If a load of mem:SI is followed by an AND that turns off the upper
4708 ;; half, then we can load mem:HI instead.
4711 [(set (match_operand:SI 0 "register_operand" "")
4712 (match_operand:SI 1 "memory_operand" ""))
4714 (and:SI (match_dup 0)
4715 (match_operand:SI 2 "const_int_operand" "")))]
4716 "(TARGET_H8300H || TARGET_H8300S)
4717 && !MEM_VOLATILE_P (operands[1])
4718 && offsettable_memref_p (operands[1])
4719 && (INTVAL (operands[2]) & ~0xffff) == 0
4720 && INTVAL (operands[2]) != 255"
4724 (and:SI (match_dup 0)
4727 operands[3] = gen_lowpart (HImode, operands[0]);
4728 operands[4] = gen_lowpart (HImode, operands[1]);
4731 ;; Convert a memory comparison to a move if there is a scratch register.
4734 [(match_scratch:QI 1 "r")
4736 (compare (match_operand:QI 0 "memory_operand" "")
4741 (set (cc0) (compare (match_dup 1)
4746 [(match_scratch:HI 1 "r")
4748 (compare (match_operand:HI 0 "memory_operand" "")
4750 "TARGET_H8300H || TARGET_H8300S"
4753 (set (cc0) (compare (match_dup 1)
4758 [(match_scratch:SI 1 "r")
4760 (compare (match_operand:SI 0 "memory_operand" "")
4762 "TARGET_H8300H || TARGET_H8300S"
4765 (set (cc0) (compare (match_dup 1)
4770 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4771 ;; the equivalent with shorter sequences. Here is the summary. Cases
4772 ;; are grouped for each define_peephole2.
4774 ;; reg const_int use insn
4775 ;; --------------------------------------------------------
4776 ;; dead -2 eq/ne inc.l
4777 ;; dead -1 eq/ne inc.l
4778 ;; dead 1 eq/ne dec.l
4779 ;; dead 2 eq/ne dec.l
4781 ;; dead 1 ge/lt shar.l
4782 ;; dead 3 (H8S) ge/lt shar.l
4784 ;; dead 1 geu/ltu shar.l
4785 ;; dead 3 (H8S) geu/ltu shar.l
4787 ;; ---- 255 ge/lt mov.b
4789 ;; ---- 255 geu/ltu mov.b
4803 (compare (match_operand:HI 0 "register_operand" "")
4804 (match_operand:HI 1 "incdec_operand" "")))
4806 (if_then_else (match_operator 3 "eqne_operator"
4807 [(cc0) (const_int 0)])
4808 (label_ref (match_operand 2 "" ""))
4810 "(TARGET_H8300H || TARGET_H8300S)
4811 && INTVAL (operands[1]) != 0
4812 && peep2_reg_dead_p (1, operands[0])"
4814 (unspec:HI [(match_dup 0)
4817 (set (cc0) (compare (match_dup 0)
4820 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4821 (label_ref (match_dup 2))
4824 operands[4] = GEN_INT (- INTVAL (operands[1]));
4839 (compare (match_operand:HI 0 "register_operand" "")
4840 (match_operand:HI 1 "const_int_operand" "")))
4842 (if_then_else (match_operator 2 "gtle_operator"
4843 [(cc0) (const_int 0)])
4844 (label_ref (match_operand 3 "" ""))
4846 "(TARGET_H8300H || TARGET_H8300S)
4847 && peep2_reg_dead_p (1, operands[0])
4848 && (INTVAL (operands[1]) == 1
4849 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4850 [(parallel [(set (match_dup 0)
4851 (ashiftrt:HI (match_dup 0)
4853 (clobber (scratch:QI))])
4854 (set (cc0) (compare (match_dup 0)
4857 (if_then_else (match_dup 2)
4858 (label_ref (match_dup 3))
4861 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4876 (compare (match_operand:HI 0 "register_operand" "")
4877 (match_operand:HI 1 "const_int_operand" "")))
4879 (if_then_else (match_operator 2 "gtuleu_operator"
4880 [(cc0) (const_int 0)])
4881 (label_ref (match_operand 3 "" ""))
4883 "(TARGET_H8300H || TARGET_H8300S)
4884 && peep2_reg_dead_p (1, operands[0])
4885 && (INTVAL (operands[1]) == 1
4886 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4887 [(parallel [(set (match_dup 0)
4888 (ashiftrt:HI (match_dup 0)
4890 (clobber (scratch:QI))])
4891 (set (cc0) (compare (match_dup 0)
4894 (if_then_else (match_dup 5)
4895 (label_ref (match_dup 3))
4898 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4899 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4900 VOIDmode, cc0_rtx, const0_rtx);
4915 (compare (match_operand:HI 0 "register_operand" "")
4918 (if_then_else (match_operator 1 "gtle_operator"
4919 [(cc0) (const_int 0)])
4920 (label_ref (match_operand 2 "" ""))
4922 "TARGET_H8300H || TARGET_H8300S"
4923 [(set (cc0) (compare (and:HI (match_dup 0)
4927 (if_then_else (match_dup 1)
4928 (label_ref (match_dup 2))
4944 (compare (match_operand:HI 0 "register_operand" "")
4947 (if_then_else (match_operator 1 "gtuleu_operator"
4948 [(cc0) (const_int 0)])
4949 (label_ref (match_operand 2 "" ""))
4951 "TARGET_H8300H || TARGET_H8300S"
4952 [(set (cc0) (compare (and:HI (match_dup 0)
4956 (if_then_else (match_dup 3)
4957 (label_ref (match_dup 2))
4960 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
4961 VOIDmode, cc0_rtx, const0_rtx);
4964 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
4965 ;; the equivalent with shorter sequences. Here is the summary. Cases
4966 ;; are grouped for each define_peephole2.
4968 ;; reg const_int use insn
4969 ;; --------------------------------------------------------
4970 ;; live -2 eq/ne copy and inc.l
4971 ;; live -1 eq/ne copy and inc.l
4972 ;; live 1 eq/ne copy and dec.l
4973 ;; live 2 eq/ne copy and dec.l
4975 ;; dead -2 eq/ne inc.l
4976 ;; dead -1 eq/ne inc.l
4977 ;; dead 1 eq/ne dec.l
4978 ;; dead 2 eq/ne dec.l
4980 ;; dead -131072 eq/ne inc.w and test
4981 ;; dead -65536 eq/ne inc.w and test
4982 ;; dead 65536 eq/ne dec.w and test
4983 ;; dead 131072 eq/ne dec.w and test
4985 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
4986 ;; dead 0x0000??00 eq/ne xor.b and test
4987 ;; dead 0x0000ffff eq/ne not.w and test
4989 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
4990 ;; dead 0xffff??ff eq/ne xor.b and not.l
4991 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
4992 ;; dead 0x80000000 eq/ne rotl.l and dec.l
4994 ;; live 1 ge/lt copy and shar.l
4995 ;; live 3 (H8S) ge/lt copy and shar.l
4997 ;; live 1 geu/ltu copy and shar.l
4998 ;; live 3 (H8S) geu/ltu copy and shar.l
5000 ;; dead 1 ge/lt shar.l
5001 ;; dead 3 (H8S) ge/lt shar.l
5003 ;; dead 1 geu/ltu shar.l
5004 ;; dead 3 (H8S) geu/ltu shar.l
5006 ;; dead 3 (H8/300H) ge/lt and.b and test
5007 ;; dead 7 ge/lt and.b and test
5008 ;; dead 15 ge/lt and.b and test
5009 ;; dead 31 ge/lt and.b and test
5010 ;; dead 63 ge/lt and.b and test
5011 ;; dead 127 ge/lt and.b and test
5012 ;; dead 255 ge/lt and.b and test
5014 ;; dead 3 (H8/300H) geu/ltu and.b and test
5015 ;; dead 7 geu/ltu and.b and test
5016 ;; dead 15 geu/ltu and.b and test
5017 ;; dead 31 geu/ltu and.b and test
5018 ;; dead 63 geu/ltu and.b and test
5019 ;; dead 127 geu/ltu and.b and test
5020 ;; dead 255 geu/ltu and.b and test
5022 ;; ---- 65535 ge/lt mov.w
5024 ;; ---- 65535 geu/ltu mov.w
5038 (compare (match_operand:SI 0 "register_operand" "")
5039 (match_operand:SI 1 "incdec_operand" "")))
5041 (if_then_else (match_operator 3 "eqne_operator"
5042 [(cc0) (const_int 0)])
5043 (label_ref (match_operand 2 "" ""))
5045 "(TARGET_H8300H || TARGET_H8300S)
5046 && INTVAL (operands[1]) != 0
5047 && peep2_reg_dead_p (1, operands[0])"
5049 (unspec:SI [(match_dup 0)
5052 (set (cc0) (compare (match_dup 0)
5055 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5056 (label_ref (match_dup 2))
5059 operands[4] = GEN_INT (- INTVAL (operands[1]));
5074 (compare (match_operand:SI 0 "register_operand" "")
5075 (match_operand:SI 1 "const_int_operand" "")))
5077 (if_then_else (match_operator 3 "eqne_operator"
5078 [(cc0) (const_int 0)])
5079 (label_ref (match_operand 2 "" ""))
5081 "(TARGET_H8300H || TARGET_H8300S)
5082 && peep2_reg_dead_p (1, operands[0])
5083 && (INTVAL (operands[1]) == -131072
5084 || INTVAL (operands[1]) == -65536
5085 || INTVAL (operands[1]) == 65536
5086 || INTVAL (operands[1]) == 131072)"
5088 (plus:SI (match_dup 0)
5090 (set (cc0) (compare (match_dup 0)
5093 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5094 (label_ref (match_dup 2))
5097 operands[4] = GEN_INT (- INTVAL (operands[1]));
5113 (compare (match_operand:SI 0 "register_operand" "")
5114 (match_operand:SI 1 "const_int_operand" "")))
5116 (if_then_else (match_operator 3 "eqne_operator"
5117 [(cc0) (const_int 0)])
5118 (label_ref (match_operand 2 "" ""))
5120 "(TARGET_H8300H || TARGET_H8300S)
5121 && peep2_reg_dead_p (1, operands[0])
5122 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5123 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5124 || INTVAL (operands[1]) == 0x0000ffff)
5125 && INTVAL (operands[1]) != 0
5126 && INTVAL (operands[1]) != 1
5127 && INTVAL (operands[1]) != 2"
5129 (xor:SI (match_dup 0)
5131 (set (cc0) (compare (match_dup 0)
5134 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5135 (label_ref (match_dup 2))
5152 (compare (match_operand:SI 0 "register_operand" "")
5153 (match_operand:SI 1 "const_int_operand" "")))
5155 (if_then_else (match_operator 3 "eqne_operator"
5156 [(cc0) (const_int 0)])
5157 (label_ref (match_operand 2 "" ""))
5159 "(TARGET_H8300H || TARGET_H8300S)
5160 && peep2_reg_dead_p (1, operands[0])
5161 && ((INTVAL (operands[1]) | 0x00ff) == -1
5162 || (INTVAL (operands[1]) | 0xff00) == -1)
5163 && INTVAL (operands[1]) != -1
5164 && INTVAL (operands[1]) != -2"
5166 (xor:SI (match_dup 0)
5169 (not:SI (match_dup 0)))
5170 (set (cc0) (compare (match_dup 0)
5173 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5174 (label_ref (match_dup 2))
5177 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
5182 ;; cmp.l #-2147483648,er0
5193 (compare (match_operand:SI 0 "register_operand" "")
5194 (match_operand:SI 1 "const_int_operand" "")))
5196 (if_then_else (match_operator 3 "eqne_operator"
5197 [(cc0) (const_int 0)])
5198 (label_ref (match_operand 2 "" ""))
5200 "(TARGET_H8300H || TARGET_H8300S)
5201 && peep2_reg_dead_p (1, operands[0])
5202 && (INTVAL (operands[1]) == -2147483647 - 1
5203 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5205 (rotate:SI (match_dup 0)
5208 (unspec:SI [(match_dup 0)
5211 (set (cc0) (compare (match_dup 0)
5214 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5215 (label_ref (match_dup 2))
5218 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
5232 ;; We avoid this transformation if we see more than one copy of the
5233 ;; same compare insn immediately before this one.
5236 [(match_scratch:SI 4 "r")
5238 (compare (match_operand:SI 0 "register_operand" "")
5239 (match_operand:SI 1 "const_int_operand" "")))
5241 (if_then_else (match_operator 2 "gtle_operator"
5242 [(cc0) (const_int 0)])
5243 (label_ref (match_operand 3 "" ""))
5245 "(TARGET_H8300H || TARGET_H8300S)
5246 && !peep2_reg_dead_p (1, operands[0])
5247 && (INTVAL (operands[1]) == 1
5248 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5249 && !same_cmp_preceding_p (insn)"
5252 (parallel [(set (match_dup 4)
5253 (ashiftrt:SI (match_dup 4)
5255 (clobber (scratch:QI))])
5256 (set (cc0) (compare (match_dup 4)
5259 (if_then_else (match_dup 2)
5260 (label_ref (match_dup 3))
5263 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5277 ;; We avoid this transformation if we see more than one copy of the
5278 ;; same compare insn immediately before this one.
5281 [(match_scratch:SI 4 "r")
5283 (compare (match_operand:SI 0 "register_operand" "")
5284 (match_operand:SI 1 "const_int_operand" "")))
5286 (if_then_else (match_operator 2 "gtuleu_operator"
5287 [(cc0) (const_int 0)])
5288 (label_ref (match_operand 3 "" ""))
5290 "(TARGET_H8300H || TARGET_H8300S)
5291 && !peep2_reg_dead_p (1, operands[0])
5292 && (INTVAL (operands[1]) == 1
5293 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5294 && !same_cmp_preceding_p (insn)"
5297 (parallel [(set (match_dup 4)
5298 (ashiftrt:SI (match_dup 4)
5300 (clobber (scratch:QI))])
5301 (set (cc0) (compare (match_dup 4)
5304 (if_then_else (match_dup 6)
5305 (label_ref (match_dup 3))
5308 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5309 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5310 VOIDmode, cc0_rtx, const0_rtx);
5325 (compare (match_operand:SI 0 "register_operand" "")
5326 (match_operand:SI 1 "const_int_operand" "")))
5328 (if_then_else (match_operator 2 "gtle_operator"
5329 [(cc0) (const_int 0)])
5330 (label_ref (match_operand 3 "" ""))
5332 "(TARGET_H8300H || TARGET_H8300S)
5333 && peep2_reg_dead_p (1, operands[0])
5334 && (INTVAL (operands[1]) == 1
5335 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5336 [(parallel [(set (match_dup 0)
5337 (ashiftrt:SI (match_dup 0)
5339 (clobber (scratch:QI))])
5340 (set (cc0) (compare (match_dup 0)
5343 (if_then_else (match_dup 2)
5344 (label_ref (match_dup 3))
5347 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5362 (compare (match_operand:SI 0 "register_operand" "")
5363 (match_operand:SI 1 "const_int_operand" "")))
5365 (if_then_else (match_operator 2 "gtuleu_operator"
5366 [(cc0) (const_int 0)])
5367 (label_ref (match_operand 3 "" ""))
5369 "(TARGET_H8300H || TARGET_H8300S)
5370 && peep2_reg_dead_p (1, operands[0])
5371 && (INTVAL (operands[1]) == 1
5372 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5373 [(parallel [(set (match_dup 0)
5374 (ashiftrt:SI (match_dup 0)
5376 (clobber (scratch:QI))])
5377 (set (cc0) (compare (match_dup 0)
5380 (if_then_else (match_dup 5)
5381 (label_ref (match_dup 3))
5384 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5385 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5386 VOIDmode, cc0_rtx, const0_rtx);
5402 (compare (match_operand:SI 0 "register_operand" "")
5403 (match_operand:SI 1 "const_int_operand" "")))
5405 (if_then_else (match_operator 2 "gtle_operator"
5406 [(cc0) (const_int 0)])
5407 (label_ref (match_operand 3 "" ""))
5409 "(TARGET_H8300H || TARGET_H8300S)
5410 && peep2_reg_dead_p (1, operands[0])
5411 && (INTVAL (operands[1]) == 3
5412 || INTVAL (operands[1]) == 7
5413 || INTVAL (operands[1]) == 15
5414 || INTVAL (operands[1]) == 31
5415 || INTVAL (operands[1]) == 63
5416 || INTVAL (operands[1]) == 127
5417 || INTVAL (operands[1]) == 255)"
5419 (and:SI (match_dup 0)
5421 (set (cc0) (compare (match_dup 0)
5424 (if_then_else (match_dup 2)
5425 (label_ref (match_dup 3))
5428 operands[4] = GEN_INT (~INTVAL (operands[1]));
5444 (compare (match_operand:SI 0 "register_operand" "")
5445 (match_operand:SI 1 "const_int_operand" "")))
5447 (if_then_else (match_operator 2 "gtuleu_operator"
5448 [(cc0) (const_int 0)])
5449 (label_ref (match_operand 3 "" ""))
5451 "(TARGET_H8300H || TARGET_H8300S)
5452 && peep2_reg_dead_p (1, operands[0])
5453 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5454 || INTVAL (operands[1]) == 7
5455 || INTVAL (operands[1]) == 15
5456 || INTVAL (operands[1]) == 31
5457 || INTVAL (operands[1]) == 63
5458 || INTVAL (operands[1]) == 127
5459 || INTVAL (operands[1]) == 255)"
5461 (and:SI (match_dup 0)
5463 (set (cc0) (compare (match_dup 0)
5466 (if_then_else (match_dup 5)
5467 (label_ref (match_dup 3))
5470 operands[4] = GEN_INT (~INTVAL (operands[1]));
5471 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5472 VOIDmode, cc0_rtx, const0_rtx);
5487 (compare (match_operand:SI 0 "register_operand" "")
5490 (if_then_else (match_operator 1 "gtle_operator"
5491 [(cc0) (const_int 0)])
5492 (label_ref (match_operand 2 "" ""))
5494 "TARGET_H8300H || TARGET_H8300S"
5495 [(set (cc0) (compare (and:SI (match_dup 0)
5499 (if_then_else (match_dup 1)
5500 (label_ref (match_dup 2))
5516 (compare (match_operand:SI 0 "register_operand" "")
5519 (if_then_else (match_operator 1 "gtuleu_operator"
5520 [(cc0) (const_int 0)])
5521 (label_ref (match_operand 2 "" ""))
5523 "TARGET_H8300H || TARGET_H8300S"
5524 [(set (cc0) (compare (and:SI (match_dup 0)
5528 (if_then_else (match_dup 3)
5529 (label_ref (match_dup 2))
5532 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5533 VOIDmode, cc0_rtx, const0_rtx);
5547 ;; We avoid this transformation if we see more than one copy of the
5548 ;; same compare insn.
5551 [(match_scratch:SI 4 "r")
5553 (compare (match_operand:SI 0 "register_operand" "")
5554 (match_operand:SI 1 "incdec_operand" "")))
5556 (if_then_else (match_operator 3 "eqne_operator"
5557 [(cc0) (const_int 0)])
5558 (label_ref (match_operand 2 "" ""))
5560 "(TARGET_H8300H || TARGET_H8300S)
5561 && INTVAL (operands[1]) != 0
5562 && !peep2_reg_dead_p (1, operands[0])
5563 && !same_cmp_following_p (insn)"
5567 (unspec:SI [(match_dup 4)
5570 (set (cc0) (compare (match_dup 4)
5573 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5574 (label_ref (match_dup 2))
5577 operands[5] = GEN_INT (- INTVAL (operands[1]));
5579 ;; Narrow the mode of testing if possible.
5582 [(set (match_operand:HI 0 "register_operand" "")
5583 (and:HI (match_dup 0)
5584 (match_operand:HI 1 "const_int_qi_operand" "")))
5585 (set (cc0) (compare (match_dup 0)
5588 (if_then_else (match_operator 3 "eqne_operator"
5589 [(cc0) (const_int 0)])
5590 (label_ref (match_operand 2 "" ""))
5592 "peep2_reg_dead_p (2, operands[0])"
5594 (and:QI (match_dup 4)
5596 (set (cc0) (compare (match_dup 4)
5599 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5600 (label_ref (match_dup 2))
5603 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5604 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5608 [(set (match_operand:SI 0 "register_operand" "")
5609 (and:SI (match_dup 0)
5610 (match_operand:SI 1 "const_int_qi_operand" "")))
5611 (set (cc0) (compare (match_dup 0)
5614 (if_then_else (match_operator 3 "eqne_operator"
5615 [(cc0) (const_int 0)])
5616 (label_ref (match_operand 2 "" ""))
5618 "peep2_reg_dead_p (2, operands[0])"
5620 (and:QI (match_dup 4)
5622 (set (cc0) (compare (match_dup 4)
5625 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5626 (label_ref (match_dup 2))
5629 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5630 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5634 [(set (match_operand:SI 0 "register_operand" "")
5635 (and:SI (match_dup 0)
5636 (match_operand:SI 1 "const_int_hi_operand" "")))
5637 (set (cc0) (compare (match_dup 0)
5640 (if_then_else (match_operator 3 "eqne_operator"
5641 [(cc0) (const_int 0)])
5642 (label_ref (match_operand 2 "" ""))
5644 "peep2_reg_dead_p (2, operands[0])"
5646 (and:HI (match_dup 4)
5648 (set (cc0) (compare (match_dup 4)
5651 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5652 (label_ref (match_dup 2))
5655 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5656 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);
5660 [(set (match_operand:SI 0 "register_operand" "")
5661 (and:SI (match_dup 0)
5662 (match_operand:SI 1 "const_int_qi_operand" "")))
5664 (xor:SI (match_dup 0)
5665 (match_operand:SI 2 "const_int_qi_operand" "")))
5666 (set (cc0) (compare (match_dup 0)
5669 (if_then_else (match_operator 4 "eqne_operator"
5670 [(cc0) (const_int 0)])
5671 (label_ref (match_operand 3 "" ""))
5673 "peep2_reg_dead_p (3, operands[0])
5674 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5676 (and:QI (match_dup 5)
5679 (xor:QI (match_dup 5)
5681 (set (cc0) (compare (match_dup 5)
5684 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5685 (label_ref (match_dup 3))
5688 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5689 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5690 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);
5693 ;; These triggers right at the end of allocation of locals in the
5694 ;; prologue (and possibly at other places).
5696 ;; stack adjustment of -4, generate one push
5698 ;; before : 6 bytes, 10 clocks
5699 ;; after : 4 bytes, 10 clocks
5702 [(set (reg:SI SP_REG)
5703 (plus:SI (reg:SI SP_REG)
5705 (set (mem:SI (reg:SI SP_REG))
5706 (match_operand:SI 0 "register_operand" ""))]
5707 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5708 && REGNO (operands[0]) != SP_REG"
5709 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5713 ;; stack adjustment of -12, generate one push
5715 ;; before : 10 bytes, 14 clocks
5716 ;; after : 8 bytes, 14 clocks
5719 [(set (reg:SI SP_REG)
5720 (plus:SI (reg:SI SP_REG)
5722 (set (mem:SI (reg:SI SP_REG))
5723 (match_operand:SI 0 "register_operand" ""))]
5724 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5725 && REGNO (operands[0]) != SP_REG"
5726 [(set (reg:SI SP_REG)
5727 (plus:SI (reg:SI SP_REG)
5729 (set (reg:SI SP_REG)
5730 (plus:SI (reg:SI SP_REG)
5732 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5746 ;; if "reg" dies at the end of the sequence.
5749 [(set (match_operand 0 "register_operand" "")
5750 (match_operand 1 "memory_operand" ""))
5752 (match_operator 2 "h8sx_binary_memory_operator"
5754 (match_operand 3 "h8300_src_operand" "")]))
5755 (set (match_operand 4 "memory_operand" "")
5757 "0 /* Disable because it breaks compiling fp-bit.c. */
5759 && peep2_reg_dead_p (3, operands[0])
5760 && !reg_overlap_mentioned_p (operands[0], operands[3])
5761 && !reg_overlap_mentioned_p (operands[0], operands[4])
5762 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
5766 operands[5] = shallow_copy_rtx (operands[2]);
5767 XEXP (operands[5], 0) = operands[1];
5779 ;; if "reg" dies in the second insn.
5782 [(set (match_operand 0 "register_operand" "")
5783 (match_operand 1 "h8300_src_operand" ""))
5784 (set (match_operand 2 "h8300_dst_operand" "")
5785 (match_operator 3 "h8sx_binary_memory_operator"
5786 [(match_operand 4 "h8300_dst_operand" "")
5788 "0 /* Disable because it breaks compiling fp-bit.c. */
5790 && peep2_reg_dead_p (2, operands[0])
5791 && !reg_overlap_mentioned_p (operands[0], operands[4])"
5795 operands[5] = shallow_copy_rtx (operands[3]);
5796 XEXP (operands[5], 1) = operands[1];
5809 ;; if "reg" dies at the end of the sequence.
5812 [(set (match_operand 0 "register_operand" "")
5813 (match_operand 1 "memory_operand" ""))
5815 (match_operator 2 "h8sx_unary_memory_operator"
5817 (set (match_operand 3 "memory_operand" "")
5820 && peep2_reg_dead_p (3, operands[0])
5821 && !reg_overlap_mentioned_p (operands[0], operands[3])
5822 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
5826 operands[4] = shallow_copy_rtx (operands[2]);
5827 XEXP (operands[4], 0) = operands[1];
5839 ;; if "reg" dies in the comparison.
5842 [(set (match_operand 0 "register_operand" "")
5843 (match_operand 1 "h8300_dst_operand" ""))
5845 (compare (match_dup 0)
5846 (match_operand 2 "h8300_src_operand" "")))]
5848 && peep2_reg_dead_p (2, operands[0])
5849 && !reg_overlap_mentioned_p (operands[0], operands[2])
5850 && operands[2] != const0_rtx"
5852 (compare (match_dup 1)
5855 ;; Likewise for the second operand.
5858 [(set (match_operand 0 "register_operand" "")
5859 (match_operand 1 "h8300_src_operand" ""))
5861 (compare (match_operand 2 "h8300_dst_operand" "")
5864 && peep2_reg_dead_p (2, operands[0])
5865 && !reg_overlap_mentioned_p (operands[0], operands[2])"
5867 (compare (match_dup 2)
5870 ;; Combine two moves.
5873 [(set (match_operand 0 "register_operand" "")
5874 (match_operand 1 "h8300_src_operand" ""))
5875 (set (match_operand 2 "h8300_dst_operand" "")
5878 && peep2_reg_dead_p (2, operands[0])
5879 && !reg_overlap_mentioned_p (operands[0], operands[2])"