1 ;; GCC machine description for Renesas H8/300
2 ;; Copyright (C) 1992-2018 Free Software Foundation, Inc.
4 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
5 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;; We compute exact length on each instruction for most of the time.
24 ;; In some case, most notably bit operations that may involve memory
25 ;; operands, the lengths in this file are "worst case".
27 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
28 ;; registers. Right now GCC doesn't expose the "e" half to the
29 ;; compiler, so using add/subs for addhi and subhi is safe. Long
30 ;; term, we want to expose the "e" half to the compiler (gives us 8
31 ;; more 16bit registers). At that point addhi and subhi can't use
34 ;; There's currently no way to have an insv/extzv expander for the H8/300H
35 ;; because word_mode is different for the H8/300 and H8/300H.
37 ;; Shifts/rotates by small constants should be handled by special
38 ;; patterns so we get the length and cc status correct.
40 ;; Bitfield operations no longer accept memory operands. We need
41 ;; to add variants which operate on memory back to the MD.
43 ;; ??? Implement remaining bit ops available on the h8300
45 ;; ----------------------------------------------------------------------
47 ;; ----------------------------------------------------------------------
70 ;; ----------------------------------------------------------------------
72 ;; ----------------------------------------------------------------------
74 (define_attr "cpu" "h8300,h8300h"
75 (const (symbol_ref "cpu_type")))
77 (define_attr "type" "branch,arith,bitbranch,call"
78 (const_string "arith"))
80 (define_attr "length_table" "none,add,logicb,movb,movw,movl,mova_zero,mova,unary,mov_imm4,short_immediate,bitfield,bitbranch"
81 (const_string "none"))
83 ;; The size of instructions in bytes.
85 (define_attr "length" ""
86 (cond [(eq_attr "type" "branch")
87 ;; In a forward delayed branch, (pc) represents the end of the
88 ;; delay sequence, not the end of the branch itself.
89 (if_then_else (and (ge (minus (match_dup 0) (pc))
91 (le (plus (minus (match_dup 0) (pc))
92 (symbol_ref "DELAY_SLOT_LENGTH (insn)"))
95 (if_then_else (and (eq_attr "cpu" "h8300h")
96 (and (ge (minus (pc) (match_dup 0))
98 (le (minus (pc) (match_dup 0))
102 (eq_attr "type" "bitbranch")
103 (if_then_else (and (ge (minus (match_dup 0) (pc))
105 (le (minus (match_dup 0) (pc))
107 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
109 (if_then_else (and (eq_attr "cpu" "h8300h")
110 (and (ge (minus (pc) (match_dup 0))
112 (le (minus (pc) (match_dup 0))
114 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
116 (plus (symbol_ref "h8300_insn_length_from_table (insn, operands)")
118 (eq_attr "length_table" "!none")
119 (symbol_ref "h8300_insn_length_from_table (insn, operands)")]
122 ;; Condition code settings.
124 ;; none - insn does not affect cc
125 ;; none_0hit - insn does not affect cc but it does modify operand 0
126 ;; This attribute is used to keep track of when operand 0 changes.
127 ;; See the description of NOTICE_UPDATE_CC for more info.
128 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
129 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
130 ;; compare - compare instruction
131 ;; clobber - value of cc is unknown
133 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
134 (const_string "clobber"))
136 ;; Type of delay slot. NONE means the instruction has no delay slot.
137 ;; JUMP means it is an unconditional jump that (if short enough)
138 ;; could be implemented using bra/s.
140 (define_attr "delay_slot" "none,jump"
141 (const_string "none"))
143 ;; "yes" if the instruction can be put into a delay slot. It's not
144 ;; entirely clear that jsr is not valid in delay slots, but it
145 ;; definitely doesn't have the effect of causing the called function
146 ;; to return to the target of the delayed branch.
148 (define_attr "can_delay" "no,yes"
149 (cond [(eq_attr "type" "branch,bitbranch,call")
151 (geu (symbol_ref "get_attr_length (insn)") (const_int 2))
153 (const_string "yes")))
155 ;; Only allow jumps to have a delay slot if we think they might
156 ;; be short enough. This is just an optimization: we don't know
157 ;; for certain whether they will be or not.
159 (define_delay (and (eq_attr "delay_slot" "jump")
160 (eq (symbol_ref "get_attr_length (insn)") (const_int 2)))
161 [(eq_attr "can_delay" "yes")
165 ;; Provide the maximum length of an assembly instruction in an asm
166 ;; statement. The maximum length of 14 bytes is achieved on H8SX.
168 (define_asm_attributes
169 [(set (attr "length")
170 (cond [(match_test "TARGET_H8300") (const_int 4)
171 (match_test "TARGET_H8300H") (const_int 10)
172 (match_test "TARGET_H8300S") (const_int 10)]
175 (include "predicates.md")
176 (include "constraints.md")
178 ;; ----------------------------------------------------------------------
180 ;; ----------------------------------------------------------------------
182 ;; This mode iterator allows :P to be used for patterns that operate on
183 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
185 (define_mode_iterator P [(HI "Pmode == HImode") (SI "Pmode == SImode")])
187 (define_mode_iterator QHI [QI HI])
189 (define_mode_iterator HSI [HI SI])
191 (define_mode_iterator QHSI [QI HI SI])
193 (define_mode_iterator QHSIF [QI HI SI SF])
195 (define_code_iterator shifts [ashift ashiftrt lshiftrt])
197 ;; ----------------------------------------------------------------------
199 ;; ----------------------------------------------------------------------
203 (define_insn "*movqi_h8nosx"
204 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
205 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
206 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
207 && h8300_move_ok (operands[0], operands[1])"
215 [(set (attr "length")
216 (symbol_ref "compute_mov_length (operands)"))
217 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
219 (define_insn "*movqi_h8sx"
220 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
221 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
226 [(set_attr "length_table" "mov_imm4,movb")
227 (set_attr "cc" "set_znv")])
229 (define_expand "mov<mode>"
230 [(set (match_operand:QHSIF 0 "general_operand_dst" "")
231 (match_operand:QHSIF 1 "general_operand_src" ""))]
234 enum machine_mode mode = <MODE>mode;
235 if (TARGET_H8300 && (mode == SImode || mode == SFmode))
237 /* The original H8/300 needs to split up 32 bit moves. */
238 if (h8300_expand_movsi (operands))
241 else if (!TARGET_H8300SX)
243 /* Other H8 chips, except the H8/SX family can only handle a
244 single memory operand, which is checked by h8300_move_ok.
246 We could perhaps have h8300_move_ok handle the H8/SX better
247 and just remove the !TARGET_H8300SX conditional. */
248 if (!h8300_move_ok (operands[0], operands[1]))
249 operands[1] = copy_to_mode_reg (mode, operand1);
253 (define_insn "movstrictqi"
254 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
255 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
260 [(set_attr "length" "2,*")
261 (set_attr "length_table" "*,movb")
262 (set_attr "cc" "set_zn,set_znv")])
266 (define_insn "*movhi_h8nosx"
267 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
268 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
269 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
270 && h8300_move_ok (operands[0], operands[1])"
278 [(set (attr "length")
279 (symbol_ref "compute_mov_length (operands)"))
280 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
282 (define_insn "*movhi_h8sx"
283 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
284 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
292 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
293 (set_attr "length" "2,2,*,*,*")
294 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
296 (define_insn "movstricthi"
297 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
298 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
304 [(set_attr "length" "2,2,*")
305 (set_attr "length_table" "*,*,movw")
306 (set_attr "cc" "set_zn,set_znv,set_znv")])
310 (define_insn "*movsi_h8300"
311 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
312 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
314 && h8300_move_ok (operands[0], operands[1])"
316 unsigned int rn = -1;
317 switch (which_alternative)
320 return "sub.w %e0,%e0\;sub.w %f0,%f0";
322 if (REGNO (operands[0]) < REGNO (operands[1]))
323 return "mov.w %e1,%e0\;mov.w %f1,%f0";
325 return "mov.w %f1,%f0\;mov.w %e1,%e0";
327 /* Make sure we don't trample the register we index with. */
328 if (GET_CODE (operands[1]) == MEM)
330 rtx inside = XEXP (operands[1], 0);
335 else if (GET_CODE (inside) == PLUS)
337 rtx lhs = XEXP (inside, 0);
338 rtx rhs = XEXP (inside, 1);
339 if (REG_P (lhs)) rn = REGNO (lhs);
340 if (REG_P (rhs)) rn = REGNO (rhs);
343 if (rn == REGNO (operands[0]))
345 /* Move the second word first. */
346 return "mov.w %f1,%f0\;mov.w %e1,%e0";
350 if (GET_CODE (operands[1]) == CONST_INT)
352 /* If either half is zero, use sub.w to clear that
354 if ((INTVAL (operands[1]) & 0xffff) == 0)
355 return "mov.w %e1,%e0\;sub.w %f0,%f0";
356 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
357 return "sub.w %e0,%e0\;mov.w %f1,%f0";
358 /* If the upper half and the lower half are the same,
359 copy one half to the other. */
360 if ((INTVAL (operands[1]) & 0xffff)
361 == ((INTVAL (operands[1]) >> 16) & 0xffff))
362 return "mov.w\\t%e1,%e0\;mov.w\\t%e0,%f0";
364 return "mov.w %e1,%e0\;mov.w %f1,%f0";
367 return "mov.w %e1,%e0\;mov.w %f1,%f0";
369 return "mov.w %f1,%T0\;mov.w %e1,%T0";
371 return "mov.w %T1,%e0\;mov.w %T1,%f0";
376 [(set (attr "length")
377 (symbol_ref "compute_mov_length (operands)"))])
379 (define_insn "*movsi_h8300hs"
380 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
381 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
382 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
383 && h8300_move_ok (operands[0], operands[1])"
385 switch (which_alternative)
388 return "sub.l %S0,%S0";
392 return "clrmac\;ldmac %1,macl";
394 return "stmac macl,%0";
396 if (GET_CODE (operands[1]) == CONST_INT)
398 int val = INTVAL (operands[1]);
400 /* Look for constants which can be made by adding an 8-bit
401 number to zero in one of the two low bytes. */
402 if (val == (val & 0xff))
404 operands[1] = GEN_INT ((char) val & 0xff);
405 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
408 if (val == (val & 0xff00))
410 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
411 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
414 /* Look for constants that can be obtained by subs, inc, and
416 switch (val & 0xffffffff)
419 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
421 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
423 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
426 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
428 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
431 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
433 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
436 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
438 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
442 return "mov.l %S1,%S0";
444 [(set (attr "length")
445 (symbol_ref "compute_mov_length (operands)"))
446 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
448 (define_insn "*movsi_h8sx"
449 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
450 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
458 clrmac\;ldmac %1,macl
460 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
461 (set_attr "length" "2,2,*,*,2,6,4")
462 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
464 (define_insn "*movsf_h8sx"
465 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
466 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
471 [(set_attr "length" "2,*")
472 (set_attr "length_table" "*,movl")
473 (set_attr "cc" "set_zn,set_znv")])
475 ;; Implement block moves using movmd. Defining movmemsi allows the full
476 ;; range of constant lengths (up to 0x40000 bytes when using movmd.l).
477 ;; See h8sx_emit_movmd for details.
479 (define_expand "movmemsi"
480 [(use (match_operand:BLK 0 "memory_operand" ""))
481 (use (match_operand:BLK 1 "memory_operand" ""))
482 (use (match_operand:SI 2 "" ""))
483 (use (match_operand:SI 3 "const_int_operand" ""))]
486 if (h8sx_emit_movmd (operands[0], operands[1], operands[2], INTVAL (operands[3])))
492 ;; Expander for generating movmd insns. Operand 0 is the destination
493 ;; memory region, operand 1 is the source, operand 2 is the counter
494 ;; register and operand 3 is the chunk size (1, 2 or 4).
496 (define_expand "movmd"
498 [(set (match_operand:BLK 0 "memory_operand" "")
499 (match_operand:BLK 1 "memory_operand" ""))
500 (unspec [(match_operand:HI 2 "register_operand" "")
501 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
502 (clobber (match_dup 4))
503 (clobber (match_dup 5))
508 operands[4] = copy_rtx (XEXP (operands[0], 0));
509 operands[5] = copy_rtx (XEXP (operands[1], 0));
512 ;; This is a difficult instruction to reload since operand 0 must be the
513 ;; frame pointer. See h8300_reg_class_from_letter for an explanation.
515 (define_insn "movmd_internal_<mode>"
516 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
517 (mem:BLK (match_operand:P 4 "register_operand" "1,1")))
518 (unspec [(match_operand:HI 5 "register_operand" "2,2")
519 (match_operand:HI 6 "const_int_operand" "n,n")] UNSPEC_MOVMD)
520 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
521 (clobber (match_operand:P 1 "register_operand" "=f,f"))
522 (set (match_operand:HI 2 "register_operand" "=c,c")
528 [(set_attr "length" "2,14")
529 (set_attr "can_delay" "no")
530 (set_attr "cc" "none,clobber")])
532 ;; Split the above instruction if the destination register isn't er6.
533 ;; We need a sequence like:
541 ;; where <dest> is the current destination register (operand 4).
542 ;; The fourth instruction will be deleted if <dest> dies here.
545 [(set (match_operand:BLK 0 "memory_operand" "")
546 (match_operand:BLK 1 "memory_operand" ""))
547 (unspec [(match_operand:HI 2 "register_operand" "")
548 (match_operand:HI 3 "const_int_operand" "")] UNSPEC_MOVMD)
549 (clobber (match_operand:P 4 "register_operand" ""))
550 (clobber (match_operand:P 5 "register_operand" ""))
553 "TARGET_H8300SX && reload_completed
554 && REGNO (operands[4]) != DESTINATION_REG"
559 h8300_swap_into_er6 (XEXP (operands[0], 0));
560 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
561 emit_insn (gen_movmd (dest, operands[1], operands[2], operands[3]));
562 h8300_swap_out_of_er6 (operands[4]);
566 ;; Expand a call to stpcpy() using movsd. Operand 0 should point to
567 ;; the final character, but movsd leaves it pointing to the character
570 (define_expand "movstr"
571 [(use (match_operand 0 "register_operand" ""))
572 (use (match_operand:BLK 1 "memory_operand" ""))
573 (use (match_operand:BLK 2 "memory_operand" ""))]
576 operands[1] = replace_equiv_address
577 (operands[1], copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
578 operands[2] = replace_equiv_address
579 (operands[2], copy_to_mode_reg (Pmode, XEXP (operands[2], 0)));
580 emit_insn (gen_movsd (operands[1], operands[2], gen_reg_rtx (Pmode)));
581 emit_insn (gen_add3_insn (operands[0], XEXP (operands[1], 0), constm1_rtx));
585 ;; Expander for generating a movsd instruction. Operand 0 is the
586 ;; destination string, operand 1 is the source string and operand 2
587 ;; is a scratch register.
589 (define_expand "movsd"
591 [(set (match_operand:BLK 0 "memory_operand" "")
592 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")]
594 (clobber (match_dup 3))
595 (clobber (match_dup 4))
596 (clobber (match_operand 2 "register_operand" ""))])]
599 operands[3] = copy_rtx (XEXP (operands[0], 0));
600 operands[4] = copy_rtx (XEXP (operands[1], 0));
603 ;; See comments above memcpy_internal().
605 (define_insn "stpcpy_internal_<mode>"
606 [(set (mem:BLK (match_operand:P 3 "register_operand" "0,r"))
607 (unspec:BLK [(mem:BLK (match_operand:P 4 "register_operand" "1,1"))]
609 (clobber (match_operand:P 0 "register_operand" "=d,??D"))
610 (clobber (match_operand:P 1 "register_operand" "=f,f"))
611 (clobber (match_operand:P 2 "register_operand" "=c,c"))]
614 \n1:\tmovsd\t2f\;bra\t1b\n2:
616 [(set_attr "length" "6,18")
617 (set_attr "cc" "none,clobber")])
619 ;; Split the above instruction if the destination isn't er6. This works
620 ;; in the same way as the movmd splitter.
623 [(set (match_operand:BLK 0 "memory_operand" "")
624 (unspec:BLK [(match_operand:BLK 1 "memory_operand" "")] UNSPEC_STPCPY))
625 (clobber (match_operand:P 2 "register_operand" ""))
626 (clobber (match_operand:P 3 "register_operand" ""))
627 (clobber (match_operand:P 4 "register_operand" ""))]
628 "TARGET_H8300SX && reload_completed
629 && REGNO (operands[2]) != DESTINATION_REG"
634 h8300_swap_into_er6 (XEXP (operands[0], 0));
635 dest = replace_equiv_address (operands[0], hard_frame_pointer_rtx);
636 emit_insn (gen_movsd (dest, operands[1], operands[4]));
637 h8300_swap_out_of_er6 (operands[2]);
643 (define_insn "*movsf_h8300"
644 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
645 (match_operand:SF 1 "general_operand_src" "G,r,io,r,r,>"))]
647 && (register_operand (operands[0], SFmode)
648 || register_operand (operands[1], SFmode))"
650 /* Copy of the movsi stuff. */
651 unsigned int rn = -1;
652 switch (which_alternative)
655 return "sub.w %e0,%e0\;sub.w %f0,%f0";
657 if (REGNO (operands[0]) < REGNO (operands[1]))
658 return "mov.w %e1,%e0\;mov.w %f1,%f0";
660 return "mov.w %f1,%f0\;mov.w %e1,%e0";
662 /* Make sure we don't trample the register we index with. */
663 if (GET_CODE (operands[1]) == MEM)
665 rtx inside = XEXP (operands[1], 0);
670 else if (GET_CODE (inside) == PLUS)
672 rtx lhs = XEXP (inside, 0);
673 rtx rhs = XEXP (inside, 1);
674 if (REG_P (lhs)) rn = REGNO (lhs);
675 if (REG_P (rhs)) rn = REGNO (rhs);
678 if (rn == REGNO (operands[0]))
679 /* Move the second word first. */
680 return "mov.w %f1,%f0\;mov.w %e1,%e0";
682 /* Move the first word first. */
683 return "mov.w %e1,%e0\;mov.w %f1,%f0";
686 return "mov.w %e1,%e0\;mov.w %f1,%f0";
688 return "mov.w %f1,%T0\;mov.w %e1,%T0";
690 return "mov.w %T1,%e0\;mov.w %T1,%f0";
695 [(set (attr "length")
696 (symbol_ref "compute_mov_length (operands)"))])
698 (define_insn "*movsf_h8300hs"
699 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
700 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
701 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
702 && (register_operand (operands[0], SFmode)
703 || register_operand (operands[1], SFmode))"
711 [(set (attr "length")
712 (symbol_ref "compute_mov_length (operands)"))
713 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
715 ;; ----------------------------------------------------------------------
717 ;; ----------------------------------------------------------------------
719 (define_insn "*pushqi1_h8300"
723 (plus:HI (reg:HI SP_REG) (const_int -2))))
724 (match_operand:QI 0 "register_no_sp_elim_operand" "r"))]
727 [(set_attr "length" "2")])
729 (define_insn "*push1_h8300hs_<mode>"
733 (plus:P (reg:P SP_REG) (const_int -4))))
734 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
735 "TARGET_H8300H || TARGET_H8300S"
737 [(set_attr "length" "4")])
740 ;; ----------------------------------------------------------------------
742 ;; ----------------------------------------------------------------------
746 (compare (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "r,U")
748 (match_operand 1 "const_int_operand" "n,n"))
752 [(set_attr "length" "2,4")
753 (set_attr "cc" "set_zn,set_zn")])
755 (define_insn_and_split "*tst_extzv_1_n"
757 (compare (zero_extract:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>")
759 (match_operand 1 "const_int_operand" "n,n,n"))
761 (clobber (match_scratch:QI 2 "=X,X,&r"))]
762 "TARGET_H8300H || TARGET_H8300S"
768 && !satisfies_constraint_U (operands[0])"
771 (parallel [(set (cc0) (compare (zero_extract:SI (match_dup 2)
775 (clobber (scratch:QI))])]
777 [(set_attr "length" "2,8,10")
778 (set_attr "cc" "set_zn,set_zn,set_zn")])
782 (compare (zero_extract:HSI (match_operand:HSI 0 "register_operand" "r")
784 (match_operand 1 "const_int_operand" "n"))
786 "(TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
787 && INTVAL (operands[1]) <= 15"
789 [(set_attr "length" "2")
790 (set_attr "cc" "set_zn")])
792 (define_insn_and_split "*tstsi_upper_bit"
794 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
796 (match_operand 1 "const_int_operand" "n"))
798 (clobber (match_scratch:SI 2 "=&r"))]
799 "(TARGET_H8300H || TARGET_H8300S)
800 && INTVAL (operands[1]) >= 16"
802 "&& reload_completed"
804 (ior:SI (and:SI (match_dup 2)
806 (lshiftrt:SI (match_dup 0)
809 (compare (zero_extract:SI (match_dup 2)
814 operands[3] = GEN_INT (INTVAL (operands[1]) - 16);
817 (define_insn "*tstsi_variable_bit"
819 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
821 (and:SI (match_operand:SI 1 "register_operand" "r")
824 "TARGET_H8300H || TARGET_H8300S"
826 [(set_attr "length" "2")
827 (set_attr "cc" "set_zn")])
829 (define_insn_and_split "*tstsi_variable_bit_qi"
831 (compare (zero_extract:SI (zero_extend:SI (match_operand:QI 0 "general_operand_src" "r,U,mn>"))
833 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
836 (clobber (match_scratch:QI 2 "=X,X,&r"))]
837 "TARGET_H8300H || TARGET_H8300S"
843 && !satisfies_constraint_U (operands[0])"
846 (parallel [(set (cc0)
847 (compare (zero_extract:SI (zero_extend:SI (match_dup 2))
849 (and:SI (match_dup 1)
852 (clobber (scratch:QI))])]
854 [(set_attr "length" "2,8,10")
855 (set_attr "cc" "set_zn,set_zn,set_zn")])
857 (define_insn "*tst<mode>"
859 (compare (match_operand:QHI 0 "register_operand" "r")
863 if (<MODE>mode == QImode)
864 return "mov.b %X0,%X0";
865 else if (<MODE>mode == HImode)
866 return "mov.w %T0,%T0";
869 [(set_attr "length" "2")
870 (set_attr "cc" "set_znv")])
872 (define_insn "*tsthi_upper"
874 (compare (and:HI (match_operand:HI 0 "register_operand" "r")
879 [(set_attr "length" "2")
880 (set_attr "cc" "set_znv")])
882 (define_insn "*tstsi"
884 (compare (match_operand:SI 0 "register_operand" "r")
886 "TARGET_H8300H || TARGET_H8300S"
888 [(set_attr "length" "2")
889 (set_attr "cc" "set_znv")])
891 (define_insn "*tstsi_upper"
893 (compare (and:SI (match_operand:SI 0 "register_operand" "r")
898 [(set_attr "length" "2")
899 (set_attr "cc" "set_znv")])
901 (define_insn "*cmpqi"
903 (compare (match_operand:QI 0 "h8300_dst_operand" "rQ")
904 (match_operand:QI 1 "h8300_src_operand" "rQi")))]
907 [(set_attr "length_table" "add")
908 (set_attr "cc" "compare")])
910 (define_insn "*cmphi_h8300_znvc"
912 (compare (match_operand:HI 0 "register_operand" "r")
913 (match_operand:HI 1 "register_operand" "r")))]
916 [(set_attr "length" "2")
917 (set_attr "cc" "compare")])
919 (define_insn "*cmphi_h8300hs_znvc"
921 (compare (match_operand:HI 0 "h8300_dst_operand" "rU,rQ")
922 (match_operand:HI 1 "h8300_src_operand" "P3>X,rQi")))]
923 "TARGET_H8300H || TARGET_H8300S"
925 switch (which_alternative)
929 return "cmp.w %T1,%T0";
931 return "cmp.w %T1:3,%T0";
933 return "cmp.w %T1,%T0";
938 [(set_attr "length_table" "short_immediate,add")
939 (set_attr "cc" "compare,compare")])
943 (compare (match_operand:SI 0 "h8300_dst_operand" "r,rQ")
944 (match_operand:SI 1 "h8300_src_operand" "P3>X,rQi")))]
945 "TARGET_H8300H || TARGET_H8300S"
947 switch (which_alternative)
951 return "cmp.l %S1,%S0";
953 return "cmp.l %S1:3,%S0";
955 return "cmp.l %S1,%S0";
960 [(set_attr "length" "2,*")
961 (set_attr "length_table" "*,add")
962 (set_attr "cc" "compare,compare")])
964 ;; ----------------------------------------------------------------------
966 ;; ----------------------------------------------------------------------
968 (define_expand "add<mode>3"
969 [(set (match_operand:QHSI 0 "register_operand" "")
970 (plus:QHSI (match_operand:QHSI 1 "register_operand" "")
971 (match_operand:QHSI 2 "h8300_src_operand" "")))]
975 (define_insn "*addqi3"
976 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
977 (plus:QI (match_operand:QI 1 "h8300_dst_operand" "%0")
978 (match_operand:QI 2 "h8300_src_operand" "rQi")))]
979 "h8300_operands_match_p (operands)"
981 [(set_attr "length_table" "add")
982 (set_attr "cc" "set_zn")])
984 (define_insn "*addhi3_h8300"
985 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
986 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
987 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
993 add.b %s2,%s0\;addx %t2,%t0
995 [(set_attr "length" "2,2,2,4,2")
996 (set_attr "cc" "none_0hit,none_0hit,clobber,clobber,set_zn")])
998 ;; This splitter is very important to make the stack adjustment
999 ;; interrupt-safe. The combination of add.b and addx is unsafe!
1001 ;; We apply this split after the peephole2 pass so that we won't end
1002 ;; up creating too many adds/subs when a scratch register is
1003 ;; available, which is actually a common case because stack unrolling
1004 ;; tends to happen immediately after a function call.
1007 [(set (match_operand:HI 0 "stack_pointer_operand" "")
1008 (plus:HI (match_dup 0)
1009 (match_operand 1 "const_int_gt_2_operand" "")))]
1010 "TARGET_H8300 && epilogue_completed"
1013 split_adds_subs (HImode, operands);
1018 [(match_scratch:HI 2 "r")
1019 (set (match_operand:HI 0 "stack_pointer_operand" "")
1020 (plus:HI (match_dup 0)
1021 (match_operand:HI 1 "const_int_ge_8_operand" "")))]
1026 (plus:HI (match_dup 0)
1030 (define_insn "*addhi3_h8300hs"
1031 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1032 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
1033 (match_operand:HI 2 "h8300_src_operand" "L,N,J,n,r")))]
1034 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
1041 [(set_attr "length" "2,2,2,4,2")
1042 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
1044 (define_insn "*add<mode>3_incdec"
1045 [(set (match_operand:HSI 0 "register_operand" "=r,r")
1046 (unspec:HSI [(match_operand:HSI 1 "register_operand" "0,0")
1047 (match_operand:HSI 2 "incdec_operand" "M,O")]
1049 "TARGET_H8300H || TARGET_H8300S"
1051 if (which_alternative == 0)
1052 return <MODE>mode == HImode ? "inc.w\t%2,%T0" : "inc.l\t%2,%S0";
1053 else if (which_alternative == 1)
1054 return <MODE>mode == HImode ? "dec.w\t%G2,%T0" : "dec.l\t%G2,%S0";
1057 [(set_attr "length" "2,2")
1058 (set_attr "cc" "set_zn,set_zn")])
1060 (define_insn "*addhi3_h8sx"
1061 [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
1062 (plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
1063 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
1064 "TARGET_H8300SX && h8300_operands_match_p (operands)"
1070 [(set_attr "length_table" "short_immediate,short_immediate,*,add")
1071 (set_attr "length" "*,*,2,*")
1072 (set_attr "cc" "set_zn")])
1075 [(set (match_operand:HI 0 "register_operand" "")
1076 (plus:HI (match_dup 0)
1077 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
1081 split_adds_subs (HImode, operands);
1086 (define_insn "*addsi_h8300"
1087 [(set (match_operand:SI 0 "register_operand" "=r,r")
1088 (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
1089 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
1092 return output_plussi (operands);
1094 [(set (attr "length")
1095 (symbol_ref "compute_plussi_length (operands)"))
1097 (symbol_ref "compute_plussi_cc (operands)"))])
1099 (define_insn "*addsi_h8300hs"
1100 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
1101 (plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
1102 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
1103 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1105 return output_plussi (operands);
1107 [(set (attr "length")
1108 (symbol_ref "compute_plussi_length (operands)"))
1110 (symbol_ref "compute_plussi_cc (operands)"))])
1113 [(set (match_operand:SI 0 "register_operand" "")
1114 (plus:SI (match_dup 0)
1115 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
1116 "TARGET_H8300H || TARGET_H8300S"
1119 split_adds_subs (SImode, operands);
1123 ;; ----------------------------------------------------------------------
1124 ;; SUBTRACT INSTRUCTIONS
1125 ;; ----------------------------------------------------------------------
1127 (define_expand "sub<mode>3"
1128 [(set (match_operand:QHSI 0 "register_operand" "")
1129 (minus:QHSI (match_operand:QHSI 1 "register_operand" "")
1130 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1133 if (TARGET_H8300 && <MODE>mode == SImode)
1134 operands[2] = force_reg (SImode, operands[2]);
1137 (define_insn "*subqi3"
1138 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1139 (minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
1140 (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
1141 "h8300_operands_match_p (operands)"
1143 [(set_attr "length_table" "add")
1144 (set_attr "cc" "set_zn")])
1146 (define_insn "*subhi3_h8300"
1147 [(set (match_operand:HI 0 "register_operand" "=r,r")
1148 (minus:HI (match_operand:HI 1 "register_operand" "0,0")
1149 (match_operand:HI 2 "h8300_src_operand" "r,n")))]
1153 add.b %E2,%s0\;addx %F2,%t0"
1154 [(set_attr "length" "2,4")
1155 (set_attr "cc" "set_zn,clobber")])
1157 (define_insn "*sub<mode>3_h8300hs"
1158 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ,rQ")
1159 (minus:HSI (match_operand:HSI 1 "h8300_dst_operand" "0,0")
1160 (match_operand:HSI 2 "h8300_src_operand" "rQ,i")))]
1161 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1163 if (<MODE>mode == HImode)
1164 return "sub.w %T2,%T0";
1165 else if (<MODE>mode == SImode)
1166 return "sub.l %S2,%S0";
1169 [(set_attr "length_table" "add")
1170 (set_attr "cc" "set_zn")])
1172 (define_insn "*subsi3_h8300"
1173 [(set (match_operand:SI 0 "register_operand" "=r")
1174 (minus:SI (match_operand:SI 1 "register_operand" "0")
1175 (match_operand:SI 2 "register_operand" "r")))]
1177 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
1178 [(set_attr "length" "6")])
1181 ;; ----------------------------------------------------------------------
1182 ;; MULTIPLY INSTRUCTIONS
1183 ;; ----------------------------------------------------------------------
1185 ;; Note that the H8/300 can only handle umulqihi3.
1187 (define_expand "mulqihi3"
1188 [(set (match_operand:HI 0 "register_operand" "")
1189 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
1190 ;; intentionally-mismatched modes
1191 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1192 "TARGET_H8300H || TARGET_H8300S"
1194 if (GET_MODE (operands[2]) != VOIDmode)
1195 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
1198 (define_insn "*mulqihi3_const"
1199 [(set (match_operand:HI 0 "register_operand" "=r")
1200 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1201 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1204 [(set_attr "length" "4")
1205 (set_attr "cc" "set_zn")])
1207 (define_insn "*mulqihi3"
1208 [(set (match_operand:HI 0 "register_operand" "=r")
1209 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1210 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1211 "TARGET_H8300H || TARGET_H8300S"
1213 [(set_attr "length" "4")
1214 (set_attr "cc" "set_zn")])
1216 (define_expand "mulhisi3"
1217 [(set (match_operand:SI 0 "register_operand" "")
1218 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
1219 ;; intentionally-mismatched modes
1220 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1221 "TARGET_H8300H || TARGET_H8300S"
1223 if (GET_MODE (operands[2]) != VOIDmode)
1224 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
1227 (define_insn "*mulhisi3_const"
1228 [(set (match_operand:SI 0 "register_operand" "=r")
1229 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1230 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1233 [(set_attr "length" "4")
1234 (set_attr "cc" "set_zn")])
1236 (define_insn "*mulhisi3"
1237 [(set (match_operand:SI 0 "register_operand" "=r")
1238 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1239 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1240 "TARGET_H8300H || TARGET_H8300S"
1242 [(set_attr "length" "4")
1243 (set_attr "cc" "set_zn")])
1245 (define_expand "umulqihi3"
1246 [(set (match_operand:HI 0 "register_operand" "")
1247 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
1248 ;; intentionally-mismatched modes
1249 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
1250 "TARGET_H8300H || TARGET_H8300S"
1252 if (GET_MODE (operands[2]) != VOIDmode)
1253 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
1256 (define_insn "*umulqihi3_const"
1257 [(set (match_operand:HI 0 "register_operand" "=r")
1258 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1259 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
1262 [(set_attr "length" "4")
1263 (set_attr "cc" "set_zn")])
1265 (define_insn "*umulqihi3"
1266 [(set (match_operand:HI 0 "register_operand" "=r")
1267 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
1268 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
1271 [(set_attr "length" "2")
1272 (set_attr "cc" "none_0hit")])
1274 (define_expand "umulhisi3"
1275 [(set (match_operand:SI 0 "register_operand" "")
1276 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
1277 ;; intentionally-mismatched modes
1278 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
1279 "TARGET_H8300H || TARGET_H8300S"
1281 if (GET_MODE (operands[2]) != VOIDmode)
1282 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
1285 (define_insn "*umulhisi3_const"
1286 [(set (match_operand:SI 0 "register_operand" "=r")
1287 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1288 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
1291 [(set_attr "length" "4")
1292 (set_attr "cc" "set_zn")])
1294 (define_insn "*umulhisi3"
1295 [(set (match_operand:SI 0 "register_operand" "=r")
1296 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
1297 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
1298 "TARGET_H8300H || TARGET_H8300S"
1300 [(set_attr "length" "2")
1301 (set_attr "cc" "none_0hit")])
1303 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
1304 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
1305 ;; on all H8SX variants.
1307 (define_insn "mul<mode>3"
1308 [(set (match_operand:HSI 0 "register_operand" "=r")
1309 (mult:HSI (match_operand:HSI 1 "register_operand" "%0")
1310 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1312 { return <MODE>mode == HImode ? "muls.w\\t%T2,%T0" : "muls.l\\t%S2,%S0"; }
1313 [(set_attr "length" "2")
1314 (set_attr "cc" "set_zn")])
1316 (define_insn "smulsi3_highpart"
1317 [(set (match_operand:SI 0 "register_operand" "=r")
1321 (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1322 (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1325 "muls/u.l\\t%S2,%S0"
1326 [(set_attr "length" "2")
1327 (set_attr "cc" "set_zn")])
1329 (define_insn "umulsi3_highpart"
1330 [(set (match_operand:SI 0 "register_operand" "=r")
1334 (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
1335 (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
1338 "mulu/u.l\\t%S2,%S0"
1339 [(set_attr "length" "2")
1340 (set_attr "cc" "none_0hit")])
1342 ;; This is a "bridge" instruction. Combine can't cram enough insns
1343 ;; together to crate a MAC instruction directly, but it can create
1344 ;; this instruction, which then allows combine to create the real
1347 ;; Unfortunately, if combine doesn't create a MAC instruction, this
1348 ;; insn must generate reasonably correct code. Egad.
1351 [(set (match_operand:SI 0 "register_operand" "=a")
1354 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1356 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
1358 "clrmac\;mac @%2+,@%1+"
1359 [(set_attr "length" "6")
1360 (set_attr "cc" "none_0hit")])
1363 [(set (match_operand:SI 0 "register_operand" "=a")
1365 (sign_extend:SI (mem:HI
1366 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
1367 (sign_extend:SI (mem:HI
1368 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
1369 (match_operand:SI 3 "register_operand" "0")))]
1372 [(set_attr "length" "4")
1373 (set_attr "cc" "none_0hit")])
1375 ;; ----------------------------------------------------------------------
1376 ;; DIVIDE/MOD INSTRUCTIONS
1377 ;; ----------------------------------------------------------------------
1379 (define_insn "udiv<mode>3"
1380 [(set (match_operand:HSI 0 "register_operand" "=r")
1381 (udiv:HSI (match_operand:HSI 1 "register_operand" "0")
1382 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1384 { return <MODE>mode == HImode ? "divu.w\\t%T2,%T0" : "divu.l\\t%S2,%S0"; }
1385 [(set_attr "length" "2")])
1387 (define_insn "div<mode>3"
1388 [(set (match_operand:HSI 0 "register_operand" "=r")
1389 (div:HSI (match_operand:HSI 1 "register_operand" "0")
1390 (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
1392 { return <MODE>mode == HImode ? "divs.w\\t%T2,%T0" : "divs.l\\t%S2,%S0"; }
1393 [(set_attr "length" "2")])
1395 (define_insn "udivmodqi4"
1396 [(set (match_operand:QI 0 "register_operand" "=r")
1399 (match_operand:HI 1 "register_operand" "0")
1400 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1401 (set (match_operand:QI 3 "register_operand" "=r")
1405 (zero_extend:HI (match_dup 2)))))]
1408 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1409 return "divxu.b\\t%X2,%T0";
1411 return "divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1413 [(set_attr "length" "4")])
1415 (define_insn "divmodqi4"
1416 [(set (match_operand:QI 0 "register_operand" "=r")
1419 (match_operand:HI 1 "register_operand" "0")
1420 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
1421 (set (match_operand:QI 3 "register_operand" "=r")
1425 (sign_extend:HI (match_dup 2)))))]
1426 "TARGET_H8300H || TARGET_H8300S"
1428 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1429 return "divxs.b\\t%X2,%T0";
1431 return "divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3";
1433 [(set_attr "length" "6")])
1435 (define_insn "udivmodhi4"
1436 [(set (match_operand:HI 0 "register_operand" "=r")
1439 (match_operand:SI 1 "register_operand" "0")
1440 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1441 (set (match_operand:HI 3 "register_operand" "=r")
1445 (zero_extend:SI (match_dup 2)))))]
1446 "TARGET_H8300H || TARGET_H8300S"
1448 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1449 return "divxu.w\\t%T2,%S0";
1451 return "divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1453 [(set_attr "length" "4")])
1455 (define_insn "divmodhi4"
1456 [(set (match_operand:HI 0 "register_operand" "=r")
1459 (match_operand:SI 1 "register_operand" "0")
1460 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
1461 (set (match_operand:HI 3 "register_operand" "=r")
1465 (sign_extend:SI (match_dup 2)))))]
1466 "TARGET_H8300H || TARGET_H8300S"
1468 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1469 return "divxs.w\\t%T2,%S0";
1471 return "divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3";
1473 [(set_attr "length" "6")])
1475 ;; ----------------------------------------------------------------------
1477 ;; ----------------------------------------------------------------------
1479 (define_insn "bclrqi_msx"
1480 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1481 (and:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1482 (match_operand:QI 2 "single_zero_operand" "Y0")))]
1483 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1485 [(set_attr "length" "8")])
1488 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1489 (and:HI (match_operand:HI 1 "bit_register_indirect_operand")
1490 (match_operand:HI 2 "single_zero_operand")))]
1493 (and:QI (match_dup 1)
1496 if (abs (INTVAL (operands[2])) > 0xFF)
1498 operands[0] = adjust_address (operands[0], QImode, 0);
1499 operands[1] = adjust_address (operands[1], QImode, 0);
1500 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1504 operands[0] = adjust_address (operands[0], QImode, 1);
1505 operands[1] = adjust_address (operands[1], QImode, 1);
1509 (define_insn "bclrhi_msx"
1510 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1511 (and:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1512 (match_operand:HI 2 "single_zero_operand" "Y0")))]
1515 [(set_attr "length" "8")])
1517 (define_insn "*andqi3_2"
1518 [(set (match_operand:QI 0 "bit_operand" "=U,rQ,r")
1519 (and:QI (match_operand:QI 1 "bit_operand" "%0,0,WU")
1520 (match_operand:QI 2 "h8300_src_operand" "Y0,rQi,IP1>X")))]
1526 [(set_attr "length" "8,*,8")
1527 (set_attr "length_table" "*,logicb,*")
1528 (set_attr "cc" "none_0hit,set_znv,none_0hit")])
1530 (define_insn "andqi3_1"
1531 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1532 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1533 (match_operand:QI 2 "h8300_src_operand" "Y0,rn")))]
1534 "register_operand (operands[0], QImode)
1535 || single_zero_operand (operands[2], QImode)"
1539 [(set_attr "length" "2,8")
1540 (set_attr "cc" "none_0hit,set_znv")])
1542 (define_expand "and<mode>3"
1543 [(set (match_operand:QHSI 0 "register_operand" "")
1544 (and:QHSI (match_operand:QHSI 1 "register_operand" "")
1545 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1549 (define_insn "*andor<mode>3"
1550 [(set (match_operand:QHSI 0 "register_operand" "=r")
1551 (ior:QHSI (and:QHSI (match_operand:QHSI 2 "register_operand" "r")
1552 (match_operand:QHSI 3 "single_one_operand" "n"))
1553 (match_operand:QHSI 1 "register_operand" "0")))]
1554 "(<MODE>mode == QImode
1555 || <MODE>mode == HImode
1556 || (<MODE>mode == SImode
1557 && (INTVAL (operands[3]) & 0xffff) != 0))"
1559 if (<MODE>mode == QImode)
1560 return "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0";
1562 if (<MODE>mode == HImode)
1564 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1565 if (INTVAL (operands[3]) > 128)
1567 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1568 return "bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0";
1570 return "bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0";
1573 if (<MODE>mode == SImode)
1575 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1576 if (INTVAL (operands[3]) > 128)
1578 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1579 return "bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0";
1581 return "bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0";
1587 [(set_attr "length" "6")])
1589 (define_insn "*andorsi3_shift_8"
1590 [(set (match_operand:SI 0 "register_operand" "=r")
1591 (ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
1594 (match_operand:SI 1 "register_operand" "0")))]
1597 [(set_attr "length" "2")])
1599 ;; ----------------------------------------------------------------------
1601 ;; ----------------------------------------------------------------------
1603 (define_insn "bsetqi_msx"
1604 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1605 (ior:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1606 (match_operand:QI 2 "single_one_operand" "Y2")))]
1607 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
1609 [(set_attr "length" "8")])
1612 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1613 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand")
1614 (match_operand:HI 2 "single_one_operand")))]
1617 (ior:QI (match_dup 1)
1620 if (abs (INTVAL (operands[2])) > 0xFF)
1622 operands[0] = adjust_address (operands[0], QImode, 0);
1623 operands[1] = adjust_address (operands[1], QImode, 0);
1624 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1628 operands[0] = adjust_address (operands[0], QImode, 1);
1629 operands[1] = adjust_address (operands[1], QImode, 1);
1633 (define_insn "bsethi_msx"
1634 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1635 (ior:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1636 (match_operand:HI 2 "single_one_operand" "Y2")))]
1639 [(set_attr "length" "8")])
1641 (define_insn "iorqi3_1"
1642 [(set (match_operand:QI 0 "bit_operand" "=U,rQ")
1643 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1644 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1645 "TARGET_H8300SX || register_operand (operands[0], QImode)
1646 || single_one_operand (operands[2], QImode)"
1650 [(set_attr "length" "8,*")
1651 (set_attr "length_table" "*,logicb")
1652 (set_attr "cc" "none_0hit,set_znv")])
1654 (define_expand "ior<mode>3"
1655 [(set (match_operand:QHSI 0 "register_operand" "")
1656 (ior:QHSI (match_operand:QHSI 1 "register_operand" "")
1657 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1661 ;; ----------------------------------------------------------------------
1663 ;; ----------------------------------------------------------------------
1665 (define_insn "bnotqi_msx"
1666 [(set (match_operand:QI 0 "bit_register_indirect_operand" "=WU")
1667 (xor:QI (match_operand:QI 1 "bit_register_indirect_operand" "%0")
1668 (match_operand:QI 2 "single_one_operand" "Y2")))]
1670 && rtx_equal_p (operands[0], operands[1])"
1672 [(set_attr "length" "8")])
1675 [(set (match_operand:HI 0 "bit_register_indirect_operand")
1676 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand")
1677 (match_operand:HI 2 "single_one_operand")))]
1680 (xor:QI (match_dup 1)
1683 if (abs (INTVAL (operands[2])) > 0xFF)
1685 operands[0] = adjust_address (operands[0], QImode, 0);
1686 operands[1] = adjust_address (operands[1], QImode, 0);
1687 operands[2] = GEN_INT ((INTVAL (operands[2])) >> 8);
1691 operands[0] = adjust_address (operands[0], QImode, 1);
1692 operands[1] = adjust_address (operands[1], QImode, 1);
1696 (define_insn "bnothi_msx"
1697 [(set (match_operand:HI 0 "bit_register_indirect_operand" "=m")
1698 (xor:HI (match_operand:HI 1 "bit_register_indirect_operand" "%0")
1699 (match_operand:HI 2 "single_one_operand" "Y2")))]
1702 [(set_attr "length" "8")])
1704 (define_insn "xorqi3_1"
1705 [(set (match_operand:QI 0 "bit_operand" "=U,r")
1706 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1707 (match_operand:QI 2 "h8300_src_operand" "Y2,rQi")))]
1708 "TARGET_H8300SX || register_operand (operands[0], QImode)
1709 || single_one_operand (operands[2], QImode)"
1713 [(set_attr "length" "8,*")
1714 (set_attr "length_table" "*,logicb")
1715 (set_attr "cc" "none_0hit,set_znv")])
1717 (define_expand "xor<mode>3"
1718 [(set (match_operand:QHSI 0 "register_operand" "")
1719 (xor:QHSI (match_operand:QHSI 1 "register_operand" "")
1720 (match_operand:QHSI 2 "h8300_src_operand" "")))]
1724 ;; ----------------------------------------------------------------------
1725 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1726 ;; ----------------------------------------------------------------------
1728 ;; We need a separate pattern here because machines other than the
1729 ;; original H8300 don't have to split the 16-bit operand into a pair
1730 ;; of high/low instructions, so we can accept literal addresses, that
1731 ;; have to be loaded into a register on H8300.
1733 (define_insn "*logical<mode>3_sn"
1734 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
1735 (match_operator:HSI 3 "bit_operator"
1736 [(match_operand:HSI 1 "h8300_dst_operand" "%0")
1737 (match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
1738 "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
1740 return output_logical_op (<MODE>mode, operands);
1742 [(set (attr "length")
1743 (symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))
1745 (symbol_ref "compute_logical_op_cc (<MODE>mode, operands)"))])
1747 (define_insn "*logical<mode>3"
1748 [(set (match_operand:HSI 0 "h8300_dst_operand" "=rQ")
1749 (match_operator:HSI 3 "bit_operator"
1750 [(match_operand:HSI 1 "h8300_dst_operand" "%0")
1751 (match_operand:HSI 2 "h8300_src_operand" "rQi")]))]
1752 "h8300_operands_match_p (operands)"
1754 return output_logical_op (<MODE>mode, operands);
1756 [(set (attr "length")
1757 (symbol_ref "compute_logical_op_length (<MODE>mode, operands)"))
1759 (symbol_ref "compute_logical_op_cc (<MODE>mode, operands)"))])
1761 ;; ----------------------------------------------------------------------
1762 ;; NEGATION INSTRUCTIONS
1763 ;; ----------------------------------------------------------------------
1765 (define_expand "neg<mode>2"
1766 [(set (match_operand:QHSIF 0 "register_operand" "")
1767 (neg:QHSIF (match_operand:QHSIF 1 "register_operand" "")))]
1770 enum machine_mode mode = <MODE>mode;
1773 if (mode == QImode || mode == SFmode)
1775 else if (mode == HImode)
1777 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1780 else if (mode == SImode)
1782 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1788 (define_insn "*negqi2"
1789 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1790 (neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1793 [(set_attr "length_table" "unary")
1794 (set_attr "cc" "set_zn")])
1796 (define_expand "neg<mode>2_h8300"
1798 (not:HSI (match_operand:HSI 1 "register_operand" "")))
1799 (set (match_dup 2) (plus:HSI (match_dup 2) (const_int 1)))
1800 (set (match_operand:HSI 0 "register_operand" "")
1804 operands[2] = gen_reg_rtx (<MODE>mode);
1807 (define_insn "*neghi2_h8300hs"
1808 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1809 (neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1810 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1812 [(set_attr "length_table" "unary")
1813 (set_attr "cc" "set_zn")])
1815 (define_insn "*negsi2_h8300hs"
1816 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1817 (neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1818 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1820 [(set_attr "length_table" "unary")
1821 (set_attr "cc" "set_zn")])
1823 (define_insn "*negsf2_h8300"
1824 [(set (match_operand:SF 0 "register_operand" "=r")
1825 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1828 [(set_attr "length" "2")])
1830 (define_insn "*negsf2_h8300hs"
1831 [(set (match_operand:SF 0 "register_operand" "=r")
1832 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
1833 "TARGET_H8300H || TARGET_H8300S"
1834 "xor.w\\t#32768,%e0"
1835 [(set_attr "length" "4")])
1837 ;; ----------------------------------------------------------------------
1838 ;; ABSOLUTE VALUE INSTRUCTIONS
1839 ;; ----------------------------------------------------------------------
1841 (define_expand "abssf2"
1842 [(set (match_operand:SF 0 "register_operand" "")
1843 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1847 (define_insn "*abssf2_h8300"
1848 [(set (match_operand:SF 0 "register_operand" "=r")
1849 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1852 [(set_attr "length" "2")])
1854 (define_insn "*abssf2_h8300hs"
1855 [(set (match_operand:SF 0 "register_operand" "=r")
1856 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
1857 "TARGET_H8300H || TARGET_H8300S"
1858 "and.w\\t#32767,%e0"
1859 [(set_attr "length" "4")])
1861 ;; ----------------------------------------------------------------------
1863 ;; ----------------------------------------------------------------------
1865 (define_expand "one_cmpl<mode>2"
1866 [(set (match_operand:QHSI 0 "register_operand" "")
1867 (not:QHSI (match_operand:QHSI 1 "register_operand" "")))]
1871 (define_insn "*one_cmplqi2"
1872 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
1873 (not:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
1876 [(set_attr "length_table" "unary")
1877 (set_attr "cc" "set_znv")])
1879 (define_insn "*one_cmplhi2_h8300"
1880 [(set (match_operand:HI 0 "register_operand" "=r")
1881 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1884 [(set_attr "length" "4")])
1886 (define_insn "*one_cmplhi2_h8300hs"
1887 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
1888 (not:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
1889 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1891 [(set_attr "cc" "set_znv")
1892 (set_attr "length_table" "unary")])
1894 (define_insn "*one_cmplsi2_h8300"
1895 [(set (match_operand:SI 0 "register_operand" "=r")
1896 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1898 "not %w0\;not %x0\;not %y0\;not %z0"
1899 [(set_attr "length" "8")])
1901 (define_insn "*one_cmplsi2_h8300hs"
1902 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
1903 (not:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
1904 "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
1906 [(set_attr "cc" "set_znv")
1907 (set_attr "length_table" "unary")])
1909 ;; ----------------------------------------------------------------------
1910 ;; JUMP INSTRUCTIONS
1911 ;; ----------------------------------------------------------------------
1913 ;; Conditional jump instructions
1915 (define_expand "cbranchqi4"
1916 [(use (match_operator 0 "ordered_comparison_operator"
1917 [(match_operand:QI 1 "h8300_dst_operand" "")
1918 (match_operand:QI 2 "h8300_src_operand" "")]))
1919 (use (match_operand 3 ""))]
1922 h8300_expand_branch (operands);
1926 (define_expand "cbranchhi4"
1927 [(use (match_operator 0 "ordered_comparison_operator"
1928 [(match_operand:HI 1 "h8300_dst_operand" "")
1929 (match_operand:HI 2 "h8300_src_operand" "")]))
1930 (use (match_operand 3 ""))]
1933 /* Force operand1 into a register if we're compiling
1935 if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
1937 operands[2] = force_reg (HImode, operands[2]);
1938 h8300_expand_branch (operands);
1942 (define_expand "cbranchsi4"
1943 [(use (match_operator 0 "ordered_comparison_operator"
1944 [(match_operand:SI 1 "h8300_dst_operand" "")
1945 (match_operand:SI 2 "h8300_src_operand" "")]))
1946 (use (match_operand 3 ""))]
1947 "TARGET_H8300H || TARGET_H8300S"
1949 h8300_expand_branch (operands);
1953 (define_insn "branch_true"
1955 (if_then_else (match_operator 1 "comparison_operator"
1956 [(cc0) (const_int 0)])
1957 (label_ref (match_operand 0 "" ""))
1961 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1962 && (GET_CODE (operands[1]) == GT
1963 || GET_CODE (operands[1]) == GE
1964 || GET_CODE (operands[1]) == LE
1965 || GET_CODE (operands[1]) == LT))
1967 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1971 if (get_attr_length (insn) == 2)
1973 else if (get_attr_length (insn) == 4)
1974 return "b%j1 %l0:16";
1976 return "b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
1978 [(set_attr "type" "branch")
1979 (set_attr "cc" "none")])
1981 (define_insn "branch_false"
1983 (if_then_else (match_operator 1 "comparison_operator"
1984 [(cc0) (const_int 0)])
1986 (label_ref (match_operand 0 "" ""))))]
1989 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1990 && (GET_CODE (operands[1]) == GT
1991 || GET_CODE (operands[1]) == GE
1992 || GET_CODE (operands[1]) == LE
1993 || GET_CODE (operands[1]) == LT))
1995 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1999 if (get_attr_length (insn) == 2)
2001 else if (get_attr_length (insn) == 4)
2002 return "b%k1 %l0:16";
2004 return "b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2006 [(set_attr "type" "branch")
2007 (set_attr "cc" "none")])
2009 (define_insn "*brabc"
2011 (if_then_else (eq (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2013 (match_operand:QI 2 "immediate_operand" "n"))
2015 (label_ref (match_operand 0 "" ""))
2019 switch (get_attr_length (insn)
2020 - h8300_insn_length_from_table (insn, operands))
2023 return "bra/bc %2,%R1,%l0";
2025 return "bra/bc %2,%R1,%l0:16";
2027 return "bra/bs %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2030 [(set_attr "type" "bitbranch")
2031 (set_attr "length_table" "bitbranch")
2032 (set_attr "cc" "none")])
2034 (define_insn "*brabs"
2036 (if_then_else (ne (zero_extract (match_operand:QI 1 "bit_memory_operand" "WU")
2038 (match_operand:QI 2 "immediate_operand" "n"))
2040 (label_ref (match_operand 0 "" ""))
2044 switch (get_attr_length (insn)
2045 - h8300_insn_length_from_table (insn, operands))
2048 return "bra/bs %2,%R1,%l0";
2050 return "bra/bs %2,%R1,%l0:16";
2052 return "bra/bc %2,%R1,.Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:";
2055 [(set_attr "type" "bitbranch")
2056 (set_attr "length_table" "bitbranch")
2057 (set_attr "cc" "none")])
2059 ;; Unconditional and other jump instructions.
2063 (label_ref (match_operand 0 "" "")))]
2066 if (final_sequence != 0)
2068 if (get_attr_length (insn) == 2)
2072 /* The branch isn't short enough to use bra/s. Output the
2073 branch and delay slot in their normal order.
2075 If this is a backward branch, it will now be branching two
2076 bytes further than previously thought. The length-based
2077 test for bra vs. jump is very conservative though, so the
2078 branch will still be within range. */
2082 seq = final_sequence;
2084 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, & seen);
2085 final_scan_insn (seq->insn (0), asm_out_file, optimize, 1, & seen);
2086 seq->insn (1)->set_deleted ();
2090 else if (get_attr_length (insn) == 2)
2092 else if (get_attr_length (insn) == 4)
2093 return "bra %l0:16";
2097 [(set_attr "type" "branch")
2098 (set (attr "delay_slot")
2099 (if_then_else (match_test "TARGET_H8300SX")
2100 (const_string "jump")
2101 (const_string "none")))
2102 (set_attr "cc" "none")])
2104 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2106 (define_expand "tablejump"
2107 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
2108 (use (label_ref (match_operand 1 "" "")))])]
2112 (define_insn "*tablejump_h8300"
2113 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2114 (use (label_ref (match_operand 1 "" "")))]
2117 [(set_attr "cc" "none")
2118 (set_attr "length" "2")])
2120 (define_insn "*tablejump_h8300hs_advanced"
2121 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
2122 (use (label_ref (match_operand 1 "" "")))]
2123 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2125 [(set_attr "cc" "none")
2126 (set_attr "length" "2")])
2128 (define_insn "*tablejump_h8300hs_normal"
2129 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
2130 (use (label_ref (match_operand 1 "" "")))]
2131 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2133 [(set_attr "cc" "none")
2134 (set_attr "length" "2")])
2136 ;; This is a define expand, because pointers may be either 16 or 32 bits.
2138 (define_expand "indirect_jump"
2139 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
2143 (define_insn "*indirect_jump_h8300"
2144 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2147 [(set_attr "cc" "none")
2148 (set_attr "length" "2")])
2150 (define_insn "*indirect_jump_h8300hs_advanced"
2151 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
2152 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE"
2154 [(set_attr "cc" "none")
2155 (set_attr "length" "2")])
2157 (define_insn "*indirect_jump_h8300hs_normal"
2158 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
2159 "(TARGET_H8300H || TARGET_H8300S) && TARGET_NORMAL_MODE"
2161 [(set_attr "cc" "none")
2162 (set_attr "length" "2")])
2164 ;; Call subroutine with no return value.
2166 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2169 [(call (match_operand:QI 0 "call_insn_operand" "or")
2170 (match_operand:HI 1 "general_operand" "g"))]
2173 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2174 && (SYMBOL_REF_FLAGS (XEXP (operands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2175 return "jsr\\t@%0:8";
2179 [(set_attr "type" "call")
2180 (set (attr "length")
2181 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2185 ;; Call subroutine, returning value in operand 0
2186 ;; (which must be a hard register).
2188 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
2190 (define_insn "call_value"
2191 [(set (match_operand 0 "" "=r")
2192 (call (match_operand:QI 1 "call_insn_operand" "or")
2193 (match_operand:HI 2 "general_operand" "g")))]
2196 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2197 && (SYMBOL_REF_FLAGS (XEXP (operands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2198 return "jsr\\t@%1:8";
2202 [(set_attr "type" "call")
2203 (set (attr "length")
2204 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
2212 [(set_attr "cc" "none")
2213 (set_attr "length" "2")])
2215 ;; ----------------------------------------------------------------------
2216 ;; PROLOGUE/EPILOGUE-RELATED INSTRUCTIONS
2217 ;; ----------------------------------------------------------------------
2219 (define_expand "push_h8300"
2220 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
2221 (match_operand:HI 0 "register_operand" ""))]
2225 (define_expand "push_h8300hs_advanced"
2226 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
2227 (match_operand:SI 0 "register_operand" ""))]
2228 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2231 (define_expand "push_h8300hs_normal"
2232 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
2233 (match_operand:SI 0 "register_operand" ""))]
2234 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2237 (define_expand "pop_h8300"
2238 [(set (match_operand:HI 0 "register_operand" "")
2239 (mem:HI (post_inc:HI (reg:HI SP_REG))))]
2243 (define_expand "pop_h8300hs_advanced"
2244 [(set (match_operand:SI 0 "register_operand" "")
2245 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
2246 "TARGET_H8300H && TARGET_H8300S && !TARGET_NORMAL_MODE"
2249 (define_expand "pop_h8300hs_normal"
2250 [(set (match_operand:SI 0 "register_operand" "")
2251 (mem:SI (post_inc:HI (reg:HI SP_REG))))]
2252 "TARGET_H8300H && TARGET_H8300S && TARGET_NORMAL_MODE"
2255 (define_insn "ldm_h8300sx"
2256 [(match_parallel 0 "h8300_ldm_parallel"
2257 [(set (match_operand:SI 1 "register_operand" "")
2258 (match_operand:SI 2 "memory_operand" ""))])]
2261 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2262 XVECLEN (operands[0], 0) - 2));
2263 return "ldm.l\t@er7+,%S1-%S3";
2265 [(set_attr "cc" "none")
2266 (set_attr "length" "4")])
2268 (define_insn "stm_h8300sx"
2269 [(match_parallel 0 "h8300_stm_parallel"
2270 [(set (match_operand:SI 1 "memory_operand" "")
2271 (match_operand:SI 2 "register_operand" ""))])]
2274 operands[3] = SET_SRC (XVECEXP (operands[0], 0,
2275 XVECLEN (operands[0], 0) - 2));
2276 return "stm.l\t%S2-%S3,@-er7";
2278 [(set_attr "cc" "none")
2279 (set_attr "length" "4")])
2281 (define_insn "return_h8sx"
2282 [(match_parallel 0 "h8300_return_parallel"
2284 (set (match_operand:SI 1 "register_operand" "")
2285 (match_operand:SI 2 "memory_operand" ""))])]
2288 operands[3] = SET_DEST (XVECEXP (operands[0], 0,
2289 XVECLEN (operands[0], 0) - 2));
2290 if (h8300_current_function_interrupt_function_p ()
2291 || h8300_current_function_monitor_function_p ())
2292 return "rte/l\t%S1-%S3";
2294 return "rts/l\t%S1-%S3";
2296 [(set_attr "cc" "none")
2297 (set_attr "can_delay" "no")
2298 (set_attr "length" "2")])
2300 (define_expand "return"
2302 "h8300_can_use_return_insn_p ()"
2305 (define_insn "*return_1"
2309 if (h8300_current_function_interrupt_function_p ()
2310 || h8300_current_function_monitor_function_p ())
2315 [(set_attr "cc" "none")
2316 (set_attr "can_delay" "no")
2317 (set_attr "length" "2")])
2319 (define_expand "prologue"
2323 h8300_expand_prologue ();
2327 (define_expand "epilogue"
2331 h8300_expand_epilogue ();
2335 (define_insn "monitor_prologue"
2336 [(unspec_volatile [(const_int 0)] UNSPEC_MONITOR)]
2340 return "subs\\t#2,r7\;mov.w\\tr0,@-r7\;stc\\tccr,r0l\;mov.b\tr0l,@(2,r7)\;mov.w\\t@r7+,r0\;orc\t#128,ccr";
2341 else if (TARGET_H8300H && TARGET_NORMAL_MODE)
2342 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2343 else if (TARGET_H8300H)
2344 return "mov.l\\ter0,@-er7\;stc\\tccr,r0l\;mov.b\\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\\t#128,ccr";
2345 else if (TARGET_H8300S && TARGET_NEXR )
2346 return "mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2347 else if (TARGET_H8300S && TARGET_NEXR && TARGET_NORMAL_MODE)
2348 return "subs\\t#2,er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(4,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2349 else if (TARGET_H8300S && TARGET_NORMAL_MODE)
2350 return "subs\\t#2,er7\;stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2351 else if (TARGET_H8300S)
2352 return "stc\texr,@-er7\;mov.l\\ter0,@-er7\;stc\tccr,r0l\;mov.b\tr0l,@(6,er7)\;mov.l\\t@er7+,er0\;orc\t#128,ccr";
2355 [(set_attr "length" "20")])
2357 ;; ----------------------------------------------------------------------
2358 ;; EXTEND INSTRUCTIONS
2359 ;; ----------------------------------------------------------------------
2361 (define_expand "zero_extendqi<mode>2"
2362 [(set (match_operand:HSI 0 "register_operand" "")
2363 (zero_extend:HSI (match_operand:QI 1 "general_operand_src" "")))]
2367 operands[1] = force_reg (QImode, operands[1]);
2370 (define_insn "*zero_extendqihi2_h8300"
2371 [(set (match_operand:HI 0 "register_operand" "=r,r")
2372 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2377 [(set_attr "length" "2,10")])
2379 (define_insn "*zero_extendqihi2_h8300hs"
2380 [(set (match_operand:HI 0 "register_operand" "=r,r")
2381 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2382 "TARGET_H8300H || TARGET_H8300S"
2386 [(set_attr "length" "2,10")
2387 (set_attr "cc" "set_znv,set_znv")])
2389 ;; Split the zero extension of a general operand (actually a memory
2390 ;; operand) into a load of the operand and the actual zero extension
2391 ;; so that 1) the length will be accurate, and 2) the zero extensions
2392 ;; appearing at the end of basic blocks may be merged.
2395 [(set (match_operand:HI 0 "register_operand" "")
2396 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
2401 (zero_extend:HI (match_dup 2)))]
2403 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2407 (define_insn "*zero_extendqisi2_h8300"
2408 [(set (match_operand:SI 0 "register_operand" "=r,r")
2409 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2412 mov.b #0,%x0\;sub.w %e0,%e0
2413 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
2414 [(set_attr "length" "4,8")])
2416 (define_insn "*zero_extendqisi2_h8300hs"
2417 [(set (match_operand:SI 0 "register_operand" "=r,r")
2418 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2419 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2423 [(set (match_operand:SI 0 "register_operand" "")
2424 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2425 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2426 && reg_overlap_mentioned_p (operands[0], operands[1])
2427 && reload_completed"
2431 (zero_extend:HI (match_dup 2)))
2433 (zero_extend:SI (match_dup 3)))]
2435 operands[2] = gen_lowpart (QImode, operands[0]);
2436 operands[3] = gen_lowpart (HImode, operands[0]);
2440 [(set (match_operand:SI 0 "register_operand" "")
2441 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "")))]
2442 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX
2443 && !reg_overlap_mentioned_p (operands[0], operands[1])
2444 && reload_completed"
2447 (set (strict_low_part (match_dup 2))
2450 operands[2] = gen_rtx_REG (QImode, REGNO (operands[0]));
2453 (define_insn "*zero_extendqisi2_h8sx"
2454 [(set (match_operand:SI 0 "register_operand" "=r")
2455 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2458 [(set_attr "length" "2")
2459 (set_attr "cc" "set_znv")])
2461 (define_expand "zero_extendhisi2"
2462 [(set (match_operand:SI 0 "register_operand" "")
2463 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2467 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
2468 (define_insn "*zero_extendhisi2_h8300"
2469 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2470 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
2474 mov.w %f1,%f0\;sub.w %e0,%e0
2475 mov.w %e1,%f0\;sub.w %e0,%e0"
2476 [(set_attr "length" "2,4,6")])
2478 (define_insn "*zero_extendhisi2_h8300hs"
2479 [(set (match_operand:SI 0 "register_operand" "=r")
2480 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2481 "TARGET_H8300H || TARGET_H8300S"
2483 [(set_attr "length" "2")
2484 (set_attr "cc" "set_znv")])
2486 (define_expand "extendqi<mode>2"
2487 [(set (match_operand:HSI 0 "register_operand" "")
2488 (sign_extend:HSI (match_operand:QI 1 "register_operand" "")))]
2492 (define_insn "*extendqihi2_h8300"
2493 [(set (match_operand:HI 0 "register_operand" "=r,r")
2494 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2497 bld #7,%s0\;subx %t0,%t0
2498 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
2499 [(set_attr "length" "4,8")])
2501 (define_insn "*extendqihi2_h8300hs"
2502 [(set (match_operand:HI 0 "register_operand" "=r")
2503 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
2504 "TARGET_H8300H || TARGET_H8300S"
2506 [(set_attr "length" "2")
2507 (set_attr "cc" "set_znv")])
2509 (define_insn "*extendqisi2_h8300"
2510 [(set (match_operand:SI 0 "register_operand" "=r,r")
2511 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
2514 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
2515 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
2516 [(set_attr "length" "8,12")])
2518 ;; The following pattern is needed because without the pattern, the
2519 ;; combiner would split (sign_extend:SI (reg:QI)) into two 24-bit
2520 ;; shifts, one ashift and one ashiftrt.
2522 (define_insn_and_split "*extendqisi2_h8300hs"
2523 [(set (match_operand:SI 0 "register_operand" "=r")
2524 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2525 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_H8300SX"
2527 "&& reload_completed"
2529 (sign_extend:HI (match_dup 1)))
2531 (sign_extend:SI (match_dup 2)))]
2533 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
2536 (define_insn "*extendqisi2_h8sx"
2537 [(set (match_operand:SI 0 "register_operand" "=r")
2538 (sign_extend:SI (match_operand:QI 1 "register_operand" "0")))]
2541 [(set_attr "length" "2")
2542 (set_attr "cc" "set_znv")])
2544 (define_expand "extendhisi2"
2545 [(set (match_operand:SI 0 "register_operand" "")
2546 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2550 (define_insn "*extendhisi2_h8300"
2551 [(set (match_operand:SI 0 "register_operand" "=r,r")
2552 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
2555 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
2556 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
2557 [(set_attr "length" "6,10")])
2559 (define_insn "*extendhisi2_h8300hs"
2560 [(set (match_operand:SI 0 "register_operand" "=r")
2561 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
2562 "TARGET_H8300H || TARGET_H8300S"
2564 [(set_attr "length" "2")
2565 (set_attr "cc" "set_znv")])
2567 ;; ----------------------------------------------------------------------
2569 ;; ----------------------------------------------------------------------
2571 ;; We make some attempt to provide real efficient shifting. One example is
2572 ;; doing an 8-bit shift of a 16-bit value by moving a byte reg into the other
2573 ;; reg and moving 0 into the former reg.
2575 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
2576 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
2577 ;; give the optimizer more cracks at the code. However, we wish to do things
2578 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
2579 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
2580 ;; 16-bit rotates. Also, if we emit complicated rtl, combine may not be able
2581 ;; to detect cases it can optimize.
2583 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
2584 ;; easier "do it at insn emit time" route.
2588 (define_expand "ashlqi3"
2589 [(set (match_operand:QI 0 "register_operand" "")
2590 (ashift:QI (match_operand:QI 1 "register_operand" "")
2591 (match_operand:QI 2 "nonmemory_operand" "")))]
2594 if (expand_a_shift (QImode, ASHIFT, operands))
2598 (define_expand "ashrqi3"
2599 [(set (match_operand:QI 0 "register_operand" "")
2600 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
2601 (match_operand:QI 2 "nonmemory_operand" "")))]
2604 if (expand_a_shift (QImode, ASHIFTRT, operands))
2608 (define_expand "lshrqi3"
2609 [(set (match_operand:QI 0 "register_operand" "")
2610 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
2611 (match_operand:QI 2 "nonmemory_operand" "")))]
2614 if (expand_a_shift (QImode, LSHIFTRT, operands))
2619 [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
2620 (match_operator:QI 3 "h8sx_unary_shift_operator"
2621 [(match_operand:QI 1 "h8300_dst_operand" "0")
2622 (match_operand:QI 2 "const_int_operand" "")]))]
2623 "h8300_operands_match_p (operands)"
2625 return output_h8sx_shift (operands, 'b', 'X');
2627 [(set_attr "length_table" "unary")
2628 (set_attr "cc" "set_znv")])
2631 [(set (match_operand:QI 0 "register_operand" "=r")
2632 (match_operator:QI 3 "h8sx_binary_shift_operator"
2633 [(match_operand:QI 1 "register_operand" "0")
2634 (match_operand:QI 2 "nonmemory_operand" "r P3>X")]))]
2637 return output_h8sx_shift (operands, 'b', 'X');
2639 [(set_attr "length" "4")
2640 (set_attr "cc" "set_znv")])
2642 (define_insn "*shiftqi"
2643 [(set (match_operand:QI 0 "register_operand" "=r,r")
2644 (match_operator:QI 3 "nshift_operator"
2645 [(match_operand:QI 1 "register_operand" "0,0")
2646 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
2647 (clobber (match_scratch:QI 4 "=X,&r"))]
2650 return output_a_shift (operands);
2652 [(set (attr "length")
2653 (symbol_ref "compute_a_shift_length (insn, operands)"))
2655 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2659 (define_expand "ashlhi3"
2660 [(set (match_operand:HI 0 "register_operand" "")
2661 (ashift:HI (match_operand:HI 1 "register_operand" "")
2662 (match_operand:QI 2 "nonmemory_operand" "")))]
2665 if (expand_a_shift (HImode, ASHIFT, operands))
2669 (define_expand "lshrhi3"
2670 [(set (match_operand:HI 0 "register_operand" "")
2671 (lshiftrt:HI (match_operand:HI 1 "register_operand" "")
2672 (match_operand:QI 2 "nonmemory_operand" "")))]
2675 if (expand_a_shift (HImode, LSHIFTRT, operands))
2679 (define_expand "ashrhi3"
2680 [(set (match_operand:HI 0 "register_operand" "")
2681 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
2682 (match_operand:QI 2 "nonmemory_operand" "")))]
2685 if (expand_a_shift (HImode, ASHIFTRT, operands))
2690 [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
2691 (match_operator:HI 3 "h8sx_unary_shift_operator"
2692 [(match_operand:HI 1 "h8300_dst_operand" "0")
2693 (match_operand:QI 2 "const_int_operand" "")]))]
2694 "h8300_operands_match_p (operands)"
2696 return output_h8sx_shift (operands, 'w', 'T');
2698 [(set_attr "length_table" "unary")
2699 (set_attr "cc" "set_znv")])
2702 [(set (match_operand:HI 0 "register_operand" "=r")
2703 (match_operator:HI 3 "h8sx_binary_shift_operator"
2704 [(match_operand:HI 1 "register_operand" "0")
2705 (match_operand:QI 2 "nonmemory_operand" "r P4>X")]))]
2708 return output_h8sx_shift (operands, 'w', 'T');
2710 [(set_attr "length" "4")
2711 (set_attr "cc" "set_znv")])
2713 (define_insn "*shifthi"
2714 [(set (match_operand:HI 0 "register_operand" "=r,r")
2715 (match_operator:HI 3 "nshift_operator"
2716 [(match_operand:HI 1 "register_operand" "0,0")
2717 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
2718 (clobber (match_scratch:QI 4 "=X,&r"))]
2721 return output_a_shift (operands);
2723 [(set (attr "length")
2724 (symbol_ref "compute_a_shift_length (insn, operands)"))
2726 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2730 (define_expand "ashlsi3"
2731 [(set (match_operand:SI 0 "register_operand" "")
2732 (ashift:SI (match_operand:SI 1 "register_operand" "")
2733 (match_operand:QI 2 "nonmemory_operand" "")))]
2736 if (expand_a_shift (SImode, ASHIFT, operands))
2740 (define_expand "lshrsi3"
2741 [(set (match_operand:SI 0 "register_operand" "")
2742 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
2743 (match_operand:QI 2 "nonmemory_operand" "")))]
2746 if (expand_a_shift (SImode, LSHIFTRT, operands))
2750 (define_expand "ashrsi3"
2751 [(set (match_operand:SI 0 "register_operand" "")
2752 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
2753 (match_operand:QI 2 "nonmemory_operand" "")))]
2756 if (expand_a_shift (SImode, ASHIFTRT, operands))
2761 [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
2762 (match_operator:SI 3 "h8sx_unary_shift_operator"
2763 [(match_operand:SI 1 "h8300_dst_operand" "0")
2764 (match_operand:QI 2 "const_int_operand" "")]))]
2765 "h8300_operands_match_p (operands)"
2767 return output_h8sx_shift (operands, 'l', 'S');
2769 [(set_attr "length_table" "unary")
2770 (set_attr "cc" "set_znv")])
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (match_operator:SI 3 "h8sx_binary_shift_operator"
2775 [(match_operand:SI 1 "register_operand" "0")
2776 (match_operand:QI 2 "nonmemory_operand" "r P5>X")]))]
2779 return output_h8sx_shift (operands, 'l', 'S');
2781 [(set_attr "length" "4")
2782 (set_attr "cc" "set_znv")])
2784 (define_insn "*shiftsi"
2785 [(set (match_operand:SI 0 "register_operand" "=r,r")
2786 (match_operator:SI 3 "nshift_operator"
2787 [(match_operand:SI 1 "register_operand" "0,0")
2788 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
2789 (clobber (match_scratch:QI 4 "=X,&r"))]
2792 return output_a_shift (operands);
2794 [(set (attr "length")
2795 (symbol_ref "compute_a_shift_length (insn, operands)"))
2797 (symbol_ref "compute_a_shift_cc (insn, operands)"))])
2799 ;; Split a variable shift into a loop. If the register containing
2800 ;; the shift count dies, then we just use that register.
2803 [(set (match_operand 0 "register_operand" "")
2804 (match_operator 2 "nshift_operator"
2806 (match_operand:QI 1 "register_operand" "")]))
2807 (clobber (match_operand:QI 3 "register_operand" ""))]
2809 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2810 [(set (cc0) (compare (match_dup 1) (const_int 0)))
2812 (if_then_else (le (cc0) (const_int 0))
2813 (label_ref (match_dup 5))
2818 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2819 (clobber (scratch:QI))])
2820 (set (match_dup 1) (plus:QI (match_dup 1) (const_int -1)))
2821 (set (cc0) (compare (match_dup 1) (const_int 0)))
2823 (if_then_else (ne (cc0) (const_int 0))
2824 (label_ref (match_dup 4))
2828 operands[4] = gen_label_rtx ();
2829 operands[5] = gen_label_rtx ();
2833 [(set (match_operand 0 "register_operand" "")
2834 (match_operator 2 "nshift_operator"
2836 (match_operand:QI 1 "register_operand" "")]))
2837 (clobber (match_operand:QI 3 "register_operand" ""))]
2839 && !find_regno_note (insn, REG_DEAD, REGNO (operands[1]))"
2842 (set (cc0) (compare (match_dup 3) (const_int 0)))
2844 (if_then_else (le (cc0) (const_int 0))
2845 (label_ref (match_dup 5))
2850 (match_op_dup 2 [(match_dup 0) (const_int 1)]))
2851 (clobber (scratch:QI))])
2852 (set (match_dup 3) (plus:QI (match_dup 3) (const_int -1)))
2853 (set (cc0) (compare (match_dup 3) (const_int 0)))
2855 (if_then_else (ne (cc0) (const_int 0))
2856 (label_ref (match_dup 4))
2860 operands[4] = gen_label_rtx ();
2861 operands[5] = gen_label_rtx ();
2864 ;; ----------------------------------------------------------------------
2866 ;; ----------------------------------------------------------------------
2868 (define_expand "rotl<mode>3"
2869 [(set (match_operand:QHI 0 "register_operand" "")
2870 (rotate:QHI (match_operand:QHI 1 "register_operand" "")
2871 (match_operand:QI 2 "nonmemory_operand" "")))]
2874 if (expand_a_rotate (operands))
2878 (define_insn "rotl<mode>3_1"
2879 [(set (match_operand:QHI 0 "register_operand" "=r")
2880 (rotate:QHI (match_operand:QHI 1 "register_operand" "0")
2881 (match_operand:QI 2 "immediate_operand" "")))]
2884 return output_a_rotate (ROTATE, operands);
2886 [(set (attr "length")
2887 (symbol_ref "compute_a_rotate_length (operands)"))])
2889 (define_expand "rotlsi3"
2890 [(set (match_operand:SI 0 "register_operand" "")
2891 (rotate:SI (match_operand:SI 1 "register_operand" "")
2892 (match_operand:QI 2 "nonmemory_operand" "")))]
2893 "TARGET_H8300H || TARGET_H8300S"
2895 if (expand_a_rotate (operands))
2899 (define_insn "rotlsi3_1"
2900 [(set (match_operand:SI 0 "register_operand" "=r")
2901 (rotate:SI (match_operand:SI 1 "register_operand" "0")
2902 (match_operand:QI 2 "immediate_operand" "")))]
2903 "TARGET_H8300H || TARGET_H8300S"
2905 return output_a_rotate (ROTATE, operands);
2907 [(set (attr "length")
2908 (symbol_ref "compute_a_rotate_length (operands)"))])
2910 ;; -----------------------------------------------------------------
2912 ;; -----------------------------------------------------------------
2913 ;; The H8/300 has given 1/8th of its opcode space to bitfield
2914 ;; instructions so let's use them as well as we can.
2916 ;; You'll never believe all these patterns perform one basic action --
2917 ;; load a bit from the source, optionally invert the bit, then store it
2918 ;; in the destination (which is known to be zero).
2920 ;; Combine obviously need some work to better identify this situation and
2921 ;; canonicalize the form better.
2924 ;; Normal loads with a 16bit destination.
2928 [(set (match_operand:HI 0 "register_operand" "=&r")
2929 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2931 (match_operand:HI 2 "immediate_operand" "n")))]
2933 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
2934 [(set_attr "length" "6")])
2937 ;; Inverted loads with a 16bit destination.
2941 [(set (match_operand:HI 0 "register_operand" "=&r")
2942 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
2943 (match_operand:HI 3 "const_int_operand" "n"))
2945 (match_operand:HI 2 "const_int_operand" "n")))]
2946 "(TARGET_H8300 || TARGET_H8300SX)
2947 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2948 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
2949 [(set_attr "length" "8")])
2952 ;; Normal loads with a 32bit destination.
2955 (define_insn "*extzv_1_r_h8300"
2956 [(set (match_operand:SI 0 "register_operand" "=&r")
2957 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
2959 (match_operand 2 "const_int_operand" "n")))]
2960 "TARGET_H8300 && INTVAL (operands[2]) < 16"
2962 return output_simode_bld (0, operands);
2964 [(set_attr "length" "8")])
2966 (define_insn "*extzv_1_r_h8300hs"
2967 [(set (match_operand:SI 0 "register_operand" "=r,r")
2968 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
2970 (match_operand 2 "const_int_operand" "n,n")))]
2971 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
2973 return output_simode_bld (0, operands);
2975 [(set_attr "cc" "set_znv,set_znv")
2976 (set_attr "length" "8,6")])
2979 ;; Inverted loads with a 32bit destination.
2982 (define_insn "*extzv_1_r_inv_h8300"
2983 [(set (match_operand:SI 0 "register_operand" "=&r")
2984 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
2985 (match_operand:HI 3 "const_int_operand" "n"))
2987 (match_operand 2 "const_int_operand" "n")))]
2988 "TARGET_H8300 && INTVAL (operands[2]) < 16
2989 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
2991 return output_simode_bld (1, operands);
2993 [(set_attr "length" "8")])
2995 (define_insn "*extzv_1_r_inv_h8300hs"
2996 [(set (match_operand:SI 0 "register_operand" "=r,r")
2997 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "?0,r")
2998 (match_operand 3 "const_int_operand" "n,n"))
3000 (match_operand 2 "const_int_operand" "n,n")))]
3001 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16
3002 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
3004 return output_simode_bld (1, operands);
3006 [(set_attr "cc" "set_znv,set_znv")
3007 (set_attr "length" "8,6")])
3009 (define_expand "insv"
3010 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
3011 (match_operand:HI 1 "general_operand" "")
3012 (match_operand:HI 2 "general_operand" ""))
3013 (match_operand:HI 3 "general_operand" ""))]
3014 "TARGET_H8300 || TARGET_H8300SX"
3018 if (GET_CODE (operands[1]) == CONST_INT
3019 && GET_CODE (operands[2]) == CONST_INT
3020 && INTVAL (operands[1]) <= 8
3021 && INTVAL (operands[2]) >= 0
3022 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
3023 && memory_operand (operands[0], GET_MODE (operands[0])))
3025 /* If the source operand is zero, it's better to use AND rather
3026 than BFST. Likewise OR if the operand is all ones. */
3027 if (GET_CODE (operands[3]) == CONST_INT)
3029 HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
3030 if ((INTVAL (operands[3]) & mask) == 0)
3032 if ((INTVAL (operands[3]) & mask) == mask)
3035 if (! bit_memory_operand (operands[0], GET_MODE (operands[0])))
3037 if (!can_create_pseudo_p ())
3039 operands[0] = replace_equiv_address (operands[0], force_reg (Pmode,
3040 XEXP (operands[0], 0)));
3042 operands[3] = gen_lowpart (QImode, operands[3]);
3045 if (! register_operand (operands[3], QImode))
3047 if (!can_create_pseudo_p ())
3049 operands[3] = force_reg (QImode, operands[3]);
3051 emit_insn (gen_bfst (adjust_address (operands[0], QImode, 0),
3052 operands[3], operands[1], operands[2]));
3058 /* We only have single bit bit-field instructions. */
3059 if (INTVAL (operands[1]) != 1)
3062 /* For now, we don't allow memory operands. */
3063 if (GET_CODE (operands[0]) == MEM
3064 || GET_CODE (operands[3]) == MEM)
3067 if (GET_CODE (operands[3]) != REG)
3068 operands[3] = force_reg (HImode, operands[3]);
3072 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
3074 (match_operand:HI 1 "immediate_operand" "n"))
3075 (match_operand:HI 2 "register_operand" "r"))]
3077 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
3078 [(set_attr "length" "4")])
3080 (define_expand "extzv"
3081 [(set (match_operand:HI 0 "register_operand" "")
3082 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
3083 (match_operand:HI 2 "general_operand" "")
3084 (match_operand:HI 3 "general_operand" "")))]
3085 "TARGET_H8300 || TARGET_H8300SX"
3089 if (GET_CODE (operands[2]) == CONST_INT
3090 && GET_CODE (operands[3]) == CONST_INT
3091 && INTVAL (operands[2]) <= 8
3092 && INTVAL (operands[3]) >= 0
3093 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
3094 && memory_operand (operands[1], QImode))
3098 /* Optimize the case where we're extracting into a paradoxical
3099 subreg. It's only necessary to extend to the inner reg. */
3100 if (GET_CODE (operands[0]) == SUBREG
3101 && subreg_lowpart_p (operands[0])
3102 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
3103 < GET_MODE_SIZE (GET_MODE (operands[0])))
3104 && (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0])))
3106 operands[0] = SUBREG_REG (operands[0]);
3108 if (!can_create_pseudo_p ())
3109 temp = gen_lowpart (QImode, operands[0]);
3111 temp = gen_reg_rtx (QImode);
3114 if (! bit_memory_operand (operands[1], QImode))
3116 if (!can_create_pseudo_p ())
3118 operands[1] = replace_equiv_address (operands[1],
3119 force_reg (Pmode, XEXP (operands[1], 0)));
3121 emit_insn (gen_bfld (temp, operands[1], operands[2], operands[3]));
3122 convert_move (operands[0], temp, 1);
3128 /* We only have single bit bit-field instructions. */
3129 if (INTVAL (operands[2]) != 1)
3132 /* For now, we don't allow memory operands. */
3133 if (GET_CODE (operands[1]) == MEM)
3137 ;; BAND, BOR, and BXOR patterns
3140 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3141 (match_operator:HI 4 "bit_operator"
3142 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3144 (match_operand:HI 2 "immediate_operand" "n"))
3145 (match_operand:HI 3 "bit_operand" "0")]))]
3147 "bld %Z2,%Y1\;b%c4 #0,%R0\;bst #0,%R0; bl1"
3148 [(set_attr "length" "6")])
3151 [(set (match_operand:HI 0 "bit_operand" "=Ur")
3152 (match_operator:HI 5 "bit_operator"
3153 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
3155 (match_operand:HI 2 "immediate_operand" "n"))
3156 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
3158 (match_operand:HI 4 "immediate_operand" "n"))]))]
3160 "bld %Z2,%Y1\;b%c5 %Z4,%Y3\;bst #0,%R0; bl3"
3161 [(set_attr "length" "6")])
3164 [(set (match_operand:QI 0 "register_operand" "=r")
3165 (zero_extract:QI (match_operand:QI 1 "bit_memory_operand" "WU")
3166 (match_operand:QI 2 "immediate_operand" "n")
3167 (match_operand:QI 3 "immediate_operand" "n")))]
3168 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3170 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3171 - (1 << INTVAL (operands[3])));
3172 return "bfld %2,%1,%R0";
3174 [(set_attr "cc" "none_0hit")
3175 (set_attr "length_table" "bitfield")])
3178 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3179 (match_operand:QI 2 "immediate_operand" "n")
3180 (match_operand:QI 3 "immediate_operand" "n"))
3181 (match_operand:QI 1 "register_operand" "r"))]
3182 "TARGET_H8300SX && INTVAL (operands[2]) + INTVAL (operands[3]) <= 8"
3184 operands[2] = GEN_INT ((1 << (INTVAL (operands[2]) + INTVAL (operands[3])))
3185 - (1 << INTVAL (operands[3])));
3186 return "bfst %R1,%2,%0";
3188 [(set_attr "cc" "none_0hit")
3189 (set_attr "length_table" "bitfield")])
3191 (define_expand "cstoreqi4"
3192 [(use (match_operator 1 "eqne_operator"
3193 [(match_operand:QI 2 "h8300_dst_operand" "")
3194 (match_operand:QI 3 "h8300_src_operand" "")]))
3195 (clobber (match_operand:HI 0 "register_operand"))]
3198 h8300_expand_store (operands);
3202 (define_expand "cstorehi4"
3203 [(use (match_operator 1 "eqne_operator"
3204 [(match_operand:HI 2 "h8300_dst_operand" "")
3205 (match_operand:HI 3 "h8300_src_operand" "")]))
3206 (clobber (match_operand:HI 0 "register_operand"))]
3209 h8300_expand_store (operands);
3213 (define_expand "cstoresi4"
3214 [(use (match_operator 1 "eqne_operator"
3215 [(match_operand:SI 2 "h8300_dst_operand" "")
3216 (match_operand:SI 3 "h8300_src_operand" "")]))
3217 (clobber (match_operand:HI 0 "register_operand"))]
3220 h8300_expand_store (operands);
3224 (define_insn "*bstzhireg"
3225 [(set (match_operand:HI 0 "register_operand" "=r")
3226 (match_operator:HI 1 "eqne_operator" [(cc0) (const_int 0)]))]
3228 "mulu.w #0,%T0\;b%k1 .Lh8BR%=\;inc.w #1,%T0\\n.Lh8BR%=:"
3229 [(set_attr "cc" "clobber")])
3231 (define_insn_and_split "*cmpstz"
3232 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU,WU")
3234 (match_operand:QI 1 "immediate_operand" "n,n"))
3235 (match_operator:QI 2 "eqne_operator"
3236 [(match_operand 3 "h8300_dst_operand" "r,rQ")
3237 (match_operand 4 "h8300_src_operand" "I,rQi")]))]
3239 && (GET_MODE (operands[3]) == GET_MODE (operands[4])
3240 || GET_CODE (operands[4]) == CONST_INT)
3241 && GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
3242 && GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
3245 [(set (cc0) (match_dup 5))
3246 (set (zero_extract:QI (match_dup 0) (const_int 1) (match_dup 1))
3247 (match_op_dup:QI 2 [(cc0) (const_int 0)]))]
3249 operands[5] = gen_rtx_COMPARE (VOIDmode, operands[3], operands[4]);
3251 [(set_attr "cc" "set_znv,compare")])
3253 (define_insn "*bstz"
3254 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3256 (match_operand:QI 1 "immediate_operand" "n"))
3257 (eq:QI (cc0) (const_int 0)))]
3258 "TARGET_H8300SX && reload_completed"
3260 [(set_attr "cc" "none_0hit")
3261 (set_attr "length_table" "unary")])
3263 (define_insn "*bistz"
3264 [(set (zero_extract:QI (match_operand:QI 0 "bit_memory_operand" "+WU")
3266 (match_operand:QI 1 "immediate_operand" "n"))
3267 (ne:QI (cc0) (const_int 0)))]
3268 "TARGET_H8300SX && reload_completed"
3270 [(set_attr "cc" "none_0hit")
3271 (set_attr "length_table" "unary")])
3273 (define_insn_and_split "*cmpcondbset"
3274 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3275 (if_then_else:QI (match_operator 1 "eqne_operator"
3276 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3277 (match_operand 3 "h8300_src_operand" "I,rQi")])
3278 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3279 (match_operand:QI 5 "single_one_operand" "n,n"))
3284 [(set (cc0) (match_dup 6))
3286 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3287 (ior:QI (match_dup 4) (match_dup 5))
3290 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3292 [(set_attr "cc" "set_znv,compare")])
3294 (define_insn "*condbset"
3295 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3296 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3297 [(cc0) (const_int 0)])
3298 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3299 (match_operand:QI 1 "single_one_operand" "n"))
3301 "TARGET_H8300SX && reload_completed"
3303 [(set_attr "cc" "none_0hit")
3304 (set_attr "length_table" "logicb")])
3306 (define_insn_and_split "*cmpcondbclr"
3307 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3308 (if_then_else:QI (match_operator 1 "eqne_operator"
3309 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3310 (match_operand 3 "h8300_src_operand" "I,rQi")])
3311 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3312 (match_operand:QI 5 "single_zero_operand" "n,n"))
3317 [(set (cc0) (match_dup 6))
3319 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3320 (and:QI (match_dup 4) (match_dup 5))
3323 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3325 [(set_attr "cc" "set_znv,compare")])
3327 (define_insn "*condbclr"
3328 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3329 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3330 [(cc0) (const_int 0)])
3331 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3332 (match_operand:QI 1 "single_zero_operand" "n"))
3334 "TARGET_H8300SX && reload_completed"
3336 [(set_attr "cc" "none_0hit")
3337 (set_attr "length_table" "logicb")])
3339 (define_insn_and_split "*cmpcondbsetreg"
3340 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3341 (if_then_else:QI (match_operator 1 "eqne_operator"
3342 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3343 (match_operand 3 "h8300_src_operand" "I,rQi")])
3344 (ior:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3345 (ashift:QI (const_int 1)
3346 (match_operand:QI 5 "register_operand" "r,r")))
3351 [(set (cc0) (match_dup 6))
3353 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3354 (ior:QI (match_dup 4)
3355 (ashift:QI (const_int 1)
3356 (match_operand:QI 5 "register_operand" "r,r")))
3359 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3361 [(set_attr "cc" "set_znv,compare")])
3363 (define_insn "*condbsetreg"
3364 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3365 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3366 [(cc0) (const_int 0)])
3367 (ior:QI (match_operand:QI 3 "bit_memory_operand" "0")
3368 (ashift:QI (const_int 1)
3369 (match_operand:QI 1 "register_operand" "r")))
3371 "TARGET_H8300SX && reload_completed"
3373 [(set_attr "cc" "none_0hit")
3374 (set_attr "length_table" "logicb")])
3376 (define_insn_and_split "*cmpcondbclrreg"
3377 [(set (match_operand:QI 0 "nonimmediate_operand" "=WU,WU")
3378 (if_then_else:QI (match_operator 1 "eqne_operator"
3379 [(match_operand 2 "h8300_dst_operand" "r,rQ")
3380 (match_operand 3 "h8300_src_operand" "I,rQi")])
3381 (and:QI (match_operand:QI 4 "bit_memory_operand" "0,0")
3382 (ashift:QI (const_int 1)
3383 (match_operand:QI 5 "register_operand" "r,r")))
3388 [(set (cc0) (match_dup 6))
3390 (if_then_else:QI (match_op_dup 1 [(cc0) (const_int 0)])
3391 (and:QI (match_dup 4)
3392 (ashift:QI (const_int 1)
3393 (match_operand:QI 5 "register_operand" "r,r")))
3396 operands[6] = gen_rtx_COMPARE (VOIDmode, operands[2], operands[3]);
3398 [(set_attr "cc" "set_znv,compare")])
3400 (define_insn "*condbclrreg"
3401 [(set (match_operand:QI 0 "bit_memory_operand" "=WU")
3402 (if_then_else:QI (match_operator:QI 2 "eqne_operator"
3403 [(cc0) (const_int 0)])
3404 (and:QI (match_operand:QI 3 "bit_memory_operand" "0")
3405 (ashift:QI (const_int 1)
3406 (match_operand:QI 1 "register_operand" "r")))
3408 "TARGET_H8300SX && reload_completed"
3410 [(set_attr "cc" "none_0hit")
3411 (set_attr "length_table" "logicb")])
3414 ;; -----------------------------------------------------------------
3416 ;; -----------------------------------------------------------------
3420 (define_insn "*insv_si_1_n"
3421 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3423 (match_operand:SI 1 "const_int_operand" "n"))
3424 (match_operand:SI 2 "register_operand" "r"))]
3425 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3426 "bld\\t#0,%w2\;bst\\t%Z1,%Y0"
3427 [(set_attr "length" "4")])
3429 (define_insn "*insv_si_1_n_lshiftrt"
3430 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3432 (match_operand:SI 1 "const_int_operand" "n"))
3433 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3434 (match_operand:SI 3 "const_int_operand" "n")))]
3435 "(TARGET_H8300H || TARGET_H8300S)
3436 && INTVAL (operands[1]) < 16
3437 && INTVAL (operands[3]) < 16"
3438 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0"
3439 [(set_attr "length" "4")])
3441 (define_insn "*insv_si_1_n_lshiftrt_16"
3442 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3444 (match_operand:SI 1 "const_int_operand" "n"))
3445 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3447 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[1]) < 16"
3448 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0"
3449 [(set_attr "length" "6")])
3451 (define_insn "*insv_si_8_8"
3452 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3455 (match_operand:SI 1 "register_operand" "r"))]
3456 "TARGET_H8300H || TARGET_H8300S"
3458 [(set_attr "length" "2")])
3460 (define_insn "*insv_si_8_8_lshiftrt_8"
3461 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
3464 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3466 "TARGET_H8300H || TARGET_H8300S"
3468 [(set_attr "length" "2")])
3472 (define_insn "*extzv_8_8"
3473 [(set (match_operand:SI 0 "register_operand" "=r,r")
3474 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r")
3477 "TARGET_H8300H || TARGET_H8300S"
3479 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0
3480 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0"
3481 [(set_attr "cc" "set_znv,clobber")
3482 (set_attr "length" "6,4")])
3484 (define_insn "*extzv_8_16"
3485 [(set (match_operand:SI 0 "register_operand" "=r")
3486 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3489 "TARGET_H8300H || TARGET_H8300S"
3490 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0"
3491 [(set_attr "cc" "set_znv")
3492 (set_attr "length" "6")])
3494 (define_insn "*extzv_16_8"
3495 [(set (match_operand:SI 0 "register_operand" "=r")
3496 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3499 (clobber (match_scratch:SI 2 "=&r"))]
3501 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0"
3502 [(set_attr "length" "8")
3503 (set_attr "cc" "set_znv")])
3505 ;; Extract the exponent of a float.
3507 (define_insn_and_split "*extzv_8_23"
3508 [(set (match_operand:SI 0 "register_operand" "=r")
3509 (zero_extract:SI (match_operand:SI 1 "register_operand" "0")
3512 "(TARGET_H8300H || TARGET_H8300S)"
3514 "&& reload_completed"
3515 [(parallel [(set (match_dup 0)
3516 (ashift:SI (match_dup 0)
3518 (clobber (scratch:QI))])
3519 (parallel [(set (match_dup 0)
3520 (lshiftrt:SI (match_dup 0)
3522 (clobber (scratch:QI))])]
3527 ;; ((SImode) HImode) << 15
3529 (define_insn_and_split "*twoshifts_l16_r1"
3530 [(set (match_operand:SI 0 "register_operand" "=r")
3531 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3533 (const_int 2147450880)))]
3534 "(TARGET_H8300H || TARGET_H8300S)"
3536 "&& reload_completed"
3537 [(parallel [(set (match_dup 0)
3538 (ashift:SI (match_dup 0)
3540 (clobber (scratch:QI))])
3541 (parallel [(set (match_dup 0)
3542 (lshiftrt:SI (match_dup 0)
3544 (clobber (scratch:QI))])]
3547 ;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B).
3549 (define_insn_and_split "*andsi3_ashift_n_lower"
3550 [(set (match_operand:SI 0 "register_operand" "=r,r")
3551 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
3552 (match_operand:QI 2 "const_int_operand" "S,n"))
3553 (match_operand:SI 3 "const_int_operand" "n,n")))
3554 (clobber (match_scratch:QI 4 "=X,&r"))]
3555 "(TARGET_H8300H || TARGET_H8300S)
3556 && INTVAL (operands[2]) <= 15
3557 && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2]))
3560 "&& reload_completed"
3561 [(parallel [(set (match_dup 5)
3562 (ashift:HI (match_dup 5)
3564 (clobber (match_dup 4))])
3566 (zero_extend:SI (match_dup 5)))]
3568 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0]));
3571 ;; Accept (A >> 30) & 2 and the like.
3573 (define_insn "*andsi3_lshiftrt_n_sb"
3574 [(set (match_operand:SI 0 "register_operand" "=r")
3575 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3576 (match_operand:SI 2 "const_int_operand" "n"))
3577 (match_operand:SI 3 "single_one_operand" "n")))]
3578 "(TARGET_H8300H || TARGET_H8300S)
3579 && exact_log2 (INTVAL (operands[3])) < 16
3580 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31"
3582 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
3583 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0";
3585 [(set_attr "length" "8")])
3587 (define_insn_and_split "*andsi3_lshiftrt_9_sb"
3588 [(set (match_operand:SI 0 "register_operand" "=r")
3589 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3591 (const_int 4194304)))]
3592 "TARGET_H8300H || TARGET_H8300S"
3594 "&& reload_completed"
3596 (and:SI (lshiftrt:SI (match_dup 0)
3599 (parallel [(set (match_dup 0)
3600 (ashift:SI (match_dup 0)
3602 (clobber (scratch:QI))])]
3607 (define_insn "*addsi3_upper"
3608 [(set (match_operand:SI 0 "register_operand" "=r")
3609 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
3611 (match_operand:SI 2 "register_operand" "0")))]
3612 "TARGET_H8300H || TARGET_H8300S"
3614 [(set_attr "length" "2")])
3616 (define_insn "*addsi3_lshiftrt_16_zexthi"
3617 [(set (match_operand:SI 0 "register_operand" "=r")
3618 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3620 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))]
3621 "TARGET_H8300H || TARGET_H8300S"
3622 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0"
3623 [(set_attr "length" "6")])
3625 (define_insn_and_split "*addsi3_and_r_1"
3626 [(set (match_operand:SI 0 "register_operand" "=r")
3627 (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r")
3629 (match_operand:SI 2 "register_operand" "0")))]
3630 "TARGET_H8300H || TARGET_H8300S"
3632 "&& reload_completed"
3633 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3638 (if_then_else (eq (cc0)
3640 (label_ref (match_dup 3))
3643 (plus:SI (match_dup 2)
3647 operands[3] = gen_label_rtx ();
3650 (define_insn_and_split "*addsi3_and_not_r_1"
3651 [(set (match_operand:SI 0 "register_operand" "=r")
3652 (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3654 (match_operand:SI 2 "register_operand" "0")))]
3655 "TARGET_H8300H || TARGET_H8300S"
3657 "&& reload_completed"
3658 [(set (cc0) (compare (zero_extract:SI (match_dup 1)
3663 (if_then_else (ne (cc0)
3665 (label_ref (match_dup 3))
3668 (plus:SI (match_dup 2)
3672 operands[3] = gen_label_rtx ();
3677 (define_insn "*ixorhi3_zext"
3678 [(set (match_operand:HI 0 "register_operand" "=r")
3679 (match_operator:HI 1 "iorxor_operator"
3680 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))
3681 (match_operand:HI 3 "register_operand" "0")]))]
3684 [(set_attr "length" "2")])
3688 (define_insn "*ixorsi3_zext_qi"
3689 [(set (match_operand:SI 0 "register_operand" "=r")
3690 (match_operator:SI 1 "iorxor_operator"
3691 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))
3692 (match_operand:SI 3 "register_operand" "0")]))]
3695 [(set_attr "length" "2")])
3697 (define_insn "*ixorsi3_zext_hi"
3698 [(set (match_operand:SI 0 "register_operand" "=r")
3699 (match_operator:SI 1 "iorxor_operator"
3700 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))
3701 (match_operand:SI 3 "register_operand" "0")]))]
3702 "TARGET_H8300H || TARGET_H8300S"
3704 [(set_attr "length" "2")])
3706 (define_insn "*ixorsi3_ashift_16"
3707 [(set (match_operand:SI 0 "register_operand" "=r")
3708 (match_operator:SI 1 "iorxor_operator"
3709 [(ashift:SI (match_operand:SI 2 "register_operand" "r")
3711 (match_operand:SI 3 "register_operand" "0")]))]
3712 "TARGET_H8300H || TARGET_H8300S"
3714 [(set_attr "length" "2")])
3716 (define_insn "*ixorsi3_lshiftrt_16"
3717 [(set (match_operand:SI 0 "register_operand" "=r")
3718 (match_operator:SI 1 "iorxor_operator"
3719 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3721 (match_operand:SI 3 "register_operand" "0")]))]
3722 "TARGET_H8300H || TARGET_H8300S"
3724 [(set_attr "length" "2")])
3728 (define_insn "*iorhi3_ashift_8"
3729 [(set (match_operand:HI 0 "register_operand" "=r")
3730 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r")
3732 (match_operand:HI 2 "register_operand" "0")))]
3735 [(set_attr "length" "2")])
3737 (define_insn "*iorhi3_lshiftrt_8"
3738 [(set (match_operand:HI 0 "register_operand" "=r")
3739 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
3741 (match_operand:HI 2 "register_operand" "0")))]
3744 [(set_attr "length" "2")])
3746 (define_insn "*iorhi3_two_qi"
3747 [(set (match_operand:HI 0 "register_operand" "=r")
3748 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
3749 (ashift:HI (match_operand:HI 2 "register_operand" "r")
3753 [(set_attr "length" "2")])
3755 (define_insn "*iorhi3_two_qi_mem"
3756 [(set (match_operand:HI 0 "register_operand" "=&r")
3757 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))
3758 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0)
3761 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0"
3762 [(set_attr "length" "16")])
3765 [(set (match_operand:HI 0 "register_operand" "")
3766 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" ""))
3767 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0)
3769 "(TARGET_H8300H || TARGET_H8300S)
3771 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))"
3775 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0));
3780 (define_insn "*iorsi3_two_hi"
3781 [(set (match_operand:SI 0 "register_operand" "=r")
3782 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
3783 (ashift:SI (match_operand:SI 2 "register_operand" "r")
3785 "TARGET_H8300H || TARGET_H8300S"
3787 [(set_attr "length" "2")])
3789 (define_insn_and_split "*iorsi3_two_qi_zext"
3790 [(set (match_operand:SI 0 "register_operand" "=&r")
3791 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m"))
3792 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
3794 (const_int 65280))))]
3795 "TARGET_H8300H || TARGET_H8300S"
3797 "&& reload_completed"
3799 (ior:HI (zero_extend:HI (match_dup 1))
3800 (ashift:HI (subreg:HI (match_dup 2) 0)
3803 (zero_extend:SI (match_dup 3)))]
3805 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3808 (define_insn "*iorsi3_e2f"
3809 [(set (match_operand:SI 0 "register_operand" "=r")
3810 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3812 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
3814 "TARGET_H8300H || TARGET_H8300S"
3816 [(set_attr "length" "2")])
3818 (define_insn_and_split "*iorsi3_two_qi_sext"
3819 [(set (match_operand:SI 0 "register_operand" "=r")
3820 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
3821 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
3823 "TARGET_H8300H || TARGET_H8300S"
3825 "&& reload_completed"
3827 (ior:HI (zero_extend:HI (match_dup 1))
3828 (ashift:HI (match_dup 4)
3831 (sign_extend:SI (match_dup 3)))]
3833 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
3834 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
3837 (define_insn "*iorsi3_w"
3838 [(set (match_operand:SI 0 "register_operand" "=r,&r")
3839 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0")
3841 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))]
3842 "TARGET_H8300H || TARGET_H8300S"
3844 [(set_attr "length" "2,8")])
3846 (define_insn "*iorsi3_ashift_31"
3847 [(set (match_operand:SI 0 "register_operand" "=&r")
3848 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3850 (match_operand:SI 2 "register_operand" "0")))]
3851 "TARGET_H8300H || TARGET_H8300S"
3852 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0"
3853 [(set_attr "length" "6")
3854 (set_attr "cc" "set_znv")])
3856 (define_insn "*iorsi3_and_ashift"
3857 [(set (match_operand:SI 0 "register_operand" "=r")
3858 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3859 (match_operand:SI 2 "const_int_operand" "n"))
3860 (match_operand:SI 3 "single_one_operand" "n"))
3861 (match_operand:SI 4 "register_operand" "0")))]
3862 "(TARGET_H8300H || TARGET_H8300S)
3863 && (INTVAL (operands[3]) & ~0xffff) == 0"
3865 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3866 - INTVAL (operands[2]));
3867 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3868 operands[2] = srcpos;
3869 operands[3] = dstpos;
3870 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3872 [(set_attr "length" "6")])
3874 (define_insn "*iorsi3_and_lshiftrt"
3875 [(set (match_operand:SI 0 "register_operand" "=r")
3876 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3877 (match_operand:SI 2 "const_int_operand" "n"))
3878 (match_operand:SI 3 "single_one_operand" "n"))
3879 (match_operand:SI 4 "register_operand" "0")))]
3880 "(TARGET_H8300H || TARGET_H8300S)
3881 && ((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0"
3883 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3]))
3884 + INTVAL (operands[2]));
3885 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3])));
3886 operands[2] = srcpos;
3887 operands[3] = dstpos;
3888 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0";
3890 [(set_attr "length" "6")])
3892 (define_insn "*iorsi3_zero_extract"
3893 [(set (match_operand:SI 0 "register_operand" "=r")
3894 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
3896 (match_operand:SI 2 "const_int_operand" "n"))
3897 (match_operand:SI 3 "register_operand" "0")))]
3898 "(TARGET_H8300H || TARGET_H8300S) && INTVAL (operands[2]) < 16"
3899 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0"
3900 [(set_attr "length" "6")])
3902 (define_insn "*iorsi3_and_lshiftrt_n_sb"
3903 [(set (match_operand:SI 0 "register_operand" "=r")
3904 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3907 (match_operand:SI 2 "register_operand" "0")))]
3908 "TARGET_H8300H || TARGET_H8300S"
3909 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0"
3910 [(set_attr "length" "8")])
3912 (define_insn "*iorsi3_and_lshiftrt_9_sb"
3913 [(set (match_operand:SI 0 "register_operand" "=r")
3914 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
3916 (const_int 4194304))
3917 (match_operand:SI 2 "register_operand" "0")))
3918 (clobber (match_scratch:HI 3 "=&r"))]
3919 "TARGET_H8300H || TARGET_H8300S"
3921 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3922 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3924 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0";
3926 [(set_attr "length" "10")])
3928 ;; Used to OR the exponent of a float.
3930 (define_insn "*iorsi3_shift"
3931 [(set (match_operand:SI 0 "register_operand" "=r")
3932 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3934 (match_operand:SI 2 "register_operand" "0")))
3935 (clobber (match_scratch:SI 3 "=&r"))]
3936 "TARGET_H8300H || TARGET_H8300S"
3940 [(set (match_operand:SI 0 "register_operand" "")
3941 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3944 (clobber (match_operand:SI 2 "register_operand" ""))]
3945 "(TARGET_H8300H || TARGET_H8300S)
3946 && epilogue_completed
3947 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3948 && REGNO (operands[0]) != REGNO (operands[1])"
3949 [(parallel [(set (match_dup 3)
3950 (ashift:HI (match_dup 3)
3952 (clobber (scratch:QI))])
3954 (ior:SI (ashift:SI (match_dup 1)
3958 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
3962 [(set (match_operand:SI 0 "register_operand" "")
3963 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
3966 (clobber (match_operand:SI 2 "register_operand" ""))]
3967 "(TARGET_H8300H || TARGET_H8300S)
3968 && epilogue_completed
3969 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
3970 && REGNO (operands[0]) != REGNO (operands[1]))"
3973 (parallel [(set (match_dup 3)
3974 (ashift:HI (match_dup 3)
3976 (clobber (scratch:QI))])
3978 (ior:SI (ashift:SI (match_dup 2)
3982 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
3985 (define_insn "*iorsi2_and_1_lshiftrt_1"
3986 [(set (match_operand:SI 0 "register_operand" "=r")
3987 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0")
3989 (lshiftrt:SI (match_dup 1)
3991 "TARGET_H8300H || TARGET_H8300S"
3992 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0"
3993 [(set_attr "length" "6")])
3995 (define_insn_and_split "*iorsi3_ashift_16_ashift_24"
3996 [(set (match_operand:SI 0 "register_operand" "=r")
3997 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
3999 (ashift:SI (match_operand:SI 2 "register_operand" "r")
4001 "TARGET_H8300H || TARGET_H8300S"
4003 "&& reload_completed"
4005 (ior:HI (ashift:HI (match_dup 4)
4008 (parallel [(set (match_dup 0)
4009 (ashift:SI (match_dup 0)
4011 (clobber (scratch:QI))])]
4013 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4014 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
4017 (define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem"
4018 [(set (match_operand:SI 0 "register_operand" "=&r")
4019 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0)
4021 (const_int 16711680))
4022 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0)
4024 "TARGET_H8300H || TARGET_H8300S"
4026 "&& reload_completed"
4028 (ior:HI (zero_extend:HI (match_dup 1))
4029 (ashift:HI (subreg:HI (match_dup 2) 0)
4031 (parallel [(set (match_dup 0)
4032 (ashift:SI (match_dup 0)
4034 (clobber (scratch:QI))])]
4036 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4039 ;; Used to add the exponent of a float.
4041 (define_insn "*addsi3_shift"
4042 [(set (match_operand:SI 0 "register_operand" "=r")
4043 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
4044 (const_int 8388608))
4045 (match_operand:SI 2 "register_operand" "0")))
4046 (clobber (match_scratch:SI 3 "=&r"))]
4047 "TARGET_H8300H || TARGET_H8300S"
4051 [(set (match_operand:SI 0 "register_operand" "")
4052 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4053 (const_int 8388608))
4055 (clobber (match_operand:SI 2 "register_operand" ""))]
4056 "(TARGET_H8300H || TARGET_H8300S)
4057 && epilogue_completed
4058 && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4059 && REGNO (operands[0]) != REGNO (operands[1])"
4060 [(parallel [(set (match_dup 3)
4061 (ashift:HI (match_dup 3)
4063 (clobber (scratch:QI))])
4065 (plus:SI (mult:SI (match_dup 1)
4069 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1]));
4073 [(set (match_operand:SI 0 "register_operand" "")
4074 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4075 (const_int 8388608))
4077 (clobber (match_operand:SI 2 "register_operand" ""))]
4078 "(TARGET_H8300H || TARGET_H8300S)
4079 && epilogue_completed
4080 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1]))
4081 && REGNO (operands[0]) != REGNO (operands[1]))"
4084 (parallel [(set (match_dup 3)
4085 (ashift:HI (match_dup 3)
4087 (clobber (scratch:QI))])
4089 (plus:SI (mult:SI (match_dup 2)
4093 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2]));
4098 (define_insn_and_split "*ashiftsi_sextqi_7"
4099 [(set (match_operand:SI 0 "register_operand" "=r")
4100 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
4102 "TARGET_H8300H || TARGET_H8300S"
4104 "&& reload_completed"
4105 [(parallel [(set (match_dup 2)
4106 (ashift:HI (match_dup 2)
4108 (clobber (scratch:QI))])
4110 (sign_extend:SI (match_dup 2)))
4111 (parallel [(set (match_dup 0)
4112 (ashiftrt:SI (match_dup 0)
4114 (clobber (scratch:QI))])]
4116 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
4119 ;; Storing a part of HImode to QImode.
4122 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4123 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
4127 [(set_attr "cc" "set_znv")
4128 (set_attr "length" "8")])
4130 ;; Storing a part of SImode to QImode.
4133 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4134 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4138 [(set_attr "cc" "set_znv")
4139 (set_attr "length" "8")])
4142 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4143 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4145 (clobber (match_scratch:SI 2 "=&r"))]
4146 "TARGET_H8300H || TARGET_H8300S"
4147 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
4148 [(set_attr "cc" "set_znv")
4149 (set_attr "length" "10")])
4152 [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
4153 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
4155 (clobber (match_scratch:SI 2 "=&r"))]
4156 "TARGET_H8300H || TARGET_H8300S"
4157 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"
4158 [(set_attr "cc" "set_znv")
4159 (set_attr "length" "10")])
4161 (define_insn_and_split ""
4163 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4167 (label_ref (match_operand 1 "" ""))
4172 [(set (cc0) (compare (match_dup 0)
4175 (if_then_else (ge (cc0)
4177 (label_ref (match_dup 1))
4181 (define_insn_and_split ""
4183 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
4187 (label_ref (match_operand 1 "" ""))
4192 [(set (cc0) (compare (match_dup 0)
4195 (if_then_else (lt (cc0)
4197 (label_ref (match_dup 1))
4201 ;; -----------------------------------------------------------------
4202 ;; PEEPHOLE PATTERNS
4203 ;; -----------------------------------------------------------------
4205 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4208 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4209 (lshiftrt:HI (match_dup 0)
4210 (match_operand:HI 1 "const_int_operand" "")))
4211 (clobber (match_operand:HI 2 "" ""))])
4213 (and:HI (match_dup 0)
4214 (match_operand:HI 3 "const_int_operand" "")))]
4215 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4217 (and:HI (match_dup 0)
4219 (parallel [(set (match_dup 0)
4220 (lshiftrt:HI (match_dup 0) (match_dup 1)))
4221 (clobber (match_dup 2))])]
4224 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4227 [(parallel [(set (match_operand:HI 0 "register_operand" "")
4228 (ashift:HI (match_dup 0)
4229 (match_operand:HI 1 "const_int_operand" "")))
4230 (clobber (match_operand:HI 2 "" ""))])
4232 (and:HI (match_dup 0)
4233 (match_operand:HI 3 "const_int_operand" "")))]
4234 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4236 (and:HI (match_dup 0)
4238 (parallel [(set (match_dup 0)
4239 (ashift:HI (match_dup 0) (match_dup 1)))
4240 (clobber (match_dup 2))])]
4243 ;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
4246 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4247 (lshiftrt:SI (match_dup 0)
4248 (match_operand:SI 1 "const_int_operand" "")))
4249 (clobber (match_operand:SI 2 "" ""))])
4251 (and:SI (match_dup 0)
4252 (match_operand:SI 3 "const_int_operand" "")))]
4253 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
4255 (and:SI (match_dup 0)
4257 (parallel [(set (match_dup 0)
4258 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4259 (clobber (match_dup 2))])]
4262 ;; Convert (A << B) & C to (A & 255) << B if C == 255 << B.
4265 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4266 (ashift:SI (match_dup 0)
4267 (match_operand:SI 1 "const_int_operand" "")))
4268 (clobber (match_operand:SI 2 "" ""))])
4270 (and:SI (match_dup 0)
4271 (match_operand:SI 3 "const_int_operand" "")))]
4272 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
4274 (and:SI (match_dup 0)
4276 (parallel [(set (match_dup 0)
4277 (ashift:SI (match_dup 0) (match_dup 1)))
4278 (clobber (match_dup 2))])]
4281 ;; Convert (A >> B) & C to (A & 65535) >> B if C == 65535 >> B.
4284 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4285 (lshiftrt:SI (match_dup 0)
4286 (match_operand:SI 1 "const_int_operand" "")))
4287 (clobber (match_operand:SI 2 "" ""))])
4289 (and:SI (match_dup 0)
4290 (match_operand:SI 3 "const_int_operand" "")))]
4291 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
4293 (and:SI (match_dup 0)
4295 (parallel [(set (match_dup 0)
4296 (lshiftrt:SI (match_dup 0) (match_dup 1)))
4297 (clobber (match_dup 2))])]
4300 ;; Convert (A << B) & C to (A & 65535) << B if C == 65535 << B.
4303 [(parallel [(set (match_operand:SI 0 "register_operand" "")
4304 (ashift:SI (match_dup 0)
4305 (match_operand:SI 1 "const_int_operand" "")))
4306 (clobber (match_operand:SI 2 "" ""))])
4308 (and:SI (match_dup 0)
4309 (match_operand:SI 3 "const_int_operand" "")))]
4310 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
4312 (and:SI (match_dup 0)
4314 (parallel [(set (match_dup 0)
4315 (ashift:SI (match_dup 0) (match_dup 1)))
4316 (clobber (match_dup 2))])]
4319 ;; Convert a QImode push into an SImode push so that the
4320 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4323 [(parallel [(set (reg:SI SP_REG)
4324 (plus:SI (reg:SI SP_REG) (const_int -4)))
4325 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
4326 (match_operand:QI 0 "register_operand" ""))])]
4327 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4328 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4331 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4335 [(parallel [(set (reg:HI SP_REG)
4336 (plus:HI (reg:HI SP_REG) (const_int -4)))
4337 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -3)))
4338 (match_operand:QI 0 "register_operand" ""))])]
4339 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4340 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4346 ;; Convert a HImode push into an SImode push so that the
4347 ;; define_peephole2 below can cram multiple pushes into one stm.l.
4350 [(parallel [(set (reg:SI SP_REG)
4351 (plus:SI (reg:SI SP_REG) (const_int -4)))
4352 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
4353 (match_operand:HI 0 "register_operand" ""))])]
4354 "TARGET_H8300S && !TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4355 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4358 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4362 [(parallel [(set (reg:HI SP_REG)
4363 (plus:HI (reg:HI SP_REG) (const_int -4)))
4364 (set (mem:HI (plus:HI (reg:HI SP_REG) (const_int -2)))
4365 (match_operand:HI 0 "register_operand" ""))])]
4366 "TARGET_H8300S && TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
4367 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4370 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
4373 ;; Cram four pushes into stm.l.
4376 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4377 (match_operand:SI 0 "register_operand" ""))
4378 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4379 (match_operand:SI 1 "register_operand" ""))
4380 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4381 (match_operand:SI 2 "register_operand" ""))
4382 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4383 (match_operand:SI 3 "register_operand" ""))]
4384 "TARGET_H8300S && !TARGET_NORMAL_MODE
4385 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4386 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4387 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4388 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4389 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4390 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4392 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4394 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4396 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -16)))
4398 (set (reg:SI SP_REG)
4399 (plus:SI (reg:SI SP_REG)
4400 (const_int -16)))])]
4404 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4405 (match_operand:SI 0 "register_operand" ""))
4406 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4407 (match_operand:SI 1 "register_operand" ""))
4408 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4409 (match_operand:SI 2 "register_operand" ""))
4410 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4411 (match_operand:SI 3 "register_operand" ""))]
4412 "TARGET_H8300S && TARGET_NORMAL_MODE
4413 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
4414 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4415 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4416 && REGNO (operands[3]) == REGNO (operands[0]) + 3
4417 && (TARGET_H8300SX || REGNO (operands[0]) == 0))"
4418 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4420 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4422 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4424 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -16)))
4426 (set (reg:HI SP_REG)
4427 (plus:HI (reg:HI SP_REG)
4428 (const_int -16)))])]
4431 ;; Cram three pushes into stm.l.
4434 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4435 (match_operand:SI 0 "register_operand" ""))
4436 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4437 (match_operand:SI 1 "register_operand" ""))
4438 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4439 (match_operand:SI 2 "register_operand" ""))]
4440 "TARGET_H8300S && !TARGET_NORMAL_MODE
4441 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4442 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4443 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4444 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4445 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4447 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4449 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -12)))
4451 (set (reg:SI SP_REG)
4452 (plus:SI (reg:SI SP_REG)
4453 (const_int -12)))])]
4457 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4458 (match_operand:SI 0 "register_operand" ""))
4459 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4460 (match_operand:SI 1 "register_operand" ""))
4461 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4462 (match_operand:SI 2 "register_operand" ""))]
4463 "TARGET_H8300S && TARGET_NORMAL_MODE
4464 && (REGNO_REG_CLASS (REGNO (operands[2])) == GENERAL_REGS
4465 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4466 && REGNO (operands[2]) == REGNO (operands[0]) + 2
4467 && (TARGET_H8300SX || (REGNO (operands[0]) & 3) == 0))"
4468 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4470 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4472 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -12)))
4474 (set (reg:HI SP_REG)
4475 (plus:HI (reg:HI SP_REG)
4476 (const_int -12)))])]
4479 ;; Cram two pushes into stm.l.
4482 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4483 (match_operand:SI 0 "register_operand" ""))
4484 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4485 (match_operand:SI 1 "register_operand" ""))]
4486 "TARGET_H8300S && !TARGET_NORMAL_MODE
4487 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4488 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4489 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4490 [(parallel [(set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
4492 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -8)))
4494 (set (reg:SI SP_REG)
4495 (plus:SI (reg:SI SP_REG)
4500 [(set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4501 (match_operand:SI 0 "register_operand" ""))
4502 (set (mem:SI (pre_dec:HI (reg:HI SP_REG)))
4503 (match_operand:SI 1 "register_operand" ""))]
4504 "TARGET_H8300S && TARGET_NORMAL_MODE
4505 && (REGNO_REG_CLASS (REGNO (operands[1])) == GENERAL_REGS
4506 && REGNO (operands[1]) == REGNO (operands[0]) + 1
4507 && (TARGET_H8300SX || (REGNO (operands[0]) & 1) == 0))"
4508 [(parallel [(set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -4)))
4510 (set (mem:SI (plus:HI (reg:HI SP_REG) (const_int -8)))
4512 (set (reg:HI SP_REG)
4513 (plus:HI (reg:HI SP_REG)
4520 ;; add.w r7,r0 (6 bytes)
4525 ;; adds #2,r0 (4 bytes)
4528 [(set (match_operand:HI 0 "register_operand" "")
4529 (match_operand:HI 1 "const_int_operand" ""))
4531 (plus:HI (match_dup 0)
4532 (match_operand:HI 2 "register_operand" "")))]
4533 "REG_P (operands[0]) && REG_P (operands[2])
4534 && REGNO (operands[0]) != REGNO (operands[2])
4535 && (satisfies_constraint_J (operands[1])
4536 || satisfies_constraint_L (operands[1])
4537 || satisfies_constraint_N (operands[1]))"
4541 (plus:HI (match_dup 0)
4549 ;; add.l er7,er0 (6 bytes)
4554 ;; adds #4,er0 (4 bytes)
4557 [(set (match_operand:SI 0 "register_operand" "")
4558 (match_operand:SI 1 "const_int_operand" ""))
4560 (plus:SI (match_dup 0)
4561 (match_operand:SI 2 "register_operand" "")))]
4562 "(TARGET_H8300H || TARGET_H8300S)
4563 && REG_P (operands[0]) && REG_P (operands[2])
4564 && REGNO (operands[0]) != REGNO (operands[2])
4565 && (satisfies_constraint_L (operands[1])
4566 || satisfies_constraint_N (operands[1]))"
4570 (plus:SI (match_dup 0)
4577 ;; add.l #10,er0 (takes 8 bytes)
4583 ;; add.l er7,er0 (takes 6 bytes)
4586 [(set (match_operand:SI 0 "register_operand" "")
4587 (match_operand:SI 1 "register_operand" ""))
4589 (plus:SI (match_dup 0)
4590 (match_operand:SI 2 "const_int_operand" "")))]
4591 "(TARGET_H8300H || TARGET_H8300S)
4592 && REG_P (operands[0]) && REG_P (operands[1])
4593 && REGNO (operands[0]) != REGNO (operands[1])
4594 && !satisfies_constraint_L (operands[2])
4595 && !satisfies_constraint_N (operands[2])
4596 && ((INTVAL (operands[2]) & 0xff) == INTVAL (operands[2])
4597 || (INTVAL (operands[2]) & 0xff00) == INTVAL (operands[2])
4598 || INTVAL (operands[2]) == 0xffff
4599 || INTVAL (operands[2]) == 0xfffe)"
4603 (plus:SI (match_dup 0)
4619 [(set (match_operand:HI 0 "register_operand" "")
4620 (plus:HI (match_dup 0)
4621 (match_operand 1 "incdec_operand" "")))
4622 (set (cc0) (compare (match_dup 0)
4625 (if_then_else (match_operator 3 "eqne_operator"
4626 [(cc0) (const_int 0)])
4627 (label_ref (match_operand 2 "" ""))
4629 "TARGET_H8300H || TARGET_H8300S"
4630 [(set (match_operand:HI 0 "register_operand" "")
4631 (unspec:HI [(match_dup 0)
4634 (set (cc0) (compare (match_dup 0)
4637 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4638 (label_ref (match_dup 2))
4642 ;; The SImode version of the previous pattern.
4645 [(set (match_operand:SI 0 "register_operand" "")
4646 (plus:SI (match_dup 0)
4647 (match_operand 1 "incdec_operand" "")))
4648 (set (cc0) (compare (match_dup 0)
4651 (if_then_else (match_operator 3 "eqne_operator"
4652 [(cc0) (const_int 0)])
4653 (label_ref (match_operand 2 "" ""))
4655 "TARGET_H8300H || TARGET_H8300S"
4656 [(set (match_operand:SI 0 "register_operand" "")
4657 (unspec:SI [(match_dup 0)
4660 (set (cc0) (compare (match_dup 0)
4663 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4664 (label_ref (match_dup 2))
4669 [(parallel [(set (cc0)
4670 (compare (zero_extract:SI (match_operand:QI 0 "register_operand" "")
4674 (clobber (scratch:QI))])
4676 (if_then_else (match_operator 1 "eqne_operator"
4677 [(cc0) (const_int 0)])
4678 (label_ref (match_operand 2 "" ""))
4680 "TARGET_H8300H || TARGET_H8300S"
4681 [(set (cc0) (compare (match_dup 0)
4684 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4685 (label_ref (match_dup 2))
4688 operands[3] = ((GET_CODE (operands[1]) == EQ)
4689 ? gen_rtx_GE (VOIDmode, cc0_rtx, const0_rtx)
4690 : gen_rtx_LT (VOIDmode, cc0_rtx, const0_rtx));
4693 ;; The next three peephole2's will try to transform
4695 ;; mov.b A,r0l (or mov.l A,er0)
4702 ;; and.b #CST,r0l (if CST is not 255)
4705 [(set (match_operand:QI 0 "register_operand" "")
4706 (match_operand:QI 1 "general_operand" ""))
4707 (set (match_operand:SI 2 "register_operand" "")
4708 (and:SI (match_dup 2)
4710 "(TARGET_H8300H || TARGET_H8300S)
4711 && !reg_overlap_mentioned_p (operands[2], operands[1])
4712 && REGNO (operands[0]) == REGNO (operands[2])"
4715 (set (strict_low_part (match_dup 0))
4720 [(set (match_operand:SI 0 "register_operand" "")
4721 (match_operand:SI 1 "general_operand" ""))
4723 (and:SI (match_dup 0)
4725 "(TARGET_H8300H || TARGET_H8300S)
4726 && !reg_overlap_mentioned_p (operands[0], operands[1])
4727 && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
4728 && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
4731 (set (strict_low_part (match_dup 2))
4734 operands[2] = gen_lowpart (QImode, operands[0]);
4735 operands[3] = gen_lowpart (QImode, operands[1]);
4739 [(set (match_operand 0 "register_operand" "")
4740 (match_operand 1 "general_operand" ""))
4741 (set (match_operand:SI 2 "register_operand" "")
4742 (and:SI (match_dup 2)
4743 (match_operand:SI 3 "const_int_qi_operand" "")))]
4744 "(TARGET_H8300H || TARGET_H8300S)
4745 && (GET_MODE (operands[0]) == QImode
4746 || GET_MODE (operands[0]) == HImode
4747 || GET_MODE (operands[0]) == SImode)
4748 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4749 && REGNO (operands[0]) == REGNO (operands[2])
4750 && !reg_overlap_mentioned_p (operands[2], operands[1])
4751 && !(GET_MODE (operands[1]) != QImode
4752 && GET_CODE (operands[1]) == MEM
4753 && !offsettable_memref_p (operands[1]))
4754 && !(GET_MODE (operands[1]) != QImode
4755 && GET_CODE (operands[1]) == MEM
4756 && MEM_VOLATILE_P (operands[1]))"
4759 (set (strict_low_part (match_dup 4))
4762 (and:SI (match_dup 2)
4765 operands[4] = gen_lowpart (QImode, operands[0]);
4766 operands[5] = gen_lowpart (QImode, operands[1]);
4767 operands[6] = GEN_INT (~0xff | INTVAL (operands[3]));
4771 [(set (match_operand:SI 0 "register_operand" "")
4772 (match_operand:SI 1 "register_operand" ""))
4774 (and:SI (match_dup 0)
4775 (const_int 65280)))]
4776 "(TARGET_H8300H || TARGET_H8300S)
4777 && !reg_overlap_mentioned_p (operands[0], operands[1])"
4780 (set (zero_extract:SI (match_dup 0)
4783 (lshiftrt:SI (match_dup 1)
4787 ;; If a load of mem:SI is followed by an AND that turns off the upper
4788 ;; half, then we can load mem:HI instead.
4791 [(set (match_operand:SI 0 "register_operand" "")
4792 (match_operand:SI 1 "memory_operand" ""))
4794 (and:SI (match_dup 0)
4795 (match_operand:SI 2 "const_int_operand" "")))]
4796 "(TARGET_H8300H || TARGET_H8300S)
4797 && !MEM_VOLATILE_P (operands[1])
4798 && offsettable_memref_p (operands[1])
4799 && (INTVAL (operands[2]) & ~0xffff) == 0
4800 && INTVAL (operands[2]) != 255"
4804 (and:SI (match_dup 0)
4807 operands[3] = gen_lowpart (HImode, operands[0]);
4808 operands[4] = gen_lowpart (HImode, operands[1]);
4811 ;; Convert a memory comparison to a move if there is a scratch register.
4814 [(match_scratch:QI 1 "r")
4816 (compare (match_operand:QI 0 "memory_operand" "")
4821 (set (cc0) (compare (match_dup 1)
4826 [(match_scratch:HI 1 "r")
4828 (compare (match_operand:HI 0 "memory_operand" "")
4830 "TARGET_H8300H || TARGET_H8300S"
4833 (set (cc0) (compare (match_dup 1)
4838 [(match_scratch:SI 1 "r")
4840 (compare (match_operand:SI 0 "memory_operand" "")
4842 "TARGET_H8300H || TARGET_H8300S"
4845 (set (cc0) (compare (match_dup 1)
4850 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
4851 ;; the equivalent with shorter sequences. Here is the summary. Cases
4852 ;; are grouped for each define_peephole2.
4854 ;; reg const_int use insn
4855 ;; --------------------------------------------------------
4856 ;; dead -2 eq/ne inc.l
4857 ;; dead -1 eq/ne inc.l
4858 ;; dead 1 eq/ne dec.l
4859 ;; dead 2 eq/ne dec.l
4861 ;; dead 1 ge/lt shar.l
4862 ;; dead 3 (H8S) ge/lt shar.l
4864 ;; dead 1 geu/ltu shar.l
4865 ;; dead 3 (H8S) geu/ltu shar.l
4867 ;; ---- 255 ge/lt mov.b
4869 ;; ---- 255 geu/ltu mov.b
4883 (compare (match_operand:HI 0 "register_operand" "")
4884 (match_operand:HI 1 "incdec_operand" "")))
4886 (if_then_else (match_operator 3 "eqne_operator"
4887 [(cc0) (const_int 0)])
4888 (label_ref (match_operand 2 "" ""))
4890 "(TARGET_H8300H || TARGET_H8300S)
4891 && INTVAL (operands[1]) != 0
4892 && peep2_reg_dead_p (1, operands[0])"
4894 (unspec:HI [(match_dup 0)
4897 (set (cc0) (compare (match_dup 0)
4900 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
4901 (label_ref (match_dup 2))
4904 operands[4] = GEN_INT (- INTVAL (operands[1]));
4919 (compare (match_operand:HI 0 "register_operand" "")
4920 (match_operand:HI 1 "const_int_operand" "")))
4922 (if_then_else (match_operator 2 "gtle_operator"
4923 [(cc0) (const_int 0)])
4924 (label_ref (match_operand 3 "" ""))
4926 "(TARGET_H8300H || TARGET_H8300S)
4927 && peep2_reg_dead_p (1, operands[0])
4928 && (INTVAL (operands[1]) == 1
4929 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4930 [(parallel [(set (match_dup 0)
4931 (ashiftrt:HI (match_dup 0)
4933 (clobber (scratch:QI))])
4934 (set (cc0) (compare (match_dup 0)
4937 (if_then_else (match_dup 2)
4938 (label_ref (match_dup 3))
4941 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4956 (compare (match_operand:HI 0 "register_operand" "")
4957 (match_operand:HI 1 "const_int_operand" "")))
4959 (if_then_else (match_operator 2 "gtuleu_operator"
4960 [(cc0) (const_int 0)])
4961 (label_ref (match_operand 3 "" ""))
4963 "(TARGET_H8300H || TARGET_H8300S)
4964 && peep2_reg_dead_p (1, operands[0])
4965 && (INTVAL (operands[1]) == 1
4966 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
4967 [(parallel [(set (match_dup 0)
4968 (ashiftrt:HI (match_dup 0)
4970 (clobber (scratch:QI))])
4971 (set (cc0) (compare (match_dup 0)
4974 (if_then_else (match_dup 5)
4975 (label_ref (match_dup 3))
4978 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
4979 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
4980 VOIDmode, cc0_rtx, const0_rtx);
4995 (compare (match_operand:HI 0 "register_operand" "")
4998 (if_then_else (match_operator 1 "gtle_operator"
4999 [(cc0) (const_int 0)])
5000 (label_ref (match_operand 2 "" ""))
5002 "TARGET_H8300H || TARGET_H8300S"
5003 [(set (cc0) (compare (and:HI (match_dup 0)
5007 (if_then_else (match_dup 1)
5008 (label_ref (match_dup 2))
5024 (compare (match_operand:HI 0 "register_operand" "")
5027 (if_then_else (match_operator 1 "gtuleu_operator"
5028 [(cc0) (const_int 0)])
5029 (label_ref (match_operand 2 "" ""))
5031 "TARGET_H8300H || TARGET_H8300S"
5032 [(set (cc0) (compare (and:HI (match_dup 0)
5036 (if_then_else (match_dup 3)
5037 (label_ref (match_dup 2))
5040 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5041 VOIDmode, cc0_rtx, const0_rtx);
5044 ;; (compare (reg:SI) (const_int)) takes 6 bytes, so we try to achieve
5045 ;; the equivalent with shorter sequences. Here is the summary. Cases
5046 ;; are grouped for each define_peephole2.
5048 ;; reg const_int use insn
5049 ;; --------------------------------------------------------
5050 ;; live -2 eq/ne copy and inc.l
5051 ;; live -1 eq/ne copy and inc.l
5052 ;; live 1 eq/ne copy and dec.l
5053 ;; live 2 eq/ne copy and dec.l
5055 ;; dead -2 eq/ne inc.l
5056 ;; dead -1 eq/ne inc.l
5057 ;; dead 1 eq/ne dec.l
5058 ;; dead 2 eq/ne dec.l
5060 ;; dead -131072 eq/ne inc.w and test
5061 ;; dead -65536 eq/ne inc.w and test
5062 ;; dead 65536 eq/ne dec.w and test
5063 ;; dead 131072 eq/ne dec.w and test
5065 ;; dead 0x000000?? except 1 and 2 eq/ne xor.b and test
5066 ;; dead 0x0000??00 eq/ne xor.b and test
5067 ;; dead 0x0000ffff eq/ne not.w and test
5069 ;; dead 0xffffff?? except -1 and -2 eq/ne xor.b and not.l
5070 ;; dead 0xffff??ff eq/ne xor.b and not.l
5071 ;; dead 0x40000000 (H8S) eq/ne rotl.l and dec.l
5072 ;; dead 0x80000000 eq/ne rotl.l and dec.l
5074 ;; live 1 ge/lt copy and shar.l
5075 ;; live 3 (H8S) ge/lt copy and shar.l
5077 ;; live 1 geu/ltu copy and shar.l
5078 ;; live 3 (H8S) geu/ltu copy and shar.l
5080 ;; dead 1 ge/lt shar.l
5081 ;; dead 3 (H8S) ge/lt shar.l
5083 ;; dead 1 geu/ltu shar.l
5084 ;; dead 3 (H8S) geu/ltu shar.l
5086 ;; dead 3 (H8/300H) ge/lt and.b and test
5087 ;; dead 7 ge/lt and.b and test
5088 ;; dead 15 ge/lt and.b and test
5089 ;; dead 31 ge/lt and.b and test
5090 ;; dead 63 ge/lt and.b and test
5091 ;; dead 127 ge/lt and.b and test
5092 ;; dead 255 ge/lt and.b and test
5094 ;; dead 3 (H8/300H) geu/ltu and.b and test
5095 ;; dead 7 geu/ltu and.b and test
5096 ;; dead 15 geu/ltu and.b and test
5097 ;; dead 31 geu/ltu and.b and test
5098 ;; dead 63 geu/ltu and.b and test
5099 ;; dead 127 geu/ltu and.b and test
5100 ;; dead 255 geu/ltu and.b and test
5102 ;; ---- 65535 ge/lt mov.w
5104 ;; ---- 65535 geu/ltu mov.w
5118 (compare (match_operand:SI 0 "register_operand" "")
5119 (match_operand:SI 1 "incdec_operand" "")))
5121 (if_then_else (match_operator 3 "eqne_operator"
5122 [(cc0) (const_int 0)])
5123 (label_ref (match_operand 2 "" ""))
5125 "(TARGET_H8300H || TARGET_H8300S)
5126 && INTVAL (operands[1]) != 0
5127 && peep2_reg_dead_p (1, operands[0])"
5129 (unspec:SI [(match_dup 0)
5132 (set (cc0) (compare (match_dup 0)
5135 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5136 (label_ref (match_dup 2))
5139 operands[4] = GEN_INT (- INTVAL (operands[1]));
5154 (compare (match_operand:SI 0 "register_operand" "")
5155 (match_operand:SI 1 "const_int_operand" "")))
5157 (if_then_else (match_operator 3 "eqne_operator"
5158 [(cc0) (const_int 0)])
5159 (label_ref (match_operand 2 "" ""))
5161 "(TARGET_H8300H || TARGET_H8300S)
5162 && peep2_reg_dead_p (1, operands[0])
5163 && (INTVAL (operands[1]) == -131072
5164 || INTVAL (operands[1]) == -65536
5165 || INTVAL (operands[1]) == 65536
5166 || INTVAL (operands[1]) == 131072)"
5168 (plus:SI (match_dup 0)
5170 (set (cc0) (compare (match_dup 0)
5173 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5174 (label_ref (match_dup 2))
5177 operands[4] = GEN_INT (- INTVAL (operands[1]));
5193 (compare (match_operand:SI 0 "register_operand" "")
5194 (match_operand:SI 1 "const_int_operand" "")))
5196 (if_then_else (match_operator 3 "eqne_operator"
5197 [(cc0) (const_int 0)])
5198 (label_ref (match_operand 2 "" ""))
5200 "(TARGET_H8300H || TARGET_H8300S)
5201 && peep2_reg_dead_p (1, operands[0])
5202 && ((INTVAL (operands[1]) & 0x00ff) == INTVAL (operands[1])
5203 || (INTVAL (operands[1]) & 0xff00) == INTVAL (operands[1])
5204 || INTVAL (operands[1]) == 0x0000ffff)
5205 && INTVAL (operands[1]) != 0
5206 && INTVAL (operands[1]) != 1
5207 && INTVAL (operands[1]) != 2"
5209 (xor:SI (match_dup 0)
5211 (set (cc0) (compare (match_dup 0)
5214 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5215 (label_ref (match_dup 2))
5232 (compare (match_operand:SI 0 "register_operand" "")
5233 (match_operand:SI 1 "const_int_operand" "")))
5235 (if_then_else (match_operator 3 "eqne_operator"
5236 [(cc0) (const_int 0)])
5237 (label_ref (match_operand 2 "" ""))
5239 "(TARGET_H8300H || TARGET_H8300S)
5240 && peep2_reg_dead_p (1, operands[0])
5241 && ((INTVAL (operands[1]) | 0x00ff) == -1
5242 || (INTVAL (operands[1]) | 0xff00) == -1)
5243 && INTVAL (operands[1]) != -1
5244 && INTVAL (operands[1]) != -2"
5246 (xor:SI (match_dup 0)
5249 (not:SI (match_dup 0)))
5250 (set (cc0) (compare (match_dup 0)
5253 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5254 (label_ref (match_dup 2))
5257 operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);
5262 ;; cmp.l #-2147483648,er0
5273 (compare (match_operand:SI 0 "register_operand" "")
5274 (match_operand:SI 1 "const_int_operand" "")))
5276 (if_then_else (match_operator 3 "eqne_operator"
5277 [(cc0) (const_int 0)])
5278 (label_ref (match_operand 2 "" ""))
5280 "(TARGET_H8300H || TARGET_H8300S)
5281 && peep2_reg_dead_p (1, operands[0])
5282 && (INTVAL (operands[1]) == -2147483647 - 1
5283 || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
5285 (rotate:SI (match_dup 0)
5288 (unspec:SI [(match_dup 0)
5291 (set (cc0) (compare (match_dup 0)
5294 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5295 (label_ref (match_dup 2))
5298 operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483647 - 1 ? 1 : 2);
5312 ;; We avoid this transformation if we see more than one copy of the
5313 ;; same compare insn immediately before this one.
5316 [(match_scratch:SI 4 "r")
5318 (compare (match_operand:SI 0 "register_operand" "")
5319 (match_operand:SI 1 "const_int_operand" "")))
5321 (if_then_else (match_operator 2 "gtle_operator"
5322 [(cc0) (const_int 0)])
5323 (label_ref (match_operand 3 "" ""))
5325 "(TARGET_H8300H || TARGET_H8300S)
5326 && !peep2_reg_dead_p (1, operands[0])
5327 && (INTVAL (operands[1]) == 1
5328 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5329 && !same_cmp_preceding_p (insn)"
5332 (parallel [(set (match_dup 4)
5333 (ashiftrt:SI (match_dup 4)
5335 (clobber (scratch:QI))])
5336 (set (cc0) (compare (match_dup 4)
5339 (if_then_else (match_dup 2)
5340 (label_ref (match_dup 3))
5343 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5357 ;; We avoid this transformation if we see more than one copy of the
5358 ;; same compare insn immediately before this one.
5361 [(match_scratch:SI 4 "r")
5363 (compare (match_operand:SI 0 "register_operand" "")
5364 (match_operand:SI 1 "const_int_operand" "")))
5366 (if_then_else (match_operator 2 "gtuleu_operator"
5367 [(cc0) (const_int 0)])
5368 (label_ref (match_operand 3 "" ""))
5370 "(TARGET_H8300H || TARGET_H8300S)
5371 && !peep2_reg_dead_p (1, operands[0])
5372 && (INTVAL (operands[1]) == 1
5373 || (TARGET_H8300S && INTVAL (operands[1]) == 3))
5374 && !same_cmp_preceding_p (insn)"
5377 (parallel [(set (match_dup 4)
5378 (ashiftrt:SI (match_dup 4)
5380 (clobber (scratch:QI))])
5381 (set (cc0) (compare (match_dup 4)
5384 (if_then_else (match_dup 6)
5385 (label_ref (match_dup 3))
5388 operands[5] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5389 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5390 VOIDmode, cc0_rtx, const0_rtx);
5405 (compare (match_operand:SI 0 "register_operand" "")
5406 (match_operand:SI 1 "const_int_operand" "")))
5408 (if_then_else (match_operator 2 "gtle_operator"
5409 [(cc0) (const_int 0)])
5410 (label_ref (match_operand 3 "" ""))
5412 "(TARGET_H8300H || TARGET_H8300S)
5413 && peep2_reg_dead_p (1, operands[0])
5414 && (INTVAL (operands[1]) == 1
5415 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5416 [(parallel [(set (match_dup 0)
5417 (ashiftrt:SI (match_dup 0)
5419 (clobber (scratch:QI))])
5420 (set (cc0) (compare (match_dup 0)
5423 (if_then_else (match_dup 2)
5424 (label_ref (match_dup 3))
5427 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5442 (compare (match_operand:SI 0 "register_operand" "")
5443 (match_operand:SI 1 "const_int_operand" "")))
5445 (if_then_else (match_operator 2 "gtuleu_operator"
5446 [(cc0) (const_int 0)])
5447 (label_ref (match_operand 3 "" ""))
5449 "(TARGET_H8300H || TARGET_H8300S)
5450 && peep2_reg_dead_p (1, operands[0])
5451 && (INTVAL (operands[1]) == 1
5452 || (TARGET_H8300S && INTVAL (operands[1]) == 3))"
5453 [(parallel [(set (match_dup 0)
5454 (ashiftrt:SI (match_dup 0)
5456 (clobber (scratch:QI))])
5457 (set (cc0) (compare (match_dup 0)
5460 (if_then_else (match_dup 5)
5461 (label_ref (match_dup 3))
5464 operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
5465 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5466 VOIDmode, cc0_rtx, const0_rtx);
5482 (compare (match_operand:SI 0 "register_operand" "")
5483 (match_operand:SI 1 "const_int_operand" "")))
5485 (if_then_else (match_operator 2 "gtle_operator"
5486 [(cc0) (const_int 0)])
5487 (label_ref (match_operand 3 "" ""))
5489 "(TARGET_H8300H || TARGET_H8300S)
5490 && peep2_reg_dead_p (1, operands[0])
5491 && (INTVAL (operands[1]) == 3
5492 || INTVAL (operands[1]) == 7
5493 || INTVAL (operands[1]) == 15
5494 || INTVAL (operands[1]) == 31
5495 || INTVAL (operands[1]) == 63
5496 || INTVAL (operands[1]) == 127
5497 || INTVAL (operands[1]) == 255)"
5499 (and:SI (match_dup 0)
5501 (set (cc0) (compare (match_dup 0)
5504 (if_then_else (match_dup 2)
5505 (label_ref (match_dup 3))
5508 operands[4] = GEN_INT (~INTVAL (operands[1]));
5524 (compare (match_operand:SI 0 "register_operand" "")
5525 (match_operand:SI 1 "const_int_operand" "")))
5527 (if_then_else (match_operator 2 "gtuleu_operator"
5528 [(cc0) (const_int 0)])
5529 (label_ref (match_operand 3 "" ""))
5531 "(TARGET_H8300H || TARGET_H8300S)
5532 && peep2_reg_dead_p (1, operands[0])
5533 && ((TARGET_H8300H && INTVAL (operands[1]) == 3)
5534 || INTVAL (operands[1]) == 7
5535 || INTVAL (operands[1]) == 15
5536 || INTVAL (operands[1]) == 31
5537 || INTVAL (operands[1]) == 63
5538 || INTVAL (operands[1]) == 127
5539 || INTVAL (operands[1]) == 255)"
5541 (and:SI (match_dup 0)
5543 (set (cc0) (compare (match_dup 0)
5546 (if_then_else (match_dup 5)
5547 (label_ref (match_dup 3))
5550 operands[4] = GEN_INT (~INTVAL (operands[1]));
5551 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[2]) == GTU ? NE : EQ,
5552 VOIDmode, cc0_rtx, const0_rtx);
5567 (compare (match_operand:SI 0 "register_operand" "")
5570 (if_then_else (match_operator 1 "gtle_operator"
5571 [(cc0) (const_int 0)])
5572 (label_ref (match_operand 2 "" ""))
5574 "TARGET_H8300H || TARGET_H8300S"
5575 [(set (cc0) (compare (and:SI (match_dup 0)
5579 (if_then_else (match_dup 1)
5580 (label_ref (match_dup 2))
5596 (compare (match_operand:SI 0 "register_operand" "")
5599 (if_then_else (match_operator 1 "gtuleu_operator"
5600 [(cc0) (const_int 0)])
5601 (label_ref (match_operand 2 "" ""))
5603 "TARGET_H8300H || TARGET_H8300S"
5604 [(set (cc0) (compare (and:SI (match_dup 0)
5608 (if_then_else (match_dup 3)
5609 (label_ref (match_dup 2))
5612 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GTU ? NE : EQ,
5613 VOIDmode, cc0_rtx, const0_rtx);
5627 ;; We avoid this transformation if we see more than one copy of the
5628 ;; same compare insn.
5631 [(match_scratch:SI 4 "r")
5633 (compare (match_operand:SI 0 "register_operand" "")
5634 (match_operand:SI 1 "incdec_operand" "")))
5636 (if_then_else (match_operator 3 "eqne_operator"
5637 [(cc0) (const_int 0)])
5638 (label_ref (match_operand 2 "" ""))
5640 "(TARGET_H8300H || TARGET_H8300S)
5641 && INTVAL (operands[1]) != 0
5642 && !peep2_reg_dead_p (1, operands[0])
5643 && !same_cmp_following_p (insn)"
5647 (unspec:SI [(match_dup 4)
5650 (set (cc0) (compare (match_dup 4)
5653 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5654 (label_ref (match_dup 2))
5657 operands[5] = GEN_INT (- INTVAL (operands[1]));
5659 ;; Narrow the mode of testing if possible.
5662 [(set (match_operand:HI 0 "register_operand" "")
5663 (and:HI (match_dup 0)
5664 (match_operand:HI 1 "const_int_qi_operand" "")))
5665 (set (cc0) (compare (match_dup 0)
5668 (if_then_else (match_operator 3 "eqne_operator"
5669 [(cc0) (const_int 0)])
5670 (label_ref (match_operand 2 "" ""))
5672 "peep2_reg_dead_p (2, operands[0])"
5674 (and:QI (match_dup 4)
5676 (set (cc0) (compare (match_dup 4)
5679 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5680 (label_ref (match_dup 2))
5683 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5684 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5688 [(set (match_operand:SI 0 "register_operand" "")
5689 (and:SI (match_dup 0)
5690 (match_operand:SI 1 "const_int_qi_operand" "")))
5691 (set (cc0) (compare (match_dup 0)
5694 (if_then_else (match_operator 3 "eqne_operator"
5695 [(cc0) (const_int 0)])
5696 (label_ref (match_operand 2 "" ""))
5698 "peep2_reg_dead_p (2, operands[0])"
5700 (and:QI (match_dup 4)
5702 (set (cc0) (compare (match_dup 4)
5705 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5706 (label_ref (match_dup 2))
5709 operands[4] = gen_rtx_REG (QImode, REGNO (operands[0]));
5710 operands[5] = gen_int_mode (INTVAL (operands[1]), QImode);
5714 [(set (match_operand:SI 0 "register_operand" "")
5715 (and:SI (match_dup 0)
5716 (match_operand:SI 1 "const_int_hi_operand" "")))
5717 (set (cc0) (compare (match_dup 0)
5720 (if_then_else (match_operator 3 "eqne_operator"
5721 [(cc0) (const_int 0)])
5722 (label_ref (match_operand 2 "" ""))
5724 "peep2_reg_dead_p (2, operands[0])"
5726 (and:HI (match_dup 4)
5728 (set (cc0) (compare (match_dup 4)
5731 (if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
5732 (label_ref (match_dup 2))
5735 operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
5736 operands[5] = gen_int_mode (INTVAL (operands[1]), HImode);
5740 [(set (match_operand:SI 0 "register_operand" "")
5741 (and:SI (match_dup 0)
5742 (match_operand:SI 1 "const_int_qi_operand" "")))
5744 (xor:SI (match_dup 0)
5745 (match_operand:SI 2 "const_int_qi_operand" "")))
5746 (set (cc0) (compare (match_dup 0)
5749 (if_then_else (match_operator 4 "eqne_operator"
5750 [(cc0) (const_int 0)])
5751 (label_ref (match_operand 3 "" ""))
5753 "peep2_reg_dead_p (3, operands[0])
5754 && (~INTVAL (operands[1]) & INTVAL (operands[2])) == 0"
5756 (and:QI (match_dup 5)
5759 (xor:QI (match_dup 5)
5761 (set (cc0) (compare (match_dup 5)
5764 (if_then_else (match_op_dup 4 [(cc0) (const_int 0)])
5765 (label_ref (match_dup 3))
5768 operands[5] = gen_rtx_REG (QImode, REGNO (operands[0]));
5769 operands[6] = gen_int_mode (INTVAL (operands[1]), QImode);
5770 operands[7] = gen_int_mode (INTVAL (operands[2]), QImode);
5773 ;; These triggers right at the end of allocation of locals in the
5774 ;; prologue (and possibly at other places).
5776 ;; stack adjustment of -4, generate one push
5778 ;; before : 6 bytes, 10 clocks
5779 ;; after : 4 bytes, 10 clocks
5782 [(set (reg:SI SP_REG)
5783 (plus:SI (reg:SI SP_REG)
5785 (set (mem:SI (reg:SI SP_REG))
5786 (match_operand:SI 0 "register_operand" ""))]
5787 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5788 && REGNO (operands[0]) != SP_REG"
5789 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5793 ;; stack adjustment of -12, generate one push
5795 ;; before : 10 bytes, 14 clocks
5796 ;; after : 8 bytes, 14 clocks
5799 [(set (reg:SI SP_REG)
5800 (plus:SI (reg:SI SP_REG)
5802 (set (mem:SI (reg:SI SP_REG))
5803 (match_operand:SI 0 "register_operand" ""))]
5804 "(TARGET_H8300H || TARGET_H8300S) && !TARGET_NORMAL_MODE
5805 && REGNO (operands[0]) != SP_REG"
5806 [(set (reg:SI SP_REG)
5807 (plus:SI (reg:SI SP_REG)
5809 (set (reg:SI SP_REG)
5810 (plus:SI (reg:SI SP_REG)
5812 (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
5826 ;; if "reg" dies at the end of the sequence.
5829 [(set (match_operand 0 "register_operand" "")
5830 (match_operand 1 "memory_operand" ""))
5832 (match_operator 2 "h8sx_binary_memory_operator"
5834 (match_operand 3 "h8300_src_operand" "")]))
5835 (set (match_operand 4 "memory_operand" "")
5837 "0 /* Disable because it breaks compiling fp-bit.c. */
5839 && peep2_reg_dead_p (3, operands[0])
5840 && !reg_overlap_mentioned_p (operands[0], operands[3])
5841 && !reg_overlap_mentioned_p (operands[0], operands[4])
5842 && h8sx_mergeable_memrefs_p (operands[4], operands[1])"
5846 operands[5] = shallow_copy_rtx (operands[2]);
5847 XEXP (operands[5], 0) = operands[1];
5859 ;; if "reg" dies in the second insn.
5862 [(set (match_operand 0 "register_operand" "")
5863 (match_operand 1 "h8300_src_operand" ""))
5864 (set (match_operand 2 "h8300_dst_operand" "")
5865 (match_operator 3 "h8sx_binary_memory_operator"
5866 [(match_operand 4 "h8300_dst_operand" "")
5868 "0 /* Disable because it breaks compiling fp-bit.c. */
5870 && peep2_reg_dead_p (2, operands[0])
5871 && !reg_overlap_mentioned_p (operands[0], operands[4])"
5875 operands[5] = shallow_copy_rtx (operands[3]);
5876 XEXP (operands[5], 1) = operands[1];
5889 ;; if "reg" dies at the end of the sequence.
5892 [(set (match_operand 0 "register_operand" "")
5893 (match_operand 1 "memory_operand" ""))
5895 (match_operator 2 "h8sx_unary_memory_operator"
5897 (set (match_operand 3 "memory_operand" "")
5900 && peep2_reg_dead_p (3, operands[0])
5901 && !reg_overlap_mentioned_p (operands[0], operands[3])
5902 && h8sx_mergeable_memrefs_p (operands[3], operands[1])"
5906 operands[4] = shallow_copy_rtx (operands[2]);
5907 XEXP (operands[4], 0) = operands[1];
5919 ;; if "reg" dies in the comparison.
5922 [(set (match_operand 0 "register_operand" "")
5923 (match_operand 1 "h8300_dst_operand" ""))
5925 (compare (match_dup 0)
5926 (match_operand 2 "h8300_src_operand" "")))]
5928 && peep2_reg_dead_p (2, operands[0])
5929 && !reg_overlap_mentioned_p (operands[0], operands[2])
5930 && operands[2] != const0_rtx"
5932 (compare (match_dup 1)
5935 ;; Likewise for the second operand.
5938 [(set (match_operand 0 "register_operand" "")
5939 (match_operand 1 "h8300_src_operand" ""))
5941 (compare (match_operand 2 "h8300_dst_operand" "")
5944 && peep2_reg_dead_p (2, operands[0])
5945 && !reg_overlap_mentioned_p (operands[0], operands[2])"
5947 (compare (match_dup 2)
5950 ;; Combine two moves.
5953 [(set (match_operand 0 "register_operand" "")
5954 (match_operand 1 "h8300_src_operand" ""))
5955 (set (match_operand 2 "h8300_dst_operand" "")
5958 && peep2_reg_dead_p (2, operands[0])
5959 && !reg_overlap_mentioned_p (operands[0], operands[2])"