1 ;; ----------------------------------------------------------------------
3 ;; ----------------------------------------------------------------------
7 (define_insn "*movqi_h8nosx"
8 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
9 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
11 && h8300_move_ok (operands[0], operands[1])"
20 (symbol_ref "compute_mov_length (operands)"))
21 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
23 (define_insn "*movqi_h8sx"
24 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
25 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
30 [(set_attr "length_table" "mov_imm4,movb")
31 (set_attr "cc" "set_znv")])
33 (define_expand "mov<mode>"
34 [(set (match_operand:QHSIF 0 "general_operand_dst" "")
35 (match_operand:QHSIF 1 "general_operand_src" ""))]
38 enum machine_mode mode = <MODE>mode;
41 /* Other H8 chips, except the H8/SX family can only handle a
42 single memory operand, which is checked by h8300_move_ok.
44 We could perhaps have h8300_move_ok handle the H8/SX better
45 and just remove the !TARGET_H8300SX conditional. */
46 if (!h8300_move_ok (operands[0], operands[1]))
47 operands[1] = copy_to_mode_reg (mode, operand1);
51 (define_insn "movstrictqi"
52 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
53 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
58 [(set_attr "length" "2,*")
59 (set_attr "length_table" "*,movb")
60 (set_attr "cc" "set_zn,set_znv")])
64 (define_insn "*movhi_h8nosx"
65 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
66 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
68 && h8300_move_ok (operands[0], operands[1])"
77 (symbol_ref "compute_mov_length (operands)"))
78 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
80 (define_insn "*movhi_h8sx"
81 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
82 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
90 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
91 (set_attr "length" "2,2,*,*,*")
92 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
94 (define_insn "movstricthi"
95 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
96 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
102 [(set_attr "length" "2,2,*")
103 (set_attr "length_table" "*,*,movw")
104 (set_attr "cc" "set_zn,set_znv,set_znv")])
107 (define_insn "*movsi_h8300hs"
108 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
109 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
110 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
111 && h8300_move_ok (operands[0], operands[1])"
113 switch (which_alternative)
116 return "sub.l %S0,%S0";
120 return "clrmac\;ldmac %1,macl";
122 return "stmac macl,%0";
124 if (GET_CODE (operands[1]) == CONST_INT)
126 int val = INTVAL (operands[1]);
128 /* Look for constants which can be made by adding an 8-bit
129 number to zero in one of the two low bytes. */
130 if (val == (val & 0xff))
132 operands[1] = GEN_INT ((char) val & 0xff);
133 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
136 if (val == (val & 0xff00))
138 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
139 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
142 /* Look for constants that can be obtained by subs, inc, and
144 switch (val & 0xffffffff)
147 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
149 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
151 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
154 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
156 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
159 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
161 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
164 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
166 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
170 return "mov.l %S1,%S0";
172 [(set (attr "length")
173 (symbol_ref "compute_mov_length (operands)"))
174 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
176 (define_insn "*movsi_h8sx"
177 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
178 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
186 clrmac\;ldmac %1,macl
188 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
189 (set_attr "length" "2,2,*,*,2,6,4")
190 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
192 (define_insn "*movsf_h8sx"
193 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
194 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
199 [(set_attr "length" "2,*")
200 (set_attr "length_table" "*,movl")
201 (set_attr "cc" "set_zn,set_znv")])
203 (define_insn "*movsf_h8300hs"
204 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
205 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
207 && (register_operand (operands[0], SFmode)
208 || register_operand (operands[1], SFmode))"
216 [(set (attr "length")
217 (symbol_ref "compute_mov_length (operands)"))
218 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
220 ;; ----------------------------------------------------------------------
222 ;; ----------------------------------------------------------------------
224 (define_insn "*push1_h8300hs_<QHI:mode>"
228 (plus:P (reg:P SP_REG) (const_int -4))))
229 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
232 [(set_attr "length" "4")])