gcc/config/h8300/multiply.md

   1 ;; ----------------------------------------------------------------------
   2 ;; MULTIPLY INSTRUCTIONS
   3 ;; ----------------------------------------------------------------------
   4
   5 ;; Note that the H8/300 can only handle umulqihi3.
   6
   7 (define_expand "mulqihi3"
   8   [(set (match_operand:HI 0 "register_operand" "")
   9         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
  10                  ;; intentionally-mismatched modes
  11                  (match_operand:QI 2 "reg_or_nibble_operand" "")))]
  12   ""
  13   {
  14     if (GET_MODE (operands[2]) != VOIDmode)
  15       operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
  16   })
  17
  18 (define_insn "*mulqihi3_const"
  19   [(set (match_operand:HI 0 "register_operand" "=r")
  20         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
  21                  (match_operand:QI 2 "nibble_operand" "IP4>X")))]
  22   "TARGET_H8300SX"
  23   "mulxs.b      %X2,%T0"
  24   [(set_attr "length" "4")
  25    (set_attr "cc" "set_zn")])
  26
  27 (define_insn "*mulqihi3"
  28   [(set (match_operand:HI 0 "register_operand" "=r")
  29         (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
  30                  (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  31   ""
  32   "mulxs.b      %X2,%T0"
  33   [(set_attr "length" "4")
  34    (set_attr "cc" "set_zn")])
  35
  36 (define_expand "mulhisi3"
  37   [(set (match_operand:SI 0 "register_operand" "")
  38         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
  39                  ;; intentionally-mismatched modes
  40                  (match_operand:HI 2 "reg_or_nibble_operand" "")))]
  41   ""
  42   {
  43     if (GET_MODE (operands[2]) != VOIDmode)
  44       operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
  45   })
  46
  47 (define_insn "*mulhisi3_const"
  48   [(set (match_operand:SI 0 "register_operand" "=r")
  49         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
  50                  (match_operand:SI 2 "nibble_operand" "IP4>X")))]
  51   "TARGET_H8300SX"
  52   "mulxs.w      %T2,%S0"
  53   [(set_attr "length" "4")
  54    (set_attr "cc" "set_zn")])
  55
  56 (define_insn "*mulhisi3"
  57   [(set (match_operand:SI 0 "register_operand" "=r")
  58         (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
  59                  (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  60   ""
  61   "mulxs.w      %T2,%S0"
  62   [(set_attr "length" "4")
  63    (set_attr "cc" "set_zn")])
  64
  65 (define_expand "umulqihi3"
  66   [(set (match_operand:HI 0 "register_operand" "")
  67         (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
  68                  ;; intentionally-mismatched modes
  69                  (match_operand:QI 2 "reg_or_nibble_operand" "")))]
  70   ""
  71   {
  72     if (GET_MODE (operands[2]) != VOIDmode)
  73       operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
  74   })
  75
  76 (define_insn "*umulqihi3_const"
  77   [(set (match_operand:HI 0 "register_operand" "=r")
  78         (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
  79                  (match_operand:QI 2 "nibble_operand" "IP4>X")))]
  80   "TARGET_H8300SX"
  81   "mulxu.b      %X2,%T0"
  82   [(set_attr "length" "4")
  83    (set_attr "cc" "set_zn")])
  84
  85 (define_insn "*umulqihi3"
  86   [(set (match_operand:HI 0 "register_operand" "=r")
  87         (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
  88                  (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  89   ""
  90   "mulxu.b      %X2,%T0"
  91   [(set_attr "length" "2")
  92    (set_attr "cc" "none_0hit")])
  93
  94 (define_expand "umulhisi3"
  95   [(set (match_operand:SI 0 "register_operand" "")
  96         (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
  97                  ;; intentionally-mismatched modes
  98                  (match_operand:HI 2 "reg_or_nibble_operand" "")))]
  99   ""
 100   {
 101     if (GET_MODE (operands[2]) != VOIDmode)
 102       operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
 103   })
 104
 105 (define_insn "*umulhisi3_const"
 106   [(set (match_operand:SI 0 "register_operand" "=r")
 107         (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 108                  (match_operand:SI 2 "nibble_operand" "IP4>X")))]
 109   "TARGET_H8300SX"
 110   "mulxu.w      %T2,%S0"
 111   [(set_attr "length" "4")
 112    (set_attr "cc" "set_zn")])
 113
 114 (define_insn "*umulhisi3"
 115   [(set (match_operand:SI 0 "register_operand" "=r")
 116         (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 117                  (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
 118   ""
 119   "mulxu.w      %T2,%S0"
 120   [(set_attr "length" "2")
 121    (set_attr "cc" "none_0hit")])
 122
 123 ;; We could have used mulu.[wl] here, but mulu.[lw] is only available
 124 ;; on a H8SX with a multiplier, whereas muls.w seems to be available
 125 ;; on all H8SX variants.
 126
 127 (define_insn "mul<mode>3"
 128   [(set (match_operand:HSI 0 "register_operand" "=r")
 129         (mult:HSI (match_operand:HSI 1 "register_operand" "%0")
 130                   (match_operand:HSI 2 "reg_or_nibble_operand" "r IP4>X")))]
 131   "TARGET_H8300SX"
 132   { return <MODE>mode == HImode ? "muls.w\\t%T2,%T0" : "muls.l\\t%S2,%S0"; }
 133   [(set_attr "length" "4")
 134    (set_attr "cc" "set_zn")])
 135
 136 (define_insn "smulsi3_highpart"
 137   [(set (match_operand:SI 0 "register_operand" "=r")
 138         (truncate:SI
 139          (lshiftrt:DI
 140           (mult:DI
 141            (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
 142            (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
 143           (const_int 32))))]
 144   "TARGET_H8300SXMUL"
 145   "muls/u.l\\t%S2,%S0"
 146   [(set_attr "length" "4")
 147    (set_attr "cc" "set_zn")])
 148
 149 (define_insn "umulsi3_highpart"
 150   [(set (match_operand:SI 0 "register_operand" "=r")
 151         (truncate:SI
 152           (ashiftrt:DI
 153             (mult:DI
 154               (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
 155               (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
 156             (const_int 32))))]
 157   "TARGET_H8300SX"
 158   "mulu/u.l\\t%S2,%S0"
 159   [(set_attr "length" "4")
 160    (set_attr "cc" "none_0hit")])
 161
 162 ;; This is a "bridge" instruction.  Combine can't cram enough insns
 163 ;; together to crate a MAC instruction directly, but it can create
 164 ;; this instruction, which then allows combine to create the real
 165 ;; MAC insn.
 166 ;;
 167 ;; Unfortunately, if combine doesn't create a MAC instruction, this
 168 ;; insn must generate reasonably correct code.  Egad.
 169
 170 (define_insn ""
 171   [(set (match_operand:SI 0 "register_operand" "=a")
 172         (mult:SI
 173           (sign_extend:SI
 174             (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
 175           (sign_extend:SI
 176             (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
 177   "TARGET_MAC"
 178   "clrmac\;mac  @%2+,@%1+"
 179   [(set_attr "length" "6")
 180    (set_attr "cc" "none_0hit")])
 181
 182 (define_insn ""
 183   [(set (match_operand:SI 0 "register_operand" "=a")
 184         (plus:SI (mult:SI
 185           (sign_extend:SI (mem:HI
 186             (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
 187           (sign_extend:SI (mem:HI
 188             (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
 189               (match_operand:SI 3 "register_operand" "0")))]
 190   "TARGET_MAC"
 191   "mac  @%2+,@%1+"
 192   [(set_attr "length" "4")
 193    (set_attr "cc" "none_0hit")])
 194