gcc/config/i386/constraints.md

   1 ;; Constraint definitions for IA-32 and x86-64.
   2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;;; Unused letters:
  21 ;;;           H
  22 ;;;           h j               z
  23
  24 ;; Integer register constraints.
  25 ;; It is not necessary to define 'r' here.
  26 (define_register_constraint "R" "LEGACY_REGS"
  27  "Legacy register---the eight integer registers available on all
  28   i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
  29   @code{si}, @code{di}, @code{bp}, @code{sp}).")
  30
  31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
  32  "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
  33   @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
  34
  35 (define_register_constraint "Q" "Q_REGS"
  36  "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
  37   @code{c}, and @code{d}.")
  38
  39 (define_register_constraint "l" "INDEX_REGS"
  40  "@internal Any register that can be used as the index in a base+index
  41   memory access: that is, any general register except the stack pointer.")
  42
  43 (define_register_constraint "a" "AREG"
  44  "The @code{a} register.")
  45
  46 (define_register_constraint "b" "BREG"
  47  "The @code{b} register.")
  48
  49 (define_register_constraint "c" "CREG"
  50  "The @code{c} register.")
  51
  52 (define_register_constraint "d" "DREG"
  53  "The @code{d} register.")
  54
  55 (define_register_constraint "S" "SIREG"
  56  "The @code{si} register.")
  57
  58 (define_register_constraint "D" "DIREG"
  59  "The @code{di} register.")
  60
  61 (define_register_constraint "A" "AD_REGS"
  62  "The @code{a} and @code{d} registers, as a pair (for instructions
  63   that return half the result in one and half in the other).")
  64
  65 (define_register_constraint "U" "CLOBBERED_REGS"
  66  "The call-clobbered integer registers.")
  67
  68 ;; Floating-point register constraints.
  69 (define_register_constraint "f"
  70  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
  71  "Any 80387 floating-point (stack) register.")
  72
  73 (define_register_constraint "t"
  74  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
  75  "Top of 80387 floating-point stack (@code{%st(0)}).")
  76
  77 (define_register_constraint "u"
  78  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
  79  "Second from top of 80387 floating-point stack (@code{%st(1)}).")
  80
  81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS"
  82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
  83
  84 (define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
  85 "@internal Any mask register.")
  86
  87 ;; Vector registers (also used for plain floating point nowadays).
  88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
  89  "Any MMX register.")
  90
  91 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
  92  "Any SSE register.")
  93
  94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
  95  "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
  96
  97 (define_register_constraint "w" "TARGET_MPX ? BND_REGS : NO_REGS"
  98  "@internal Any bound register.")
  99
 100 ;; We use the Y prefix to denote any number of conditional register sets:
 101 ;;  z   First SSE register.
 102 ;;  i   SSE2 inter-unit moves to SSE register enabled
 103 ;;  j   SSE2 inter-unit moves from SSE register enabled
 104 ;;  m   MMX inter-unit moves to MMX register enabled
 105 ;;  n   MMX inter-unit moves from MMX register enabled
 106 ;;  a   Integer register when zero extensions with AND are disabled
 107 ;;  p   Integer register when TARGET_PARTIAL_REG_STALL is disabled
 108 ;;  d   Integer register when integer DFmode moves are enabled
 109 ;;  x   Integer register when integer XFmode moves are enabled
 110 ;;  f   x87 register when 80387 floating point arithmetic is enabled
 111
 112 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
 113  "First SSE register (@code{%xmm0}).")
 114
 115 (define_register_constraint "Yi"
 116  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS"
 117  "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.")
 118
 119 (define_register_constraint "Yj"
 120  "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_FROM_VEC ? ALL_SSE_REGS : NO_REGS"
 121  "@internal Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled.")
 122
 123 (define_register_constraint "Ym"
 124  "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS"
 125  "@internal Any MMX register, when inter-unit moves to vector registers are enabled.")
 126
 127 (define_register_constraint "Yn"
 128  "TARGET_MMX && TARGET_INTER_UNIT_MOVES_FROM_VEC ? MMX_REGS : NO_REGS"
 129  "@internal Any MMX register, when inter-unit moves from vector registers are enabled.")
 130
 131 (define_register_constraint "Yp"
 132  "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
 133  "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
 134
 135 (define_register_constraint "Ya"
 136  "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
 137   ? NO_REGS : GENERAL_REGS"
 138  "@internal Any integer register when zero extensions with AND are disabled.")
 139
 140 (define_register_constraint "Yd"
 141  "TARGET_INTEGER_DFMODE_MOVES && optimize_function_for_speed_p (cfun)
 142   ? GENERAL_REGS : NO_REGS"
 143  "@internal Any integer register when integer DFmode moves are enabled.")
 144
 145 (define_register_constraint "Yx"
 146  "optimize_function_for_speed_p (cfun) ? GENERAL_REGS : NO_REGS"
 147  "@internal Any integer register when integer XFmode moves are enabled.")
 148
 149 (define_register_constraint "Yf"
 150  "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
 151  "@internal Any x87 register when 80387 FP arithmetic is enabled.")
 152
 153 ;; We use the B prefix to denote any number of internal operands:
 154 ;;  s  Sibcall memory operand, not valid for TARGET_X32
 155 ;;  w  Call memory operand, not valid for TARGET_X32
 156 ;;  z  Constant call address operand.
 157
 158 (define_constraint "Bs"
 159   "@internal Sibcall memory operand."
 160   (and (not (match_test "TARGET_X32"))
 161        (match_operand 0 "sibcall_memory_operand")))
 162
 163 (define_constraint "Bw"
 164   "@internal Call memory operand."
 165   (and (not (match_test "TARGET_X32"))
 166        (match_operand 0 "memory_operand")))
 167
 168 (define_constraint "Bz"
 169   "@internal Constant call address operand."
 170   (match_operand 0 "constant_call_address_operand"))
 171
 172 ;; Integer constant constraints.
 173 (define_constraint "I"
 174   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
 175   (and (match_code "const_int")
 176        (match_test "IN_RANGE (ival, 0, 31)")))
 177
 178 (define_constraint "J"
 179   "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
 180   (and (match_code "const_int")
 181        (match_test "IN_RANGE (ival, 0, 63)")))
 182
 183 (define_constraint "K"
 184   "Signed 8-bit integer constant."
 185   (and (match_code "const_int")
 186        (match_test "IN_RANGE (ival, -128, 127)")))
 187
 188 (define_constraint "L"
 189   "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
 190    for AND as a zero-extending move."
 191   (and (match_code "const_int")
 192        (match_test "ival == 0xff || ival == 0xffff
 193                     || ival == (HOST_WIDE_INT) 0xffffffff")))
 194
 195 (define_constraint "M"
 196   "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
 197   (and (match_code "const_int")
 198        (match_test "IN_RANGE (ival, 0, 3)")))
 199
 200 (define_constraint "N"
 201   "Unsigned 8-bit integer constant (for @code{in} and @code{out}
 202    instructions)."
 203   (and (match_code "const_int")
 204        (match_test "IN_RANGE (ival, 0, 255)")))
 205
 206 (define_constraint "O"
 207   "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
 208   (and (match_code "const_int")
 209        (match_test "IN_RANGE (ival, 0, 127)")))
 210
 211 ;; Floating-point constant constraints.
 212 ;; We allow constants even if TARGET_80387 isn't set, because the
 213 ;; stack register converter may need to load 0.0 into the function
 214 ;; value register (top of stack).
 215 (define_constraint "G"
 216   "Standard 80387 floating point constant."
 217   (and (match_code "const_double")
 218        (match_test "standard_80387_constant_p (op) > 0")))
 219
 220 ;; This can theoretically be any mode's CONST0_RTX.
 221 (define_constraint "C"
 222   "Standard SSE floating point constant."
 223   (match_test "standard_sse_constant_p (op)"))
 224
 225 ;; Constant-or-symbol-reference constraints.
 226
 227 (define_constraint "e"
 228   "32-bit signed integer constant, or a symbolic reference known
 229    to fit that range (for immediate operands in sign-extending x86-64
 230    instructions)."
 231   (match_operand 0 "x86_64_immediate_operand"))
 232
 233 ;; We use W prefix to denote any number of
 234 ;; constant-or-symbol-reference constraints
 235
 236 (define_constraint "We"
 237   "32-bit signed integer constant, or a symbolic reference known
 238    to fit that range (for sign-extending conversion operations that
 239    require non-VOIDmode immediate operands)."
 240   (and (match_operand 0 "x86_64_immediate_operand")
 241        (match_test "GET_MODE (op) != VOIDmode")))
 242
 243 (define_constraint "Wz"
 244   "32-bit unsigned integer constant, or a symbolic reference known
 245    to fit that range (for zero-extending conversion operations that
 246    require non-VOIDmode immediate operands)."
 247   (and (match_operand 0 "x86_64_zext_immediate_operand")
 248        (match_test "GET_MODE (op) != VOIDmode")))
 249
 250 (define_constraint "Z"
 251   "32-bit unsigned integer constant, or a symbolic reference known
 252    to fit that range (for immediate operands in zero-extending x86-64
 253    instructions)."
 254   (match_operand 0 "x86_64_zext_immediate_operand"))
 255
 256 ;; T prefix is used for different address constraints
 257 ;;   v - VSIB address
 258 ;;   s - address with no segment register
 259 ;;   i - address with no index and no rip
 260 ;;   b - address with no base and no rip
 261
 262 (define_address_constraint "Tv"
 263   "VSIB address operand"
 264   (match_operand 0 "vsib_address_operand"))
 265
 266 (define_address_constraint "Ts"
 267   "Address operand without segment register"
 268   (match_operand 0 "address_no_seg_operand"))
 269
 270 (define_address_constraint "Ti"
 271   "MPX address operand without index"
 272   (match_operand 0 "address_mpx_no_index_operand"))
 273
 274 (define_address_constraint "Tb"
 275   "MPX address operand without base"
 276   (match_operand 0 "address_mpx_no_base_operand"))