gcc/config/i386/cpuid.h

   1 /*
   2  * Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3  *
   4  * This file is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 3, or (at your option) any
   7  * later version.
   8  *
   9  * This file is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * Under Section 7 of GPL version 3, you are granted additional
  15  * permissions described in the GCC Runtime Library Exception, version
  16  * 3.1, as published by the Free Software Foundation.
  17  *
  18  * You should have received a copy of the GNU General Public License and
  19  * a copy of the GCC Runtime Library Exception along with this program;
  20  * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21  * <http://www.gnu.org/licenses/>.
  22  */
  23
  24 /* %ecx */
  25 #define bit_SSE3        (1 << 0)
  26 #define bit_PCLMUL      (1 << 1)
  27 #define bit_LZCNT       (1 << 5)
  28 #define bit_SSSE3       (1 << 9)
  29 #define bit_FMA         (1 << 12)
  30 #define bit_CMPXCHG16B  (1 << 13)
  31 #define bit_SSE4_1      (1 << 19)
  32 #define bit_SSE4_2      (1 << 20)
  33 #define bit_MOVBE       (1 << 22)
  34 #define bit_POPCNT      (1 << 23)
  35 #define bit_AES         (1 << 25)
  36 #define bit_XSAVE       (1 << 26)
  37 #define bit_OSXSAVE     (1 << 27)
  38 #define bit_AVX         (1 << 28)
  39 #define bit_F16C        (1 << 29)
  40 #define bit_RDRND       (1 << 30)
  41
  42 /* %edx */
  43 #define bit_CMPXCHG8B   (1 << 8)
  44 #define bit_CMOV        (1 << 15)
  45 #define bit_MMX         (1 << 23)
  46 #define bit_FXSAVE      (1 << 24)
  47 #define bit_SSE         (1 << 25)
  48 #define bit_SSE2        (1 << 26)
  49
  50 /* Extended Features */
  51 /* %ecx */
  52 #define bit_LAHF_LM     (1 << 0)
  53 #define bit_ABM         (1 << 5)
  54 #define bit_SSE4a       (1 << 6)
  55 #define bit_PRFCHW      (1 << 8)
  56 #define bit_XOP         (1 << 11)
  57 #define bit_LWP         (1 << 15)
  58 #define bit_FMA4        (1 << 16)
  59 #define bit_TBM         (1 << 21)
  60
  61 /* %edx */
  62 #define bit_MMXEXT      (1 << 22)
  63 #define bit_LM          (1 << 29)
  64 #define bit_3DNOWP      (1 << 30)
  65 #define bit_3DNOW       (1 << 31)
  66
  67 /* Extended Features (%eax == 7) */
  68 #define bit_FSGSBASE    (1 << 0)
  69 #define bit_BMI (1 << 3)
  70 #define bit_HLE (1 << 4)
  71 #define bit_AVX2        (1 << 5)
  72 #define bit_BMI2        (1 << 8)
  73 #define bit_RTM (1 << 11)
  74 #define bit_AVX512F     (1 << 16)
  75 #define bit_RDSEED      (1 << 18)
  76 #define bit_ADX (1 << 19)
  77 #define bit_AVX512PF    (1 << 26)
  78 #define bit_AVX512ER    (1 << 27)
  79 #define bit_AVX512CD    (1 << 28)
  80 #define bit_SHA         (1 << 29)
  81
  82 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
  83 #define bit_XSAVEOPT    (1 << 0)
  84
  85 /* Signatures for different CPU implementations as returned in uses
  86    of cpuid with level 0.  */
  87 #define signature_AMD_ebx       0x68747541
  88 #define signature_AMD_ecx       0x444d4163
  89 #define signature_AMD_edx       0x69746e65
  90
  91 #define signature_CENTAUR_ebx   0x746e6543
  92 #define signature_CENTAUR_ecx   0x736c7561
  93 #define signature_CENTAUR_edx   0x48727561
  94
  95 #define signature_CYRIX_ebx     0x69727943
  96 #define signature_CYRIX_ecx     0x64616574
  97 #define signature_CYRIX_edx     0x736e4978
  98
  99 #define signature_INTEL_ebx     0x756e6547
 100 #define signature_INTEL_ecx     0x6c65746e
 101 #define signature_INTEL_edx     0x49656e69
 102
 103 #define signature_TM1_ebx       0x6e617254
 104 #define signature_TM1_ecx       0x55504361
 105 #define signature_TM1_edx       0x74656d73
 106
 107 #define signature_TM2_ebx       0x756e6547
 108 #define signature_TM2_ecx       0x3638784d
 109 #define signature_TM2_edx       0x54656e69
 110
 111 #define signature_NSC_ebx       0x646f6547
 112 #define signature_NSC_ecx       0x43534e20
 113 #define signature_NSC_edx       0x79622065
 114
 115 #define signature_NEXGEN_ebx    0x4778654e
 116 #define signature_NEXGEN_ecx    0x6e657669
 117 #define signature_NEXGEN_edx    0x72446e65
 118
 119 #define signature_RISE_ebx      0x65736952
 120 #define signature_RISE_ecx      0x65736952
 121 #define signature_RISE_edx      0x65736952
 122
 123 #define signature_SIS_ebx       0x20536953
 124 #define signature_SIS_ecx       0x20536953
 125 #define signature_SIS_edx       0x20536953
 126
 127 #define signature_UMC_ebx       0x20434d55
 128 #define signature_UMC_ecx       0x20434d55
 129 #define signature_UMC_edx       0x20434d55
 130
 131 #define signature_VIA_ebx       0x20414956
 132 #define signature_VIA_ecx       0x20414956
 133 #define signature_VIA_edx       0x20414956
 134
 135 #define signature_VORTEX_ebx    0x74726f56
 136 #define signature_VORTEX_ecx    0x436f5320
 137 #define signature_VORTEX_edx    0x36387865
 138
 139 #if defined(__i386__) && defined(__PIC__)
 140 /* %ebx may be the PIC register.  */
 141 #if __GNUC__ >= 3
 142 #define __cpuid(level, a, b, c, d)                      \
 143   __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                  \
 144            "cpuid\n\t"                                  \
 145            "xchg{l}\t{%%}ebx, %k1\n\t"                  \
 146            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 147            : "0" (level))
 148
 149 #define __cpuid_count(level, count, a, b, c, d)         \
 150   __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"                  \
 151            "cpuid\n\t"                                  \
 152            "xchg{l}\t{%%}ebx, %k1\n\t"                  \
 153            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 154            : "0" (level), "2" (count))
 155 #else
 156 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 157    nor alternatives in i386 code.  */
 158 #define __cpuid(level, a, b, c, d)                      \
 159   __asm__ ("xchgl\t%%ebx, %k1\n\t"                      \
 160            "cpuid\n\t"                                  \
 161            "xchgl\t%%ebx, %k1\n\t"                      \
 162            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 163            : "0" (level))
 164
 165 #define __cpuid_count(level, count, a, b, c, d)         \
 166   __asm__ ("xchgl\t%%ebx, %k1\n\t"                      \
 167            "cpuid\n\t"                                  \
 168            "xchgl\t%%ebx, %k1\n\t"                      \
 169            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 170            : "0" (level), "2" (count))
 171 #endif
 172 #elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
 173 /* %rbx may be the PIC register.  */
 174 #define __cpuid(level, a, b, c, d)                      \
 175   __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                  \
 176            "cpuid\n\t"                                  \
 177            "xchg{q}\t{%%}rbx, %q1\n\t"                  \
 178            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 179            : "0" (level))
 180
 181 #define __cpuid_count(level, count, a, b, c, d)         \
 182   __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"                  \
 183            "cpuid\n\t"                                  \
 184            "xchg{q}\t{%%}rbx, %q1\n\t"                  \
 185            : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)    \
 186            : "0" (level), "2" (count))
 187 #else
 188 #define __cpuid(level, a, b, c, d)                      \
 189   __asm__ ("cpuid\n\t"                                  \
 190            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 191            : "0" (level))
 192
 193 #define __cpuid_count(level, count, a, b, c, d)         \
 194   __asm__ ("cpuid\n\t"                                  \
 195            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 196            : "0" (level), "2" (count))
 197 #endif
 198
 199 /* Return highest supported input value for cpuid instruction.  ext can
 200    be either 0x0 or 0x8000000 to return highest supported value for
 201    basic or extended cpuid information.  Function returns 0 if cpuid
 202    is not supported or whatever cpuid returns in eax register.  If sig
 203    pointer is non-null, then first four bytes of the signature
 204    (as found in ebx register) are returned in location pointed by sig.  */
 205
 206 static __inline unsigned int
 207 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 208 {
 209   unsigned int __eax, __ebx, __ecx, __edx;
 210
 211 #ifndef __x86_64__
 212   /* See if we can use cpuid.  On AMD64 we always can.  */
 213 #if __GNUC__ >= 3
 214   __asm__ ("pushf{l|d}\n\t"
 215            "pushf{l|d}\n\t"
 216            "pop{l}\t%0\n\t"
 217            "mov{l}\t{%0, %1|%1, %0}\n\t"
 218            "xor{l}\t{%2, %0|%0, %2}\n\t"
 219            "push{l}\t%0\n\t"
 220            "popf{l|d}\n\t"
 221            "pushf{l|d}\n\t"
 222            "pop{l}\t%0\n\t"
 223            "popf{l|d}\n\t"
 224            : "=&r" (__eax), "=&r" (__ebx)
 225            : "i" (0x00200000));
 226 #else
 227 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 228    nor alternatives in i386 code.  */
 229   __asm__ ("pushfl\n\t"
 230            "pushfl\n\t"
 231            "popl\t%0\n\t"
 232            "movl\t%0, %1\n\t"
 233            "xorl\t%2, %0\n\t"
 234            "pushl\t%0\n\t"
 235            "popfl\n\t"
 236            "pushfl\n\t"
 237            "popl\t%0\n\t"
 238            "popfl\n\t"
 239            : "=&r" (__eax), "=&r" (__ebx)
 240            : "i" (0x00200000));
 241 #endif
 242
 243   if (!((__eax ^ __ebx) & 0x00200000))
 244     return 0;
 245 #endif
 246
 247   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 248   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 249
 250   if (__sig)
 251     *__sig = __ebx;
 252
 253   return __eax;
 254 }
 255
 256 /* Return cpuid data for requested cpuid level, as found in returned
 257    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 258    supported and returns 1 for valid cpuid information or 0 for
 259    unsupported cpuid level.  All pointers are required to be non-null.  */
 260
 261 static __inline int
 262 __get_cpuid (unsigned int __level,
 263              unsigned int *__eax, unsigned int *__ebx,
 264              unsigned int *__ecx, unsigned int *__edx)
 265 {
 266   unsigned int __ext = __level & 0x80000000;
 267
 268   if (__get_cpuid_max (__ext, 0) < __level)
 269     return 0;
 270
 271   __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
 272   return 1;
 273 }