gcc/config/i386/cpuid.h

   1 /*
   2  * Copyright (C) 2007, 2008 Free Software Foundation, Inc.
   3  *
   4  * This file is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2, or (at your option) any
   7  * later version.
   8  *
   9  * In addition to the permissions in the GNU General Public License, the
  10  * Free Software Foundation gives you unlimited permission to link the
  11  * compiled version of this file with other programs, and to distribute
  12  * those programs without any restriction coming from the use of this
  13  * file.  (The General Public License restrictions do apply in other
  14  * respects; for example, they cover modification of the file, and
  15  * distribution when not linked into another program.)
  16  *
  17  * This file is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20  * General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; see the file COPYING.  If not, write to
  24  * the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  25  * Boston, MA 02110-1301, USA.
  26  *
  27  *    As a special exception, if you link this library with files
  28  *    compiled with GCC to produce an executable, this does not cause
  29  *    the resulting executable to be covered by the GNU General Public License.
  30  *    This exception does not however invalidate any other reasons why
  31  *    the executable file might be covered by the GNU General Public License.
  32  */
  33
  34 /* %ecx */
  35 #define bit_SSE3        (1 << 0)
  36 #define bit_PCLMUL      (1 << 1)
  37 #define bit_SSSE3       (1 << 9)
  38 #define bit_FMA         (1 << 12)
  39 #define bit_CMPXCHG16B  (1 << 13)
  40 #define bit_SSE4_1      (1 << 19)
  41 #define bit_SSE4_2      (1 << 20)
  42 #define bit_POPCNT      (1 << 23)
  43 #define bit_AES         (1 << 25)
  44 #define bit_XSAVE       (1 << 26)
  45 #define bit_OSXSAVE     (1 << 27)
  46 #define bit_AVX         (1 << 28)
  47
  48 /* %edx */
  49 #define bit_CMPXCHG8B   (1 << 8)
  50 #define bit_CMOV        (1 << 15)
  51 #define bit_MMX         (1 << 23)
  52 #define bit_FXSAVE      (1 << 24)
  53 #define bit_SSE         (1 << 25)
  54 #define bit_SSE2        (1 << 26)
  55
  56 /* Extended Features */
  57 /* %ecx */
  58 #define bit_LAHF_LM     (1 << 0)
  59 #define bit_SSE4a       (1 << 6)
  60 #define bit_SSE5        (1 << 11)
  61
  62 /* %edx */
  63 #define bit_LM          (1 << 29)
  64 #define bit_3DNOWP      (1 << 30)
  65 #define bit_3DNOW       (1 << 31)
  66
  67
  68 #if defined(__i386__) && defined(__PIC__)
  69 /* %ebx may be the PIC register.  */
  70 #if __GNUC__ >= 3
  71 #define __cpuid(level, a, b, c, d)                      \
  72   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  73            "cpuid\n\t"                                  \
  74            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  75            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  76            : "0" (level))
  77
  78 #define __cpuid_count(level, count, a, b, c, d)         \
  79   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  80            "cpuid\n\t"                                  \
  81            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  82            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  83            : "0" (level), "2" (count))
  84 #else
  85 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
  86    nor alternatives in i386 code.  */
  87 #define __cpuid(level, a, b, c, d)                      \
  88   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
  89            "cpuid\n\t"                                  \
  90            "xchgl\t%%ebx, %1\n\t"                       \
  91            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  92            : "0" (level))
  93
  94 #define __cpuid_count(level, count, a, b, c, d)         \
  95   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
  96            "cpuid\n\t"                                  \
  97            "xchgl\t%%ebx, %1\n\t"                       \
  98            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  99            : "0" (level), "2" (count))
 100 #endif
 101 #else
 102 #define __cpuid(level, a, b, c, d)                      \
 103   __asm__ ("cpuid\n\t"                                  \
 104            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 105            : "0" (level))
 106
 107 #define __cpuid_count(level, count, a, b, c, d)         \
 108   __asm__ ("cpuid\n\t"                                  \
 109            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 110            : "0" (level), "2" (count))
 111 #endif
 112
 113 /* Return highest supported input value for cpuid instruction.  ext can
 114    be either 0x0 or 0x8000000 to return highest supported value for
 115    basic or extended cpuid information.  Function returns 0 if cpuid
 116    is not supported or whatever cpuid returns in eax register.  If sig
 117    pointer is non-null, then first four bytes of the signature
 118    (as found in ebx register) are returned in location pointed by sig.  */
 119
 120 static __inline unsigned int
 121 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 122 {
 123   unsigned int __eax, __ebx, __ecx, __edx;
 124
 125 #ifndef __x86_64__
 126 #if __GNUC__ >= 3
 127   /* See if we can use cpuid.  On AMD64 we always can.  */
 128   __asm__ ("pushf{l|d}\n\t"
 129            "pushf{l|d}\n\t"
 130            "pop{l}\t%0\n\t"
 131            "mov{l}\t{%0, %1|%1, %0}\n\t"
 132            "xor{l}\t{%2, %0|%0, %2}\n\t"
 133            "push{l}\t%0\n\t"
 134            "popf{l|d}\n\t"
 135            "pushf{l|d}\n\t"
 136            "pop{l}\t%0\n\t"
 137            "popf{l|d}\n\t"
 138            : "=&r" (__eax), "=&r" (__ebx)
 139            : "i" (0x00200000));
 140 #else
 141 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 142    nor alternatives in i386 code.  */
 143   __asm__ ("pushfl\n\t"
 144            "pushfl\n\t"
 145            "popl\t%0\n\t"
 146            "movl\t%0, %1\n\t"
 147            "xorl\t%2, %0\n\t"
 148            "pushl\t%0\n\t"
 149            "popfl\n\t"
 150            "pushfl\n\t"
 151            "popl\t%0\n\t"
 152            "popfl\n\t"
 153            : "=&r" (__eax), "=&r" (__ebx)
 154            : "i" (0x00200000));
 155 #endif
 156
 157   if (!((__eax ^ __ebx) & 0x00200000))
 158     return 0;
 159 #endif
 160
 161   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 162   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 163
 164   if (__sig)
 165     *__sig = __ebx;
 166
 167   return __eax;
 168 }
 169
 170 /* Return cpuid data for requested cpuid level, as found in returned
 171    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 172    supported and returns 1 for valid cpuid information or 0 for
 173    unsupported cpuid level.  All pointers are required to be non-null.  */
 174
 175 static __inline int
 176 __get_cpuid (unsigned int __level,
 177              unsigned int *__eax, unsigned int *__ebx,
 178              unsigned int *__ecx, unsigned int *__edx)
 179 {
 180   unsigned int __ext = __level & 0x80000000;
 181
 182   if (__get_cpuid_max (__ext, 0) < __level)
 183     return 0;
 184
 185   __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
 186   return 1;
 187 }