gcc/config/i386/cpuid.h

   1 /*
   2  * Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3  *
   4  * This file is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 3, or (at your option) any
   7  * later version.
   8  *
   9  * This file is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * Under Section 7 of GPL version 3, you are granted additional
  15  * permissions described in the GCC Runtime Library Exception, version
  16  * 3.1, as published by the Free Software Foundation.
  17  *
  18  * You should have received a copy of the GNU General Public License and
  19  * a copy of the GCC Runtime Library Exception along with this program;
  20  * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21  * <http://www.gnu.org/licenses/>.
  22  */
  23
  24 /* %ecx */
  25 #define bit_SSE3        (1 << 0)
  26 #define bit_PCLMUL      (1 << 1)
  27 #define bit_LZCNT       (1 << 5)
  28 #define bit_SSSE3       (1 << 9)
  29 #define bit_FMA         (1 << 12)
  30 #define bit_CMPXCHG16B  (1 << 13)
  31 #define bit_SSE4_1      (1 << 19)
  32 #define bit_SSE4_2      (1 << 20)
  33 #define bit_MOVBE       (1 << 22)
  34 #define bit_POPCNT      (1 << 23)
  35 #define bit_AES         (1 << 25)
  36 #define bit_XSAVE       (1 << 26)
  37 #define bit_OSXSAVE     (1 << 27)
  38 #define bit_AVX         (1 << 28)
  39 #define bit_F16C        (1 << 29)
  40 #define bit_RDRND       (1 << 30)
  41
  42 /* %edx */
  43 #define bit_CMPXCHG8B   (1 << 8)
  44 #define bit_CMOV        (1 << 15)
  45 #define bit_MMX         (1 << 23)
  46 #define bit_FXSAVE      (1 << 24)
  47 #define bit_SSE         (1 << 25)
  48 #define bit_SSE2        (1 << 26)
  49
  50 /* Extended Features */
  51 /* %ecx */
  52 #define bit_LAHF_LM     (1 << 0)
  53 #define bit_ABM         (1 << 5)
  54 #define bit_SSE4a       (1 << 6)
  55 #define bit_PRFCHW      (1 << 8)
  56 #define bit_XOP         (1 << 11)
  57 #define bit_LWP         (1 << 15)
  58 #define bit_FMA4        (1 << 16)
  59 #define bit_TBM         (1 << 21)
  60 #define bit_MWAITX      (1 << 29)
  61
  62 /* %edx */
  63 #define bit_AVX5124VNNIW (1 << 2)
  64 #define bit_AVX5124FMAPS (1 << 3)
  65 #define bit_MMXEXT      (1 << 22)
  66 #define bit_LM          (1 << 29)
  67 #define bit_3DNOWP      (1 << 30)
  68 #define bit_3DNOW       (1 << 31)
  69
  70 /* %ebx.  */
  71 #define bit_CLZERO      (1 << 0)
  72
  73 /* Extended Features (%eax == 7) */
  74 /* %ebx */
  75 #define bit_FSGSBASE    (1 << 0)
  76 #define bit_BMI (1 << 3)
  77 #define bit_HLE (1 << 4)
  78 #define bit_AVX2        (1 << 5)
  79 #define bit_BMI2        (1 << 8)
  80 #define bit_RTM (1 << 11)
  81 #define bit_MPX (1 << 14)
  82 #define bit_AVX512F     (1 << 16)
  83 #define bit_AVX512DQ    (1 << 17)
  84 #define bit_RDSEED      (1 << 18)
  85 #define bit_ADX (1 << 19)
  86 #define bit_AVX512IFMA  (1 << 21)
  87 #define bit_CLFLUSHOPT  (1 << 23)
  88 #define bit_CLWB        (1 << 24)
  89 #define bit_AVX512PF    (1 << 26)
  90 #define bit_AVX512ER    (1 << 27)
  91 #define bit_AVX512CD    (1 << 28)
  92 #define bit_SHA         (1 << 29)
  93 #define bit_AVX512BW    (1 << 30)
  94 #define bit_AVX512VL    (1 << 31)
  95
  96 /* %ecx */
  97 #define bit_PREFETCHWT1   (1 << 0)
  98 #define bit_AVX512VBMI  (1 << 1)
  99 #define bit_PKU (1 << 3)
 100 #define bit_OSPKE       (1 << 4)
 101
 102 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
 103 #define bit_BNDREGS     (1 << 3)
 104 #define bit_BNDCSR      (1 << 4)
 105
 106 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
 107 #define bit_XSAVEOPT    (1 << 0)
 108 #define bit_XSAVEC      (1 << 1)
 109 #define bit_XSAVES      (1 << 3)
 110
 111 /* Signatures for different CPU implementations as returned in uses
 112    of cpuid with level 0.  */
 113 #define signature_AMD_ebx       0x68747541
 114 #define signature_AMD_ecx       0x444d4163
 115 #define signature_AMD_edx       0x69746e65
 116
 117 #define signature_CENTAUR_ebx   0x746e6543
 118 #define signature_CENTAUR_ecx   0x736c7561
 119 #define signature_CENTAUR_edx   0x48727561
 120
 121 #define signature_CYRIX_ebx     0x69727943
 122 #define signature_CYRIX_ecx     0x64616574
 123 #define signature_CYRIX_edx     0x736e4978
 124
 125 #define signature_INTEL_ebx     0x756e6547
 126 #define signature_INTEL_ecx     0x6c65746e
 127 #define signature_INTEL_edx     0x49656e69
 128
 129 #define signature_TM1_ebx       0x6e617254
 130 #define signature_TM1_ecx       0x55504361
 131 #define signature_TM1_edx       0x74656d73
 132
 133 #define signature_TM2_ebx       0x756e6547
 134 #define signature_TM2_ecx       0x3638784d
 135 #define signature_TM2_edx       0x54656e69
 136
 137 #define signature_NSC_ebx       0x646f6547
 138 #define signature_NSC_ecx       0x43534e20
 139 #define signature_NSC_edx       0x79622065
 140
 141 #define signature_NEXGEN_ebx    0x4778654e
 142 #define signature_NEXGEN_ecx    0x6e657669
 143 #define signature_NEXGEN_edx    0x72446e65
 144
 145 #define signature_RISE_ebx      0x65736952
 146 #define signature_RISE_ecx      0x65736952
 147 #define signature_RISE_edx      0x65736952
 148
 149 #define signature_SIS_ebx       0x20536953
 150 #define signature_SIS_ecx       0x20536953
 151 #define signature_SIS_edx       0x20536953
 152
 153 #define signature_UMC_ebx       0x20434d55
 154 #define signature_UMC_ecx       0x20434d55
 155 #define signature_UMC_edx       0x20434d55
 156
 157 #define signature_VIA_ebx       0x20414956
 158 #define signature_VIA_ecx       0x20414956
 159 #define signature_VIA_edx       0x20414956
 160
 161 #define signature_VORTEX_ebx    0x74726f56
 162 #define signature_VORTEX_ecx    0x436f5320
 163 #define signature_VORTEX_edx    0x36387865
 164
 165 #define __cpuid(level, a, b, c, d)                      \
 166   __asm__ ("cpuid\n\t"                                  \
 167            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 168            : "0" (level))
 169
 170 #define __cpuid_count(level, count, a, b, c, d)         \
 171   __asm__ ("cpuid\n\t"                                  \
 172            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 173            : "0" (level), "2" (count))
 174
 175
 176 /* Return highest supported input value for cpuid instruction.  ext can
 177    be either 0x0 or 0x8000000 to return highest supported value for
 178    basic or extended cpuid information.  Function returns 0 if cpuid
 179    is not supported or whatever cpuid returns in eax register.  If sig
 180    pointer is non-null, then first four bytes of the signature
 181    (as found in ebx register) are returned in location pointed by sig.  */
 182
 183 static __inline unsigned int
 184 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 185 {
 186   unsigned int __eax, __ebx, __ecx, __edx;
 187
 188 #ifndef __x86_64__
 189   /* See if we can use cpuid.  On AMD64 we always can.  */
 190 #if __GNUC__ >= 3
 191   __asm__ ("pushf{l|d}\n\t"
 192            "pushf{l|d}\n\t"
 193            "pop{l}\t%0\n\t"
 194            "mov{l}\t{%0, %1|%1, %0}\n\t"
 195            "xor{l}\t{%2, %0|%0, %2}\n\t"
 196            "push{l}\t%0\n\t"
 197            "popf{l|d}\n\t"
 198            "pushf{l|d}\n\t"
 199            "pop{l}\t%0\n\t"
 200            "popf{l|d}\n\t"
 201            : "=&r" (__eax), "=&r" (__ebx)
 202            : "i" (0x00200000));
 203 #else
 204 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 205    nor alternatives in i386 code.  */
 206   __asm__ ("pushfl\n\t"
 207            "pushfl\n\t"
 208            "popl\t%0\n\t"
 209            "movl\t%0, %1\n\t"
 210            "xorl\t%2, %0\n\t"
 211            "pushl\t%0\n\t"
 212            "popfl\n\t"
 213            "pushfl\n\t"
 214            "popl\t%0\n\t"
 215            "popfl\n\t"
 216            : "=&r" (__eax), "=&r" (__ebx)
 217            : "i" (0x00200000));
 218 #endif
 219
 220   if (!((__eax ^ __ebx) & 0x00200000))
 221     return 0;
 222 #endif
 223
 224   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 225   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 226
 227   if (__sig)
 228     *__sig = __ebx;
 229
 230   return __eax;
 231 }
 232
 233 /* Return cpuid data for requested cpuid leaf, as found in returned
 234    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 235    supported and returns 1 for valid cpuid information or 0 for
 236    unsupported cpuid leaf.  All pointers are required to be non-null.  */
 237
 238 static __inline int
 239 __get_cpuid (unsigned int __leaf,
 240              unsigned int *__eax, unsigned int *__ebx,
 241              unsigned int *__ecx, unsigned int *__edx)
 242 {
 243   unsigned int __ext = __leaf & 0x80000000;
 244
 245   if (__get_cpuid_max (__ext, 0) < __leaf)
 246     return 0;
 247
 248   __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
 249   return 1;
 250 }
 251
 252 /* Same as above, but sub-leaf can be specified.  */
 253
 254 static __inline int
 255 __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
 256                    unsigned int *__eax, unsigned int *__ebx,
 257                    unsigned int *__ecx, unsigned int *__edx)
 258 {
 259   unsigned int __ext = __leaf & 0x80000000;
 260
 261   if (__get_cpuid_max (__ext, 0) < __leaf)
 262     return 0;
 263
 264   __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
 265   return 1;
 266 }