gcc/config/i386/cpuid.h

   1 /*
   2  * Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc.
   3  *
   4  * This file is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 3, or (at your option) any
   7  * later version.
   8  *
   9  * This file is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * Under Section 7 of GPL version 3, you are granted additional
  15  * permissions described in the GCC Runtime Library Exception, version
  16  * 3.1, as published by the Free Software Foundation.
  17  *
  18  * You should have received a copy of the GNU General Public License and
  19  * a copy of the GCC Runtime Library Exception along with this program;
  20  * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21  * <http://www.gnu.org/licenses/>.
  22  */
  23
  24 /* %ecx */
  25 #define bit_SSE3        (1 << 0)
  26 #define bit_PCLMUL      (1 << 1)
  27 #define bit_SSSE3       (1 << 9)
  28 #define bit_FMA         (1 << 12)
  29 #define bit_CMPXCHG16B  (1 << 13)
  30 #define bit_SSE4_1      (1 << 19)
  31 #define bit_SSE4_2      (1 << 20)
  32 #define bit_MOVBE       (1 << 22)
  33 #define bit_POPCNT      (1 << 23)
  34 #define bit_AES         (1 << 25)
  35 #define bit_XSAVE       (1 << 26)
  36 #define bit_OSXSAVE     (1 << 27)
  37 #define bit_AVX         (1 << 28)
  38
  39 /* %edx */
  40 #define bit_CMPXCHG8B   (1 << 8)
  41 #define bit_CMOV        (1 << 15)
  42 #define bit_MMX         (1 << 23)
  43 #define bit_FXSAVE      (1 << 24)
  44 #define bit_SSE         (1 << 25)
  45 #define bit_SSE2        (1 << 26)
  46
  47 /* Extended Features */
  48 /* %ecx */
  49 #define bit_LAHF_LM     (1 << 0)
  50 #define bit_SSE4a       (1 << 6)
  51 #define bit_FMA4        (1 << 16)
  52
  53 /* %edx */
  54 #define bit_LM          (1 << 29)
  55 #define bit_3DNOWP      (1 << 30)
  56 #define bit_3DNOW       (1 << 31)
  57
  58
  59 #if defined(__i386__) && defined(__PIC__)
  60 /* %ebx may be the PIC register.  */
  61 #if __GNUC__ >= 3
  62 #define __cpuid(level, a, b, c, d)                      \
  63   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  64            "cpuid\n\t"                                  \
  65            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  66            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  67            : "0" (level))
  68
  69 #define __cpuid_count(level, count, a, b, c, d)         \
  70   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  71            "cpuid\n\t"                                  \
  72            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  73            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  74            : "0" (level), "2" (count))
  75 #else
  76 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
  77    nor alternatives in i386 code.  */
  78 #define __cpuid(level, a, b, c, d)                      \
  79   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
  80            "cpuid\n\t"                                  \
  81            "xchgl\t%%ebx, %1\n\t"                       \
  82            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  83            : "0" (level))
  84
  85 #define __cpuid_count(level, count, a, b, c, d)         \
  86   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
  87            "cpuid\n\t"                                  \
  88            "xchgl\t%%ebx, %1\n\t"                       \
  89            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  90            : "0" (level), "2" (count))
  91 #endif
  92 #else
  93 #define __cpuid(level, a, b, c, d)                      \
  94   __asm__ ("cpuid\n\t"                                  \
  95            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
  96            : "0" (level))
  97
  98 #define __cpuid_count(level, count, a, b, c, d)         \
  99   __asm__ ("cpuid\n\t"                                  \
 100            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 101            : "0" (level), "2" (count))
 102 #endif
 103
 104 /* Return highest supported input value for cpuid instruction.  ext can
 105    be either 0x0 or 0x8000000 to return highest supported value for
 106    basic or extended cpuid information.  Function returns 0 if cpuid
 107    is not supported or whatever cpuid returns in eax register.  If sig
 108    pointer is non-null, then first four bytes of the signature
 109    (as found in ebx register) are returned in location pointed by sig.  */
 110
 111 static __inline unsigned int
 112 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 113 {
 114   unsigned int __eax, __ebx, __ecx, __edx;
 115
 116 #ifndef __x86_64__
 117 #if __GNUC__ >= 3
 118   /* See if we can use cpuid.  On AMD64 we always can.  */
 119   __asm__ ("pushf{l|d}\n\t"
 120            "pushf{l|d}\n\t"
 121            "pop{l}\t%0\n\t"
 122            "mov{l}\t{%0, %1|%1, %0}\n\t"
 123            "xor{l}\t{%2, %0|%0, %2}\n\t"
 124            "push{l}\t%0\n\t"
 125            "popf{l|d}\n\t"
 126            "pushf{l|d}\n\t"
 127            "pop{l}\t%0\n\t"
 128            "popf{l|d}\n\t"
 129            : "=&r" (__eax), "=&r" (__ebx)
 130            : "i" (0x00200000));
 131 #else
 132 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 133    nor alternatives in i386 code.  */
 134   __asm__ ("pushfl\n\t"
 135            "pushfl\n\t"
 136            "popl\t%0\n\t"
 137            "movl\t%0, %1\n\t"
 138            "xorl\t%2, %0\n\t"
 139            "pushl\t%0\n\t"
 140            "popfl\n\t"
 141            "pushfl\n\t"
 142            "popl\t%0\n\t"
 143            "popfl\n\t"
 144            : "=&r" (__eax), "=&r" (__ebx)
 145            : "i" (0x00200000));
 146 #endif
 147
 148   if (!((__eax ^ __ebx) & 0x00200000))
 149     return 0;
 150 #endif
 151
 152   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 153   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 154
 155   if (__sig)
 156     *__sig = __ebx;
 157
 158   return __eax;
 159 }
 160
 161 /* Return cpuid data for requested cpuid level, as found in returned
 162    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 163    supported and returns 1 for valid cpuid information or 0 for
 164    unsupported cpuid level.  All pointers are required to be non-null.  */
 165
 166 static __inline int
 167 __get_cpuid (unsigned int __level,
 168              unsigned int *__eax, unsigned int *__ebx,
 169              unsigned int *__ecx, unsigned int *__edx)
 170 {
 171   unsigned int __ext = __level & 0x80000000;
 172
 173   if (__get_cpuid_max (__ext, 0) < __level)
 174     return 0;
 175
 176   __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
 177   return 1;
 178 }