gcc/config/i386/cpuid.h

   1 /*
   2  * Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
   3  *
   4  * This file is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 3, or (at your option) any
   7  * later version.
   8  *
   9  * This file is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * Under Section 7 of GPL version 3, you are granted additional
  15  * permissions described in the GCC Runtime Library Exception, version
  16  * 3.1, as published by the Free Software Foundation.
  17  *
  18  * You should have received a copy of the GNU General Public License and
  19  * a copy of the GCC Runtime Library Exception along with this program;
  20  * see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21  * <http://www.gnu.org/licenses/>.
  22  */
  23
  24 /* %ecx */
  25 #define bit_SSE3        (1 << 0)
  26 #define bit_PCLMUL      (1 << 1)
  27 #define bit_LZCNT       (1 << 5)
  28 #define bit_SSSE3       (1 << 9)
  29 #define bit_FMA         (1 << 12)
  30 #define bit_CMPXCHG16B  (1 << 13)
  31 #define bit_SSE4_1      (1 << 19)
  32 #define bit_SSE4_2      (1 << 20)
  33 #define bit_MOVBE       (1 << 22)
  34 #define bit_POPCNT      (1 << 23)
  35 #define bit_AES         (1 << 25)
  36 #define bit_XSAVE       (1 << 26)
  37 #define bit_OSXSAVE     (1 << 27)
  38 #define bit_AVX         (1 << 28)
  39 #define bit_F16C        (1 << 29)
  40 #define bit_RDRND       (1 << 30)
  41
  42 /* %edx */
  43 #define bit_CMPXCHG8B   (1 << 8)
  44 #define bit_CMOV        (1 << 15)
  45 #define bit_MMX         (1 << 23)
  46 #define bit_FXSAVE      (1 << 24)
  47 #define bit_SSE         (1 << 25)
  48 #define bit_SSE2        (1 << 26)
  49
  50 /* Extended Features */
  51 /* %ecx */
  52 #define bit_LAHF_LM     (1 << 0)
  53 #define bit_ABM         (1 << 5)
  54 #define bit_SSE4a       (1 << 6)
  55 #define bit_XOP         (1 << 11)
  56 #define bit_LWP         (1 << 15)
  57 #define bit_FMA4        (1 << 16)
  58 #define bit_TBM         (1 << 21)
  59
  60 /* %edx */
  61 #define bit_MMXEXT      (1 << 22)
  62 #define bit_LM          (1 << 29)
  63 #define bit_3DNOWP      (1 << 30)
  64 #define bit_3DNOW       (1 << 31)
  65
  66 /* Extended Features (%eax == 7) */
  67 #define bit_FSGSBASE    (1 << 0)
  68 #define bit_BMI (1 << 3)
  69 #define bit_HLE (1 << 4)
  70 #define bit_AVX2        (1 << 5)
  71 #define bit_BMI2        (1 << 8)
  72 #define bit_PRFCHW      (1 << 8)
  73 #define bit_RTM (1 << 11)
  74 #define bit_RDSEED      (1 << 18)
  75 #define bit_ADX (1 << 19)
  76
  77 #if defined(__i386__) && defined(__PIC__)
  78 /* %ebx may be the PIC register.  */
  79 #if __GNUC__ >= 3
  80 #define __cpuid(level, a, b, c, d)                      \
  81   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  82            "cpuid\n\t"                                  \
  83            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  84            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  85            : "0" (level))
  86
  87 #define __cpuid_count(level, count, a, b, c, d)         \
  88   __asm__ ("xchg{l}\t{%%}ebx, %1\n\t"                   \
  89            "cpuid\n\t"                                  \
  90            "xchg{l}\t{%%}ebx, %1\n\t"                   \
  91            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
  92            : "0" (level), "2" (count))
  93 #else
  94 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
  95    nor alternatives in i386 code.  */
  96 #define __cpuid(level, a, b, c, d)                      \
  97   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
  98            "cpuid\n\t"                                  \
  99            "xchgl\t%%ebx, %1\n\t"                       \
 100            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
 101            : "0" (level))
 102
 103 #define __cpuid_count(level, count, a, b, c, d)         \
 104   __asm__ ("xchgl\t%%ebx, %1\n\t"                       \
 105            "cpuid\n\t"                                  \
 106            "xchgl\t%%ebx, %1\n\t"                       \
 107            : "=a" (a), "=r" (b), "=c" (c), "=d" (d)     \
 108            : "0" (level), "2" (count))
 109 #endif
 110 #else
 111 #define __cpuid(level, a, b, c, d)                      \
 112   __asm__ ("cpuid\n\t"                                  \
 113            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 114            : "0" (level))
 115
 116 #define __cpuid_count(level, count, a, b, c, d)         \
 117   __asm__ ("cpuid\n\t"                                  \
 118            : "=a" (a), "=b" (b), "=c" (c), "=d" (d)     \
 119            : "0" (level), "2" (count))
 120 #endif
 121
 122 /* Return highest supported input value for cpuid instruction.  ext can
 123    be either 0x0 or 0x8000000 to return highest supported value for
 124    basic or extended cpuid information.  Function returns 0 if cpuid
 125    is not supported or whatever cpuid returns in eax register.  If sig
 126    pointer is non-null, then first four bytes of the signature
 127    (as found in ebx register) are returned in location pointed by sig.  */
 128
 129 static __inline unsigned int
 130 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
 131 {
 132   unsigned int __eax, __ebx, __ecx, __edx;
 133
 134 #ifndef __x86_64__
 135   /* See if we can use cpuid.  On AMD64 we always can.  */
 136 #if __GNUC__ >= 3
 137   __asm__ ("pushf{l|d}\n\t"
 138            "pushf{l|d}\n\t"
 139            "pop{l}\t%0\n\t"
 140            "mov{l}\t{%0, %1|%1, %0}\n\t"
 141            "xor{l}\t{%2, %0|%0, %2}\n\t"
 142            "push{l}\t%0\n\t"
 143            "popf{l|d}\n\t"
 144            "pushf{l|d}\n\t"
 145            "pop{l}\t%0\n\t"
 146            "popf{l|d}\n\t"
 147            : "=&r" (__eax), "=&r" (__ebx)
 148            : "i" (0x00200000));
 149 #else
 150 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
 151    nor alternatives in i386 code.  */
 152   __asm__ ("pushfl\n\t"
 153            "pushfl\n\t"
 154            "popl\t%0\n\t"
 155            "movl\t%0, %1\n\t"
 156            "xorl\t%2, %0\n\t"
 157            "pushl\t%0\n\t"
 158            "popfl\n\t"
 159            "pushfl\n\t"
 160            "popl\t%0\n\t"
 161            "popfl\n\t"
 162            : "=&r" (__eax), "=&r" (__ebx)
 163            : "i" (0x00200000));
 164 #endif
 165
 166   if (!((__eax ^ __ebx) & 0x00200000))
 167     return 0;
 168 #endif
 169
 170   /* Host supports cpuid.  Return highest supported cpuid input value.  */
 171   __cpuid (__ext, __eax, __ebx, __ecx, __edx);
 172
 173   if (__sig)
 174     *__sig = __ebx;
 175
 176   return __eax;
 177 }
 178
 179 /* Return cpuid data for requested cpuid level, as found in returned
 180    eax, ebx, ecx and edx registers.  The function checks if cpuid is
 181    supported and returns 1 for valid cpuid information or 0 for
 182    unsupported cpuid level.  All pointers are required to be non-null.  */
 183
 184 static __inline int
 185 __get_cpuid (unsigned int __level,
 186              unsigned int *__eax, unsigned int *__ebx,
 187              unsigned int *__ecx, unsigned int *__edx)
 188 {
 189   unsigned int __ext = __level & 0x80000000;
 190
 191   if (__get_cpuid_max (__ext, 0) < __level)
 192     return 0;
 193
 194   __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
 195   return 1;
 196 }