1 /* Subroutines for the gcc driver.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
25 const char *host_detect_local_cpu (int argc
, const char **argv
);
37 /* Returns command line parameters that describe size and
38 cache line size of the processor caches. */
41 describe_cache (struct cache_desc level1
, struct cache_desc level2
)
43 char size
[100], line
[100], size2
[100];
45 /* At the moment, gcc does not use the information
46 about the associativity of the cache. */
48 snprintf (size
, sizeof (size
),
49 "--param l1-cache-size=%u ", level1
.sizekb
);
50 snprintf (line
, sizeof (line
),
51 "--param l1-cache-line-size=%u ", level1
.line
);
53 snprintf (size2
, sizeof (size2
),
54 "--param l2-cache-size=%u ", level2
.sizekb
);
56 return concat (size
, line
, size2
, NULL
);
59 /* Detect L2 cache parameters using CPUID extended function 0x80000006. */
62 detect_l2_cache (struct cache_desc
*level2
)
64 unsigned eax
, ebx
, ecx
, edx
;
67 __cpuid (0x80000006, eax
, ebx
, ecx
, edx
);
69 level2
->sizekb
= (ecx
>> 16) & 0xffff;
70 level2
->line
= ecx
& 0xff;
72 assoc
= (ecx
>> 12) & 0xf;
77 else if (assoc
>= 0xa && assoc
<= 0xc)
78 assoc
= 32 + (assoc
- 0xa) * 16;
79 else if (assoc
>= 0xd && assoc
<= 0xe)
80 assoc
= 96 + (assoc
- 0xd) * 32;
82 level2
->assoc
= assoc
;
85 /* Returns the description of caches for an AMD processor. */
88 detect_caches_amd (unsigned max_ext_level
)
90 unsigned eax
, ebx
, ecx
, edx
;
92 struct cache_desc level1
, level2
= {0, 0, 0};
94 if (max_ext_level
< 0x80000005)
97 __cpuid (0x80000005, eax
, ebx
, ecx
, edx
);
99 level1
.sizekb
= (ecx
>> 24) & 0xff;
100 level1
.assoc
= (ecx
>> 16) & 0xff;
101 level1
.line
= ecx
& 0xff;
103 if (max_ext_level
>= 0x80000006)
104 detect_l2_cache (&level2
);
106 return describe_cache (level1
, level2
);
109 /* Decodes the size, the associativity and the cache line size of
110 L1/L2 caches of an Intel processor. Values are based on
111 "Intel Processor Identification and the CPUID Instruction"
112 [Application Note 485], revision -032, December 2007. */
115 decode_caches_intel (unsigned reg
, bool xeon_mp
,
116 struct cache_desc
*level1
, struct cache_desc
*level2
)
120 for (i
= 24; i
>= 0; i
-= 8)
121 switch ((reg
>> i
) & 0xff)
124 level1
->sizekb
= 8; level1
->assoc
= 2; level1
->line
= 32;
127 level1
->sizekb
= 16; level1
->assoc
= 4; level1
->line
= 32;
130 level1
->sizekb
= 16; level1
->assoc
= 4; level1
->line
= 64;
133 level1
->sizekb
= 24; level1
->assoc
= 6; level1
->line
= 64;
136 level2
->sizekb
= 256; level2
->assoc
= 8; level2
->line
= 64;
139 level2
->sizekb
= 1024; level2
->assoc
= 16; level2
->line
= 64;
142 level1
->sizekb
= 32; level1
->assoc
= 8; level1
->line
= 64;
145 level2
->sizekb
= 128; level2
->assoc
= 4; level2
->line
= 64;
148 level2
->sizekb
= 192; level2
->assoc
= 6; level2
->line
= 64;
151 level2
->sizekb
= 128; level2
->assoc
= 2; level2
->line
= 64;
154 level2
->sizekb
= 256; level2
->assoc
= 4; level2
->line
= 64;
157 level2
->sizekb
= 384; level2
->assoc
= 6; level2
->line
= 64;
160 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 64;
163 level2
->sizekb
= 128; level2
->assoc
= 4; level2
->line
= 32;
166 level2
->sizekb
= 256; level2
->assoc
= 4; level2
->line
= 32;
169 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 32;
172 level2
->sizekb
= 1024; level2
->assoc
= 4; level2
->line
= 32;
175 level2
->sizekb
= 2048; level2
->assoc
= 4; level2
->line
= 32;
178 level2
->sizekb
= 3072; level2
->assoc
= 12; level2
->line
= 64;
183 level2
->sizekb
= 4096; level2
->assoc
= 16; level2
->line
= 64;
186 level2
->sizekb
= 6144; level2
->assoc
= 24; level2
->line
= 64;
189 level1
->sizekb
= 16; level1
->assoc
= 8; level1
->line
= 64;
192 level1
->sizekb
= 8; level1
->assoc
= 4; level1
->line
= 64;
195 level1
->sizekb
= 16; level1
->assoc
= 4; level1
->line
= 64;
198 level1
->sizekb
= 32; level1
->assoc
= 4; level1
->line
= 64;
201 level2
->sizekb
= 1024; level2
->assoc
= 4; level2
->line
= 64;
204 level2
->sizekb
= 128; level2
->assoc
= 8; level2
->line
= 64;
207 level2
->sizekb
= 256; level2
->assoc
= 8; level2
->line
= 64;
210 level2
->sizekb
= 512; level2
->assoc
= 8; level2
->line
= 64;
213 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 64;
216 level2
->sizekb
= 2048; level2
->assoc
= 8; level2
->line
= 64;
219 level2
->sizekb
= 512; level2
->assoc
= 2; level2
->line
= 64;
222 level2
->sizekb
= 512; level2
->assoc
= 8; level2
->line
= 64;
225 level2
->sizekb
= 256; level2
->assoc
= 8; level2
->line
= 32;
228 level2
->sizekb
= 512; level2
->assoc
= 8; level2
->line
= 32;
231 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 32;
234 level2
->sizekb
= 2048; level2
->assoc
= 8; level2
->line
= 32;
237 level2
->sizekb
= 512; level2
->assoc
= 4; level2
->line
= 64;
240 level2
->sizekb
= 1024; level2
->assoc
= 8; level2
->line
= 64;
247 /* Detect cache parameters using CPUID function 2. */
250 detect_caches_cpuid2 (bool xeon_mp
,
251 struct cache_desc
*level1
, struct cache_desc
*level2
)
256 __cpuid (2, regs
[0], regs
[1], regs
[2], regs
[3]);
258 nreps
= regs
[0] & 0x0f;
263 for (i
= 0; i
< 4; i
++)
264 if (regs
[i
] && !((regs
[i
] >> 31) & 1))
265 decode_caches_intel (regs
[i
], xeon_mp
, level1
, level2
);
268 __cpuid (2, regs
[0], regs
[1], regs
[2], regs
[3]);
272 /* Detect cache parameters using CPUID function 4. This
273 method doesn't require hardcoded tables. */
284 detect_caches_cpuid4 (struct cache_desc
*level1
, struct cache_desc
*level2
,
285 struct cache_desc
*level3
)
287 struct cache_desc
*cache
;
289 unsigned eax
, ebx
, ecx
, edx
;
292 for (count
= 0;; count
++)
294 __cpuid_count(4, count
, eax
, ebx
, ecx
, edx
);
302 switch ((eax
>> 5) & 0x07)
319 unsigned sets
= ecx
+ 1;
320 unsigned part
= ((ebx
>> 12) & 0x03ff) + 1;
322 cache
->assoc
= ((ebx
>> 22) & 0x03ff) + 1;
323 cache
->line
= (ebx
& 0x0fff) + 1;
325 cache
->sizekb
= (cache
->assoc
* part
326 * cache
->line
* sets
) / 1024;
335 /* Returns the description of caches for an Intel processor. */
338 detect_caches_intel (bool xeon_mp
, unsigned max_level
,
339 unsigned max_ext_level
, unsigned *l2sizekb
)
341 struct cache_desc level1
= {0, 0, 0}, level2
= {0, 0, 0}, level3
= {0, 0, 0};
344 detect_caches_cpuid4 (&level1
, &level2
, &level3
);
345 else if (max_level
>= 2)
346 detect_caches_cpuid2 (xeon_mp
, &level1
, &level2
);
350 if (level1
.sizekb
== 0)
353 /* Let the L3 replace the L2. This assumes inclusive caches
354 and single threaded program for now. */
358 /* Intel CPUs are equipped with AMD style L2 cache info. Try this
359 method if other methods fail to provide L2 cache parameters. */
360 if (level2
.sizekb
== 0 && max_ext_level
>= 0x80000006)
361 detect_l2_cache (&level2
);
363 *l2sizekb
= level2
.sizekb
;
365 return describe_cache (level1
, level2
);
368 /* This will be called by the spec parser in gcc.c when it sees
369 a %:local_cpu_detect(args) construct. Currently it will be called
370 with either "arch" or "tune" as argument depending on if -march=native
371 or -mtune=native is to be substituted.
373 It returns a string containing new command line parameters to be
374 put at the place of the above two options, depending on what CPU
375 this is executed. E.g. "-march=k8" on an AMD64 machine
378 ARGC and ARGV are set depending on the actual arguments given
381 const char *host_detect_local_cpu (int argc
, const char **argv
)
383 enum processor_type processor
= PROCESSOR_I386
;
384 const char *cpu
= "i386";
386 const char *cache
= "";
387 const char *options
= "";
389 unsigned int eax
, ebx
, ecx
, edx
;
391 unsigned int max_level
, ext_level
;
394 unsigned int model
, family
;
396 unsigned int has_sse3
, has_ssse3
, has_cmpxchg16b
;
397 unsigned int has_cmpxchg8b
, has_cmov
, has_mmx
, has_sse
, has_sse2
;
399 /* Extended features */
400 unsigned int has_lahf_lm
= 0, has_sse4a
= 0;
401 unsigned int has_longmode
= 0, has_3dnowp
= 0, has_3dnow
= 0;
402 unsigned int has_movbe
= 0, has_sse4_1
= 0, has_sse4_2
= 0;
403 unsigned int has_popcnt
= 0, has_aes
= 0, has_avx
= 0, has_avx2
= 0;
404 unsigned int has_pclmul
= 0, has_abm
= 0, has_lwp
= 0;
405 unsigned int has_fma
= 0, has_fma4
= 0, has_xop
= 0;
406 unsigned int has_bmi
= 0, has_bmi2
= 0, has_tbm
= 0, has_lzcnt
= 0;
407 unsigned int has_hle
= 0, has_rtm
= 0;
408 unsigned int has_rdrnd
= 0, has_f16c
= 0, has_fsgsbase
= 0;
409 unsigned int has_rdseed
= 0, has_prfchw
= 0, has_adx
= 0;
410 unsigned int has_osxsave
= 0, has_fxsr
= 0, has_xsave
= 0, has_xsaveopt
= 0;
411 unsigned int has_avx512er
= 0, has_avx512pf
= 0, has_avx512cd
= 0;
412 unsigned int has_avx512f
= 0, has_sha
= 0, has_prefetchwt1
= 0;
416 unsigned int l2sizekb
= 0;
421 arch
= !strcmp (argv
[0], "arch");
423 if (!arch
&& strcmp (argv
[0], "tune"))
426 max_level
= __get_cpuid_max (0, &vendor
);
430 __cpuid (1, eax
, ebx
, ecx
, edx
);
432 model
= (eax
>> 4) & 0x0f;
433 family
= (eax
>> 8) & 0x0f;
434 if (vendor
== signature_INTEL_ebx
)
436 unsigned int extended_model
, extended_family
;
438 extended_model
= (eax
>> 12) & 0xf0;
439 extended_family
= (eax
>> 20) & 0xff;
442 family
+= extended_family
;
443 model
+= extended_model
;
445 else if (family
== 0x06)
446 model
+= extended_model
;
449 has_sse3
= ecx
& bit_SSE3
;
450 has_ssse3
= ecx
& bit_SSSE3
;
451 has_sse4_1
= ecx
& bit_SSE4_1
;
452 has_sse4_2
= ecx
& bit_SSE4_2
;
453 has_avx
= ecx
& bit_AVX
;
454 has_osxsave
= ecx
& bit_OSXSAVE
;
455 has_cmpxchg16b
= ecx
& bit_CMPXCHG16B
;
456 has_movbe
= ecx
& bit_MOVBE
;
457 has_popcnt
= ecx
& bit_POPCNT
;
458 has_aes
= ecx
& bit_AES
;
459 has_pclmul
= ecx
& bit_PCLMUL
;
460 has_fma
= ecx
& bit_FMA
;
461 has_f16c
= ecx
& bit_F16C
;
462 has_rdrnd
= ecx
& bit_RDRND
;
463 has_xsave
= ecx
& bit_XSAVE
;
465 has_cmpxchg8b
= edx
& bit_CMPXCHG8B
;
466 has_cmov
= edx
& bit_CMOV
;
467 has_mmx
= edx
& bit_MMX
;
468 has_fxsr
= edx
& bit_FXSAVE
;
469 has_sse
= edx
& bit_SSE
;
470 has_sse2
= edx
& bit_SSE2
;
474 __cpuid_count (7, 0, eax
, ebx
, ecx
, edx
);
476 has_bmi
= ebx
& bit_BMI
;
477 has_hle
= ebx
& bit_HLE
;
478 has_rtm
= ebx
& bit_RTM
;
479 has_avx2
= ebx
& bit_AVX2
;
480 has_bmi2
= ebx
& bit_BMI2
;
481 has_fsgsbase
= ebx
& bit_FSGSBASE
;
482 has_rdseed
= ebx
& bit_RDSEED
;
483 has_adx
= ebx
& bit_ADX
;
484 has_avx512f
= ebx
& bit_AVX512F
;
485 has_avx512er
= ebx
& bit_AVX512ER
;
486 has_avx512pf
= ebx
& bit_AVX512PF
;
487 has_avx512cd
= ebx
& bit_AVX512CD
;
488 has_sha
= ebx
& bit_SHA
;
490 has_prefetchwt1
= ecx
& bit_PREFETCHWT1
;
495 __cpuid_count (13, 1, eax
, ebx
, ecx
, edx
);
497 has_xsaveopt
= eax
& bit_XSAVEOPT
;
500 /* Check cpuid level of extended features. */
501 __cpuid (0x80000000, ext_level
, ebx
, ecx
, edx
);
503 if (ext_level
> 0x80000000)
505 __cpuid (0x80000001, eax
, ebx
, ecx
, edx
);
507 has_lahf_lm
= ecx
& bit_LAHF_LM
;
508 has_sse4a
= ecx
& bit_SSE4a
;
509 has_abm
= ecx
& bit_ABM
;
510 has_lwp
= ecx
& bit_LWP
;
511 has_fma4
= ecx
& bit_FMA4
;
512 has_xop
= ecx
& bit_XOP
;
513 has_tbm
= ecx
& bit_TBM
;
514 has_lzcnt
= ecx
& bit_LZCNT
;
515 has_prfchw
= ecx
& bit_PRFCHW
;
517 has_longmode
= edx
& bit_LM
;
518 has_3dnowp
= edx
& bit_3DNOWP
;
519 has_3dnow
= edx
& bit_3DNOW
;
522 /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */
523 #define XCR_XFEATURE_ENABLED_MASK 0x0
524 #define XSTATE_FP 0x1
525 #define XSTATE_SSE 0x2
526 #define XSTATE_YMM 0x4
528 asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
529 : "=a" (eax
), "=d" (edx
)
530 : "c" (XCR_XFEATURE_ENABLED_MASK
));
532 /* Check if SSE and YMM states are supported. */
534 || (eax
& (XSTATE_SSE
| XSTATE_YMM
)) != (XSTATE_SSE
| XSTATE_YMM
))
548 if (vendor
== signature_AMD_ebx
549 || vendor
== signature_CENTAUR_ebx
550 || vendor
== signature_CYRIX_ebx
551 || vendor
== signature_NSC_ebx
)
552 cache
= detect_caches_amd (ext_level
);
553 else if (vendor
== signature_INTEL_ebx
)
555 bool xeon_mp
= (family
== 15 && model
== 6);
556 cache
= detect_caches_intel (xeon_mp
, max_level
,
557 ext_level
, &l2sizekb
);
561 if (vendor
== signature_AMD_ebx
)
565 /* Detect geode processor by its processor signature. */
566 if (ext_level
> 0x80000001)
567 __cpuid (0x80000002, name
, ebx
, ecx
, edx
);
571 if (name
== signature_NSC_ebx
)
572 processor
= PROCESSOR_GEODE
;
574 processor
= PROCESSOR_BTVER2
;
576 processor
= PROCESSOR_BDVER4
;
577 else if (has_xsaveopt
)
578 processor
= PROCESSOR_BDVER3
;
580 processor
= PROCESSOR_BDVER2
;
582 processor
= PROCESSOR_BDVER1
;
583 else if (has_sse4a
&& has_ssse3
)
584 processor
= PROCESSOR_BTVER1
;
586 processor
= PROCESSOR_AMDFAM10
;
587 else if (has_sse2
|| has_longmode
)
588 processor
= PROCESSOR_K8
;
589 else if (has_3dnowp
&& family
== 6)
590 processor
= PROCESSOR_ATHLON
;
592 processor
= PROCESSOR_K6
;
594 processor
= PROCESSOR_PENTIUM
;
596 else if (vendor
== signature_CENTAUR_ebx
)
604 /* Use the default detection procedure. */
605 processor
= PROCESSOR_GENERIC
;
611 processor
= PROCESSOR_GENERIC
;
619 processor
= PROCESSOR_GENERIC
;
622 /* We have no idea. */
623 processor
= PROCESSOR_GENERIC
;
632 processor
= PROCESSOR_I486
;
635 processor
= PROCESSOR_PENTIUM
;
638 processor
= PROCESSOR_PENTIUMPRO
;
641 processor
= PROCESSOR_PENTIUM4
;
644 /* We have no idea. */
645 processor
= PROCESSOR_GENERIC
;
657 case PROCESSOR_PENTIUM
:
663 case PROCESSOR_PENTIUMPRO
:
715 /* This is unknown family 0x6 CPU. */
719 /* Assume Haswell. */
722 /* Assume Sandy Bridge. */
727 /* Assume Silvermont. */
730 /* Assume Nehalem. */
736 /* Assume Bonnell. */
743 /* It is Core Duo. */
746 /* It is Pentium M. */
749 /* It is Pentium III. */
752 /* It is Pentium II. */
755 /* Default to Pentium Pro. */
759 /* For -mtune, we default to -mtune=generic. */
764 case PROCESSOR_PENTIUM4
:
775 case PROCESSOR_GEODE
:
779 if (arch
&& has_3dnow
)
784 case PROCESSOR_ATHLON
:
791 if (arch
&& has_sse3
)
796 case PROCESSOR_AMDFAM10
:
799 case PROCESSOR_BDVER1
:
802 case PROCESSOR_BDVER2
:
805 case PROCESSOR_BDVER3
:
808 case PROCESSOR_BDVER4
:
811 case PROCESSOR_BTVER1
:
814 case PROCESSOR_BTVER2
:
819 /* Use something reasonable. */
837 else if (has_cmpxchg8b
)
846 const char *mmx
= has_mmx
? " -mmmx" : " -mno-mmx";
847 const char *mmx3dnow
= has_3dnow
? " -m3dnow" : " -mno-3dnow";
848 const char *sse
= has_sse
? " -msse" : " -mno-sse";
849 const char *sse2
= has_sse2
? " -msse2" : " -mno-sse2";
850 const char *sse3
= has_sse3
? " -msse3" : " -mno-sse3";
851 const char *ssse3
= has_ssse3
? " -mssse3" : " -mno-ssse3";
852 const char *sse4a
= has_sse4a
? " -msse4a" : " -mno-sse4a";
853 const char *cx16
= has_cmpxchg16b
? " -mcx16" : " -mno-cx16";
854 const char *sahf
= has_lahf_lm
? " -msahf" : " -mno-sahf";
855 const char *movbe
= has_movbe
? " -mmovbe" : " -mno-movbe";
856 const char *aes
= has_aes
? " -maes" : " -mno-aes";
857 const char *sha
= has_sha
? " -msha" : " -mno-sha";
858 const char *pclmul
= has_pclmul
? " -mpclmul" : " -mno-pclmul";
859 const char *popcnt
= has_popcnt
? " -mpopcnt" : " -mno-popcnt";
860 const char *abm
= has_abm
? " -mabm" : " -mno-abm";
861 const char *lwp
= has_lwp
? " -mlwp" : " -mno-lwp";
862 const char *fma
= has_fma
? " -mfma" : " -mno-fma";
863 const char *fma4
= has_fma4
? " -mfma4" : " -mno-fma4";
864 const char *xop
= has_xop
? " -mxop" : " -mno-xop";
865 const char *bmi
= has_bmi
? " -mbmi" : " -mno-bmi";
866 const char *bmi2
= has_bmi2
? " -mbmi2" : " -mno-bmi2";
867 const char *tbm
= has_tbm
? " -mtbm" : " -mno-tbm";
868 const char *avx
= has_avx
? " -mavx" : " -mno-avx";
869 const char *avx2
= has_avx2
? " -mavx2" : " -mno-avx2";
870 const char *sse4_2
= has_sse4_2
? " -msse4.2" : " -mno-sse4.2";
871 const char *sse4_1
= has_sse4_1
? " -msse4.1" : " -mno-sse4.1";
872 const char *lzcnt
= has_lzcnt
? " -mlzcnt" : " -mno-lzcnt";
873 const char *hle
= has_hle
? " -mhle" : " -mno-hle";
874 const char *rtm
= has_rtm
? " -mrtm" : " -mno-rtm";
875 const char *rdrnd
= has_rdrnd
? " -mrdrnd" : " -mno-rdrnd";
876 const char *f16c
= has_f16c
? " -mf16c" : " -mno-f16c";
877 const char *fsgsbase
= has_fsgsbase
? " -mfsgsbase" : " -mno-fsgsbase";
878 const char *rdseed
= has_rdseed
? " -mrdseed" : " -mno-rdseed";
879 const char *prfchw
= has_prfchw
? " -mprfchw" : " -mno-prfchw";
880 const char *adx
= has_adx
? " -madx" : " -mno-adx";
881 const char *fxsr
= has_fxsr
? " -mfxsr" : " -mno-fxsr";
882 const char *xsave
= has_xsave
? " -mxsave" : " -mno-xsave";
883 const char *xsaveopt
= has_xsaveopt
? " -mxsaveopt" : " -mno-xsaveopt";
884 const char *avx512f
= has_avx512f
? " -mavx512f" : " -mno-avx512f";
885 const char *avx512er
= has_avx512er
? " -mavx512er" : " -mno-avx512er";
886 const char *avx512cd
= has_avx512cd
? " -mavx512cd" : " -mno-avx512cd";
887 const char *avx512pf
= has_avx512pf
? " -mavx512pf" : " -mno-avx512pf";
888 const char *prefetchwt1
= has_prefetchwt1
? " -mprefetchwt1" : " -mno-prefetchwt1";
890 options
= concat (options
, mmx
, mmx3dnow
, sse
, sse2
, sse3
, ssse3
,
891 sse4a
, cx16
, sahf
, movbe
, aes
, sha
, pclmul
,
892 popcnt
, abm
, lwp
, fma
, fma4
, xop
, bmi
, bmi2
,
893 tbm
, avx
, avx2
, sse4_2
, sse4_1
, lzcnt
, rtm
,
894 hle
, rdrnd
, f16c
, fsgsbase
, rdseed
, prfchw
, adx
,
895 fxsr
, xsave
, xsaveopt
, avx512f
, avx512er
,
896 avx512cd
, avx512pf
, prefetchwt1
, NULL
);
900 return concat (cache
, "-m", argv
[0], "=", cpu
, options
, NULL
);
904 /* If we aren't compiling with GCC then the driver will just ignore
905 -march and -mtune "native" target and will leave to the newly
906 built compiler to generate code for its default target. */
908 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED
,
909 const char **argv ATTRIBUTE_UNUSED
)
913 #endif /* __GNUC__ */