gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2018 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #define IN_TARGET_CODE 1
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26
  27 const char *host_detect_local_cpu (int argc, const char **argv);
  28
  29 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  30 #include "cpuid.h"
  31
  32 struct cache_desc
  33 {
  34   unsigned sizekb;
  35   unsigned assoc;
  36   unsigned line;
  37 };
  38
  39 /* Returns command line parameters that describe size and
  40    cache line size of the processor caches.  */
  41
  42 static char *
  43 describe_cache (struct cache_desc level1, struct cache_desc level2)
  44 {
  45   char size[100], line[100], size2[100];
  46
  47   /* At the moment, gcc does not use the information
  48      about the associativity of the cache.  */
  49
  50   snprintf (size, sizeof (size),
  51             "--param l1-cache-size=%u ", level1.sizekb);
  52   snprintf (line, sizeof (line),
  53             "--param l1-cache-line-size=%u ", level1.line);
  54
  55   snprintf (size2, sizeof (size2),
  56             "--param l2-cache-size=%u ", level2.sizekb);
  57
  58   return concat (size, line, size2, NULL);
  59 }
  60
  61 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  62
  63 static void
  64 detect_l2_cache (struct cache_desc *level2)
  65 {
  66   unsigned eax, ebx, ecx, edx;
  67   unsigned assoc;
  68
  69   __cpuid (0x80000006, eax, ebx, ecx, edx);
  70
  71   level2->sizekb = (ecx >> 16) & 0xffff;
  72   level2->line = ecx & 0xff;
  73
  74   assoc = (ecx >> 12) & 0xf;
  75   if (assoc == 6)
  76     assoc = 8;
  77   else if (assoc == 8)
  78     assoc = 16;
  79   else if (assoc >= 0xa && assoc <= 0xc)
  80     assoc = 32 + (assoc - 0xa) * 16;
  81   else if (assoc >= 0xd && assoc <= 0xe)
  82     assoc = 96 + (assoc - 0xd) * 32;
  83
  84   level2->assoc = assoc;
  85 }
  86
  87 /* Returns the description of caches for an AMD processor.  */
  88
  89 static const char *
  90 detect_caches_amd (unsigned max_ext_level)
  91 {
  92   unsigned eax, ebx, ecx, edx;
  93
  94   struct cache_desc level1, level2 = {0, 0, 0};
  95
  96   if (max_ext_level < 0x80000005)
  97     return "";
  98
  99   __cpuid (0x80000005, eax, ebx, ecx, edx);
 100
 101   level1.sizekb = (ecx >> 24) & 0xff;
 102   level1.assoc = (ecx >> 16) & 0xff;
 103   level1.line = ecx & 0xff;
 104
 105   if (max_ext_level >= 0x80000006)
 106     detect_l2_cache (&level2);
 107
 108   return describe_cache (level1, level2);
 109 }
 110
 111 /* Decodes the size, the associativity and the cache line size of
 112    L1/L2 caches of an Intel processor.  Values are based on
 113    "Intel Processor Identification and the CPUID Instruction"
 114    [Application Note 485], revision -032, December 2007.  */
 115
 116 static void
 117 decode_caches_intel (unsigned reg, bool xeon_mp,
 118                      struct cache_desc *level1, struct cache_desc *level2)
 119 {
 120   int i;
 121
 122   for (i = 24; i >= 0; i -= 8)
 123     switch ((reg >> i) & 0xff)
 124       {
 125       case 0x0a:
 126         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 127         break;
 128       case 0x0c:
 129         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 130         break;
 131       case 0x0d:
 132         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 133         break;
 134       case 0x0e:
 135         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 136         break;
 137       case 0x21:
 138         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 139         break;
 140       case 0x24:
 141         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 142         break;
 143       case 0x2c:
 144         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 145         break;
 146       case 0x39:
 147         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 148         break;
 149       case 0x3a:
 150         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 151         break;
 152       case 0x3b:
 153         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 154         break;
 155       case 0x3c:
 156         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 157         break;
 158       case 0x3d:
 159         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 160         break;
 161       case 0x3e:
 162         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 163         break;
 164       case 0x41:
 165         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 166         break;
 167       case 0x42:
 168         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 169         break;
 170       case 0x43:
 171         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 172         break;
 173       case 0x44:
 174         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 175         break;
 176       case 0x45:
 177         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 178         break;
 179       case 0x48:
 180         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 181         break;
 182       case 0x49:
 183         if (xeon_mp)
 184           break;
 185         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 186         break;
 187       case 0x4e:
 188         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 189         break;
 190       case 0x60:
 191         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 192         break;
 193       case 0x66:
 194         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 195         break;
 196       case 0x67:
 197         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 198         break;
 199       case 0x68:
 200         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 201         break;
 202       case 0x78:
 203         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 204         break;
 205       case 0x79:
 206         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 207         break;
 208       case 0x7a:
 209         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 210         break;
 211       case 0x7b:
 212         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 213         break;
 214       case 0x7c:
 215         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 216         break;
 217       case 0x7d:
 218         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 219         break;
 220       case 0x7f:
 221         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 222         break;
 223       case 0x80:
 224         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 225         break;
 226       case 0x82:
 227         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 228         break;
 229       case 0x83:
 230         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 231         break;
 232       case 0x84:
 233         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 234         break;
 235       case 0x85:
 236         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 237         break;
 238       case 0x86:
 239         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 240         break;
 241       case 0x87:
 242         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 243
 244       default:
 245         break;
 246       }
 247 }
 248
 249 /* Detect cache parameters using CPUID function 2.  */
 250
 251 static void
 252 detect_caches_cpuid2 (bool xeon_mp,
 253                       struct cache_desc *level1, struct cache_desc *level2)
 254 {
 255   unsigned regs[4];
 256   int nreps, i;
 257
 258   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 259
 260   nreps = regs[0] & 0x0f;
 261   regs[0] &= ~0x0f;
 262
 263   while (--nreps >= 0)
 264     {
 265       for (i = 0; i < 4; i++)
 266         if (regs[i] && !((regs[i] >> 31) & 1))
 267           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 268
 269       if (nreps)
 270         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 271     }
 272 }
 273
 274 /* Detect cache parameters using CPUID function 4. This
 275    method doesn't require hardcoded tables.  */
 276
 277 enum cache_type
 278 {
 279   CACHE_END = 0,
 280   CACHE_DATA = 1,
 281   CACHE_INST = 2,
 282   CACHE_UNIFIED = 3
 283 };
 284
 285 static void
 286 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 287                       struct cache_desc *level3)
 288 {
 289   struct cache_desc *cache;
 290
 291   unsigned eax, ebx, ecx, edx;
 292   int count;
 293
 294   for (count = 0;; count++)
 295     {
 296       __cpuid_count(4, count, eax, ebx, ecx, edx);
 297       switch (eax & 0x1f)
 298         {
 299         case CACHE_END:
 300           return;
 301         case CACHE_DATA:
 302         case CACHE_UNIFIED:
 303           {
 304             switch ((eax >> 5) & 0x07)
 305               {
 306               case 1:
 307                 cache = level1;
 308                 break;
 309               case 2:
 310                 cache = level2;
 311                 break;
 312               case 3:
 313                 cache = level3;
 314                 break;
 315               default:
 316                 cache = NULL;
 317               }
 318
 319             if (cache)
 320               {
 321                 unsigned sets = ecx + 1;
 322                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 323
 324                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 325                 cache->line = (ebx & 0x0fff) + 1;
 326
 327                 cache->sizekb = (cache->assoc * part
 328                                  * cache->line * sets) / 1024;
 329               }
 330           }
 331         default:
 332           break;
 333         }
 334     }
 335 }
 336
 337 /* Returns the description of caches for an Intel processor.  */
 338
 339 static const char *
 340 detect_caches_intel (bool xeon_mp, unsigned max_level,
 341                      unsigned max_ext_level, unsigned *l2sizekb)
 342 {
 343   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 344
 345   if (max_level >= 4)
 346     detect_caches_cpuid4 (&level1, &level2, &level3);
 347   else if (max_level >= 2)
 348     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 349   else
 350     return "";
 351
 352   if (level1.sizekb == 0)
 353     return "";
 354
 355   /* Let the L3 replace the L2. This assumes inclusive caches
 356      and single threaded program for now. */
 357   if (level3.sizekb)
 358     level2 = level3;
 359
 360   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 361      method if other methods fail to provide L2 cache parameters.  */
 362   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 363     detect_l2_cache (&level2);
 364
 365   *l2sizekb = level2.sizekb;
 366
 367   return describe_cache (level1, level2);
 368 }
 369
 370 /* This will be called by the spec parser in gcc.c when it sees
 371    a %:local_cpu_detect(args) construct.  Currently it will be called
 372    with either "arch" or "tune" as argument depending on if -march=native
 373    or -mtune=native is to be substituted.
 374
 375    It returns a string containing new command line parameters to be
 376    put at the place of the above two options, depending on what CPU
 377    this is executed.  E.g. "-march=k8" on an AMD64 machine
 378    for -march=native.
 379
 380    ARGC and ARGV are set depending on the actual arguments given
 381    in the spec.  */
 382
 383 const char *host_detect_local_cpu (int argc, const char **argv)
 384 {
 385   enum processor_type processor = PROCESSOR_I386;
 386   const char *cpu = "i386";
 387
 388   const char *cache = "";
 389   const char *options = "";
 390
 391   unsigned int eax, ebx, ecx, edx;
 392
 393   unsigned int max_level, ext_level;
 394
 395   unsigned int vendor;
 396   unsigned int model, family;
 397
 398   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 399   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 400
 401   /* Extended features */
 402   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 403   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 404   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 405   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 406   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 407   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 408   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 409   unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
 410   unsigned int has_pconfig = 0, has_wbnoinvd = 0;
 411   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 412   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 413   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 414   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 415   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 416   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 417   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 418   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 419   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
 420   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
 421   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
 422   unsigned int has_avx512bitalg = 0;
 423   unsigned int has_ibt = 0, has_shstk = 0;
 424   unsigned int has_avx512vnni = 0, has_vaes = 0;
 425   unsigned int has_vpclmulqdq = 0;
 426
 427   bool arch;
 428
 429   unsigned int l2sizekb = 0;
 430
 431   if (argc < 1)
 432     return NULL;
 433
 434   arch = !strcmp (argv[0], "arch");
 435
 436   if (!arch && strcmp (argv[0], "tune"))
 437     return NULL;
 438
 439   max_level = __get_cpuid_max (0, &vendor);
 440   if (max_level < 1)
 441     goto done;
 442
 443   __cpuid (1, eax, ebx, ecx, edx);
 444
 445   model = (eax >> 4) & 0x0f;
 446   family = (eax >> 8) & 0x0f;
 447   if (vendor == signature_INTEL_ebx
 448       || vendor == signature_AMD_ebx)
 449     {
 450       unsigned int extended_model, extended_family;
 451
 452       extended_model = (eax >> 12) & 0xf0;
 453       extended_family = (eax >> 20) & 0xff;
 454       if (family == 0x0f)
 455         {
 456           family += extended_family;
 457           model += extended_model;
 458         }
 459       else if (family == 0x06)
 460         model += extended_model;
 461     }
 462
 463   has_sse3 = ecx & bit_SSE3;
 464   has_ssse3 = ecx & bit_SSSE3;
 465   has_sse4_1 = ecx & bit_SSE4_1;
 466   has_sse4_2 = ecx & bit_SSE4_2;
 467   has_avx = ecx & bit_AVX;
 468   has_osxsave = ecx & bit_OSXSAVE;
 469   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 470   has_movbe = ecx & bit_MOVBE;
 471   has_popcnt = ecx & bit_POPCNT;
 472   has_aes = ecx & bit_AES;
 473   has_pclmul = ecx & bit_PCLMUL;
 474   has_fma = ecx & bit_FMA;
 475   has_f16c = ecx & bit_F16C;
 476   has_rdrnd = ecx & bit_RDRND;
 477   has_xsave = ecx & bit_XSAVE;
 478
 479   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 480   has_cmov = edx & bit_CMOV;
 481   has_mmx = edx & bit_MMX;
 482   has_fxsr = edx & bit_FXSAVE;
 483   has_sse = edx & bit_SSE;
 484   has_sse2 = edx & bit_SSE2;
 485
 486   if (max_level >= 7)
 487     {
 488       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 489
 490       has_bmi = ebx & bit_BMI;
 491       has_sgx = ebx & bit_SGX;
 492       has_hle = ebx & bit_HLE;
 493       has_rtm = ebx & bit_RTM;
 494       has_avx2 = ebx & bit_AVX2;
 495       has_bmi2 = ebx & bit_BMI2;
 496       has_fsgsbase = ebx & bit_FSGSBASE;
 497       has_rdseed = ebx & bit_RDSEED;
 498       has_adx = ebx & bit_ADX;
 499       has_avx512f = ebx & bit_AVX512F;
 500       has_avx512er = ebx & bit_AVX512ER;
 501       has_avx512pf = ebx & bit_AVX512PF;
 502       has_avx512cd = ebx & bit_AVX512CD;
 503       has_sha = ebx & bit_SHA;
 504       has_clflushopt = ebx & bit_CLFLUSHOPT;
 505       has_clwb = ebx & bit_CLWB;
 506       has_avx512dq = ebx & bit_AVX512DQ;
 507       has_avx512bw = ebx & bit_AVX512BW;
 508       has_avx512vl = ebx & bit_AVX512VL;
 509       has_avx512ifma = ebx & bit_AVX512IFMA;
 510
 511       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 512       has_avx512vbmi = ecx & bit_AVX512VBMI;
 513       has_pku = ecx & bit_OSPKE;
 514       has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
 515       has_avx512vnni = ecx & bit_AVX512VNNI;
 516       has_rdpid = ecx & bit_RDPID;
 517       has_gfni = ecx & bit_GFNI;
 518       has_vaes = ecx & bit_VAES;
 519       has_vpclmulqdq = ecx & bit_VPCLMULQDQ;
 520       has_avx512bitalg = ecx & bit_AVX512BITALG;
 521
 522       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
 523       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
 524
 525       has_shstk = ecx & bit_SHSTK;
 526       has_ibt = edx & bit_IBT;
 527       has_pconfig = edx & bit_PCONFIG;
 528     }
 529
 530   if (max_level >= 13)
 531     {
 532       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 533
 534       has_xsaveopt = eax & bit_XSAVEOPT;
 535       has_xsavec = eax & bit_XSAVEC;
 536       has_xsaves = eax & bit_XSAVES;
 537     }
 538
 539   /* Check cpuid level of extended features.  */
 540   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 541
 542   if (ext_level >= 0x80000001)
 543     {
 544       __cpuid (0x80000001, eax, ebx, ecx, edx);
 545
 546       has_lahf_lm = ecx & bit_LAHF_LM;
 547       has_sse4a = ecx & bit_SSE4a;
 548       has_abm = ecx & bit_ABM;
 549       has_lwp = ecx & bit_LWP;
 550       has_fma4 = ecx & bit_FMA4;
 551       has_xop = ecx & bit_XOP;
 552       has_tbm = ecx & bit_TBM;
 553       has_lzcnt = ecx & bit_LZCNT;
 554       has_prfchw = ecx & bit_PRFCHW;
 555
 556       has_longmode = edx & bit_LM;
 557       has_3dnowp = edx & bit_3DNOWP;
 558       has_3dnow = edx & bit_3DNOW;
 559       has_mwaitx = ecx & bit_MWAITX;
 560     }
 561
 562   if (ext_level >= 0x80000008)
 563     {
 564       __cpuid (0x80000008, eax, ebx, ecx, edx);
 565       has_clzero = ebx & bit_CLZERO;
 566       has_wbnoinvd = ebx & bit_WBNOINVD;
 567     }
 568
 569   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 570 #define XCR_XFEATURE_ENABLED_MASK       0x0
 571 #define XSTATE_FP                       0x1
 572 #define XSTATE_SSE                      0x2
 573 #define XSTATE_YMM                      0x4
 574 #define XSTATE_OPMASK                   0x20
 575 #define XSTATE_ZMM                      0x40
 576 #define XSTATE_HI_ZMM                   0x80
 577
 578 #define XCR_AVX_ENABLED_MASK \
 579   (XSTATE_SSE | XSTATE_YMM)
 580 #define XCR_AVX512F_ENABLED_MASK \
 581   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 582
 583   if (has_osxsave)
 584     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 585          : "=a" (eax), "=d" (edx)
 586          : "c" (XCR_XFEATURE_ENABLED_MASK));
 587   else
 588     eax = 0;
 589
 590   /* Check if AVX registers are supported.  */
 591   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 592     {
 593       has_avx = 0;
 594       has_avx2 = 0;
 595       has_fma = 0;
 596       has_fma4 = 0;
 597       has_f16c = 0;
 598       has_xop = 0;
 599       has_xsave = 0;
 600       has_xsaveopt = 0;
 601       has_xsaves = 0;
 602       has_xsavec = 0;
 603     }
 604
 605   /* Check if AVX512F registers are supported.  */
 606   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 607     {
 608       has_avx512f = 0;
 609       has_avx512er = 0;
 610       has_avx512pf = 0;
 611       has_avx512cd = 0;
 612       has_avx512dq = 0;
 613       has_avx512bw = 0;
 614       has_avx512vl = 0;
 615     }
 616
 617   if (!arch)
 618     {
 619       if (vendor == signature_AMD_ebx
 620           || vendor == signature_CENTAUR_ebx
 621           || vendor == signature_CYRIX_ebx
 622           || vendor == signature_NSC_ebx)
 623         cache = detect_caches_amd (ext_level);
 624       else if (vendor == signature_INTEL_ebx)
 625         {
 626           bool xeon_mp = (family == 15 && model == 6);
 627           cache = detect_caches_intel (xeon_mp, max_level,
 628                                        ext_level, &l2sizekb);
 629         }
 630     }
 631
 632   if (vendor == signature_AMD_ebx)
 633     {
 634       unsigned int name;
 635
 636       /* Detect geode processor by its processor signature.  */
 637       if (ext_level >= 0x80000002)
 638         __cpuid (0x80000002, name, ebx, ecx, edx);
 639       else
 640         name = 0;
 641
 642       if (name == signature_NSC_ebx)
 643         processor = PROCESSOR_GEODE;
 644       else if (has_movbe && family == 22)
 645         processor = PROCESSOR_BTVER2;
 646       else if (has_clzero)
 647         processor = PROCESSOR_ZNVER1;
 648       else if (has_avx2)
 649         processor = PROCESSOR_BDVER4;
 650       else if (has_xsaveopt)
 651         processor = PROCESSOR_BDVER3;
 652       else if (has_bmi)
 653         processor = PROCESSOR_BDVER2;
 654       else if (has_xop)
 655         processor = PROCESSOR_BDVER1;
 656       else if (has_sse4a && has_ssse3)
 657         processor = PROCESSOR_BTVER1;
 658       else if (has_sse4a)
 659         processor = PROCESSOR_AMDFAM10;
 660       else if (has_sse2 || has_longmode)
 661         processor = PROCESSOR_K8;
 662       else if (has_3dnowp && family == 6)
 663         processor = PROCESSOR_ATHLON;
 664       else if (has_mmx)
 665         processor = PROCESSOR_K6;
 666       else
 667         processor = PROCESSOR_PENTIUM;
 668     }
 669   else if (vendor == signature_CENTAUR_ebx)
 670     {
 671       processor = PROCESSOR_GENERIC;
 672
 673       switch (family)
 674         {
 675         default:
 676           /* We have no idea.  */
 677           break;
 678
 679         case 5:
 680           if (has_3dnow || has_mmx)
 681             processor = PROCESSOR_I486;
 682           break;
 683
 684         case 6:
 685           if (has_longmode)
 686             processor = PROCESSOR_K8;
 687           else if (model >= 9)
 688             processor = PROCESSOR_PENTIUMPRO;
 689           else if (model >= 6)
 690             processor = PROCESSOR_I486;
 691         }
 692     }
 693   else
 694     {
 695       switch (family)
 696         {
 697         case 4:
 698           processor = PROCESSOR_I486;
 699           break;
 700         case 5:
 701           processor = PROCESSOR_PENTIUM;
 702           break;
 703         case 6:
 704           processor = PROCESSOR_PENTIUMPRO;
 705           break;
 706         case 15:
 707           processor = PROCESSOR_PENTIUM4;
 708           break;
 709         default:
 710           /* We have no idea.  */
 711           processor = PROCESSOR_GENERIC;
 712         }
 713     }
 714
 715   switch (processor)
 716     {
 717     case PROCESSOR_I386:
 718       /* Default.  */
 719       break;
 720     case PROCESSOR_I486:
 721       if (arch && vendor == signature_CENTAUR_ebx)
 722         {
 723           if (model >= 6)
 724             cpu = "c3";
 725           else if (has_3dnow)
 726             cpu = "winchip2";
 727           else
 728             /* Assume WinChip C6.  */
 729             cpu = "winchip-c6";
 730         }
 731       else
 732         cpu = "i486";
 733       break;
 734     case PROCESSOR_PENTIUM:
 735       if (arch && has_mmx)
 736         cpu = "pentium-mmx";
 737       else
 738         cpu = "pentium";
 739       break;
 740     case PROCESSOR_PENTIUMPRO:
 741       switch (model)
 742         {
 743         case 0x1c:
 744         case 0x26:
 745           /* Bonnell.  */
 746           cpu = "bonnell";
 747           break;
 748         case 0x37:
 749         case 0x4a:
 750         case 0x4d:
 751         case 0x5a:
 752         case 0x5d:
 753           /* Silvermont.  */
 754           cpu = "silvermont";
 755           break;
 756         case 0x0f:
 757           /* Merom.  */
 758         case 0x17:
 759         case 0x1d:
 760           /* Penryn.  */
 761           cpu = "core2";
 762           break;
 763         case 0x1a:
 764         case 0x1e:
 765         case 0x1f:
 766         case 0x2e:
 767           /* Nehalem.  */
 768           cpu = "nehalem";
 769           break;
 770         case 0x25:
 771         case 0x2c:
 772         case 0x2f:
 773           /* Westmere.  */
 774           cpu = "westmere";
 775           break;
 776         case 0x2a:
 777         case 0x2d:
 778           /* Sandy Bridge.  */
 779           cpu = "sandybridge";
 780           break;
 781         case 0x3a:
 782         case 0x3e:
 783           /* Ivy Bridge.  */
 784           cpu = "ivybridge";
 785           break;
 786         case 0x3c:
 787         case 0x3f:
 788         case 0x45:
 789         case 0x46:
 790           /* Haswell.  */
 791           cpu = "haswell";
 792           break;
 793         case 0x3d:
 794         case 0x47:
 795         case 0x4f:
 796         case 0x56:
 797           /* Broadwell.  */
 798           cpu = "broadwell";
 799           break;
 800         case 0x4e:
 801         case 0x5e:
 802           /* Skylake.  */
 803         case 0x8e:
 804         case 0x9e:
 805           /* Kaby Lake.  */
 806           cpu = "skylake";
 807           break;
 808         case 0x55:
 809           /* Skylake with AVX-512.  */
 810           cpu = "skylake-avx512";
 811           break;
 812         case 0x57:
 813           /* Knights Landing.  */
 814           cpu = "knl";
 815           break;
 816         case 0x66:
 817           /* Cannon Lake.  */
 818           cpu = "cannonlake";
 819           break;
 820         case 0x85:
 821           /* Knights Mill.  */
 822           cpu = "knm";
 823           break;
 824         default:
 825           if (arch)
 826             {
 827               /* This is unknown family 0x6 CPU.  */
 828               /* Assume Ice Lake Server.  */
 829               if (has_wbnoinvd)
 830                 cpu = "icelake-server";
 831               /* Assume Ice Lake.  */
 832               else if (has_gfni)
 833                 cpu = "icelake-client";
 834               /* Assume Cannon Lake.  */
 835               else if (has_avx512vbmi)
 836                 cpu = "cannonlake";
 837               /* Assume Knights Mill.  */
 838               else if (has_avx5124vnniw)
 839                 cpu = "knm";
 840               /* Assume Knights Landing.  */
 841               else if (has_avx512er)
 842                 cpu = "knl";
 843               /* Assume Skylake with AVX-512.  */
 844               else if (has_avx512f)
 845                 cpu = "skylake-avx512";
 846               /* Assume Skylake.  */
 847               else if (has_clflushopt)
 848                 cpu = "skylake";
 849               /* Assume Broadwell.  */
 850               else if (has_adx)
 851                 cpu = "broadwell";
 852               else if (has_avx2)
 853                 /* Assume Haswell.  */
 854                 cpu = "haswell";
 855               else if (has_avx)
 856                 /* Assume Sandy Bridge.  */
 857                 cpu = "sandybridge";
 858               else if (has_sse4_2)
 859                 {
 860                   if (has_movbe)
 861                     /* Assume Silvermont.  */
 862                     cpu = "silvermont";
 863                   else
 864                     /* Assume Nehalem.  */
 865                     cpu = "nehalem";
 866                 }
 867               else if (has_ssse3)
 868                 {
 869                   if (has_movbe)
 870                     /* Assume Bonnell.  */
 871                     cpu = "bonnell";
 872                   else
 873                     /* Assume Core 2.  */
 874                     cpu = "core2";
 875                 }
 876               else if (has_longmode)
 877                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 878                    -march=native would be unusable for 64-bit compilations,
 879                    as all the CPUs below are 32-bit only.  */
 880                 cpu = "x86-64";
 881               else if (has_sse3)
 882                 {
 883                   if (vendor == signature_CENTAUR_ebx)
 884                     /* C7 / Eden "Esther" */
 885                     cpu = "c7";
 886                   else
 887                     /* It is Core Duo.  */
 888                     cpu = "pentium-m";
 889                 }
 890               else if (has_sse2)
 891                 /* It is Pentium M.  */
 892                 cpu = "pentium-m";
 893               else if (has_sse)
 894                 {
 895                   if (vendor == signature_CENTAUR_ebx)
 896                     {
 897                       if (model >= 9)
 898                         /* Eden "Nehemiah" */
 899                         cpu = "nehemiah";
 900                       else
 901                         cpu = "c3-2";
 902                     }
 903                   else
 904                     /* It is Pentium III.  */
 905                     cpu = "pentium3";
 906                 }
 907               else if (has_mmx)
 908                 /* It is Pentium II.  */
 909                 cpu = "pentium2";
 910               else
 911                 /* Default to Pentium Pro.  */
 912                 cpu = "pentiumpro";
 913             }
 914           else
 915             /* For -mtune, we default to -mtune=generic.  */
 916             cpu = "generic";
 917           break;
 918         }
 919       break;
 920     case PROCESSOR_PENTIUM4:
 921       if (has_sse3)
 922         {
 923           if (has_longmode)
 924             cpu = "nocona";
 925           else
 926             cpu = "prescott";
 927         }
 928       else
 929         cpu = "pentium4";
 930       break;
 931     case PROCESSOR_GEODE:
 932       cpu = "geode";
 933       break;
 934     case PROCESSOR_K6:
 935       if (arch && has_3dnow)
 936         cpu = "k6-3";
 937       else
 938         cpu = "k6";
 939       break;
 940     case PROCESSOR_ATHLON:
 941       if (arch && has_sse)
 942         cpu = "athlon-4";
 943       else
 944         cpu = "athlon";
 945       break;
 946     case PROCESSOR_K8:
 947       if (arch)
 948         {
 949           if (vendor == signature_CENTAUR_ebx)
 950             {
 951               if (has_sse4_1)
 952                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 953                 cpu = "nano-3000";
 954               else if (has_ssse3)
 955                 /* Nano 1000 | Nano 2000 */
 956                 cpu = "nano";
 957               else if (has_sse3)
 958                 /* Eden X2 */
 959                 cpu = "eden-x2";
 960               else
 961                 /* Default to k8 */
 962                 cpu = "k8";
 963             }
 964           else if (has_sse3)
 965             cpu = "k8-sse3";
 966           else
 967             cpu = "k8";
 968         }
 969       else
 970         /* For -mtune, we default to -mtune=k8 */
 971         cpu = "k8";
 972       break;
 973     case PROCESSOR_AMDFAM10:
 974       cpu = "amdfam10";
 975       break;
 976     case PROCESSOR_BDVER1:
 977       cpu = "bdver1";
 978       break;
 979     case PROCESSOR_BDVER2:
 980       cpu = "bdver2";
 981       break;
 982     case PROCESSOR_BDVER3:
 983       cpu = "bdver3";
 984       break;
 985     case PROCESSOR_BDVER4:
 986       cpu = "bdver4";
 987       break;
 988     case PROCESSOR_ZNVER1:
 989       cpu = "znver1";
 990       break;
 991     case PROCESSOR_BTVER1:
 992       cpu = "btver1";
 993       break;
 994     case PROCESSOR_BTVER2:
 995       cpu = "btver2";
 996       break;
 997
 998     default:
 999       /* Use something reasonable.  */
1000       if (arch)
1001         {
1002           if (has_ssse3)
1003             cpu = "core2";
1004           else if (has_sse3)
1005             {
1006               if (has_longmode)
1007                 cpu = "nocona";
1008               else
1009                 cpu = "prescott";
1010             }
1011           else if (has_longmode)
1012             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
1013                -march=native would be unusable for 64-bit compilations,
1014                as all the CPUs below are 32-bit only.  */
1015             cpu = "x86-64";
1016           else if (has_sse2)
1017             cpu = "pentium4";
1018           else if (has_cmov)
1019             cpu = "pentiumpro";
1020           else if (has_mmx)
1021             cpu = "pentium-mmx";
1022           else if (has_cmpxchg8b)
1023             cpu = "pentium";
1024         }
1025       else
1026         cpu = "generic";
1027     }
1028
1029   if (arch)
1030     {
1031       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
1032       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
1033       const char *sse = has_sse ? " -msse" : " -mno-sse";
1034       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
1035       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
1036       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
1037       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
1038       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
1039       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
1040       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
1041       const char *aes = has_aes ? " -maes" : " -mno-aes";
1042       const char *sha = has_sha ? " -msha" : " -mno-sha";
1043       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
1044       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
1045       const char *abm = has_abm ? " -mabm" : " -mno-abm";
1046       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
1047       const char *fma = has_fma ? " -mfma" : " -mno-fma";
1048       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
1049       const char *xop = has_xop ? " -mxop" : " -mno-xop";
1050       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
1051       const char *pconfig = has_pconfig ? " -mpconfig" : " -mno-pconfig";
1052       const char *wbnoinvd = has_wbnoinvd ? " -mwbnoinvd" : " -mno-wbnoinvd";
1053       const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
1054       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
1055       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
1056       const char *avx = has_avx ? " -mavx" : " -mno-avx";
1057       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
1058       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
1059       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
1060       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1061       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1062       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1063       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1064       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1065       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1066       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1067       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1068       const char *adx = has_adx ? " -madx" : " -mno-adx";
1069       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1070       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1071       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1072       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1073       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1074       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1075       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1076       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1077       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1078       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1079       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1080       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1081       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1082       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1083       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1084       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1085       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
1086       const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
1087       const char *avx512vnni = has_avx512vnni ? " -mavx512vnni" : " -mno-avx512vnni";
1088       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
1089       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1090       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1091       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1092       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1093       const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
1094       const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
1095       const char *ibt = has_ibt ? " -mibt" : " -mno-ibt";
1096       const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
1097       const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
1098       const char *vpclmulqdq = has_vpclmulqdq ? " -mvpclmulqdq" : " -mno-vpclmulqdq";
1099       const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
1100       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1101                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1102                         popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
1103                         pconfig, wbnoinvd,
1104                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1105                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1106                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1107                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1108                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1109                         avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
1110                         clwb, mwaitx, clzero, pku, rdpid, gfni, ibt, shstk,
1111                         avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
1112                         avx512bitalg, NULL);
1113     }
1114
1115 done:
1116   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1117 }
1118 #else
1119
1120 /* If we are compiling with GCC where %EBX register is fixed, then the
1121    driver will just ignore -march and -mtune "native" target and will leave
1122    to the newly built compiler to generate code for its default target.  */
1123
1124 const char *host_detect_local_cpu (int, const char **)
1125 {
1126   return NULL;
1127 }
1128 #endif /* __GNUC__ */