gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_pcommit = 0;
 417
 418   bool arch;
 419
 420   unsigned int l2sizekb = 0;
 421
 422   if (argc < 1)
 423     return NULL;
 424
 425   arch = !strcmp (argv[0], "arch");
 426
 427   if (!arch && strcmp (argv[0], "tune"))
 428     return NULL;
 429
 430   max_level = __get_cpuid_max (0, &vendor);
 431   if (max_level < 1)
 432     goto done;
 433
 434   __cpuid (1, eax, ebx, ecx, edx);
 435
 436   model = (eax >> 4) & 0x0f;
 437   family = (eax >> 8) & 0x0f;
 438   if (vendor == signature_INTEL_ebx
 439       || vendor == signature_AMD_ebx)
 440     {
 441       unsigned int extended_model, extended_family;
 442
 443       extended_model = (eax >> 12) & 0xf0;
 444       extended_family = (eax >> 20) & 0xff;
 445       if (family == 0x0f)
 446         {
 447           family += extended_family;
 448           model += extended_model;
 449         }
 450       else if (family == 0x06)
 451         model += extended_model;
 452     }
 453
 454   has_sse3 = ecx & bit_SSE3;
 455   has_ssse3 = ecx & bit_SSSE3;
 456   has_sse4_1 = ecx & bit_SSE4_1;
 457   has_sse4_2 = ecx & bit_SSE4_2;
 458   has_avx = ecx & bit_AVX;
 459   has_osxsave = ecx & bit_OSXSAVE;
 460   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 461   has_movbe = ecx & bit_MOVBE;
 462   has_popcnt = ecx & bit_POPCNT;
 463   has_aes = ecx & bit_AES;
 464   has_pclmul = ecx & bit_PCLMUL;
 465   has_fma = ecx & bit_FMA;
 466   has_f16c = ecx & bit_F16C;
 467   has_rdrnd = ecx & bit_RDRND;
 468   has_xsave = ecx & bit_XSAVE;
 469
 470   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 471   has_cmov = edx & bit_CMOV;
 472   has_mmx = edx & bit_MMX;
 473   has_fxsr = edx & bit_FXSAVE;
 474   has_sse = edx & bit_SSE;
 475   has_sse2 = edx & bit_SSE2;
 476
 477   if (max_level >= 7)
 478     {
 479       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 480
 481       has_bmi = ebx & bit_BMI;
 482       has_hle = ebx & bit_HLE;
 483       has_rtm = ebx & bit_RTM;
 484       has_avx2 = ebx & bit_AVX2;
 485       has_bmi2 = ebx & bit_BMI2;
 486       has_fsgsbase = ebx & bit_FSGSBASE;
 487       has_rdseed = ebx & bit_RDSEED;
 488       has_adx = ebx & bit_ADX;
 489       has_avx512f = ebx & bit_AVX512F;
 490       has_avx512er = ebx & bit_AVX512ER;
 491       has_avx512pf = ebx & bit_AVX512PF;
 492       has_avx512cd = ebx & bit_AVX512CD;
 493       has_sha = ebx & bit_SHA;
 494       has_pcommit = ebx & bit_PCOMMIT;
 495       has_clflushopt = ebx & bit_CLFLUSHOPT;
 496       has_clwb = ebx & bit_CLWB;
 497       has_avx512dq = ebx & bit_AVX512DQ;
 498       has_avx512bw = ebx & bit_AVX512BW;
 499       has_avx512vl = ebx & bit_AVX512VL;
 500       has_avx512vl = ebx & bit_AVX512IFMA;
 501
 502       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 503       has_avx512vl = ecx & bit_AVX512VBMI;
 504     }
 505
 506   if (max_level >= 13)
 507     {
 508       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 509
 510       has_xsaveopt = eax & bit_XSAVEOPT;
 511       has_xsavec = eax & bit_XSAVEC;
 512       has_xsaves = eax & bit_XSAVES;
 513     }
 514
 515   /* Check cpuid level of extended features.  */
 516   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 517
 518   if (ext_level > 0x80000000)
 519     {
 520       __cpuid (0x80000001, eax, ebx, ecx, edx);
 521
 522       has_lahf_lm = ecx & bit_LAHF_LM;
 523       has_sse4a = ecx & bit_SSE4a;
 524       has_abm = ecx & bit_ABM;
 525       has_lwp = ecx & bit_LWP;
 526       has_fma4 = ecx & bit_FMA4;
 527       has_xop = ecx & bit_XOP;
 528       has_tbm = ecx & bit_TBM;
 529       has_lzcnt = ecx & bit_LZCNT;
 530       has_prfchw = ecx & bit_PRFCHW;
 531
 532       has_longmode = edx & bit_LM;
 533       has_3dnowp = edx & bit_3DNOWP;
 534       has_3dnow = edx & bit_3DNOW;
 535     }
 536
 537   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 538 #define XCR_XFEATURE_ENABLED_MASK       0x0
 539 #define XSTATE_FP                       0x1
 540 #define XSTATE_SSE                      0x2
 541 #define XSTATE_YMM                      0x4
 542 #define XSTATE_OPMASK                   0x20
 543 #define XSTATE_ZMM                      0x40
 544 #define XSTATE_HI_ZMM                   0x80
 545   if (has_osxsave)
 546     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 547          : "=a" (eax), "=d" (edx)
 548          : "c" (XCR_XFEATURE_ENABLED_MASK));
 549
 550   /* Check if SSE and YMM states are supported.  */
 551   if (!has_osxsave
 552       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 553     {
 554       has_avx = 0;
 555       has_avx2 = 0;
 556       has_fma = 0;
 557       has_fma4 = 0;
 558       has_f16c = 0;
 559       has_xop = 0;
 560       has_xsave = 0;
 561       has_xsaveopt = 0;
 562       has_xsaves = 0;
 563       has_xsavec = 0;
 564     }
 565
 566   if (!has_osxsave
 567       || (eax &
 568           (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 569           != (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM))
 570     {
 571       has_avx512f = 0;
 572       has_avx512er = 0;
 573       has_avx512pf = 0;
 574       has_avx512cd = 0;
 575       has_avx512dq = 0;
 576       has_avx512bw = 0;
 577       has_avx512vl = 0;
 578     }
 579
 580   if (!arch)
 581     {
 582       if (vendor == signature_AMD_ebx
 583           || vendor == signature_CENTAUR_ebx
 584           || vendor == signature_CYRIX_ebx
 585           || vendor == signature_NSC_ebx)
 586         cache = detect_caches_amd (ext_level);
 587       else if (vendor == signature_INTEL_ebx)
 588         {
 589           bool xeon_mp = (family == 15 && model == 6);
 590           cache = detect_caches_intel (xeon_mp, max_level,
 591                                        ext_level, &l2sizekb);
 592         }
 593     }
 594
 595   if (vendor == signature_AMD_ebx)
 596     {
 597       unsigned int name;
 598
 599       /* Detect geode processor by its processor signature.  */
 600       if (ext_level > 0x80000001)
 601         __cpuid (0x80000002, name, ebx, ecx, edx);
 602       else
 603         name = 0;
 604
 605       if (name == signature_NSC_ebx)
 606         processor = PROCESSOR_GEODE;
 607       else if (has_movbe && family == 22)
 608         processor = PROCESSOR_BTVER2;
 609       else if (has_avx2)
 610         processor = PROCESSOR_BDVER4;
 611       else if (has_xsaveopt)
 612         processor = PROCESSOR_BDVER3;
 613       else if (has_bmi)
 614         processor = PROCESSOR_BDVER2;
 615       else if (has_xop)
 616         processor = PROCESSOR_BDVER1;
 617       else if (has_sse4a && has_ssse3)
 618         processor = PROCESSOR_BTVER1;
 619       else if (has_sse4a)
 620         processor = PROCESSOR_AMDFAM10;
 621       else if (has_sse2 || has_longmode)
 622         processor = PROCESSOR_K8;
 623       else if (has_3dnowp && family == 6)
 624         processor = PROCESSOR_ATHLON;
 625       else if (has_mmx)
 626         processor = PROCESSOR_K6;
 627       else
 628         processor = PROCESSOR_PENTIUM;
 629     }
 630   else if (vendor == signature_CENTAUR_ebx)
 631     {
 632       if (arch)
 633         {
 634           switch (family)
 635             {
 636             case 6:
 637               if (model > 9)
 638                 /* Use the default detection procedure.  */
 639                 processor = PROCESSOR_GENERIC;
 640               else if (model == 9)
 641                 cpu = "c3-2";
 642               else if (model >= 6)
 643                 cpu = "c3";
 644               else
 645                 processor = PROCESSOR_GENERIC;
 646               break;
 647             case 5:
 648               if (has_3dnow)
 649                 cpu = "winchip2";
 650               else if (has_mmx)
 651                 cpu = "winchip2-c6";
 652               else
 653                 processor = PROCESSOR_GENERIC;
 654               break;
 655             default:
 656               /* We have no idea.  */
 657               processor = PROCESSOR_GENERIC;
 658             }
 659         }
 660     }
 661   else
 662     {
 663       switch (family)
 664         {
 665         case 4:
 666           processor = PROCESSOR_I486;
 667           break;
 668         case 5:
 669           processor = PROCESSOR_PENTIUM;
 670           break;
 671         case 6:
 672           processor = PROCESSOR_PENTIUMPRO;
 673           break;
 674         case 15:
 675           processor = PROCESSOR_PENTIUM4;
 676           break;
 677         default:
 678           /* We have no idea.  */
 679           processor = PROCESSOR_GENERIC;
 680         }
 681     }
 682
 683   switch (processor)
 684     {
 685     case PROCESSOR_I386:
 686       /* Default.  */
 687       break;
 688     case PROCESSOR_I486:
 689       cpu = "i486";
 690       break;
 691     case PROCESSOR_PENTIUM:
 692       if (arch && has_mmx)
 693         cpu = "pentium-mmx";
 694       else
 695         cpu = "pentium";
 696       break;
 697     case PROCESSOR_PENTIUMPRO:
 698       switch (model)
 699         {
 700         case 0x1c:
 701         case 0x26:
 702           /* Bonnell.  */
 703           cpu = "bonnell";
 704           break;
 705         case 0x37:
 706         case 0x4a:
 707         case 0x4d:
 708         case 0x5a:
 709         case 0x5d:
 710           /* Silvermont.  */
 711           cpu = "silvermont";
 712           break;
 713         case 0x0f:
 714           /* Merom.  */
 715         case 0x17:
 716         case 0x1d:
 717           /* Penryn.  */
 718           cpu = "core2";
 719           break;
 720         case 0x1a:
 721         case 0x1e:
 722         case 0x1f:
 723         case 0x2e:
 724           /* Nehalem.  */
 725           cpu = "nehalem";
 726           break;
 727         case 0x25:
 728         case 0x2c:
 729         case 0x2f:
 730           /* Westmere.  */
 731           cpu = "westmere";
 732           break;
 733         case 0x2a:
 734         case 0x2d:
 735           /* Sandy Bridge.  */
 736           cpu = "sandybridge";
 737           break;
 738         case 0x3a:
 739         case 0x3e:
 740           /* Ivy Bridge.  */
 741           cpu = "ivybridge";
 742           break;
 743         case 0x3c:
 744         case 0x3f:
 745         case 0x45:
 746         case 0x46:
 747           /* Haswell.  */
 748           cpu = "haswell";
 749           break;
 750         case 0x3d:
 751         case 0x4f:
 752         case 0x56:
 753           /* Broadwell.  */
 754           cpu = "broadwell";
 755           break;
 756         case 0x57:
 757           /* Knights Landing.  */
 758           cpu = "knl";
 759           break;
 760         default:
 761           if (arch)
 762             {
 763               /* This is unknown family 0x6 CPU.  */
 764               /* Assume Knights Landing.  */
 765               if (has_avx512f)
 766                 cpu = "knl";
 767               /* Assume Broadwell.  */
 768               else if (has_adx)
 769                 cpu = "broadwell";
 770               else if (has_avx2)
 771                 /* Assume Haswell.  */
 772                 cpu = "haswell";
 773               else if (has_avx)
 774                 /* Assume Sandy Bridge.  */
 775                 cpu = "sandybridge";
 776               else if (has_sse4_2)
 777                 {
 778                   if (has_movbe)
 779                     /* Assume Silvermont.  */
 780                     cpu = "silvermont";
 781                   else
 782                     /* Assume Nehalem.  */
 783                     cpu = "nehalem";
 784                 }
 785               else if (has_ssse3)
 786                 {
 787                   if (has_movbe)
 788                     /* Assume Bonnell.  */
 789                     cpu = "bonnell";
 790                   else
 791                     /* Assume Core 2.  */
 792                     cpu = "core2";
 793                 }
 794               else if (has_longmode)
 795                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 796                    -march=native would be unusable for 64-bit compilations,
 797                    as all the CPUs below are 32-bit only.  */
 798                 cpu = "x86-64";
 799               else if (has_sse3)
 800                 /* It is Core Duo.  */
 801                 cpu = "pentium-m";
 802               else if (has_sse2)
 803                 /* It is Pentium M.  */
 804                 cpu = "pentium-m";
 805               else if (has_sse)
 806                 /* It is Pentium III.  */
 807                 cpu = "pentium3";
 808               else if (has_mmx)
 809                 /* It is Pentium II.  */
 810                 cpu = "pentium2";
 811               else
 812                 /* Default to Pentium Pro.  */
 813                 cpu = "pentiumpro";
 814             }
 815           else
 816             /* For -mtune, we default to -mtune=generic.  */
 817             cpu = "generic";
 818           break;
 819         }
 820       break;
 821     case PROCESSOR_PENTIUM4:
 822       if (has_sse3)
 823         {
 824           if (has_longmode)
 825             cpu = "nocona";
 826           else
 827             cpu = "prescott";
 828         }
 829       else
 830         cpu = "pentium4";
 831       break;
 832     case PROCESSOR_GEODE:
 833       cpu = "geode";
 834       break;
 835     case PROCESSOR_K6:
 836       if (arch && has_3dnow)
 837         cpu = "k6-3";
 838       else
 839         cpu = "k6";
 840       break;
 841     case PROCESSOR_ATHLON:
 842       if (arch && has_sse)
 843         cpu = "athlon-4";
 844       else
 845         cpu = "athlon";
 846       break;
 847     case PROCESSOR_K8:
 848       if (arch && has_sse3)
 849         cpu = "k8-sse3";
 850       else
 851         cpu = "k8";
 852       break;
 853     case PROCESSOR_AMDFAM10:
 854       cpu = "amdfam10";
 855       break;
 856     case PROCESSOR_BDVER1:
 857       cpu = "bdver1";
 858       break;
 859     case PROCESSOR_BDVER2:
 860       cpu = "bdver2";
 861       break;
 862     case PROCESSOR_BDVER3:
 863       cpu = "bdver3";
 864       break;
 865     case PROCESSOR_BDVER4:
 866       cpu = "bdver4";
 867       break;
 868     case PROCESSOR_BTVER1:
 869       cpu = "btver1";
 870       break;
 871     case PROCESSOR_BTVER2:
 872       cpu = "btver2";
 873       break;
 874
 875     default:
 876       /* Use something reasonable.  */
 877       if (arch)
 878         {
 879           if (has_ssse3)
 880             cpu = "core2";
 881           else if (has_sse3)
 882             {
 883               if (has_longmode)
 884                 cpu = "nocona";
 885               else
 886                 cpu = "prescott";
 887             }
 888           else if (has_sse2)
 889             cpu = "pentium4";
 890           else if (has_cmov)
 891             cpu = "pentiumpro";
 892           else if (has_mmx)
 893             cpu = "pentium-mmx";
 894           else if (has_cmpxchg8b)
 895             cpu = "pentium";
 896         }
 897       else
 898         cpu = "generic";
 899     }
 900
 901   if (arch)
 902     {
 903       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 904       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 905       const char *sse = has_sse ? " -msse" : " -mno-sse";
 906       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 907       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 908       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 909       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 910       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 911       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 912       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 913       const char *aes = has_aes ? " -maes" : " -mno-aes";
 914       const char *sha = has_sha ? " -msha" : " -mno-sha";
 915       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 916       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 917       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 918       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 919       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 920       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 921       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 922       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 923       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 924       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 925       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 926       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 927       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 928       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 929       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 930       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 931       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 932       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 933       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 934       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 935       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 936       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 937       const char *adx = has_adx ? " -madx" : " -mno-adx";
 938       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
 939       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
 940       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
 941       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
 942       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
 943       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
 944       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
 945       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
 946       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
 947       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
 948       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
 949       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
 950       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
 951       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
 952       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
 953       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
 954       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
 955       const char *pcommit = has_pcommit ? " -mpcommit" : " -mno-pcommit";
 956
 957       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 958                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
 959                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 960                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 961                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
 962                         fxsr, xsave, xsaveopt, avx512f, avx512er,
 963                         avx512cd, avx512pf, prefetchwt1, clflushopt,
 964                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
 965                         avx512ifma, avx512vbmi, clwb, pcommit, NULL);
 966     }
 967
 968 done:
 969   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 970 }
 971 #else
 972
 973 /* If we are compiling with GCC where %EBX register is fixed, then the
 974    driver will just ignore -march and -mtune "native" target and will leave
 975    to the newly built compiler to generate code for its default target.  */
 976
 977 const char *host_detect_local_cpu (int, const char **)
 978 {
 979   return NULL;
 980 }
 981 #endif /* __GNUC__ */