gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2014 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #ifdef __GNUC__
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414
 415   bool arch;
 416
 417   unsigned int l2sizekb = 0;
 418
 419   if (argc < 1)
 420     return NULL;
 421
 422   arch = !strcmp (argv[0], "arch");
 423
 424   if (!arch && strcmp (argv[0], "tune"))
 425     return NULL;
 426
 427   max_level = __get_cpuid_max (0, &vendor);
 428   if (max_level < 1)
 429     goto done;
 430
 431   __cpuid (1, eax, ebx, ecx, edx);
 432
 433   model = (eax >> 4) & 0x0f;
 434   family = (eax >> 8) & 0x0f;
 435   if (vendor == signature_INTEL_ebx
 436       || vendor == signature_AMD_ebx)
 437     {
 438       unsigned int extended_model, extended_family;
 439
 440       extended_model = (eax >> 12) & 0xf0;
 441       extended_family = (eax >> 20) & 0xff;
 442       if (family == 0x0f)
 443         {
 444           family += extended_family;
 445           model += extended_model;
 446         }
 447       else if (family == 0x06)
 448         model += extended_model;
 449     }
 450
 451   has_sse3 = ecx & bit_SSE3;
 452   has_ssse3 = ecx & bit_SSSE3;
 453   has_sse4_1 = ecx & bit_SSE4_1;
 454   has_sse4_2 = ecx & bit_SSE4_2;
 455   has_avx = ecx & bit_AVX;
 456   has_osxsave = ecx & bit_OSXSAVE;
 457   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 458   has_movbe = ecx & bit_MOVBE;
 459   has_popcnt = ecx & bit_POPCNT;
 460   has_aes = ecx & bit_AES;
 461   has_pclmul = ecx & bit_PCLMUL;
 462   has_fma = ecx & bit_FMA;
 463   has_f16c = ecx & bit_F16C;
 464   has_rdrnd = ecx & bit_RDRND;
 465   has_xsave = ecx & bit_XSAVE;
 466
 467   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 468   has_cmov = edx & bit_CMOV;
 469   has_mmx = edx & bit_MMX;
 470   has_fxsr = edx & bit_FXSAVE;
 471   has_sse = edx & bit_SSE;
 472   has_sse2 = edx & bit_SSE2;
 473
 474   if (max_level >= 7)
 475     {
 476       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 477
 478       has_bmi = ebx & bit_BMI;
 479       has_hle = ebx & bit_HLE;
 480       has_rtm = ebx & bit_RTM;
 481       has_avx2 = ebx & bit_AVX2;
 482       has_bmi2 = ebx & bit_BMI2;
 483       has_fsgsbase = ebx & bit_FSGSBASE;
 484       has_rdseed = ebx & bit_RDSEED;
 485       has_adx = ebx & bit_ADX;
 486       has_avx512f = ebx & bit_AVX512F;
 487       has_avx512er = ebx & bit_AVX512ER;
 488       has_avx512pf = ebx & bit_AVX512PF;
 489       has_avx512cd = ebx & bit_AVX512CD;
 490       has_sha = ebx & bit_SHA;
 491       has_clflushopt = ebx & bit_CLFLUSHOPT;
 492
 493       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 494     }
 495
 496   if (max_level >= 13)
 497     {
 498       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 499
 500       has_xsaveopt = eax & bit_XSAVEOPT;
 501       has_xsavec = eax & bit_XSAVEC;
 502       has_xsaves = eax & bit_XSAVES;
 503     }
 504
 505   /* Check cpuid level of extended features.  */
 506   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 507
 508   if (ext_level > 0x80000000)
 509     {
 510       __cpuid (0x80000001, eax, ebx, ecx, edx);
 511
 512       has_lahf_lm = ecx & bit_LAHF_LM;
 513       has_sse4a = ecx & bit_SSE4a;
 514       has_abm = ecx & bit_ABM;
 515       has_lwp = ecx & bit_LWP;
 516       has_fma4 = ecx & bit_FMA4;
 517       has_xop = ecx & bit_XOP;
 518       has_tbm = ecx & bit_TBM;
 519       has_lzcnt = ecx & bit_LZCNT;
 520       has_prfchw = ecx & bit_PRFCHW;
 521
 522       has_longmode = edx & bit_LM;
 523       has_3dnowp = edx & bit_3DNOWP;
 524       has_3dnow = edx & bit_3DNOW;
 525     }
 526
 527   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 528 #define XCR_XFEATURE_ENABLED_MASK       0x0
 529 #define XSTATE_FP                       0x1
 530 #define XSTATE_SSE                      0x2
 531 #define XSTATE_YMM                      0x4
 532   if (has_osxsave)
 533     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 534          : "=a" (eax), "=d" (edx)
 535          : "c" (XCR_XFEATURE_ENABLED_MASK));
 536
 537   /* Check if SSE and YMM states are supported.  */
 538   if (!has_osxsave
 539       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 540     {
 541       has_avx = 0;
 542       has_avx2 = 0;
 543       has_fma = 0;
 544       has_fma4 = 0;
 545       has_f16c = 0;
 546       has_xop = 0;
 547       has_xsave = 0;
 548       has_xsaveopt = 0;
 549       has_xsaves = 0;
 550       has_xsavec = 0;
 551     }
 552
 553   if (!arch)
 554     {
 555       if (vendor == signature_AMD_ebx
 556           || vendor == signature_CENTAUR_ebx
 557           || vendor == signature_CYRIX_ebx
 558           || vendor == signature_NSC_ebx)
 559         cache = detect_caches_amd (ext_level);
 560       else if (vendor == signature_INTEL_ebx)
 561         {
 562           bool xeon_mp = (family == 15 && model == 6);
 563           cache = detect_caches_intel (xeon_mp, max_level,
 564                                        ext_level, &l2sizekb);
 565         }
 566     }
 567
 568   if (vendor == signature_AMD_ebx)
 569     {
 570       unsigned int name;
 571
 572       /* Detect geode processor by its processor signature.  */
 573       if (ext_level > 0x80000001)
 574         __cpuid (0x80000002, name, ebx, ecx, edx);
 575       else
 576         name = 0;
 577
 578       if (name == signature_NSC_ebx)
 579         processor = PROCESSOR_GEODE;
 580       else if (has_movbe && family == 22)
 581         processor = PROCESSOR_BTVER2;
 582       else if (has_avx2)
 583         processor = PROCESSOR_BDVER4;
 584       else if (has_xsaveopt)
 585         processor = PROCESSOR_BDVER3;
 586       else if (has_bmi)
 587         processor = PROCESSOR_BDVER2;
 588       else if (has_xop)
 589         processor = PROCESSOR_BDVER1;
 590       else if (has_sse4a && has_ssse3)
 591         processor = PROCESSOR_BTVER1;
 592       else if (has_sse4a)
 593         processor = PROCESSOR_AMDFAM10;
 594       else if (has_sse2 || has_longmode)
 595         processor = PROCESSOR_K8;
 596       else if (has_3dnowp && family == 6)
 597         processor = PROCESSOR_ATHLON;
 598       else if (has_mmx)
 599         processor = PROCESSOR_K6;
 600       else
 601         processor = PROCESSOR_PENTIUM;
 602     }
 603   else if (vendor == signature_CENTAUR_ebx)
 604     {
 605       if (arch)
 606         {
 607           switch (family)
 608             {
 609             case 6:
 610               if (model > 9)
 611                 /* Use the default detection procedure.  */
 612                 processor = PROCESSOR_GENERIC;
 613               else if (model == 9)
 614                 cpu = "c3-2";
 615               else if (model >= 6)
 616                 cpu = "c3";
 617               else
 618                 processor = PROCESSOR_GENERIC;
 619               break;
 620             case 5:
 621               if (has_3dnow)
 622                 cpu = "winchip2";
 623               else if (has_mmx)
 624                 cpu = "winchip2-c6";
 625               else
 626                 processor = PROCESSOR_GENERIC;
 627               break;
 628             default:
 629               /* We have no idea.  */
 630               processor = PROCESSOR_GENERIC;
 631             }
 632         }
 633     }
 634   else
 635     {
 636       switch (family)
 637         {
 638         case 4:
 639           processor = PROCESSOR_I486;
 640           break;
 641         case 5:
 642           processor = PROCESSOR_PENTIUM;
 643           break;
 644         case 6:
 645           processor = PROCESSOR_PENTIUMPRO;
 646           break;
 647         case 15:
 648           processor = PROCESSOR_PENTIUM4;
 649           break;
 650         default:
 651           /* We have no idea.  */
 652           processor = PROCESSOR_GENERIC;
 653         }
 654     }
 655
 656   switch (processor)
 657     {
 658     case PROCESSOR_I386:
 659       /* Default.  */
 660       break;
 661     case PROCESSOR_I486:
 662       cpu = "i486";
 663       break;
 664     case PROCESSOR_PENTIUM:
 665       if (arch && has_mmx)
 666         cpu = "pentium-mmx";
 667       else
 668         cpu = "pentium";
 669       break;
 670     case PROCESSOR_PENTIUMPRO:
 671       switch (model)
 672         {
 673         case 0x1c:
 674         case 0x26:
 675           /* Bonnell.  */
 676           cpu = "bonnell";
 677           break;
 678         case 0x37:
 679         case 0x4d:
 680           /* Silvermont.  */
 681           cpu = "silvermont";
 682           break;
 683         case 0x0f:
 684           /* Merom.  */
 685         case 0x17:
 686         case 0x1d:
 687           /* Penryn.  */
 688           cpu = "core2";
 689           break;
 690         case 0x1a:
 691         case 0x1e:
 692         case 0x1f:
 693         case 0x2e:
 694           /* Nehalem.  */
 695           cpu = "nehalem";
 696           break;
 697         case 0x25:
 698         case 0x2c:
 699         case 0x2f:
 700           /* Westmere.  */
 701           cpu = "westmere";
 702           break;
 703         case 0x2a:
 704         case 0x2d:
 705           /* Sandy Bridge.  */
 706           cpu = "sandybridge";
 707           break;
 708         case 0x3a:
 709         case 0x3e:
 710           /* Ivy Bridge.  */
 711           cpu = "ivybridge";
 712           break;
 713         case 0x3c:
 714         case 0x45:
 715         case 0x46:
 716           /* Haswell.  */
 717           cpu = "haswell";
 718           break;
 719         default:
 720           if (arch)
 721             {
 722               /* This is unknown family 0x6 CPU.  */
 723               if (has_adx)
 724                 cpu = "broadwell";
 725               else if (has_avx2)
 726                 /* Assume Haswell.  */
 727                 cpu = "haswell";
 728               else if (has_avx)
 729                 /* Assume Sandy Bridge.  */
 730                 cpu = "sandybridge";
 731               else if (has_sse4_2)
 732                 {
 733                   if (has_movbe)
 734                     /* Assume Silvermont.  */
 735                     cpu = "silvermont";
 736                   else
 737                     /* Assume Nehalem.  */
 738                     cpu = "nehalem";
 739                 }
 740               else if (has_ssse3)
 741                 {
 742                   if (has_movbe)
 743                     /* Assume Bonnell.  */
 744                     cpu = "bonnell";
 745                   else
 746                     /* Assume Core 2.  */
 747                     cpu = "core2";
 748                 }
 749               else if (has_longmode)
 750                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 751                    -march=native would be unusable for 64-bit compilations,
 752                    as all the CPUs below are 32-bit only.  */
 753                 cpu = "x86-64";
 754               else if (has_sse3)
 755                 /* It is Core Duo.  */
 756                 cpu = "pentium-m";
 757               else if (has_sse2)
 758                 /* It is Pentium M.  */
 759                 cpu = "pentium-m";
 760               else if (has_sse)
 761                 /* It is Pentium III.  */
 762                 cpu = "pentium3";
 763               else if (has_mmx)
 764                 /* It is Pentium II.  */
 765                 cpu = "pentium2";
 766               else
 767                 /* Default to Pentium Pro.  */
 768                 cpu = "pentiumpro";
 769             }
 770           else
 771             /* For -mtune, we default to -mtune=generic.  */
 772             cpu = "generic";
 773           break;
 774         }
 775       break;
 776     case PROCESSOR_PENTIUM4:
 777       if (has_sse3)
 778         {
 779           if (has_longmode)
 780             cpu = "nocona";
 781           else
 782             cpu = "prescott";
 783         }
 784       else
 785         cpu = "pentium4";
 786       break;
 787     case PROCESSOR_GEODE:
 788       cpu = "geode";
 789       break;
 790     case PROCESSOR_K6:
 791       if (arch && has_3dnow)
 792         cpu = "k6-3";
 793       else
 794         cpu = "k6";
 795       break;
 796     case PROCESSOR_ATHLON:
 797       if (arch && has_sse)
 798         cpu = "athlon-4";
 799       else
 800         cpu = "athlon";
 801       break;
 802     case PROCESSOR_K8:
 803       if (arch && has_sse3)
 804         cpu = "k8-sse3";
 805       else
 806         cpu = "k8";
 807       break;
 808     case PROCESSOR_AMDFAM10:
 809       cpu = "amdfam10";
 810       break;
 811     case PROCESSOR_BDVER1:
 812       cpu = "bdver1";
 813       break;
 814     case PROCESSOR_BDVER2:
 815       cpu = "bdver2";
 816       break;
 817     case PROCESSOR_BDVER3:
 818       cpu = "bdver3";
 819       break;
 820     case PROCESSOR_BDVER4:
 821       cpu = "bdver4";
 822       break;
 823     case PROCESSOR_BTVER1:
 824       cpu = "btver1";
 825       break;
 826     case PROCESSOR_BTVER2:
 827       cpu = "btver2";
 828       break;
 829
 830     default:
 831       /* Use something reasonable.  */
 832       if (arch)
 833         {
 834           if (has_ssse3)
 835             cpu = "core2";
 836           else if (has_sse3)
 837             {
 838               if (has_longmode)
 839                 cpu = "nocona";
 840               else
 841                 cpu = "prescott";
 842             }
 843           else if (has_sse2)
 844             cpu = "pentium4";
 845           else if (has_cmov)
 846             cpu = "pentiumpro";
 847           else if (has_mmx)
 848             cpu = "pentium-mmx";
 849           else if (has_cmpxchg8b)
 850             cpu = "pentium";
 851         }
 852       else
 853         cpu = "generic";
 854     }
 855
 856   if (arch)
 857     {
 858       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 859       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 860       const char *sse = has_sse ? " -msse" : " -mno-sse";
 861       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 862       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 863       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 864       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 865       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 866       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 867       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 868       const char *aes = has_aes ? " -maes" : " -mno-aes";
 869       const char *sha = has_sha ? " -msha" : " -mno-sha";
 870       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 871       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 872       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 873       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 874       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 875       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 876       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 877       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 878       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 879       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 880       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 881       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 882       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 883       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 884       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 885       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 886       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 887       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 888       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 889       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 890       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 891       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 892       const char *adx = has_adx ? " -madx" : " -mno-adx";
 893       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
 894       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
 895       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
 896       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
 897       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
 898       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
 899       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
 900       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
 901       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
 902       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
 903       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
 904
 905       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 906                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
 907                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 908                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 909                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
 910                         fxsr, xsave, xsaveopt, avx512f, avx512er,
 911                         avx512cd, avx512pf, prefetchwt1, clflushopt,
 912                         xsavec, xsaves, NULL);
 913     }
 914
 915 done:
 916   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 917 }
 918 #else
 919
 920 /* If we aren't compiling with GCC then the driver will just ignore
 921    -march and -mtune "native" target and will leave to the newly
 922    built compiler to generate code for its default target.  */
 923
 924 const char *host_detect_local_cpu (int, const char **)
 925 {
 926   return NULL;
 927 }
 928 #endif /* __GNUC__ */