gcc/config/i386/glm.md

   1 ;; Goldmont(GLM) Scheduling
   2 ;; Copyright (C) 2018-2020 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19 ;;
  20 ;; Goldmont has 3 out-of-order IEC, 2 out-of--order FEC and out-of-order MEC.
  21
  22
  23 (define_automaton "glm")
  24
  25 ;;  EU: Execution Unit
  26 ;;  Goldmont has 3 clusters - IEC, FPC, MEC
  27
  28 ;;  IEC has three execution ports - IEC-0, IEC-1 and IEC-2.
  29 ;;  FPC has two execution ports - FPC-0 and FPC-1.
  30 ;;  MEC has two execution ports - MEC-0 (load) and MEC-1 (store0.
  31 (define_cpu_unit "glm-iec-0,glm-iec-1,glm-iec-2" "glm")
  32 (define_cpu_unit "glm-fec-0,glm-fec-1,glm-load,glm-store" "glm")
  33
  34 ;; Some EUs have duplicated copied and can be accessed via either ports 0, 1 or 2.
  35 (define_reservation "glm-iec-any" "(glm-iec-0 | glm-iec-1 | glm-iec-2)")
  36 (define_reservation "glm-iec-any-load" "(glm-iec-0|glm-iec-1|glm-iec-2)+glm-load")
  37 (define_reservation "glm-iec-any-store" "(glm-iec-0|glm-iec-1|glm-iec-2)+glm-store")
  38 (define_reservation "glm-iec-any-both" "(glm-iec-0 | glm-iec-1 | glm-iec-2) + glm-load + glm-store")
  39 (define_reservation "glm-fec-all" "(glm-fec-0 + glm-fec-1)")
  40 (define_reservation "glm-all" "(glm-iec-0+glm-iec-1+glm-iec-2)+(glm-fec-0+glm-fec-1)+(glm-load+glm-store)")
  41 (define_reservation "glm-int-0" "glm-iec-0")
  42 (define_reservation "glm-int-0-load" "glm-iec-0 + glm-load")
  43 (define_reservation "glm-int-0-both" "glm-iec-0 + glm-load + glm-store")
  44 (define_reservation "glm-int-1" "glm-iec-1")
  45 (define_reservation "glm-int-1-mem" "glm-iec-1 + glm-load")
  46 (define_reservation "glm-int-2" "glm-iec-2")
  47 (define_reservation "glm-int-2-mem" "glm-iec-2 + glm-load")
  48 (define_reservation "glm-fp-0" "glm-fec-0")
  49 (define_reservation "glm-fec-any" "(glm-fec-0 | glm-fec-1)")
  50
  51 ;;; fmul insn can have 4 or 5 cycles latency for scalar and vector types.
  52 (define_reservation "glm-fmul-4c" "glm-fec-0, nothing*3")
  53 (define_reservation "glm-fmul-4c-mem" "glm-fec-0+glm-load, nothing*3")
  54 (define_reservation "glm-fmul-5c" "glm-fec-0, nothing*4")
  55
  56 ;;; fadd has 3 cycles latency.
  57 (define_reservation "glm-fadd-3c" "glm-fec-1, nothing*2")
  58 (define_reservation "glm-fadd-3c-mem" "glm-fec-1+glm-load, nothing*2")
  59
  60 ;;; imul insn has 3 cycles latency for SI operands
  61 (define_reservation "glm-imul-32" "glm-iec-1, nothing*2")
  62 (define_reservation "glm-imul-mem-32"
  63                     "(glm-iec-1+glm-load), nothing*2")
  64 ;;; imul has 5 cycles latency for DI operands with 1/2 tput
  65 (define_reservation "glm-imul-64"
  66                     "glm-iec-1, glm-iec-1, nothing*3")
  67 (define_reservation "glm-imul-mem-64"
  68                     "glm-iec-1+glm-load, glm-iec-1, nothing*3")
  69
  70
  71 (define_insn_reservation  "glm_other" 9
  72   (and (eq_attr "cpu" "glm")
  73        (and (eq_attr "type" "other")
  74             (eq_attr "atom_unit" "!jeu")))
  75   "glm-all*9")
  76
  77 ;; return has type "other" with atom_unit "jeu"
  78 (define_insn_reservation  "glm_other_2" 1
  79   (and (eq_attr "cpu" "glm")
  80        (and (eq_attr "type" "other")
  81             (eq_attr "atom_unit" "jeu")))
  82   "glm-all")
  83
  84 (define_insn_reservation  "glm_multi" 9
  85   (and (eq_attr "cpu" "glm")
  86        (eq_attr "type" "multi"))
  87   "glm-all*9")
  88
  89 ;; Normal alu insns without carry
  90 (define_insn_reservation  "glm_alu" 1
  91   (and (eq_attr "cpu" "glm")
  92        (and (eq_attr "type" "alu")
  93             (and (eq_attr "memory" "none")
  94                  (eq_attr "use_carry" "0"))))
  95   "glm-iec-any")
  96
  97 ;; Normal alu insns without carry, but use MEC.
  98 (define_insn_reservation  "glm_alu_load" 1
  99   (and (eq_attr "cpu" "glm")
 100        (and (eq_attr "type" "alu")
 101             (and (eq_attr "memory" "load")
 102                  (eq_attr "use_carry" "0"))))
 103   "glm-iec-any-load")
 104
 105 (define_insn_reservation  "glm_alu_mem" 1
 106   (and (eq_attr "cpu" "glm")
 107        (and (eq_attr "type" "alu")
 108             (and (eq_attr "memory" "both")
 109                  (eq_attr "use_carry" "0"))))
 110   "glm-iec-any-both")
 111
 112
 113 ;; Alu insn consuming CF, such as add/sbb
 114 (define_insn_reservation  "glm_alu_carry" 2
 115   (and (eq_attr "cpu" "glm")
 116        (and (eq_attr "type" "alu")
 117             (and (eq_attr "memory" "none")
 118                  (eq_attr "use_carry" "1"))))
 119   "glm-int-2, nothing")
 120
 121 ;; Alu insn consuming CF, such as add/sbb
 122 (define_insn_reservation  "glm_alu_carry_mem" 2
 123   (and (eq_attr "cpu" "glm")
 124        (and (eq_attr "type" "alu")
 125             (and (eq_attr "memory" "!none")
 126                 (eq_attr "use_carry" "1"))))
 127   "glm-int-2-mem, nothing")
 128
 129 (define_insn_reservation  "glm_alu1" 1
 130   (and (eq_attr "cpu" "glm")
 131        (and (eq_attr "type" "alu1")
 132             (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))
 133   "glm-int-1")
 134
 135 ;; bsf and bsf insn
 136 (define_insn_reservation  "glm_alu1_1" 10
 137   (and (eq_attr "cpu" "glm")
 138        (and (eq_attr "type" "alu1")
 139             (eq_attr "memory" "none") (eq_attr "prefix_0f" "1")))
 140   "glm-int-1*8,nothing*2")
 141
 142 (define_insn_reservation  "glm_alu1_mem" 1
 143   (and (eq_attr "cpu" "glm")
 144        (and (eq_attr "type" "alu1")
 145             (eq_attr "memory" "!none")))
 146   "glm-int-1-mem")
 147
 148 (define_insn_reservation  "glm_negnot" 1
 149   (and (eq_attr "cpu" "glm")
 150        (and (eq_attr "type" "negnot")
 151             (eq_attr "memory" "none")))
 152   "glm-iec-any")
 153
 154 (define_insn_reservation  "glm_negnot_mem" 1
 155   (and (eq_attr "cpu" "glm")
 156        (and (eq_attr "type" "negnot")
 157             (eq_attr "memory" "!none")))
 158   "glm-iec-any-both")
 159
 160 (define_insn_reservation  "glm_imov" 1
 161   (and (eq_attr "cpu" "glm")
 162        (and (eq_attr "type" "imov")
 163             (eq_attr "memory" "none")))
 164   "glm-iec-any")
 165
 166 (define_insn_reservation  "glm_imov_load" 2
 167   (and (eq_attr "cpu" "glm")
 168        (and (eq_attr "type" "imov")
 169             (eq_attr "memory" "load")))
 170   "glm-iec-any-load,nothing")
 171
 172 (define_insn_reservation  "glm_imov_store" 1
 173   (and (eq_attr "cpu" "glm")
 174        (and (eq_attr "type" "imov")
 175             (eq_attr "memory" "store")))
 176   "glm-iec-any-store")
 177
 178 ;; 16<-16, 32<-32
 179 (define_insn_reservation  "glm_imovx" 1
 180   (and (eq_attr "cpu" "glm")
 181        (and (eq_attr "type" "imovx")
 182             (and (eq_attr "memory" "none")
 183                  (ior (and (match_operand:HI 0 "register_operand")
 184                            (match_operand:HI 1 "general_operand"))
 185                       (and (match_operand:SI 0 "register_operand")
 186                            (match_operand:SI 1 "general_operand"))))))
 187   "glm-iec-any")
 188
 189 ;; 16<-16, 32<-32, mem
 190 (define_insn_reservation  "glm_imovx_mem" 1
 191   (and (eq_attr "cpu" "glm")
 192        (and (eq_attr "type" "imovx")
 193             (and (eq_attr "memory" "!none")
 194                  (ior (and (match_operand:HI 0 "register_operand")
 195                            (match_operand:HI 1 "general_operand"))
 196                       (and (match_operand:SI 0 "register_operand")
 197                            (match_operand:SI 1 "general_operand"))))))
 198   "glm-iec-any-load")
 199
 200
 201 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
 202 (define_insn_reservation  "glm_imovx_2" 1
 203   (and (eq_attr "cpu" "glm")
 204        (and (eq_attr "type" "imovx")
 205             (and (eq_attr "memory" "none")
 206                  (ior (match_operand:QI 0 "register_operand")
 207                       (ior (and (match_operand:SI 0 "register_operand")
 208                                 (not (match_operand:SI 1 "general_operand")))
 209                            (match_operand:DI 0 "register_operand"))))))
 210   "glm-iec-any")
 211
 212 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
 213 (define_insn_reservation  "glm_imovx_2_load" 2
 214   (and (eq_attr "cpu" "glm")
 215        (and (eq_attr "type" "imovx")
 216             (and (eq_attr "memory" "load")
 217                  (ior (match_operand:QI 0 "register_operand")
 218                       (ior (and (match_operand:SI 0 "register_operand")
 219                                 (not (match_operand:SI 1 "general_operand")))
 220                            (match_operand:DI 0 "register_operand"))))))
 221   "glm-iec-any-load,nothing")
 222
 223 (define_insn_reservation  "glm_imovx_2_mem" 1
 224   (and (eq_attr "cpu" "glm")
 225        (and (eq_attr "type" "imovx")
 226             (and (eq_attr "memory" "!none")
 227                  (ior (match_operand:QI 0 "register_operand")
 228                       (ior (and (match_operand:SI 0 "register_operand")
 229                                 (not (match_operand:SI 1 "general_operand")))
 230                            (match_operand:DI 0 "register_operand"))))))
 231   "glm-iec-any-both")
 232
 233
 234 ;; 16<-8
 235 (define_insn_reservation  "glm_imovx_3" 3
 236   (and (eq_attr "cpu" "glm")
 237        (and (eq_attr "type" "imovx")
 238             (and (match_operand:HI 0 "register_operand")
 239                  (match_operand:QI 1 "general_operand"))))
 240   "glm-int-0, nothing*2")
 241
 242 (define_insn_reservation  "glm_lea" 1
 243   (and (eq_attr "cpu" "glm")
 244        (and (eq_attr "type" "lea")
 245             (eq_attr "mode" "!HI")))
 246   "glm-iec-any")
 247
 248 ;; lea 16bit address is complex insn
 249 (define_insn_reservation  "glm_lea_2" 2
 250   (and (eq_attr "cpu" "glm")
 251        (and (eq_attr "type" "lea")
 252             (eq_attr "mode" "HI")))
 253   "glm-all*2")
 254
 255 (define_insn_reservation  "glm_incdec" 1
 256   (and (eq_attr "cpu" "glm")
 257        (and (eq_attr "type" "incdec")
 258             (eq_attr "memory" "none")))
 259   "glm-int-0")
 260
 261 (define_insn_reservation  "glm_incdec_mem" 3
 262   (and (eq_attr "cpu" "glm")
 263        (and (eq_attr "type" "incdec")
 264             (eq_attr "memory" "!none")))
 265   "glm-int-0-both, nothing*2")
 266
 267 ;; simple shift instruction use SHIFT eu, none memory
 268 (define_insn_reservation  "glm_ishift" 1
 269   (and (eq_attr "cpu" "glm")
 270        (and (eq_attr "type" "ishift")
 271             (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
 272   "glm-int-0")
 273
 274 ;; simple shift instruction use SHIFT eu, memory
 275 (define_insn_reservation  "glm_ishift_mem" 2
 276   (and (eq_attr "cpu" "glm")
 277        (and (eq_attr "type" "ishift")
 278             (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
 279   "glm-int-0-both,nothing")
 280
 281 ;; DF shift (prefixed with 0f) is complex insn with latency of 4 cycles
 282 (define_insn_reservation  "glm_ishift_3" 4
 283   (and (eq_attr "cpu" "glm")
 284        (and (eq_attr "type" "ishift")
 285             (eq_attr "prefix_0f" "1")))
 286   "glm-all*4")
 287
 288 (define_insn_reservation  "glm_ishift1" 1
 289   (and (eq_attr "cpu" "glm")
 290        (and (eq_attr "type" "ishift1")
 291             (eq_attr "memory" "none")))
 292   "glm-int-0")
 293
 294 (define_insn_reservation  "glm_ishift1_mem" 2
 295   (and (eq_attr "cpu" "glm")
 296        (and (eq_attr "type" "ishift1")
 297             (eq_attr "memory" "!none")))
 298   "glm-int-0-both,nothing")
 299
 300 (define_insn_reservation  "glm_rotate" 1
 301   (and (eq_attr "cpu" "glm")
 302        (and (eq_attr "type" "rotate")
 303             (eq_attr "memory" "none")))
 304   "glm-int-0")
 305
 306 (define_insn_reservation  "glm_rotate_mem" 2
 307   (and (eq_attr "cpu" "glm")
 308        (and (eq_attr "type" "rotate")
 309             (eq_attr "memory" "!none")))
 310   "glm-int-0-both,nothing")
 311
 312 (define_insn_reservation  "glm_imul" 3
 313   (and (eq_attr "cpu" "glm")
 314        (and (eq_attr "type" "imul")
 315             (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
 316   "glm-imul-32")
 317
 318 (define_insn_reservation  "glm_imul_load" 3
 319   (and (eq_attr "cpu" "glm")
 320        (and (eq_attr "type" "imul")
 321             (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
 322   "glm-imul-mem-32")
 323
 324
 325 ;; latency set to 5 as common 64x64 imul with 1/2 tput
 326 (define_insn_reservation  "glm_imul64" 5
 327   (and (eq_attr "cpu" "glm")
 328        (and (eq_attr "type" "imul")
 329             (and (eq_attr "memory" "none") (eq_attr "mode" "!SI"))))
 330   "glm-imul-64")
 331
 332 (define_insn_reservation  "glm_imul64-load" 5
 333   (and (eq_attr "cpu" "glm")
 334        (and (eq_attr "type" "imul")
 335             (and (eq_attr "memory" "!none") (eq_attr "mode" "!SI"))))
 336   "glm-imul-mem-64")
 337
 338 (define_insn_reservation  "glm_idiv" 25
 339   (and (eq_attr "cpu" "glm")
 340        (eq_attr "type" "idiv"))
 341   "glm-all*16, nothing*9")
 342
 343 (define_insn_reservation  "glm_icmp" 1
 344   (and (eq_attr "cpu" "glm")
 345        (and (eq_attr "type" "icmp")
 346             (eq_attr "memory" "none")))
 347   "glm-int-0")
 348
 349 (define_insn_reservation  "glm_icmp_mem" 2
 350   (and (eq_attr "cpu" "glm")
 351        (and (eq_attr "type" "icmp")
 352             (eq_attr "memory" "!none")))
 353   "glm-int-0-load,nothing")
 354
 355 (define_insn_reservation  "glm_test" 1
 356   (and (eq_attr "cpu" "glm")
 357        (and (eq_attr "type" "test")
 358             (eq_attr "memory" "none")))
 359   "glm-int-0")
 360
 361 (define_insn_reservation  "glm_test_mem" 2
 362   (and (eq_attr "cpu" "glm")
 363        (and (eq_attr "type" "test")
 364             (eq_attr "memory" "!none")))
 365   "glm-int-0-load,nothing")
 366
 367 (define_insn_reservation  "glm_ibr" 1
 368   (and (eq_attr "cpu" "glm")
 369        (and (eq_attr "type" "ibr")
 370             (eq_attr "memory" "!load")))
 371   "glm-int-1")
 372
 373 ;; complex if jump target is from address
 374 (define_insn_reservation  "glm_ibr_2" 2
 375   (and (eq_attr "cpu" "glm")
 376        (and (eq_attr "type" "ibr")
 377             (eq_attr "memory" "load")))
 378   "glm-all*2")
 379
 380 (define_insn_reservation  "glm_setcc" 1
 381   (and (eq_attr "cpu" "glm")
 382        (and (eq_attr "type" "setcc")
 383             (eq_attr "memory" "!store")))
 384   "glm-iec-any")
 385
 386 ;; 2 cycles complex if target is in memory
 387 (define_insn_reservation  "glm_setcc_2" 2
 388   (and (eq_attr "cpu" "glm")
 389        (and (eq_attr "type" "setcc")
 390             (eq_attr "memory" "store")))
 391   "glm-all*2")
 392
 393 (define_insn_reservation  "glm_icmov" 2
 394   (and (eq_attr "cpu" "glm")
 395        (and (eq_attr "type" "icmov")
 396             (eq_attr "memory" "none")))
 397   "glm-iec-any, nothing")
 398
 399 (define_insn_reservation  "glm_icmov_mem" 2
 400   (and (eq_attr "cpu" "glm")
 401        (and (eq_attr "type" "icmov")
 402             (eq_attr "memory" "!none")))
 403   "glm-int-0-load, nothing")
 404
 405 ;; UCODE if segreg, ignored
 406 (define_insn_reservation  "glm_push" 2
 407   (and (eq_attr "cpu" "glm")
 408        (eq_attr "type" "push"))
 409   "(glm-int-1+glm-int-2)*2")
 410
 411 ;; pop r64 is 1 cycle. UCODE if segreg, ignored
 412 (define_insn_reservation  "glm_pop" 1
 413   (and (eq_attr "cpu" "glm")
 414        (and (eq_attr "type" "pop")
 415             (eq_attr "mode" "DI")))
 416   "glm-int-1+glm-int-2")
 417
 418 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
 419 (define_insn_reservation  "glm_pop_2" 2
 420   (and (eq_attr "cpu" "glm")
 421        (and (eq_attr "type" "pop")
 422             (eq_attr "mode" "!DI")))
 423   "(glm-int-1+glm-int-2)*2")
 424
 425 ;; UCODE if segreg, ignored
 426 (define_insn_reservation  "glm_call" 1
 427   (and (eq_attr "cpu" "glm")
 428        (eq_attr "type" "call,callv"))
 429   "(glm-int-0+glm-int-1)")
 430
 431 (define_insn_reservation  "glm_leave" 3
 432   (and (eq_attr "cpu" "glm")
 433        (eq_attr "type" "leave"))
 434   "glm-all*3")
 435
 436 (define_insn_reservation  "glm_str" 3
 437   (and (eq_attr "cpu" "glm")
 438        (eq_attr "type" "str"))
 439   "glm-all*3")
 440
 441 (define_insn_reservation  "glm_sselog" 1
 442   (and (eq_attr "cpu" "glm")
 443        (and (eq_attr "type" "sselog")
 444             (eq_attr "memory" "none")))
 445   "glm-fec-all")
 446
 447 (define_insn_reservation  "glm_sselog_mem" 1
 448   (and (eq_attr "cpu" "glm")
 449        (and (eq_attr "type" "sselog")
 450             (eq_attr "memory" "!none")))
 451   "glm-fec-all+glm-load")
 452
 453 (define_insn_reservation  "glm_sselog1" 1
 454   (and (eq_attr "cpu" "glm")
 455        (and (eq_attr "type" "sselog1")
 456             (eq_attr "memory" "none")))
 457   "glm-fp-0")
 458
 459 (define_insn_reservation  "glm_sselog1_mem" 1
 460   (and (eq_attr "cpu" "glm")
 461        (and (eq_attr "type" "sselog1")
 462             (eq_attr "memory" "!none")))
 463   "glm-fp-0+glm-load")
 464
 465 ;; not pmad, not psad
 466 (define_insn_reservation  "glm_sseiadd" 3
 467   (and (eq_attr "cpu" "glm")
 468        (and (eq_attr "type" "sseiadd")
 469             (and (not (match_operand:V2DI 0 "register_operand"))
 470                  (and (eq_attr "atom_unit" "!simul")
 471                       (eq_attr "atom_unit" "!complex")))))
 472   "glm-fadd-3c")
 473
 474 ;; pmad, psad and 64
 475 (define_insn_reservation  "glm_sseiadd_2" 4
 476   (and (eq_attr "cpu" "glm")
 477        (and (eq_attr "type" "sseiadd")
 478             (and (not (match_operand:V2DI 0 "register_operand"))
 479                  (and (eq_attr "atom_unit" "simul")
 480                       (eq_attr "mode" "DI,TI")))))
 481   "glm-fmul-4c")
 482
 483 ;; if paddq(64 bit op), phadd/phsub
 484 (define_insn_reservation  "glm_sseiadd_3" 5
 485   (and (eq_attr "cpu" "glm")
 486        (and (eq_attr "type" "sseiadd")
 487             (ior (match_operand:V2DI 0 "register_operand")
 488                  (eq_attr "atom_unit" "complex"))))
 489   "glm-fmul-5c")
 490
 491 ;; if immediate op.
 492 (define_insn_reservation  "glm_sseishft" 2
 493   (and (eq_attr "cpu" "glm")
 494        (and (eq_attr "type" "sseishft")
 495             (match_operand 2 "immediate_operand")))
 496   "glm-fp-0, nothing")
 497
 498 (define_insn_reservation  "glm_sseimul" 4
 499   (and (eq_attr "cpu" "glm")
 500        (and (eq_attr "type" "sseimul")
 501             (eq_attr "memory" "none")))
 502   "glm-fmul-4c")
 503
 504 (define_insn_reservation  "glm_sseimul_load" 4
 505   (and (eq_attr "cpu" "glm")
 506        (and (eq_attr "type" "sseimul")
 507             (eq_attr "memory" "!none")))
 508   "glm-fmul-4c-mem")
 509
 510
 511 ;; rcpss or rsqrtss
 512 (define_insn_reservation  "glm_sse" 4
 513   (and (eq_attr "cpu" "glm")
 514        (and (eq_attr "type" "sse")
 515             (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
 516   "glm-fmul-4c")
 517
 518 ;; movshdup, movsldup. Suggest to type sseishft
 519 (define_insn_reservation  "glm_sse_2" 1
 520   (and (eq_attr "cpu" "glm")
 521        (and (eq_attr "type" "sse")
 522             (eq_attr "atom_sse_attr" "movdup")))
 523   "glm-fec-any")
 524
 525 ;; lfence
 526 (define_insn_reservation  "glm_sse_3" 1
 527   (and (eq_attr "cpu" "glm")
 528        (and (eq_attr "type" "sse")
 529             (eq_attr "atom_sse_attr" "lfence")))
 530   "glm-fec-any")
 531
 532 ;; sfence,clflush,mfence, prefetch
 533 (define_insn_reservation  "glm_sse_4" 1
 534   (and (eq_attr "cpu" "glm")
 535        (and (eq_attr "type" "sse")
 536             (ior (eq_attr "atom_sse_attr" "fence")
 537                  (eq_attr "atom_sse_attr" "prefetch"))))
 538   "glm-fp-0")
 539
 540 ;; rcpps, rsqrtss, sqrt, ldmxcsr
 541 (define_insn_reservation  "glm_sse_5" 9
 542   (and (eq_attr "cpu" "glm")
 543        (and (eq_attr "type" "sse")
 544             (ior (ior (eq_attr "atom_sse_attr" "sqrt")
 545                       (eq_attr "atom_sse_attr" "mxcsr"))
 546                  (and (eq_attr "atom_sse_attr" "rcp")
 547                       (eq_attr "mode" "V4SF")))))
 548   "glm-fec-all*6, nothing*3")
 549
 550 ;; xmm->xmm
 551 (define_insn_reservation  "glm_ssemov" 1
 552   (and (eq_attr "cpu" "glm")
 553        (and (eq_attr "type" "ssemov")
 554             (and (match_operand 0 "register_operand" "xy")
 555                  (match_operand 1 "register_operand" "xy"))))
 556   "glm-fec-any")
 557
 558 ;; reg->xmm
 559 (define_insn_reservation  "glm_ssemov_2" 1
 560   (and (eq_attr "cpu" "glm")
 561        (and (eq_attr "type" "ssemov")
 562             (and (match_operand 0 "register_operand" "xy")
 563                  (match_operand 1 "register_operand" "r"))))
 564   "glm-fp-0")
 565
 566 ;; xmm->reg
 567 (define_insn_reservation  "glm_ssemov_3" 3
 568   (and (eq_attr "cpu" "glm")
 569        (and (eq_attr "type" "ssemov")
 570             (and (match_operand 0 "register_operand" "r")
 571                  (match_operand 1 "register_operand" "xy"))))
 572   "glm-fp-0, nothing*2")
 573
 574 ;; mov mem
 575 (define_insn_reservation  "glm_ssemov_load" 2
 576   (and (eq_attr "cpu" "glm")
 577        (and (eq_attr "type" "ssemov")
 578             (eq_attr "memory" "load")))
 579   "glm-fec-any+glm-load,nothing")
 580
 581 (define_insn_reservation  "glm_ssemov_store" 1
 582   (and (eq_attr "cpu" "glm")
 583        (and (eq_attr "type" "ssemov")
 584             (eq_attr "memory" "store")))
 585   "glm-fec-any+glm-store")
 586
 587 ;; no memory simple
 588 (define_insn_reservation  "glm_sseadd" 3
 589   (and (eq_attr "cpu" "glm")
 590        (and (eq_attr "type" "sseadd")
 591             (eq_attr "memory" "none")))
 592   "glm-fadd-3c")
 593
 594 ;; memory simple
 595 (define_insn_reservation  "glm_sseadd_mem" 3
 596   (and (eq_attr "cpu" "glm")
 597        (and (eq_attr "type" "sseadd")
 598             (eq_attr "memory" "!none")))
 599   "glm-fadd-3c-mem")
 600
 601 ;; Except dppd/dpps
 602 (define_insn_reservation  "glm_ssemul" 4
 603   (and (eq_attr "cpu" "glm")
 604        (and (eq_attr "type" "ssemul")
 605             (eq_attr "memory" "none")))
 606   "glm-fmul-4c")
 607
 608 (define_insn_reservation  "glm_ssemul_mem" 4
 609   (and (eq_attr "cpu" "glm")
 610        (and (eq_attr "type" "ssemul")
 611             (eq_attr "memory" "!none")))
 612   "glm-fmul-4c-mem")
 613
 614 (define_insn_reservation  "glm_ssecmp" 1
 615   (and (eq_attr "cpu" "glm")
 616        (eq_attr "type" "ssecmp"))
 617   "glm-fec-any")
 618
 619 (define_insn_reservation  "glm_ssecomi" 1
 620   (and (eq_attr "cpu" "glm")
 621        (eq_attr "type" "ssecomi"))
 622   "glm-fp-0")
 623
 624 ;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
 625 (define_insn_reservation  "glm_ssecvt" 4
 626   (and (eq_attr "cpu" "glm")
 627        (and (eq_attr "type" "ssecvt")
 628             (ior (and (match_operand:V2SI 0 "register_operand")
 629                       (match_operand:V4SF 1 "register_operand"))
 630                  (and (match_operand:V4SF 0 "register_operand")
 631                       (match_operand:V2SI 1 "register_operand")))))
 632   "glm-fp-0, nothing*3")
 633
 634 ;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
 635 (define_insn_reservation  "glm_ssecvt_mem" 4
 636   (and (eq_attr "cpu" "glm")
 637        (and (eq_attr "type" "ssecvt")
 638             (ior (and (match_operand:V2SI 0 "register_operand")
 639                       (match_operand:V4SF 1 "memory_operand"))
 640                  (and (match_operand:V4SF 0 "register_operand")
 641                       (match_operand:V2SI 1 "memory_operand")))))
 642   "glm-fp-0+glm-load, nothing*3")
 643
 644 ;; memory and cvtsi2sd
 645 (define_insn_reservation  "glm_sseicvt" 1
 646   (and (eq_attr "cpu" "glm")
 647        (and (eq_attr "type" "sseicvt")
 648             (and (match_operand:V2DF 0 "register_operand")
 649                  (match_operand:SI 1 "nonimmediate_operand"))))
 650   "glm-fp-0")
 651
 652 ;; otherwise. 8 cycles average for cvtsd2si
 653 (define_insn_reservation  "glm_sseicvt_2" 4
 654   (and (eq_attr "cpu" "glm")
 655        (and (eq_attr "type" "sseicvt")
 656             (not (and (match_operand:V2DF 0 "register_operand")
 657                       (match_operand:SI 1 "memory_operand")))))
 658   "glm-fp-0, nothing*3")
 659
 660 (define_insn_reservation  "glm_ssediv" 13
 661   (and (eq_attr "cpu" "glm")
 662        (eq_attr "type" "ssediv"))
 663   "glm-fec-all*12, nothing")
 664
 665 ;; simple for fmov
 666 (define_insn_reservation  "glm_fmov" 1
 667   (and (eq_attr "cpu" "glm")
 668        (and (eq_attr "type" "fmov")
 669             (eq_attr "memory" "none")))
 670   "glm-fec-any")
 671
 672 ;; simple for fmov
 673 (define_insn_reservation  "glm_fmov_load" 3
 674   (and (eq_attr "cpu" "glm")
 675        (and (eq_attr "type" "fmov")
 676             (eq_attr "memory" "load")))
 677   "glm-fec-any+glm-load, nothing*2")
 678
 679 (define_insn_reservation  "glm_fmov_store" 1
 680   (and (eq_attr "cpu" "glm")
 681        (and (eq_attr "type" "fmov")
 682             (eq_attr "memory" "store")))
 683   "glm-fec-any+glm-store")
 684
 685 ;; Define bypass here
 686
 687 ;; There will be 0 cycle stall from cmp/test to jcc
 688
 689 ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
 690 (define_bypass 2 "glm_icmp, glm_test, glm_alu, glm_alu_carry,
 691                   glm_alu1, glm_negnot, glm_incdec, glm_ishift,
 692                   glm_ishift1, glm_rotate"
 693                  "glm_icmov, glm_alu_carry")
 694
 695 ;; lea to shift source stall is 1 cycle
 696 (define_bypass 2 "glm_lea"
 697                  "glm_ishift, glm_ishift1, glm_rotate"
 698                  "!ix86_dep_by_shift_count")
 699
 700 ;; non-lea to shift count stall is 1 cycle
 701 (define_bypass 2 "glm_alu_carry,
 702                   glm_alu,glm_alu1,glm_negnot,glm_imov,glm_imovx,
 703                   glm_incdec,glm_ishift,glm_ishift1,glm_rotate,
 704                   glm_setcc, glm_icmov, glm_pop, glm_imov_store,
 705                   glm_alu_mem, glm_alu_carry_mem, glm_alu1_mem,
 706                   glm_alu_load, glm_imovx_mem, glm_imovx_2_mem,
 707                   glm_imov_load, glm_icmov_mem, glm_fmov_load, glm_fmov_store"
 708                  "glm_ishift, glm_ishift1, glm_rotate,
 709                   glm_ishift_mem, glm_ishift1_mem,
 710                   glm_rotate_mem"
 711                  "ix86_dep_by_shift_count")