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1 /* Subroutines used for macro/preprocessor support on the ia-32.
2 Copyright (C) 2008-2015 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "target.h"
24 #include "c-family/c-common.h"
25 #include "tm_p.h"
26 #include "c-family/c-pragma.h"
27
28 static bool ix86_pragma_target_parse (tree, tree);
29 static void ix86_target_macros_internal
30 (HOST_WIDE_INT, enum processor_type, enum processor_type, enum fpmath_unit,
31 void (*def_or_undef) (cpp_reader *, const char *));
32
33 \f
34 /* Internal function to either define or undef the appropriate system
35 macros. */
36 static void
37 ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
38 enum processor_type arch,
39 enum processor_type tune,
40 enum fpmath_unit fpmath,
41 void (*def_or_undef) (cpp_reader *,
42 const char *))
43 {
44 /* For some of the k6/pentium varients there weren't separate ISA bits to
45 identify which tune/arch flag was passed, so figure it out here. */
46 size_t arch_len = strlen (ix86_arch_string);
47 size_t tune_len = strlen (ix86_tune_string);
48 int last_arch_char = ix86_arch_string[arch_len - 1];
49 int last_tune_char = ix86_tune_string[tune_len - 1];
50
51 /* Built-ins based on -march=. */
52 switch (arch)
53 {
54 case PROCESSOR_I386:
55 break;
56 case PROCESSOR_I486:
57 def_or_undef (parse_in, "__i486");
58 def_or_undef (parse_in, "__i486__");
59 break;
60 case PROCESSOR_LAKEMONT:
61 /* Intel MCU is based on Intel Pentium CPU. */
62 case PROCESSOR_PENTIUM:
63 def_or_undef (parse_in, "__i586");
64 def_or_undef (parse_in, "__i586__");
65 def_or_undef (parse_in, "__pentium");
66 def_or_undef (parse_in, "__pentium__");
67 if (isa_flag & OPTION_MASK_ISA_MMX)
68 def_or_undef (parse_in, "__pentium_mmx__");
69 break;
70 case PROCESSOR_PENTIUMPRO:
71 def_or_undef (parse_in, "__i686");
72 def_or_undef (parse_in, "__i686__");
73 def_or_undef (parse_in, "__pentiumpro");
74 def_or_undef (parse_in, "__pentiumpro__");
75 break;
76 case PROCESSOR_GEODE:
77 def_or_undef (parse_in, "__geode");
78 def_or_undef (parse_in, "__geode__");
79 break;
80 case PROCESSOR_K6:
81 def_or_undef (parse_in, "__k6");
82 def_or_undef (parse_in, "__k6__");
83 if (last_arch_char == '2')
84 def_or_undef (parse_in, "__k6_2__");
85 else if (last_arch_char == '3')
86 def_or_undef (parse_in, "__k6_3__");
87 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
88 def_or_undef (parse_in, "__k6_3__");
89 break;
90 case PROCESSOR_ATHLON:
91 def_or_undef (parse_in, "__athlon");
92 def_or_undef (parse_in, "__athlon__");
93 if (isa_flag & OPTION_MASK_ISA_SSE)
94 def_or_undef (parse_in, "__athlon_sse__");
95 break;
96 case PROCESSOR_K8:
97 def_or_undef (parse_in, "__k8");
98 def_or_undef (parse_in, "__k8__");
99 break;
100 case PROCESSOR_AMDFAM10:
101 def_or_undef (parse_in, "__amdfam10");
102 def_or_undef (parse_in, "__amdfam10__");
103 break;
104 case PROCESSOR_BDVER1:
105 def_or_undef (parse_in, "__bdver1");
106 def_or_undef (parse_in, "__bdver1__");
107 break;
108 case PROCESSOR_BDVER2:
109 def_or_undef (parse_in, "__bdver2");
110 def_or_undef (parse_in, "__bdver2__");
111 break;
112 case PROCESSOR_BDVER3:
113 def_or_undef (parse_in, "__bdver3");
114 def_or_undef (parse_in, "__bdver3__");
115 break;
116 case PROCESSOR_BDVER4:
117 def_or_undef (parse_in, "__bdver4");
118 def_or_undef (parse_in, "__bdver4__");
119 break;
120 case PROCESSOR_ZNVER1:
121 def_or_undef (parse_in, "__znver1");
122 def_or_undef (parse_in, "__znver1__");
123 break;
124 case PROCESSOR_BTVER1:
125 def_or_undef (parse_in, "__btver1");
126 def_or_undef (parse_in, "__btver1__");
127 break;
128 case PROCESSOR_BTVER2:
129 def_or_undef (parse_in, "__btver2");
130 def_or_undef (parse_in, "__btver2__");
131 break;
132 case PROCESSOR_PENTIUM4:
133 def_or_undef (parse_in, "__pentium4");
134 def_or_undef (parse_in, "__pentium4__");
135 break;
136 case PROCESSOR_NOCONA:
137 def_or_undef (parse_in, "__nocona");
138 def_or_undef (parse_in, "__nocona__");
139 break;
140 case PROCESSOR_CORE2:
141 def_or_undef (parse_in, "__core2");
142 def_or_undef (parse_in, "__core2__");
143 break;
144 case PROCESSOR_NEHALEM:
145 def_or_undef (parse_in, "__corei7");
146 def_or_undef (parse_in, "__corei7__");
147 def_or_undef (parse_in, "__nehalem");
148 def_or_undef (parse_in, "__nehalem__");
149 break;
150 case PROCESSOR_SANDYBRIDGE:
151 def_or_undef (parse_in, "__corei7_avx");
152 def_or_undef (parse_in, "__corei7_avx__");
153 def_or_undef (parse_in, "__sandybridge");
154 def_or_undef (parse_in, "__sandybridge__");
155 break;
156 case PROCESSOR_HASWELL:
157 def_or_undef (parse_in, "__core_avx2");
158 def_or_undef (parse_in, "__core_avx2__");
159 def_or_undef (parse_in, "__haswell");
160 def_or_undef (parse_in, "__haswell__");
161 break;
162 case PROCESSOR_BONNELL:
163 def_or_undef (parse_in, "__atom");
164 def_or_undef (parse_in, "__atom__");
165 def_or_undef (parse_in, "__bonnell");
166 def_or_undef (parse_in, "__bonnell__");
167 break;
168 case PROCESSOR_SILVERMONT:
169 def_or_undef (parse_in, "__slm");
170 def_or_undef (parse_in, "__slm__");
171 def_or_undef (parse_in, "__silvermont");
172 def_or_undef (parse_in, "__silvermont__");
173 break;
174 case PROCESSOR_KNL:
175 def_or_undef (parse_in, "__knl");
176 def_or_undef (parse_in, "__knl__");
177 break;
178 case PROCESSOR_SKYLAKE_AVX512:
179 def_or_undef (parse_in, "__skylake_avx512");
180 def_or_undef (parse_in, "__skylake_avx512__");
181 break;
182 /* use PROCESSOR_max to not set/unset the arch macro. */
183 case PROCESSOR_max:
184 break;
185 case PROCESSOR_INTEL:
186 case PROCESSOR_GENERIC:
187 gcc_unreachable ();
188 }
189
190 /* Built-ins based on -mtune=. */
191 switch (tune)
192 {
193 case PROCESSOR_I386:
194 def_or_undef (parse_in, "__tune_i386__");
195 break;
196 case PROCESSOR_I486:
197 def_or_undef (parse_in, "__tune_i486__");
198 break;
199 case PROCESSOR_PENTIUM:
200 def_or_undef (parse_in, "__tune_i586__");
201 def_or_undef (parse_in, "__tune_pentium__");
202 if (last_tune_char == 'x')
203 def_or_undef (parse_in, "__tune_pentium_mmx__");
204 break;
205 case PROCESSOR_PENTIUMPRO:
206 def_or_undef (parse_in, "__tune_i686__");
207 def_or_undef (parse_in, "__tune_pentiumpro__");
208 switch (last_tune_char)
209 {
210 case '3':
211 def_or_undef (parse_in, "__tune_pentium3__");
212 /* FALLTHRU */
213 case '2':
214 def_or_undef (parse_in, "__tune_pentium2__");
215 break;
216 }
217 break;
218 case PROCESSOR_GEODE:
219 def_or_undef (parse_in, "__tune_geode__");
220 break;
221 case PROCESSOR_K6:
222 def_or_undef (parse_in, "__tune_k6__");
223 if (last_tune_char == '2')
224 def_or_undef (parse_in, "__tune_k6_2__");
225 else if (last_tune_char == '3')
226 def_or_undef (parse_in, "__tune_k6_3__");
227 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
228 def_or_undef (parse_in, "__tune_k6_3__");
229 break;
230 case PROCESSOR_ATHLON:
231 def_or_undef (parse_in, "__tune_athlon__");
232 if (isa_flag & OPTION_MASK_ISA_SSE)
233 def_or_undef (parse_in, "__tune_athlon_sse__");
234 break;
235 case PROCESSOR_K8:
236 def_or_undef (parse_in, "__tune_k8__");
237 break;
238 case PROCESSOR_AMDFAM10:
239 def_or_undef (parse_in, "__tune_amdfam10__");
240 break;
241 case PROCESSOR_BDVER1:
242 def_or_undef (parse_in, "__tune_bdver1__");
243 break;
244 case PROCESSOR_BDVER2:
245 def_or_undef (parse_in, "__tune_bdver2__");
246 break;
247 case PROCESSOR_BDVER3:
248 def_or_undef (parse_in, "__tune_bdver3__");
249 break;
250 case PROCESSOR_BDVER4:
251 def_or_undef (parse_in, "__tune_bdver4__");
252 break;
253 case PROCESSOR_ZNVER1:
254 def_or_undef (parse_in, "__tune_znver1__");
255 break;
256 case PROCESSOR_BTVER1:
257 def_or_undef (parse_in, "__tune_btver1__");
258 break;
259 case PROCESSOR_BTVER2:
260 def_or_undef (parse_in, "__tune_btver2__");
261 break;
262 case PROCESSOR_PENTIUM4:
263 def_or_undef (parse_in, "__tune_pentium4__");
264 break;
265 case PROCESSOR_NOCONA:
266 def_or_undef (parse_in, "__tune_nocona__");
267 break;
268 case PROCESSOR_CORE2:
269 def_or_undef (parse_in, "__tune_core2__");
270 break;
271 case PROCESSOR_NEHALEM:
272 def_or_undef (parse_in, "__tune_corei7__");
273 def_or_undef (parse_in, "__tune_nehalem__");
274 break;
275 case PROCESSOR_SANDYBRIDGE:
276 def_or_undef (parse_in, "__tune_corei7_avx__");
277 def_or_undef (parse_in, "__tune_sandybridge__");
278 break;
279 case PROCESSOR_HASWELL:
280 def_or_undef (parse_in, "__tune_core_avx2__");
281 def_or_undef (parse_in, "__tune_haswell__");
282 break;
283 case PROCESSOR_BONNELL:
284 def_or_undef (parse_in, "__tune_atom__");
285 def_or_undef (parse_in, "__tune_bonnell__");
286 break;
287 case PROCESSOR_SILVERMONT:
288 def_or_undef (parse_in, "__tune_slm__");
289 def_or_undef (parse_in, "__tune_silvermont__");
290 break;
291 case PROCESSOR_KNL:
292 def_or_undef (parse_in, "__tune_knl__");
293 break;
294 case PROCESSOR_SKYLAKE_AVX512:
295 def_or_undef (parse_in, "__tune_skylake_avx512__");
296 break;
297 case PROCESSOR_LAKEMONT:
298 def_or_undef (parse_in, "__tune_lakemont__");
299 break;
300 case PROCESSOR_INTEL:
301 case PROCESSOR_GENERIC:
302 break;
303 /* use PROCESSOR_max to not set/unset the tune macro. */
304 case PROCESSOR_max:
305 break;
306 }
307
308 switch (ix86_cmodel)
309 {
310 case CM_SMALL:
311 case CM_SMALL_PIC:
312 def_or_undef (parse_in, "__code_model_small__");
313 break;
314 case CM_MEDIUM:
315 case CM_MEDIUM_PIC:
316 def_or_undef (parse_in, "__code_model_medium__");
317 break;
318 case CM_LARGE:
319 case CM_LARGE_PIC:
320 def_or_undef (parse_in, "__code_model_large__");
321 break;
322 case CM_32:
323 def_or_undef (parse_in, "__code_model_32__");
324 break;
325 case CM_KERNEL:
326 def_or_undef (parse_in, "__code_model_kernel__");
327 break;
328 default:
329 ;
330 }
331
332 if (isa_flag & OPTION_MASK_ISA_MMX)
333 def_or_undef (parse_in, "__MMX__");
334 if (isa_flag & OPTION_MASK_ISA_3DNOW)
335 def_or_undef (parse_in, "__3dNOW__");
336 if (isa_flag & OPTION_MASK_ISA_3DNOW_A)
337 def_or_undef (parse_in, "__3dNOW_A__");
338 if (isa_flag & OPTION_MASK_ISA_SSE)
339 def_or_undef (parse_in, "__SSE__");
340 if (isa_flag & OPTION_MASK_ISA_SSE2)
341 def_or_undef (parse_in, "__SSE2__");
342 if (isa_flag & OPTION_MASK_ISA_SSE3)
343 def_or_undef (parse_in, "__SSE3__");
344 if (isa_flag & OPTION_MASK_ISA_SSSE3)
345 def_or_undef (parse_in, "__SSSE3__");
346 if (isa_flag & OPTION_MASK_ISA_SSE4_1)
347 def_or_undef (parse_in, "__SSE4_1__");
348 if (isa_flag & OPTION_MASK_ISA_SSE4_2)
349 def_or_undef (parse_in, "__SSE4_2__");
350 if (isa_flag & OPTION_MASK_ISA_AES)
351 def_or_undef (parse_in, "__AES__");
352 if (isa_flag & OPTION_MASK_ISA_SHA)
353 def_or_undef (parse_in, "__SHA__");
354 if (isa_flag & OPTION_MASK_ISA_PCLMUL)
355 def_or_undef (parse_in, "__PCLMUL__");
356 if (isa_flag & OPTION_MASK_ISA_AVX)
357 def_or_undef (parse_in, "__AVX__");
358 if (isa_flag & OPTION_MASK_ISA_AVX2)
359 def_or_undef (parse_in, "__AVX2__");
360 if (isa_flag & OPTION_MASK_ISA_AVX512F)
361 def_or_undef (parse_in, "__AVX512F__");
362 if (isa_flag & OPTION_MASK_ISA_AVX512ER)
363 def_or_undef (parse_in, "__AVX512ER__");
364 if (isa_flag & OPTION_MASK_ISA_AVX512CD)
365 def_or_undef (parse_in, "__AVX512CD__");
366 if (isa_flag & OPTION_MASK_ISA_AVX512PF)
367 def_or_undef (parse_in, "__AVX512PF__");
368 if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
369 def_or_undef (parse_in, "__AVX512DQ__");
370 if (isa_flag & OPTION_MASK_ISA_AVX512BW)
371 def_or_undef (parse_in, "__AVX512BW__");
372 if (isa_flag & OPTION_MASK_ISA_AVX512VL)
373 def_or_undef (parse_in, "__AVX512VL__");
374 if (isa_flag & OPTION_MASK_ISA_AVX512VBMI)
375 def_or_undef (parse_in, "__AVX512VBMI__");
376 if (isa_flag & OPTION_MASK_ISA_AVX512IFMA)
377 def_or_undef (parse_in, "__AVX512IFMA__");
378 if (isa_flag & OPTION_MASK_ISA_FMA)
379 def_or_undef (parse_in, "__FMA__");
380 if (isa_flag & OPTION_MASK_ISA_RTM)
381 def_or_undef (parse_in, "__RTM__");
382 if (isa_flag & OPTION_MASK_ISA_SSE4A)
383 def_or_undef (parse_in, "__SSE4A__");
384 if (isa_flag & OPTION_MASK_ISA_FMA4)
385 def_or_undef (parse_in, "__FMA4__");
386 if (isa_flag & OPTION_MASK_ISA_XOP)
387 def_or_undef (parse_in, "__XOP__");
388 if (isa_flag & OPTION_MASK_ISA_LWP)
389 def_or_undef (parse_in, "__LWP__");
390 if (isa_flag & OPTION_MASK_ISA_ABM)
391 def_or_undef (parse_in, "__ABM__");
392 if (isa_flag & OPTION_MASK_ISA_BMI)
393 def_or_undef (parse_in, "__BMI__");
394 if (isa_flag & OPTION_MASK_ISA_BMI2)
395 def_or_undef (parse_in, "__BMI2__");
396 if (isa_flag & OPTION_MASK_ISA_LZCNT)
397 def_or_undef (parse_in, "__LZCNT__");
398 if (isa_flag & OPTION_MASK_ISA_TBM)
399 def_or_undef (parse_in, "__TBM__");
400 if (isa_flag & OPTION_MASK_ISA_POPCNT)
401 def_or_undef (parse_in, "__POPCNT__");
402 if (isa_flag & OPTION_MASK_ISA_FSGSBASE)
403 def_or_undef (parse_in, "__FSGSBASE__");
404 if (isa_flag & OPTION_MASK_ISA_RDRND)
405 def_or_undef (parse_in, "__RDRND__");
406 if (isa_flag & OPTION_MASK_ISA_F16C)
407 def_or_undef (parse_in, "__F16C__");
408 if (isa_flag & OPTION_MASK_ISA_RDSEED)
409 def_or_undef (parse_in, "__RDSEED__");
410 if (isa_flag & OPTION_MASK_ISA_PRFCHW)
411 def_or_undef (parse_in, "__PRFCHW__");
412 if (isa_flag & OPTION_MASK_ISA_ADX)
413 def_or_undef (parse_in, "__ADX__");
414 if (isa_flag & OPTION_MASK_ISA_FXSR)
415 def_or_undef (parse_in, "__FXSR__");
416 if (isa_flag & OPTION_MASK_ISA_XSAVE)
417 def_or_undef (parse_in, "__XSAVE__");
418 if (isa_flag & OPTION_MASK_ISA_XSAVEOPT)
419 def_or_undef (parse_in, "__XSAVEOPT__");
420 if (isa_flag & OPTION_MASK_ISA_PREFETCHWT1)
421 def_or_undef (parse_in, "__PREFETCHWT1__");
422 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
423 def_or_undef (parse_in, "__SSE_MATH__");
424 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
425 def_or_undef (parse_in, "__SSE2_MATH__");
426 if (isa_flag & OPTION_MASK_ISA_CLFLUSHOPT)
427 def_or_undef (parse_in, "__CLFLUSHOPT__");
428 if (isa_flag & OPTION_MASK_ISA_CLZERO)
429 def_or_undef (parse_in, "__CLZERO__");
430 if (isa_flag & OPTION_MASK_ISA_XSAVEC)
431 def_or_undef (parse_in, "__XSAVEC__");
432 if (isa_flag & OPTION_MASK_ISA_XSAVES)
433 def_or_undef (parse_in, "__XSAVES__");
434 if (isa_flag & OPTION_MASK_ISA_MPX)
435 def_or_undef (parse_in, "__MPX__");
436 if (isa_flag & OPTION_MASK_ISA_PCOMMIT)
437 def_or_undef (parse_in, "__PCOMMIT__");
438 if (isa_flag & OPTION_MASK_ISA_CLWB)
439 def_or_undef (parse_in, "__CLWB__");
440 if (isa_flag & OPTION_MASK_ISA_MWAITX)
441 def_or_undef (parse_in, "__MWAITX__");
442 if (TARGET_IAMCU)
443 {
444 def_or_undef (parse_in, "__iamcu");
445 def_or_undef (parse_in, "__iamcu__");
446 }
447 }
448
449 \f
450 /* Hook to validate the current #pragma GCC target and set the state, and
451 update the macros based on what was changed. If ARGS is NULL, then
452 POP_TARGET is used to reset the options. */
453
454 static bool
455 ix86_pragma_target_parse (tree args, tree pop_target)
456 {
457 tree prev_tree = build_target_option_node (&global_options);
458 tree cur_tree;
459 struct cl_target_option *prev_opt;
460 struct cl_target_option *cur_opt;
461 HOST_WIDE_INT prev_isa;
462 HOST_WIDE_INT cur_isa;
463 HOST_WIDE_INT diff_isa;
464 enum processor_type prev_arch;
465 enum processor_type prev_tune;
466 enum processor_type cur_arch;
467 enum processor_type cur_tune;
468
469 if (! args)
470 {
471 cur_tree = (pop_target ? pop_target : target_option_default_node);
472 cl_target_option_restore (&global_options,
473 TREE_TARGET_OPTION (cur_tree));
474 }
475 else
476 {
477 cur_tree = ix86_valid_target_attribute_tree (args, &global_options,
478 &global_options_set);
479 if (!cur_tree || cur_tree == error_mark_node)
480 {
481 cl_target_option_restore (&global_options,
482 TREE_TARGET_OPTION (prev_tree));
483 return false;
484 }
485 }
486
487 target_option_current_node = cur_tree;
488 ix86_reset_previous_fndecl ();
489
490 /* Figure out the previous/current isa, arch, tune and the differences. */
491 prev_opt = TREE_TARGET_OPTION (prev_tree);
492 cur_opt = TREE_TARGET_OPTION (cur_tree);
493 prev_isa = prev_opt->x_ix86_isa_flags;
494 cur_isa = cur_opt->x_ix86_isa_flags;
495 diff_isa = (prev_isa ^ cur_isa);
496 prev_arch = (enum processor_type) prev_opt->arch;
497 prev_tune = (enum processor_type) prev_opt->tune;
498 cur_arch = (enum processor_type) cur_opt->arch;
499 cur_tune = (enum processor_type) cur_opt->tune;
500
501 /* If the same processor is used for both previous and current options, don't
502 change the macros. */
503 if (cur_arch == prev_arch)
504 cur_arch = prev_arch = PROCESSOR_max;
505
506 if (cur_tune == prev_tune)
507 cur_tune = prev_tune = PROCESSOR_max;
508
509 /* Undef all of the macros for that are no longer current. */
510 ix86_target_macros_internal (prev_isa & diff_isa,
511 prev_arch,
512 prev_tune,
513 (enum fpmath_unit) prev_opt->x_ix86_fpmath,
514 cpp_undef);
515
516 /* For the definitions, ensure all newly defined macros are considered
517 as used for -Wunused-macros. There is no point warning about the
518 compiler predefined macros. */
519 cpp_options *cpp_opts = cpp_get_options (parse_in);
520 unsigned char saved_warn_unused_macros = cpp_opts->warn_unused_macros;
521 cpp_opts->warn_unused_macros = 0;
522
523 /* Define all of the macros for new options that were just turned on. */
524 ix86_target_macros_internal (cur_isa & diff_isa,
525 cur_arch,
526 cur_tune,
527 (enum fpmath_unit) cur_opt->x_ix86_fpmath,
528 cpp_define);
529
530 cpp_opts->warn_unused_macros = saved_warn_unused_macros;
531
532 return true;
533 }
534 \f
535 /* Function to tell the preprocessor about the defines for the current target. */
536
537 void
538 ix86_target_macros (void)
539 {
540 /* 32/64-bit won't change with target specific options, so do the assert and
541 builtin_define_std calls here. */
542 if (TARGET_64BIT)
543 {
544 cpp_assert (parse_in, "cpu=x86_64");
545 cpp_assert (parse_in, "machine=x86_64");
546 cpp_define (parse_in, "__amd64");
547 cpp_define (parse_in, "__amd64__");
548 cpp_define (parse_in, "__x86_64");
549 cpp_define (parse_in, "__x86_64__");
550 if (TARGET_X32)
551 {
552 cpp_define (parse_in, "_ILP32");
553 cpp_define (parse_in, "__ILP32__");
554 }
555 }
556 else
557 {
558 cpp_assert (parse_in, "cpu=i386");
559 cpp_assert (parse_in, "machine=i386");
560 builtin_define_std ("i386");
561 }
562
563 if (!TARGET_80387)
564 cpp_define (parse_in, "_SOFT_FLOAT");
565
566 if (TARGET_LONG_DOUBLE_64)
567 cpp_define (parse_in, "__LONG_DOUBLE_64__");
568
569 if (TARGET_LONG_DOUBLE_128)
570 cpp_define (parse_in, "__LONG_DOUBLE_128__");
571
572 if (TARGET_128BIT_LONG_DOUBLE)
573 cpp_define (parse_in, "__SIZEOF_FLOAT80__=16");
574 else
575 cpp_define (parse_in, "__SIZEOF_FLOAT80__=12");
576
577 cpp_define (parse_in, "__SIZEOF_FLOAT128__=16");
578
579 cpp_define_formatted (parse_in, "__ATOMIC_HLE_ACQUIRE=%d", IX86_HLE_ACQUIRE);
580 cpp_define_formatted (parse_in, "__ATOMIC_HLE_RELEASE=%d", IX86_HLE_RELEASE);
581
582 cpp_define (parse_in, "__GCC_ASM_FLAG_OUTPUTS__");
583
584 ix86_target_macros_internal (ix86_isa_flags,
585 ix86_arch,
586 ix86_tune,
587 ix86_fpmath,
588 cpp_define);
589 }
590
591 \f
592 /* Register target pragmas. We need to add the hook for parsing #pragma GCC
593 option here rather than in i386.c since it will pull in various preprocessor
594 functions, and those are not present in languages like fortran without a
595 preprocessor. */
596
597 void
598 ix86_register_pragmas (void)
599 {
600 /* Update pragma hook to allow parsing #pragma GCC target. */
601 targetm.target_option.pragma_parse = ix86_pragma_target_parse;
602
603 #ifdef REGISTER_SUBTARGET_PRAGMAS
604 REGISTER_SUBTARGET_PRAGMAS ();
605 #endif
606 }