1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 Under Section 7 of GPL version 3, you are granted additional
17 permissions described in the GCC Runtime Library Exception, version
18 3.1, as published by the Free Software Foundation.
20 You should have received a copy of the GNU General Public License and
21 a copy of the GCC Runtime Library Exception along with this program;
22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
23 <http://www.gnu.org/licenses/>. */
25 /* The purpose of this file is to define the characteristics of the i386,
26 independent of assembler syntax or operating system.
28 Three other files build on this one to describe a specific assembler syntax:
29 bsd386.h, att386.h, and sun386.h.
31 The actual tm.h file for a particular system should include
32 this file, and then the file for the appropriate assembler syntax.
34 Many macros that specify assembler syntax are omitted entirely from
35 this file because they really belong in the files for particular
36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
38 that start with ASM_ or end in ASM_OP. */
40 /* Redefines for option macros. */
42 #define TARGET_64BIT TARGET_ISA_64BIT
43 #define TARGET_64BIT_P(x) TARGET_ISA_64BIT_P(x)
44 #define TARGET_MMX TARGET_ISA_MMX
45 #define TARGET_MMX_P(x) TARGET_ISA_MMX_P(x)
46 #define TARGET_3DNOW TARGET_ISA_3DNOW
47 #define TARGET_3DNOW_P(x) TARGET_ISA_3DNOW_P(x)
48 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A
49 #define TARGET_3DNOW_A_P(x) TARGET_ISA_3DNOW_A_P(x)
50 #define TARGET_SSE TARGET_ISA_SSE
51 #define TARGET_SSE_P(x) TARGET_ISA_SSE_P(x)
52 #define TARGET_SSE2 TARGET_ISA_SSE2
53 #define TARGET_SSE2_P(x) TARGET_ISA_SSE2_P(x)
54 #define TARGET_SSE3 TARGET_ISA_SSE3
55 #define TARGET_SSE3_P(x) TARGET_ISA_SSE3_P(x)
56 #define TARGET_SSSE3 TARGET_ISA_SSSE3
57 #define TARGET_SSSE3_P(x) TARGET_ISA_SSSE3_P(x)
58 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1
59 #define TARGET_SSE4_1_P(x) TARGET_ISA_SSE4_1_P(x)
60 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2
61 #define TARGET_SSE4_2_P(x) TARGET_ISA_SSE4_2_P(x)
62 #define TARGET_AVX TARGET_ISA_AVX
63 #define TARGET_AVX_P(x) TARGET_ISA_AVX_P(x)
64 #define TARGET_AVX2 TARGET_ISA_AVX2
65 #define TARGET_AVX2_P(x) TARGET_ISA_AVX2_P(x)
66 #define TARGET_AVX512F TARGET_ISA_AVX512F
67 #define TARGET_AVX512F_P(x) TARGET_ISA_AVX512F_P(x)
68 #define TARGET_AVX512PF TARGET_ISA_AVX512PF
69 #define TARGET_AVX512PF_P(x) TARGET_ISA_AVX512PF_P(x)
70 #define TARGET_AVX512ER TARGET_ISA_AVX512ER
71 #define TARGET_AVX512ER_P(x) TARGET_ISA_AVX512ER_P(x)
72 #define TARGET_AVX512CD TARGET_ISA_AVX512CD
73 #define TARGET_AVX512CD_P(x) TARGET_ISA_AVX512CD_P(x)
74 #define TARGET_FMA TARGET_ISA_FMA
75 #define TARGET_FMA_P(x) TARGET_ISA_FMA_P(x)
76 #define TARGET_SSE4A TARGET_ISA_SSE4A
77 #define TARGET_SSE4A_P(x) TARGET_ISA_SSE4A_P(x)
78 #define TARGET_FMA4 TARGET_ISA_FMA4
79 #define TARGET_FMA4_P(x) TARGET_ISA_FMA4_P(x)
80 #define TARGET_XOP TARGET_ISA_XOP
81 #define TARGET_XOP_P(x) TARGET_ISA_XOP_P(x)
82 #define TARGET_LWP TARGET_ISA_LWP
83 #define TARGET_LWP_P(x) TARGET_ISA_LWP_P(x)
84 #define TARGET_ROUND TARGET_ISA_ROUND
85 #define TARGET_ABM TARGET_ISA_ABM
86 #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x)
87 #define TARGET_BMI TARGET_ISA_BMI
88 #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x)
89 #define TARGET_BMI2 TARGET_ISA_BMI2
90 #define TARGET_BMI2_P(x) TARGET_ISA_BMI2_P(x)
91 #define TARGET_LZCNT TARGET_ISA_LZCNT
92 #define TARGET_LZCNT_P(x) TARGET_ISA_LZCNT_P(x)
93 #define TARGET_TBM TARGET_ISA_TBM
94 #define TARGET_TBM_P(x) TARGET_ISA_TBM_P(x)
95 #define TARGET_POPCNT TARGET_ISA_POPCNT
96 #define TARGET_POPCNT_P(x) TARGET_ISA_POPCNT_P(x)
97 #define TARGET_SAHF TARGET_ISA_SAHF
98 #define TARGET_SAHF_P(x) TARGET_ISA_SAHF_P(x)
99 #define TARGET_MOVBE TARGET_ISA_MOVBE
100 #define TARGET_MOVBE_P(x) TARGET_ISA_MOVBE_P(x)
101 #define TARGET_CRC32 TARGET_ISA_CRC32
102 #define TARGET_CRC32_P(x) TARGET_ISA_CRC32_P(x)
103 #define TARGET_AES TARGET_ISA_AES
104 #define TARGET_AES_P(x) TARGET_ISA_AES_P(x)
105 #define TARGET_SHA TARGET_ISA_SHA
106 #define TARGET_SHA_P(x) TARGET_ISA_SHA_P(x)
107 #define TARGET_PCLMUL TARGET_ISA_PCLMUL
108 #define TARGET_PCLMUL_P(x) TARGET_ISA_PCLMUL_P(x)
109 #define TARGET_CMPXCHG16B TARGET_ISA_CX16
110 #define TARGET_CMPXCHG16B_P(x) TARGET_ISA_CX16_P(x)
111 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE
112 #define TARGET_FSGSBASE_P(x) TARGET_ISA_FSGSBASE_P(x)
113 #define TARGET_RDRND TARGET_ISA_RDRND
114 #define TARGET_RDRND_P(x) TARGET_ISA_RDRND_P(x)
115 #define TARGET_F16C TARGET_ISA_F16C
116 #define TARGET_F16C_P(x) TARGET_ISA_F16C_P(x)
117 #define TARGET_RTM TARGET_ISA_RTM
118 #define TARGET_RTM_P(x) TARGET_ISA_RTM_P(x)
119 #define TARGET_HLE TARGET_ISA_HLE
120 #define TARGET_HLE_P(x) TARGET_ISA_HLE_P(x)
121 #define TARGET_RDSEED TARGET_ISA_RDSEED
122 #define TARGET_RDSEED_P(x) TARGET_ISA_RDSEED_P(x)
123 #define TARGET_PRFCHW TARGET_ISA_PRFCHW
124 #define TARGET_PRFCHW_P(x) TARGET_ISA_PRFCHW_P(x)
125 #define TARGET_ADX TARGET_ISA_ADX
126 #define TARGET_ADX_P(x) TARGET_ISA_ADX_P(x)
127 #define TARGET_FXSR TARGET_ISA_FXSR
128 #define TARGET_FXSR_P(x) TARGET_ISA_FXSR_P(x)
129 #define TARGET_XSAVE TARGET_ISA_XSAVE
130 #define TARGET_XSAVE_P(x) TARGET_ISA_XSAVE_P(x)
131 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT
132 #define TARGET_XSAVEOPT_P(x) TARGET_ISA_XSAVEOPT_P(x)
134 #define TARGET_LP64 TARGET_ABI_64
135 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x)
136 #define TARGET_X32 TARGET_ABI_X32
137 #define TARGET_X32_P(x) TARGET_ABI_X32_P(x)
139 /* SSE4.1 defines round instructions */
140 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1
141 #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
143 #include "config/vxworks-dummy.h"
145 #include "config/i386/i386-opts.h"
147 #define MAX_STRINGOP_ALGS 4
149 /* Specify what algorithm to use for stringops on known size.
150 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
151 known at compile time or estimated via feedback, the SIZE array
152 is walked in order until MAX is greater then the estimate (or -1
153 means infinity). Corresponding ALG is used then.
154 When NOALIGN is true the code guaranting the alignment of the memory
157 For example initializer:
158 {{256, loop}, {-1, rep_prefix_4_byte}}
159 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
160 be used otherwise. */
163 const enum stringop_alg unknown_size
;
164 const struct stringop_strategy
{
166 const enum stringop_alg alg
;
168 } size
[MAX_STRINGOP_ALGS
];
171 /* Define the specific costs for a given cpu */
173 struct processor_costs
{
174 const int add
; /* cost of an add instruction */
175 const int lea
; /* cost of a lea instruction */
176 const int shift_var
; /* variable shift costs */
177 const int shift_const
; /* constant shift costs */
178 const int mult_init
[5]; /* cost of starting a multiply
179 in QImode, HImode, SImode, DImode, TImode*/
180 const int mult_bit
; /* cost of multiply per each bit set */
181 const int divide
[5]; /* cost of a divide/mod
182 in QImode, HImode, SImode, DImode, TImode*/
183 int movsx
; /* The cost of movsx operation. */
184 int movzx
; /* The cost of movzx operation. */
185 const int large_insn
; /* insns larger than this cost more */
186 const int move_ratio
; /* The threshold of number of scalar
187 memory-to-memory move insns. */
188 const int movzbl_load
; /* cost of loading using movzbl */
189 const int int_load
[3]; /* cost of loading integer registers
190 in QImode, HImode and SImode relative
191 to reg-reg move (2). */
192 const int int_store
[3]; /* cost of storing integer register
193 in QImode, HImode and SImode */
194 const int fp_move
; /* cost of reg,reg fld/fst */
195 const int fp_load
[3]; /* cost of loading FP register
196 in SFmode, DFmode and XFmode */
197 const int fp_store
[3]; /* cost of storing FP register
198 in SFmode, DFmode and XFmode */
199 const int mmx_move
; /* cost of moving MMX register. */
200 const int mmx_load
[2]; /* cost of loading MMX register
201 in SImode and DImode */
202 const int mmx_store
[2]; /* cost of storing MMX register
203 in SImode and DImode */
204 const int sse_move
; /* cost of moving SSE register. */
205 const int sse_load
[3]; /* cost of loading SSE register
206 in SImode, DImode and TImode*/
207 const int sse_store
[3]; /* cost of storing SSE register
208 in SImode, DImode and TImode*/
209 const int mmxsse_to_integer
; /* cost of moving mmxsse register to
210 integer and vice versa. */
211 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
212 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
213 const int prefetch_block
; /* bytes moved to cache for prefetch. */
214 const int simultaneous_prefetches
; /* number of parallel prefetch
216 const int branch_cost
; /* Default value for BRANCH_COST. */
217 const int fadd
; /* cost of FADD and FSUB instructions. */
218 const int fmul
; /* cost of FMUL instruction. */
219 const int fdiv
; /* cost of FDIV instruction. */
220 const int fabs
; /* cost of FABS instruction. */
221 const int fchs
; /* cost of FCHS instruction. */
222 const int fsqrt
; /* cost of FSQRT instruction. */
223 /* Specify what algorithm
224 to use for stringops on unknown size. */
225 struct stringop_algs
*memcpy
, *memset
;
226 const int scalar_stmt_cost
; /* Cost of any scalar operation, excluding
228 const int scalar_load_cost
; /* Cost of scalar load. */
229 const int scalar_store_cost
; /* Cost of scalar store. */
230 const int vec_stmt_cost
; /* Cost of any vector operation, excluding
231 load, store, vector-to-scalar and
232 scalar-to-vector operation. */
233 const int vec_to_scalar_cost
; /* Cost of vect-to-scalar operation. */
234 const int scalar_to_vec_cost
; /* Cost of scalar-to-vector operation. */
235 const int vec_align_load_cost
; /* Cost of aligned vector load. */
236 const int vec_unalign_load_cost
; /* Cost of unaligned vector load. */
237 const int vec_store_cost
; /* Cost of vector store. */
238 const int cond_taken_branch_cost
; /* Cost of taken branch for vectorizer
240 const int cond_not_taken_branch_cost
;/* Cost of not taken branch for
241 vectorizer cost model. */
244 extern const struct processor_costs
*ix86_cost
;
245 extern const struct processor_costs ix86_size_cost
;
247 #define ix86_cur_cost() \
248 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
250 /* Macros used in the machine description to test the flags. */
252 /* configure can arrange to change it. */
254 #ifndef TARGET_CPU_DEFAULT
255 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC
258 #ifndef TARGET_FPMATH_DEFAULT
259 #define TARGET_FPMATH_DEFAULT \
260 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
263 #ifndef TARGET_FPMATH_DEFAULT_P
264 #define TARGET_FPMATH_DEFAULT_P(x) \
265 (TARGET_64BIT_P(x) && TARGET_SSE_P(x) ? FPMATH_SSE : FPMATH_387)
268 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
269 #define TARGET_FLOAT_RETURNS_IN_80387_P(x) TARGET_FLOAT_RETURNS_P(x)
271 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
272 compile-time constant. */
276 #define TARGET_64BIT 1
278 #define TARGET_64BIT 0
281 #ifndef TARGET_BI_ARCH
283 #if TARGET_64BIT_DEFAULT
284 #define TARGET_64BIT 1
286 #define TARGET_64BIT 0
291 #define HAS_LONG_COND_BRANCH 1
292 #define HAS_LONG_UNCOND_BRANCH 1
294 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
295 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
296 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
297 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
298 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
299 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
300 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
301 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
302 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
303 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
304 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
305 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
306 #define TARGET_NEHALEM (ix86_tune == PROCESSOR_NEHALEM)
307 #define TARGET_SANDYBRIDGE (ix86_tune == PROCESSOR_SANDYBRIDGE)
308 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
309 #define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
310 #define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
311 #define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
312 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
313 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
314 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
315 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3)
316 #define TARGET_BDVER4 (ix86_tune == PROCESSOR_BDVER4)
317 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
318 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2)
320 /* Feature tests against the various tunings. */
321 enum ix86_tune_indices
{
323 #define DEF_TUNE(tune, name, selector) tune,
324 #include "x86-tune.def"
329 extern unsigned char ix86_tune_features
[X86_TUNE_LAST
];
331 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
332 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
333 #define TARGET_ZERO_EXTEND_WITH_AND \
334 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
335 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
336 #define TARGET_BRANCH_PREDICTION_HINTS \
337 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
338 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
339 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
340 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
341 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
342 #define TARGET_PARTIAL_FLAG_REG_STALL \
343 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
344 #define TARGET_LCP_STALL \
345 ix86_tune_features[X86_TUNE_LCP_STALL]
346 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
347 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
348 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
349 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
350 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
351 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
352 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
353 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
354 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
355 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
356 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
357 #define TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES \
358 ix86_tune_features[X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES]
359 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
360 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
361 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
362 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
363 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP]
364 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP]
365 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH]
366 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH]
367 #define TARGET_INTEGER_DFMODE_MOVES \
368 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
369 #define TARGET_PARTIAL_REG_DEPENDENCY \
370 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
371 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
372 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
373 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \
374 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
375 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \
376 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
377 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \
378 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
379 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
380 #define TARGET_SSE_TYPELESS_STORES \
381 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
382 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
383 #define TARGET_MEMORY_MISMATCH_STALL \
384 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
385 #define TARGET_PROLOGUE_USING_MOVE \
386 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
387 #define TARGET_EPILOGUE_USING_MOVE \
388 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
389 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
390 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
391 #define TARGET_INTER_UNIT_MOVES_TO_VEC \
392 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC]
393 #define TARGET_INTER_UNIT_MOVES_FROM_VEC \
394 ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_FROM_VEC]
395 #define TARGET_INTER_UNIT_CONVERSIONS \
396 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
397 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
398 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
399 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
400 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
401 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
402 #define TARGET_PAD_SHORT_FUNCTION \
403 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION]
404 #define TARGET_EXT_80387_CONSTANTS \
405 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
406 #define TARGET_AVOID_VECTOR_DECODE \
407 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
408 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
409 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
410 #define TARGET_SLOW_IMUL_IMM32_MEM \
411 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
412 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
413 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
414 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
415 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
416 #define TARGET_USE_VECTOR_FP_CONVERTS \
417 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
418 #define TARGET_USE_VECTOR_CONVERTS \
419 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
420 #define TARGET_FUSE_CMP_AND_BRANCH_32 \
421 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32]
422 #define TARGET_FUSE_CMP_AND_BRANCH_64 \
423 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_64]
424 #define TARGET_FUSE_CMP_AND_BRANCH \
425 (TARGET_64BIT ? TARGET_FUSE_CMP_AND_BRANCH_64 \
426 : TARGET_FUSE_CMP_AND_BRANCH_32)
427 #define TARGET_FUSE_CMP_AND_BRANCH_SOFLAGS \
428 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS]
429 #define TARGET_FUSE_ALU_AND_BRANCH \
430 ix86_tune_features[X86_TUNE_FUSE_ALU_AND_BRANCH]
431 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
432 #define TARGET_VECTORIZE_DOUBLE \
433 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
434 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
435 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
436 #define TARGET_AVX128_OPTIMAL \
437 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
438 #define TARGET_REASSOC_INT_TO_PARALLEL \
439 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL]
440 #define TARGET_REASSOC_FP_TO_PARALLEL \
441 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL]
442 #define TARGET_GENERAL_REGS_SSE_SPILL \
443 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL]
444 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
445 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
446 #define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
447 ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
448 #define TARGET_ADJUST_UNROLL \
449 ix86_tune_features[X86_TUNE_ADJUST_UNROLL]
451 /* Feature tests against the various architecture variations. */
452 enum ix86_arch_indices
{
462 extern unsigned char ix86_arch_features
[X86_ARCH_LAST
];
464 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
465 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
466 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
467 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
468 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
470 /* For sane SSE instruction set generation we need fcomi instruction.
471 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
472 expands to a sequence that includes conditional move. */
473 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
475 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
477 extern unsigned char x86_prefetch_sse
;
478 #define TARGET_PREFETCH_SSE x86_prefetch_sse
480 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
482 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
483 #define TARGET_MIX_SSE_I387 \
484 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
486 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
487 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
488 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
489 #define TARGET_SUN_TLS 0
491 #ifndef TARGET_64BIT_DEFAULT
492 #define TARGET_64BIT_DEFAULT 0
494 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
495 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
498 #define TARGET_SSP_GLOBAL_GUARD (ix86_stack_protector_guard == SSP_GLOBAL)
499 #define TARGET_SSP_TLS_GUARD (ix86_stack_protector_guard == SSP_TLS)
501 /* Fence to use after loop using storent. */
503 extern tree x86_mfence
;
504 #define FENCE_FOLLOWING_MOVNT x86_mfence
506 /* Once GDB has been enhanced to deal with functions without frame
507 pointers, we can change this to allow for elimination of
508 the frame pointer in leaf functions. */
509 #define TARGET_DEFAULT 0
511 /* Extra bits to force. */
512 #define TARGET_SUBTARGET_DEFAULT 0
513 #define TARGET_SUBTARGET_ISA_DEFAULT 0
515 /* Extra bits to force on w/ 32-bit mode. */
516 #define TARGET_SUBTARGET32_DEFAULT 0
517 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
519 /* Extra bits to force on w/ 64-bit mode. */
520 #define TARGET_SUBTARGET64_DEFAULT 0
521 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
523 /* Replace MACH-O, ifdefs by in-line tests, where possible.
524 (a) Macros defined in config/i386/darwin.h */
525 #define TARGET_MACHO 0
526 #define TARGET_MACHO_BRANCH_ISLANDS 0
527 #define MACHOPIC_ATT_STUB 0
528 /* (b) Macros defined in config/darwin.h */
529 #define MACHO_DYNAMIC_NO_PIC_P 0
530 #define MACHOPIC_INDIRECT 0
531 #define MACHOPIC_PURE 0
534 #define TARGET_RDOS 0
536 /* For the Windows 64-bit ABI. */
537 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
539 /* For the Windows 32-bit ABI. */
540 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
542 /* This is re-defined by cygming.h. */
545 /* This is re-defined by cygming.h. */
546 #define TARGET_PECOFF 0
548 /* The default abi used by target. */
549 #define DEFAULT_ABI SYSV_ABI
551 /* The default TLS segment register used by target. */
552 #define DEFAULT_TLS_SEG_REG (TARGET_64BIT ? SEG_FS : SEG_GS)
554 /* Subtargets may reset this to 1 in order to enable 96-bit long double
555 with the rounding mode forced to 53 bits. */
556 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
558 /* -march=native handling only makes sense with compiler running on
559 an x86 or x86_64 chip. If changing this condition, also change
560 the condition in driver-i386.c. */
561 #if defined(__i386__) || defined(__x86_64__)
562 /* In driver-i386.c. */
563 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
564 #define EXTRA_SPEC_FUNCTIONS \
565 { "local_cpu_detect", host_detect_local_cpu },
566 #define HAVE_LOCAL_CPU_DETECT
569 #if TARGET_64BIT_DEFAULT
570 #define OPT_ARCH64 "!m32"
571 #define OPT_ARCH32 "m32"
573 #define OPT_ARCH64 "m64|mx32"
574 #define OPT_ARCH32 "m64|mx32:;"
577 /* Support for configure-time defaults of some command line options.
578 The order here is important so that -march doesn't squash the
579 tune or cpu values. */
580 #define OPTION_DEFAULT_SPECS \
581 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
582 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
583 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
584 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
585 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
586 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
587 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
588 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
589 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
591 /* Specs for the compiler proper */
594 #define CC1_CPU_SPEC_1 ""
596 #ifndef HAVE_LOCAL_CPU_DETECT
597 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
599 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
600 "%{march=native:%>march=native %:local_cpu_detect(arch) \
601 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \
602 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}"
606 /* Target CPU builtins. */
607 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
609 /* Target Pragmas. */
610 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
613 #define CC1_SPEC "%(cc1_cpu) "
616 /* This macro defines names of additional specifications to put in the
617 specs that can be used in various specifications like CC1_SPEC. Its
618 definition is an initializer with a subgrouping for each command option.
620 Each subgrouping contains a string constant, that defines the
621 specification name, and a string constant that used by the GCC driver
624 Do not define this macro if it does not need to do anything. */
626 #ifndef SUBTARGET_EXTRA_SPECS
627 #define SUBTARGET_EXTRA_SPECS
630 #define EXTRA_SPECS \
631 { "cc1_cpu", CC1_CPU_SPEC }, \
632 SUBTARGET_EXTRA_SPECS
635 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
636 FPU, assume that the fpcw is set to extended precision; when using
637 only SSE, rounding is correct; when using both SSE and the FPU,
638 the rounding precision is indeterminate, since either may be chosen
639 apparently at random. */
640 #define TARGET_FLT_EVAL_METHOD \
641 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
643 /* Whether to allow x87 floating-point arithmetic on MODE (one of
644 SFmode, DFmode and XFmode) in the current excess precision
646 #define X87_ENABLE_ARITH(MODE) \
647 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
649 /* Likewise, whether to allow direct conversions from integer mode
650 IMODE (HImode, SImode or DImode) to MODE. */
651 #define X87_ENABLE_FLOAT(MODE, IMODE) \
652 (flag_excess_precision == EXCESS_PRECISION_FAST \
653 || (MODE) == XFmode \
654 || ((MODE) == DFmode && (IMODE) == SImode) \
655 || (IMODE) == HImode)
657 /* target machine storage layout */
659 #define SHORT_TYPE_SIZE 16
660 #define INT_TYPE_SIZE 32
661 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
662 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD)
663 #define LONG_LONG_TYPE_SIZE 64
664 #define FLOAT_TYPE_SIZE 32
665 #define DOUBLE_TYPE_SIZE 64
666 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 80)
668 /* Define this to set long double type size to use in libgcc2.c, which can
669 not depend on target_flags. */
670 #ifdef __LONG_DOUBLE_64__
671 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
673 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
676 #define WIDEST_HARDWARE_FP_SIZE 80
678 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
679 #define MAX_BITS_PER_WORD 64
681 #define MAX_BITS_PER_WORD 32
684 /* Define this if most significant byte of a word is the lowest numbered. */
685 /* That is true on the 80386. */
687 #define BITS_BIG_ENDIAN 0
689 /* Define this if most significant byte of a word is the lowest numbered. */
690 /* That is not true on the 80386. */
691 #define BYTES_BIG_ENDIAN 0
693 /* Define this if most significant word of a multiword number is the lowest
695 /* Not true for 80386 */
696 #define WORDS_BIG_ENDIAN 0
698 /* Width of a word, in units (bytes). */
699 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
702 #define MIN_UNITS_PER_WORD 4
705 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
706 #define PARM_BOUNDARY BITS_PER_WORD
708 /* Boundary (in *bits*) on which stack pointer should be aligned. */
709 #define STACK_BOUNDARY \
710 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
712 /* Stack boundary of the main function guaranteed by OS. */
713 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
715 /* Minimum stack boundary. */
716 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32)
718 /* Boundary (in *bits*) on which the stack pointer prefers to be
719 aligned; the compiler cannot rely on having this alignment. */
720 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
722 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
723 both 32bit and 64bit, to support codes that need 128 bit stack
724 alignment for SSE instructions, but can't realign the stack. */
725 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
727 /* 1 if -mstackrealign should be turned on by default. It will
728 generate an alternate prologue and epilogue that realigns the
729 runtime stack if nessary. This supports mixing codes that keep a
730 4-byte aligned stack, as specified by i386 psABI, with codes that
731 need a 16-byte aligned stack, as required by SSE instructions. */
732 #define STACK_REALIGN_DEFAULT 0
734 /* Boundary (in *bits*) on which the incoming stack is aligned. */
735 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
737 /* According to Windows x64 software convention, the maximum stack allocatable
738 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of
739 instructions allowed to adjust the stack pointer in the epilog, forcing the
740 use of frame pointer for frames larger than 2 GB. This theorical limit
741 is reduced by 256, an over-estimated upper bound for the stack use by the
743 We define only one threshold for both the prolog and the epilog. When the
744 frame size is larger than this threshold, we allocate the area to save SSE
745 regs, then save them, and then allocate the remaining. There is no SEH
746 unwind info for this later allocation. */
747 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256)
749 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
750 mandatory for the 64-bit ABI, and may or may not be true for other
751 operating systems. */
752 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
754 /* Minimum allocation boundary for the code of a function. */
755 #define FUNCTION_BOUNDARY 8
757 /* C++ stores the virtual bit in the lowest bit of function pointers. */
758 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
760 /* Minimum size in bits of the largest boundary to which any
761 and all fundamental data types supported by the hardware
762 might need to be aligned. No data type wants to be aligned
765 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
766 and Pentium Pro XFmode values at 128 bit boundaries. */
768 #define BIGGEST_ALIGNMENT \
769 (TARGET_AVX512F ? 512 : (TARGET_AVX ? 256 : 128))
771 /* Maximum stack alignment. */
772 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
774 /* Alignment value for attribute ((aligned)). It is a constant since
775 it is the part of the ABI. We shouldn't change it with -mavx. */
776 #define ATTRIBUTE_ALIGNED_VALUE 128
778 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
779 #define ALIGN_MODE_128(MODE) \
780 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
782 /* The published ABIs say that doubles should be aligned on word
783 boundaries, so lower the alignment for structure fields unless
784 -malign-double is set. */
786 /* ??? Blah -- this macro is used directly by libobjc. Since it
787 supports no vector modes, cut out the complexity and fall back
788 on BIGGEST_FIELD_ALIGNMENT. */
789 #ifdef IN_TARGET_LIBS
791 #define BIGGEST_FIELD_ALIGNMENT 128
793 #define BIGGEST_FIELD_ALIGNMENT 32
796 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
797 x86_field_alignment (FIELD, COMPUTED)
800 /* If defined, a C expression to compute the alignment given to a
801 constant that is being placed in memory. EXP is the constant
802 and ALIGN is the alignment that the object would ordinarily have.
803 The value of this macro is used instead of that alignment to align
806 If this macro is not defined, then ALIGN is used.
808 The typical use of this macro is to increase alignment for string
809 constants to be word aligned so that `strcpy' calls that copy
810 constants can be done inline. */
812 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
814 /* If defined, a C expression to compute the alignment for a static
815 variable. TYPE is the data type, and ALIGN is the alignment that
816 the object would ordinarily have. The value of this macro is used
817 instead of that alignment to align the object.
819 If this macro is not defined, then ALIGN is used.
821 One use of this macro is to increase alignment of medium-size
822 data to make it all fit in fewer cache lines. Another is to
823 cause character arrays to be word-aligned so that `strcpy' calls
824 that copy constants to character arrays can be done inline. */
826 #define DATA_ALIGNMENT(TYPE, ALIGN) \
827 ix86_data_alignment ((TYPE), (ALIGN), true)
829 /* Similar to DATA_ALIGNMENT, but for the cases where the ABI mandates
830 some alignment increase, instead of optimization only purposes. E.g.
831 AMD x86-64 psABI says that variables with array type larger than 15 bytes
832 must be aligned to 16 byte boundaries.
834 If this macro is not defined, then ALIGN is used. */
836 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
837 ix86_data_alignment ((TYPE), (ALIGN), false)
839 /* If defined, a C expression to compute the alignment for a local
840 variable. TYPE is the data type, and ALIGN is the alignment that
841 the object would ordinarily have. The value of this macro is used
842 instead of that alignment to align the object.
844 If this macro is not defined, then ALIGN is used.
846 One use of this macro is to increase alignment of medium-size
847 data to make it all fit in fewer cache lines. */
849 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
850 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
852 /* If defined, a C expression to compute the alignment for stack slot.
853 TYPE is the data type, MODE is the widest mode available, and ALIGN
854 is the alignment that the slot would ordinarily have. The value of
855 this macro is used instead of that alignment to align the slot.
857 If this macro is not defined, then ALIGN is used when TYPE is NULL,
858 Otherwise, LOCAL_ALIGNMENT will be used.
860 One use of this macro is to set alignment of stack slot to the
861 maximum alignment of all possible modes which the slot may have. */
863 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
864 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
866 /* If defined, a C expression to compute the alignment for a local
869 If this macro is not defined, then
870 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
872 One use of this macro is to increase alignment of medium-size
873 data to make it all fit in fewer cache lines. */
875 #define LOCAL_DECL_ALIGNMENT(DECL) \
876 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
878 /* If defined, a C expression to compute the minimum required alignment
879 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
880 MODE, assuming normal alignment ALIGN.
882 If this macro is not defined, then (ALIGN) will be used. */
884 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
885 ix86_minimum_alignment (EXP, MODE, ALIGN)
888 /* Set this nonzero if move instructions will actually fail to work
889 when given unaligned data. */
890 #define STRICT_ALIGNMENT 0
892 /* If bit field type is int, don't let it cross an int,
893 and give entire struct the alignment of an int. */
894 /* Required on the 386 since it doesn't have bit-field insns. */
895 #define PCC_BITFIELD_TYPE_MATTERS 1
897 /* Standard register usage. */
899 /* This processor has special stack-like registers. See reg-stack.c
904 #define IS_STACK_MODE(MODE) \
905 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \
906 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \
909 /* Number of actual hardware registers.
910 The hardware registers are assigned numbers for the compiler
911 from 0 to just below FIRST_PSEUDO_REGISTER.
912 All registers that the compiler knows about must be given numbers,
913 even those that are not normally considered general registers.
915 In the 80386 we give the 8 general purpose registers the numbers 0-7.
916 We number the floating point registers 8-15.
917 Note that registers 0-7 can be accessed as a short or int,
918 while only 0-3 may be used with byte `mov' instructions.
920 Reg 16 does not correspond to any hardware register, but instead
921 appears in the RTL as an argument pointer prior to reload, and is
922 eliminated during reloading in favor of either the stack or frame
925 #define FIRST_PSEUDO_REGISTER 77
927 /* Number of hardware registers that go into the DWARF-2 unwind info.
928 If not defined, equals FIRST_PSEUDO_REGISTER. */
930 #define DWARF_FRAME_REGISTERS 17
932 /* 1 for registers that have pervasive standard uses
933 and are not available for the register allocator.
934 On the 80386, the stack pointer is such, as is the arg pointer.
936 REX registers are disabled for 32bit targets in
937 TARGET_CONDITIONAL_REGISTER_USAGE. */
939 #define FIXED_REGISTERS \
940 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
941 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
942 /*arg,flags,fpsr,fpcr,frame*/ \
944 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
945 0, 0, 0, 0, 0, 0, 0, 0, \
946 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
947 0, 0, 0, 0, 0, 0, 0, 0, \
948 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
949 0, 0, 0, 0, 0, 0, 0, 0, \
950 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
951 0, 0, 0, 0, 0, 0, 0, 0, \
952 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
953 0, 0, 0, 0, 0, 0, 0, 0, \
954 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
955 0, 0, 0, 0, 0, 0, 0, 0, \
956 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
957 0, 0, 0, 0, 0, 0, 0, 0 }
959 /* 1 for registers not available across function calls.
960 These must include the FIXED_REGISTERS and also any
961 registers that can be used without being saved.
962 The latter must include the registers where values are returned
963 and the register where structure-value addresses are passed.
964 Aside from that, you can include as many other registers as you like.
966 Value is set to 1 if the register is call used unconditionally.
967 Bit one is set if the register is call used on TARGET_32BIT ABI.
968 Bit two is set if the register is call used on TARGET_64BIT ABI.
969 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI.
971 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */
973 #define CALL_USED_REGISTERS \
974 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
975 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
976 /*arg,flags,fpsr,fpcr,frame*/ \
978 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
979 1, 1, 1, 1, 1, 1, 6, 6, \
980 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
981 1, 1, 1, 1, 1, 1, 1, 1, \
982 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
983 1, 1, 1, 1, 2, 2, 2, 2, \
984 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
985 6, 6, 6, 6, 6, 6, 6, 6, \
986 /*xmm16,xmm17,xmm18,xmm19,xmm20,xmm21,xmm22,xmm23*/ \
987 6, 6, 6, 6, 6, 6, 6, 6, \
988 /*xmm24,xmm25,xmm26,xmm27,xmm28,xmm29,xmm30,xmm31*/ \
989 6, 6, 6, 6, 6, 6, 6, 6, \
990 /* k0, k1, k2, k3, k4, k5, k6, k7*/ \
991 1, 1, 1, 1, 1, 1, 1, 1 }
993 /* Order in which to allocate registers. Each register must be
994 listed once, even those in FIXED_REGISTERS. List frame pointer
995 late and fixed registers last. Note that, in general, we prefer
996 registers listed in CALL_USED_REGISTERS, keeping the others
997 available for storage of persistent values.
999 The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
1000 so this is just empty initializer for array. */
1002 #define REG_ALLOC_ORDER \
1003 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1004 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1005 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1006 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
1007 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76 }
1009 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1010 to be rearranged based on a particular function. When using sse math,
1011 we want to allocate SSE before x87 registers and vice versa. */
1013 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
1016 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1018 /* Return number of consecutive hard regs needed starting at reg REGNO
1019 to hold something of mode MODE.
1020 This is ordinarily the length in words of a value of mode MODE
1021 but can be less for certain modes in special long registers.
1023 Actually there are no two word move instructions for consecutive
1024 registers. And only registers 0-3 may have mov byte instructions
1027 #define HARD_REGNO_NREGS(REGNO, MODE) \
1028 (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1029 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1030 : ((MODE) == XFmode \
1031 ? (TARGET_64BIT ? 2 : 3) \
1032 : (MODE) == XCmode \
1033 ? (TARGET_64BIT ? 4 : 6) \
1034 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1036 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1037 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1038 ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1040 : ((MODE) == XFmode || (MODE) == XCmode)) \
1043 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1045 #define VALID_AVX256_REG_MODE(MODE) \
1046 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1047 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \
1048 || (MODE) == V4DFmode)
1050 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \
1051 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode)
1053 #define VALID_AVX512F_SCALAR_MODE(MODE) \
1054 ((MODE) == DImode || (MODE) == DFmode || (MODE) == SImode \
1055 || (MODE) == SFmode)
1057 #define VALID_AVX512F_REG_MODE(MODE) \
1058 ((MODE) == V8DImode || (MODE) == V8DFmode || (MODE) == V64QImode \
1059 || (MODE) == V16SImode || (MODE) == V16SFmode || (MODE) == V32HImode)
1061 #define VALID_SSE2_REG_MODE(MODE) \
1062 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1063 || (MODE) == V2DImode || (MODE) == DFmode)
1065 #define VALID_SSE_REG_MODE(MODE) \
1066 ((MODE) == V1TImode || (MODE) == TImode \
1067 || (MODE) == V4SFmode || (MODE) == V4SImode \
1068 || (MODE) == SFmode || (MODE) == TFmode)
1070 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1071 ((MODE) == V2SFmode || (MODE) == SFmode)
1073 #define VALID_MMX_REG_MODE(MODE) \
1074 ((MODE == V1DImode) || (MODE) == DImode \
1075 || (MODE) == V2SImode || (MODE) == SImode \
1076 || (MODE) == V4HImode || (MODE) == V8QImode)
1078 #define VALID_DFP_MODE_P(MODE) \
1079 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1081 #define VALID_FP_MODE_P(MODE) \
1082 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1083 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1085 #define VALID_INT_MODE_P(MODE) \
1086 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1087 || (MODE) == DImode \
1088 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1089 || (MODE) == CDImode \
1090 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1091 || (MODE) == TFmode || (MODE) == TCmode)))
1093 /* Return true for modes passed in SSE registers. */
1094 #define SSE_REG_MODE_P(MODE) \
1095 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \
1096 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \
1097 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1098 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1099 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \
1100 || (MODE) == V2TImode || (MODE) == V8DImode || (MODE) == V64QImode \
1101 || (MODE) == V16SImode || (MODE) == V32HImode || (MODE) == V8DFmode \
1102 || (MODE) == V16SFmode)
1104 #define VALID_MASK_REG_MODE(MODE) ((MODE) == HImode || (MODE) == QImode)
1106 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1108 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1109 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1111 /* Value is 1 if it is a good idea to tie two pseudo registers
1112 when one has mode MODE1 and one has mode MODE2.
1113 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1114 for any hard reg, then this must be 0 for correct output. */
1116 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1118 /* It is possible to write patterns to move flags; but until someone
1120 #define AVOID_CCMODE_COPIES
1122 /* Specify the modes required to caller save a given hard regno.
1123 We do this on i386 to prevent flags from being saved at all.
1125 Kill any attempts to combine saving of modes. */
1127 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1128 (CC_REGNO_P (REGNO) ? VOIDmode \
1129 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1130 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1131 : (MODE) == HImode && !(TARGET_PARTIAL_REG_STALL \
1132 || MASK_REGNO_P (REGNO)) ? SImode \
1133 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO) \
1134 || MASK_REGNO_P (REGNO)) ? SImode \
1137 /* The only ABI that saves SSE registers across calls is Win64 (thus no
1138 need to check the current ABI here), and with AVX enabled Win64 only
1139 guarantees that the low 16 bytes are saved. */
1140 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1141 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16)
1143 /* Specify the registers used for certain standard purposes.
1144 The values of these macros are register numbers. */
1146 /* on the 386 the pc register is %eip, and is not usable as a general
1147 register. The ordinary mov instructions won't work */
1148 /* #define PC_REGNUM */
1150 /* Register to use for pushing function arguments. */
1151 #define STACK_POINTER_REGNUM 7
1153 /* Base register for access to local variables of the function. */
1154 #define HARD_FRAME_POINTER_REGNUM 6
1156 /* Base register for access to local variables of the function. */
1157 #define FRAME_POINTER_REGNUM 20
1159 /* First floating point reg */
1160 #define FIRST_FLOAT_REG 8
1162 /* First & last stack-like regs */
1163 #define FIRST_STACK_REG FIRST_FLOAT_REG
1164 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1166 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1167 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1169 #define FIRST_MMX_REG (LAST_SSE_REG + 1) /*29*/
1170 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1172 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) /*37*/
1173 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1175 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) /*45*/
1176 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1178 #define FIRST_EXT_REX_SSE_REG (LAST_REX_SSE_REG + 1) /*53*/
1179 #define LAST_EXT_REX_SSE_REG (FIRST_EXT_REX_SSE_REG + 15) /*68*/
1181 #define FIRST_MASK_REG (LAST_EXT_REX_SSE_REG + 1) /*69*/
1182 #define LAST_MASK_REG (FIRST_MASK_REG + 7) /*76*/
1184 /* Override this in other tm.h files to cope with various OS lossage
1185 requiring a frame pointer. */
1186 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1187 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1190 /* Make sure we can access arbitrary call frames. */
1191 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1193 /* Base register for access to arguments of the function. */
1194 #define ARG_POINTER_REGNUM 16
1196 /* Register to hold the addressing base for position independent
1197 code access to data items. We don't use PIC pointer for 64bit
1198 mode. Define the regnum to dummy value to prevent gcc from
1199 pessimizing code dealing with EBX.
1201 To avoid clobbering a call-saved register unnecessarily, we renumber
1202 the pic register when possible. The change is visible after the
1203 prologue has been emitted. */
1205 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1207 #define PIC_OFFSET_TABLE_REGNUM \
1208 ((TARGET_64BIT && (ix86_cmodel == CM_SMALL_PIC \
1209 || TARGET_PECOFF)) \
1210 || !flag_pic ? INVALID_REGNUM \
1211 : reload_completed ? REGNO (pic_offset_table_rtx) \
1212 : REAL_PIC_OFFSET_TABLE_REGNUM)
1214 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1216 /* This is overridden by <cygwin.h>. */
1217 #define MS_AGGREGATE_RETURN 0
1219 #define KEEP_AGGREGATE_RETURN_POINTER 0
1221 /* Define the classes of registers for register constraints in the
1222 machine description. Also define ranges of constants.
1224 One of the classes must always be named ALL_REGS and include all hard regs.
1225 If there is more than one class, another class must be named NO_REGS
1226 and contain no registers.
1228 The name GENERAL_REGS must be the name of a class (or an alias for
1229 another name such as ALL_REGS). This is the class of registers
1230 that is allowed by "g" or "r" in a register constraint.
1231 Also, registers outside this class are allocated only when
1232 instructions express preferences for them.
1234 The classes must be numbered in nondecreasing order; that is,
1235 a larger-numbered class must never be contained completely
1236 in a smaller-numbered class.
1238 For any two classes, it is very desirable that there be another
1239 class that represents their union.
1241 It might seem that class BREG is unnecessary, since no useful 386
1242 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1243 and the "b" register constraint is useful in asms for syscalls.
1245 The flags, fpsr and fpcr registers are in no class. */
1250 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1251 AD_REGS
, /* %eax/%edx for DImode */
1252 Q_REGS
, /* %eax %ebx %ecx %edx */
1253 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1254 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1255 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1256 CLOBBERED_REGS
, /* call-clobbered integer registers */
1257 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
1258 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
1259 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1274 ALL_REGS
, LIM_REG_CLASSES
1277 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1279 #define INTEGER_CLASS_P(CLASS) \
1280 reg_class_subset_p ((CLASS), GENERAL_REGS)
1281 #define FLOAT_CLASS_P(CLASS) \
1282 reg_class_subset_p ((CLASS), FLOAT_REGS)
1283 #define SSE_CLASS_P(CLASS) \
1284 reg_class_subset_p ((CLASS), ALL_SSE_REGS)
1285 #define MMX_CLASS_P(CLASS) \
1286 ((CLASS) == MMX_REGS)
1287 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1288 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1289 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1290 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1291 #define MAYBE_SSE_CLASS_P(CLASS) \
1292 reg_classes_intersect_p ((CLASS), ALL_SSE_REGS)
1293 #define MAYBE_MMX_CLASS_P(CLASS) \
1294 reg_classes_intersect_p ((CLASS), MMX_REGS)
1295 #define MAYBE_MASK_CLASS_P(CLASS) \
1296 reg_classes_intersect_p ((CLASS), MASK_REGS)
1298 #define Q_CLASS_P(CLASS) \
1299 reg_class_subset_p ((CLASS), Q_REGS)
1301 #define MAYBE_NON_Q_CLASS_P(CLASS) \
1302 reg_classes_intersect_p ((CLASS), NON_Q_REGS)
1304 /* Give names of register classes as strings for dump file. */
1306 #define REG_CLASS_NAMES \
1308 "AREG", "DREG", "CREG", "BREG", \
1311 "Q_REGS", "NON_Q_REGS", \
1316 "FP_TOP_REG", "FP_SECOND_REG", \
1323 "FP_TOP_SSE_REGS", \
1324 "FP_SECOND_SSE_REGS", \
1328 "FLOAT_INT_SSE_REGS", \
1333 /* Define which registers fit in which classes. This is an initializer
1334 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1336 Note that CLOBBERED_REGS are calculated by
1337 TARGET_CONDITIONAL_REGISTER_USAGE. */
1339 #define REG_CLASS_CONTENTS \
1340 { { 0x00, 0x0, 0x0 }, \
1341 { 0x01, 0x0, 0x0 }, /* AREG */ \
1342 { 0x02, 0x0, 0x0 }, /* DREG */ \
1343 { 0x04, 0x0, 0x0 }, /* CREG */ \
1344 { 0x08, 0x0, 0x0 }, /* BREG */ \
1345 { 0x10, 0x0, 0x0 }, /* SIREG */ \
1346 { 0x20, 0x0, 0x0 }, /* DIREG */ \
1347 { 0x03, 0x0, 0x0 }, /* AD_REGS */ \
1348 { 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
1349 { 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
1350 { 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
1351 { 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
1352 { 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
1353 { 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
1354 { 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
1355 { 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
1356 { 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
1357 { 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
1358 { 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
1359 { 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
1360 { 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
1361 { 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
1362 { 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
1363 { 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
1364 { 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
1365 { 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
1366 { 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
1367 { 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
1368 { 0x0, 0x0,0x1fc0 }, /* MASK_EVEX_REGS */ \
1369 { 0x0, 0x0,0x1fe0 }, /* MASK_REGS */ \
1370 { 0xffffffff,0xffffffff,0x1fff } \
1373 /* The same information, inverted:
1374 Return the class number of the smallest class containing
1375 reg number REGNO. This could be a conditional expression
1376 or could index an array. */
1378 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1380 /* When this hook returns true for MODE, the compiler allows
1381 registers explicitly used in the rtl to be used as spill registers
1382 but prevents the compiler from extending the lifetime of these
1384 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
1386 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X)))
1387 #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG)
1389 #define GENERAL_REG_P(X) \
1390 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1391 #define GENERAL_REGNO_P(N) \
1392 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N))
1394 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X)))
1395 #define ANY_QI_REGNO_P(N) \
1396 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N))
1398 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1399 #define REX_INT_REGNO_P(N) \
1400 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1402 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X)))
1403 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1405 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1406 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N))
1408 #define X87_FLOAT_MODE_P(MODE) \
1409 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1411 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X)))
1412 #define SSE_REGNO_P(N) \
1413 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1414 || REX_SSE_REGNO_P (N) \
1415 || EXT_REX_SSE_REGNO_P (N))
1417 #define REX_SSE_REGNO_P(N) \
1418 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1420 #define EXT_REX_SSE_REGNO_P(N) \
1421 IN_RANGE ((N), FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG)
1423 #define SSE_REGNO(N) \
1424 ((N) < 8 ? FIRST_SSE_REG + (N) \
1425 : (N) <= LAST_REX_SSE_REG ? (FIRST_REX_SSE_REG + (N) - 8) \
1426 : (FIRST_EXT_REX_SSE_REG + (N) - 16))
1428 #define MASK_REGNO_P(N) IN_RANGE ((N), FIRST_MASK_REG, LAST_MASK_REG)
1429 #define ANY_MASK_REG_P(X) (REG_P (X) && MASK_REGNO_P (REGNO (X)))
1431 #define SSE_FLOAT_MODE_P(MODE) \
1432 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1434 #define FMA4_VEC_FLOAT_MODE_P(MODE) \
1435 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1436 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1438 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X)))
1439 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1441 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG)
1443 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1444 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1446 /* The class value for index registers, and the one for base regs. */
1448 #define INDEX_REG_CLASS INDEX_REGS
1449 #define BASE_REG_CLASS GENERAL_REGS
1451 /* Place additional restrictions on the register class to use when it
1452 is necessary to be able to hold a value of mode MODE in a reload
1453 register for which class CLASS would ordinarily be used.
1455 We avoid classes containing registers from multiple units due to
1456 the limitation in ix86_secondary_memory_needed. We limit these
1457 classes to their "natural mode" single unit register class, depending
1458 on the unit availability.
1460 Please note that reg_class_subset_p is not commutative, so these
1461 conditions mean "... if (CLASS) includes ALL registers from the
1464 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1465 (((MODE) == QImode && !TARGET_64BIT \
1466 && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \
1467 : (((MODE) == SImode || (MODE) == DImode) \
1468 && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \
1469 : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \
1470 && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \
1471 : (X87_FLOAT_MODE_P (MODE) \
1472 && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \
1475 /* If we are copying between general and FP registers, we need a memory
1476 location. The same is true for SSE and MMX registers. */
1477 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1478 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1480 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1481 There is no need to emit full 64 bit move on 64 bit targets
1482 for integral modes that can be moved using 32 bit move. */
1483 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1484 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1485 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1488 /* Return a class of registers that cannot change FROM mode to TO mode. */
1490 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1491 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1493 /* Stack layout; function entry, exit and calling. */
1495 /* Define this if pushing a word on the stack
1496 makes the stack pointer a smaller address. */
1497 #define STACK_GROWS_DOWNWARD
1499 /* Define this to nonzero if the nominal address of the stack frame
1500 is at the high-address end of the local variables;
1501 that is, each additional local variable allocated
1502 goes at a more negative offset in the frame. */
1503 #define FRAME_GROWS_DOWNWARD 1
1505 /* Offset within stack frame to start allocating local variables at.
1506 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1507 first local allocated. Otherwise, it is the offset to the BEGINNING
1508 of the first local allocated. */
1509 #define STARTING_FRAME_OFFSET 0
1511 /* If we generate an insn to push BYTES bytes, this says how many the stack
1512 pointer really advances by. On 386, we have pushw instruction that
1513 decrements by exactly 2 no matter what the position was, there is no pushb.
1515 But as CIE data alignment factor on this arch is -4 for 32bit targets
1516 and -8 for 64bit targets, we need to make sure all stack pointer adjustments
1517 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */
1519 #define PUSH_ROUNDING(BYTES) \
1520 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
1522 /* If defined, the maximum amount of space required for outgoing arguments
1523 will be computed and placed into the variable `crtl->outgoing_args_size'.
1524 No space will be pushed onto the stack for each call; instead, the
1525 function prologue should increase the stack frame size by this amount.
1527 In 32bit mode enabling argument accumulation results in about 5% code size
1528 growth becuase move instructions are less compact than push. In 64bit
1529 mode the difference is less drastic but visible.
1531 FIXME: Unlike earlier implementations, the size of unwind info seems to
1532 actually grouw with accumulation. Is that because accumulated args
1533 unwind info became unnecesarily bloated?
1535 64-bit MS ABI seem to require 16 byte alignment everywhere except for
1536 function prologue and epilogue. This is not possible without
1537 ACCUMULATE_OUTGOING_ARGS.
1539 If stack probes are required, the space used for large function
1540 arguments on the stack must also be probed, so enable
1541 -maccumulate-outgoing-args so this happens in the prologue. */
1543 #define ACCUMULATE_OUTGOING_ARGS \
1544 ((TARGET_ACCUMULATE_OUTGOING_ARGS && optimize_function_for_speed_p (cfun)) \
1545 || TARGET_STACK_PROBE || TARGET_64BIT_MS_ABI)
1547 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1548 instructions to pass outgoing arguments. */
1550 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1552 /* We want the stack and args grow in opposite directions, even if
1554 #define PUSH_ARGS_REVERSED 1
1556 /* Offset of first parameter from the argument pointer register value. */
1557 #define FIRST_PARM_OFFSET(FNDECL) 0
1559 /* Define this macro if functions should assume that stack space has been
1560 allocated for arguments even when their values are passed in registers.
1562 The value of this macro is the size, in bytes, of the area reserved for
1563 arguments passed in registers for the function represented by FNDECL.
1565 This space can be allocated by the caller, or be a part of the
1566 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1568 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1570 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1571 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI)
1573 /* Define how to find the value returned by a library function
1574 assuming the value has mode MODE. */
1576 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1578 /* Define the size of the result block used for communication between
1579 untyped_call and untyped_return. The block contains a DImode value
1580 followed by the block used by fnsave and frstor. */
1582 #define APPLY_RESULT_SIZE (8+108)
1584 /* 1 if N is a possible register number for function argument passing. */
1585 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1587 /* Define a data type for recording info about an argument list
1588 during the scan of that argument list. This data type should
1589 hold all necessary information about the function itself
1590 and about the args processed so far, enough to enable macros
1591 such as FUNCTION_ARG to determine where the next arg should go. */
1593 typedef struct ix86_args
{
1594 int words
; /* # words passed so far */
1595 int nregs
; /* # registers available for passing */
1596 int regno
; /* next available register number */
1597 int fastcall
; /* fastcall or thiscall calling convention
1599 int sse_words
; /* # sse words passed so far */
1600 int sse_nregs
; /* # sse registers available for passing */
1601 int warn_avx
; /* True when we want to warn about AVX ABI. */
1602 int warn_sse
; /* True when we want to warn about SSE ABI. */
1603 int warn_mmx
; /* True when we want to warn about MMX ABI. */
1604 int sse_regno
; /* next available sse register number */
1605 int mmx_words
; /* # mmx words passed so far */
1606 int mmx_nregs
; /* # mmx registers available for passing */
1607 int mmx_regno
; /* next available mmx register number */
1608 int maybe_vaarg
; /* true for calls to possibly vardic fncts. */
1609 int caller
; /* true if it is caller. */
1610 int float_in_sse
; /* Set to 1 or 2 for 32bit targets if
1611 SFmode/DFmode arguments should be passed
1612 in SSE registers. Otherwise 0. */
1613 enum calling_abi call_abi
; /* Set to SYSV_ABI for sysv abi. Otherwise
1614 MS_ABI for ms abi. */
1617 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1618 for a call to a function whose data type is FNTYPE.
1619 For a library call, FNTYPE is 0. */
1621 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1622 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
1623 (N_NAMED_ARGS) != -1)
1625 /* Output assembler code to FILE to increment profiler label # LABELNO
1626 for profiling a function entry. */
1628 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1630 #define MCOUNT_NAME "_mcount"
1632 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__"
1634 #define PROFILE_COUNT_REGISTER "edx"
1636 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1637 the stack pointer does not matter. The value is tested only in
1638 functions that have frame pointers.
1639 No definition is equivalent to always zero. */
1640 /* Note on the 386 it might be more efficient not to define this since
1641 we have to restore it ourselves from the frame pointer, in order to
1644 #define EXIT_IGNORE_STACK 1
1646 /* Output assembler code for a block containing the constant parts
1647 of a trampoline, leaving space for the variable parts. */
1649 /* On the 386, the trampoline contains two instructions:
1652 The trampoline is generated entirely at runtime. The operand of JMP
1653 is the address of FUNCTION relative to the instruction following the
1654 JMP (which is 5 bytes long). */
1656 /* Length in units of the trampoline for entering a nested function. */
1658 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10)
1660 /* Definitions for register eliminations.
1662 This is an array of structures. Each structure initializes one pair
1663 of eliminable registers. The "from" register number is given first,
1664 followed by "to". Eliminations of the same "from" register are listed
1665 in order of preference.
1667 There are two registers that can always be eliminated on the i386.
1668 The frame pointer and the arg pointer can be replaced by either the
1669 hard frame pointer or to the stack pointer, depending upon the
1670 circumstances. The hard frame pointer is not used before reload and
1671 so it is not eligible for elimination. */
1673 #define ELIMINABLE_REGS \
1674 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1675 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1676 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1677 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1679 /* Define the offset between two registers, one to be eliminated, and the other
1680 its replacement, at the start of a routine. */
1682 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1683 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1685 /* Addressing modes, and classification of registers for them. */
1687 /* Macros to check register numbers against specific register classes. */
1689 /* These assume that REGNO is a hard or pseudo reg number.
1690 They give nonzero only if REGNO is a hard reg of the suitable class
1691 or a pseudo reg currently allocated to a suitable hard reg.
1692 Since they use reg_renumber, they are safe only once reg_renumber
1693 has been allocated, which happens in reginfo.c during register
1696 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1697 ((REGNO) < STACK_POINTER_REGNUM \
1698 || REX_INT_REGNO_P (REGNO) \
1699 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1700 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1702 #define REGNO_OK_FOR_BASE_P(REGNO) \
1703 (GENERAL_REGNO_P (REGNO) \
1704 || (REGNO) == ARG_POINTER_REGNUM \
1705 || (REGNO) == FRAME_POINTER_REGNUM \
1706 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1708 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1709 and check its validity for a certain class.
1710 We have two alternate definitions for each of them.
1711 The usual definition accepts all pseudo regs; the other rejects
1712 them unless they have been allocated suitable hard regs.
1713 The symbol REG_OK_STRICT causes the latter definition to be used.
1715 Most source files want to accept pseudo regs in the hope that
1716 they will get allocated to the class that the insn wants them to be in.
1717 Source files for reload pass need to be strict.
1718 After reload, it makes no difference, since pseudo regs have
1719 been eliminated by then. */
1722 /* Non strict versions, pseudos are ok. */
1723 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1724 (REGNO (X) < STACK_POINTER_REGNUM \
1725 || REX_INT_REGNO_P (REGNO (X)) \
1726 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1728 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1729 (GENERAL_REGNO_P (REGNO (X)) \
1730 || REGNO (X) == ARG_POINTER_REGNUM \
1731 || REGNO (X) == FRAME_POINTER_REGNUM \
1732 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1734 /* Strict versions, hard registers only */
1735 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1736 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1738 #ifndef REG_OK_STRICT
1739 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1740 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1743 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1744 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1747 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1748 that is a valid memory address for an instruction.
1749 The MODE argument is the machine mode for the MEM expression
1750 that wants to use this address.
1752 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1753 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1755 See legitimize_pic_address in i386.c for details as to what
1756 constitutes a legitimate address when -fpic is used. */
1758 #define MAX_REGS_PER_ADDRESS 2
1760 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1762 /* Try a machine-dependent way of reloading an illegitimate address
1763 operand. If we find one, push the reload and jump to WIN. This
1764 macro is used in only one place: `find_reloads_address' in reload.c. */
1766 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \
1768 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \
1769 (int)(TYPE), (INDL))) \
1773 /* If defined, a C expression to determine the base term of address X.
1774 This macro is used in only one place: `find_base_term' in alias.c.
1776 It is always safe for this macro to not be defined. It exists so
1777 that alias analysis can understand machine-dependent addresses.
1779 The typical use of this macro is to handle addresses containing
1780 a label_ref or symbol_ref within an UNSPEC. */
1782 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1784 /* Nonzero if the constant value X is a legitimate general operand
1785 when generating PIC code. It is given that flag_pic is on and
1786 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1788 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1790 #define SYMBOLIC_CONST(X) \
1791 (GET_CODE (X) == SYMBOL_REF \
1792 || GET_CODE (X) == LABEL_REF \
1793 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1795 /* Max number of args passed in registers. If this is more than 3, we will
1796 have problems with ebx (register #4), since it is a caller save register and
1797 is also used as the pic register in ELF. So for now, don't allow more than
1798 3 registers to be passed in registers. */
1800 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1801 #define X86_64_REGPARM_MAX 6
1802 #define X86_64_MS_REGPARM_MAX 4
1804 #define X86_32_REGPARM_MAX 3
1806 #define REGPARM_MAX \
1808 ? (TARGET_64BIT_MS_ABI \
1809 ? X86_64_MS_REGPARM_MAX \
1810 : X86_64_REGPARM_MAX) \
1811 : X86_32_REGPARM_MAX)
1813 #define X86_64_SSE_REGPARM_MAX 8
1814 #define X86_64_MS_SSE_REGPARM_MAX 4
1816 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0)
1818 #define SSE_REGPARM_MAX \
1820 ? (TARGET_64BIT_MS_ABI \
1821 ? X86_64_MS_SSE_REGPARM_MAX \
1822 : X86_64_SSE_REGPARM_MAX) \
1823 : X86_32_SSE_REGPARM_MAX)
1825 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1827 /* Specify the machine mode that this machine uses
1828 for the index in the tablejump instruction. */
1829 #define CASE_VECTOR_MODE \
1830 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1832 /* Define this as 1 if `char' should by default be signed; else as 0. */
1833 #define DEFAULT_SIGNED_CHAR 1
1835 /* Max number of bytes we can move from memory to memory
1836 in one reasonably fast instruction. */
1839 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1840 move efficiently, as opposed to MOVE_MAX which is the maximum
1841 number of bytes we can move with a single instruction. */
1842 #define MOVE_MAX_PIECES UNITS_PER_WORD
1844 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1845 move-instruction pairs, we will do a movmem or libcall instead.
1846 Increasing the value will always make code faster, but eventually
1847 incurs high cost in increased code size.
1849 If you don't define this, a reasonable default is used. */
1851 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1853 /* If a clear memory operation would take CLEAR_RATIO or more simple
1854 move-instruction sequences, we will do a clrmem or libcall instead. */
1856 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1858 /* Define if shifts truncate the shift count which implies one can
1859 omit a sign-extension or zero-extension of a shift count.
1861 On i386, shifts do truncate the count. But bit test instructions
1862 take the modulo of the bit offset operand. */
1864 /* #define SHIFT_COUNT_TRUNCATED */
1866 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1867 is done just by pretending it is already truncated. */
1868 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1870 /* A macro to update M and UNSIGNEDP when an object whose type is
1871 TYPE and which has the specified mode and signedness is to be
1872 stored in a register. This macro is only called when TYPE is a
1875 On i386 it is sometimes useful to promote HImode and QImode
1876 quantities to SImode. The choice depends on target type. */
1878 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1880 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1881 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1885 /* Specify the machine mode that pointers have.
1886 After generation of rtl, the compiler makes no further distinction
1887 between pointers and any other objects of this machine mode. */
1888 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode)
1890 /* A C expression whose value is zero if pointers that need to be extended
1891 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1892 greater then zero if they are zero-extended and less then zero if the
1893 ptr_extend instruction should be used. */
1895 #define POINTERS_EXTEND_UNSIGNED 1
1897 /* A function address in a call instruction
1898 is a byte address (for indexing purposes)
1899 so give the MEM rtx a byte's mode. */
1900 #define FUNCTION_MODE QImode
1903 /* A C expression for the cost of a branch instruction. A value of 1
1904 is the default; other values are interpreted relative to that. */
1906 #define BRANCH_COST(speed_p, predictable_p) \
1907 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1909 /* An integer expression for the size in bits of the largest integer machine
1910 mode that should actually be used. We allow pairs of registers. */
1911 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
1913 /* Define this macro as a C expression which is nonzero if accessing
1914 less than a word of memory (i.e. a `char' or a `short') is no
1915 faster than accessing a word of memory, i.e., if such access
1916 require more than one instruction or if there is no difference in
1917 cost between byte and (aligned) word loads.
1919 When this macro is not defined, the compiler will access a field by
1920 finding the smallest containing object; when it is defined, a
1921 fullword load will be used if alignment permits. Unless bytes
1922 accesses are faster than word accesses, using word accesses is
1923 preferable since it may eliminate subsequent memory access if
1924 subsequent accesses occur to other fields in the same word of the
1925 structure, but to different bytes. */
1927 #define SLOW_BYTE_ACCESS 0
1929 /* Nonzero if access to memory by shorts is slow and undesirable. */
1930 #define SLOW_SHORT_ACCESS 0
1932 /* Define this macro to be the value 1 if unaligned accesses have a
1933 cost many times greater than aligned accesses, for example if they
1934 are emulated in a trap handler.
1936 When this macro is nonzero, the compiler will act as if
1937 `STRICT_ALIGNMENT' were nonzero when generating code for block
1938 moves. This can cause significantly more instructions to be
1939 produced. Therefore, do not set this macro nonzero if unaligned
1940 accesses only add a cycle or two to the time for a memory access.
1942 If the value of this macro is always zero, it need not be defined. */
1944 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1946 /* Define this macro if it is as good or better to call a constant
1947 function address than to call an address kept in a register.
1949 Desirable on the 386 because a CALL with a constant address is
1950 faster than one with a register address. */
1952 #define NO_FUNCTION_CSE
1954 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1955 return the mode to be used for the comparison.
1957 For floating-point equality comparisons, CCFPEQmode should be used.
1958 VOIDmode should be used in all other cases.
1960 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1961 possible, to allow for more combinations. */
1963 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1965 /* Return nonzero if MODE implies a floating point inequality can be
1968 #define REVERSIBLE_CC_MODE(MODE) 1
1970 /* A C expression whose value is reversed condition code of the CODE for
1971 comparison done in CC_MODE mode. */
1972 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1975 /* Control the assembler format that we output, to the extent
1976 this does not vary between assemblers. */
1978 /* How to refer to registers in assembler output.
1979 This sequence is indexed by compiler's hard-register-number (see above). */
1981 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
1982 For non floating point regs, the following are the HImode names.
1984 For float regs, the stack top is sometimes referred to as "%st(0)"
1985 instead of just "%st". TARGET_PRINT_OPERAND handles this with the
1988 #define HI_REGISTER_NAMES \
1989 {"ax","dx","cx","bx","si","di","bp","sp", \
1990 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1991 "argp", "flags", "fpsr", "fpcr", "frame", \
1992 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1993 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1994 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1995 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", \
1996 "xmm16", "xmm17", "xmm18", "xmm19", \
1997 "xmm20", "xmm21", "xmm22", "xmm23", \
1998 "xmm24", "xmm25", "xmm26", "xmm27", \
1999 "xmm28", "xmm29", "xmm30", "xmm31", \
2000 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }
2002 #define REGISTER_NAMES HI_REGISTER_NAMES
2004 /* Table of additional register names to use in user input. */
2006 #define ADDITIONAL_REGISTER_NAMES \
2007 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2008 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2009 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2010 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2011 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2012 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2014 /* Note we are omitting these since currently I don't know how
2015 to get gcc to use these, since they want the same but different
2016 number as al, and ax.
2019 #define QI_REGISTER_NAMES \
2020 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2022 /* These parallel the array above, and can be used to access bits 8:15
2023 of regs 0 through 3. */
2025 #define QI_HIGH_REGISTER_NAMES \
2026 {"ah", "dh", "ch", "bh", }
2028 /* How to renumber registers for dbx and gdb. */
2030 #define DBX_REGISTER_NUMBER(N) \
2031 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2033 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2034 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
2035 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2037 extern int const x86_64_ms_sysv_extra_clobbered_registers
[12];
2039 /* Before the prologue, RA is at 0(%esp). */
2040 #define INCOMING_RETURN_ADDR_RTX \
2041 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2043 /* After the prologue, RA is at -4(AP) in the current frame. */
2044 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2046 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \
2048 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD)))
2050 /* PC is dbx register 8; let's use that column for RA. */
2051 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2053 /* Before the prologue, the top of the frame is at 4(%esp). */
2054 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2056 /* Describe how we implement __builtin_eh_return. */
2057 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM)
2058 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG)
2061 /* Select a format to encode pointers in exception handling data. CODE
2062 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2063 true if the symbol may be affected by dynamic relocations.
2065 ??? All x86 object file formats are capable of representing this.
2066 After all, the relocation needed is the same as for the call insn.
2067 Whether or not a particular assembler allows us to enter such, I
2068 guess we'll have to see. */
2069 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2070 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2072 /* This is how to output an insn to push a register on the stack.
2073 It need not be very fast code. */
2075 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2078 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2079 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2081 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2084 /* This is how to output an insn to pop a register from the stack.
2085 It need not be very fast code. */
2087 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2090 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2091 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2093 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2096 /* This is how to output an element of a case-vector that is absolute. */
2098 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2099 ix86_output_addr_vec_elt ((FILE), (VALUE))
2101 /* This is how to output an element of a case-vector that is relative. */
2103 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2104 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2106 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */
2108 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2110 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2111 (PTR) += TARGET_AVX ? 1 : 2; \
2114 /* A C statement or statements which output an assembler instruction
2115 opcode to the stdio stream STREAM. The macro-operand PTR is a
2116 variable of type `char *' which points to the opcode name in
2117 its "internal" form--the form that is written in the machine
2120 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2121 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2123 /* A C statement to output to the stdio stream FILE an assembler
2124 command to pad the location counter to a multiple of 1<<LOG
2125 bytes if it is within MAX_SKIP bytes. */
2127 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2128 #undef ASM_OUTPUT_MAX_SKIP_PAD
2129 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2132 if ((MAX_SKIP) == 0) \
2133 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2135 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2139 /* Write the extra assembler code needed to declare a function
2142 #undef ASM_OUTPUT_FUNCTION_LABEL
2143 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \
2144 ix86_asm_output_function_label (FILE, NAME, DECL)
2146 /* Under some conditions we need jump tables in the text section,
2147 because the assembler cannot handle label differences between
2148 sections. This is the case for x86_64 on Mach-O for example. */
2150 #define JUMP_TABLES_IN_TEXT_SECTION \
2151 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2152 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2154 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2155 and switch back. For x86 we do this only to save a few bytes that
2156 would otherwise be unused in the text section. */
2157 #define CRT_MKSTR2(VAL) #VAL
2158 #define CRT_MKSTR(x) CRT_MKSTR2(x)
2160 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2161 asm (SECTION_OP "\n\t" \
2162 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \
2163 TEXT_SECTION_ASM_OP);
2165 /* Default threshold for putting data in large sections
2166 with x86-64 medium memory model */
2167 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536
2169 /* Which processor to tune code generation for. These must be in sync
2170 with processor_target_table in i386.c. */
2174 PROCESSOR_GENERIC
= 0,
2175 PROCESSOR_I386
, /* 80386 */
2176 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
2178 PROCESSOR_PENTIUMPRO
,
2183 PROCESSOR_SANDYBRIDGE
,
2186 PROCESSOR_SILVERMONT
,
2201 extern enum processor_type ix86_tune
;
2202 extern enum processor_type ix86_arch
;
2204 /* Size of the RED_ZONE area. */
2205 #define RED_ZONE_SIZE 128
2206 /* Reserved area of the red zone for temporaries. */
2207 #define RED_ZONE_RESERVE 8
2209 extern unsigned int ix86_preferred_stack_boundary
;
2210 extern unsigned int ix86_incoming_stack_boundary
;
2212 /* Smallest class containing REGNO. */
2213 extern enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
];
2215 enum ix86_fpcmp_strategy
{
2221 /* To properly truncate FP values into integers, we need to set i387 control
2222 word. We can't emit proper mode switching code before reload, as spills
2223 generated by reload may truncate values incorrectly, but we still can avoid
2224 redundant computation of new control word by the mode switching pass.
2225 The fldcw instructions are still emitted redundantly, but this is probably
2226 not going to be noticeable problem, as most CPUs do have fast path for
2229 The machinery is to emit simple truncation instructions and split them
2230 before reload to instructions having USEs of two memory locations that
2231 are filled by this code to old and new control word.
2233 Post-reload pass may be later used to eliminate the redundant fildcw if
2246 enum ix86_stack_slot
2254 MAX_386_STACK_LOCALS
2264 /* Define this macro if the port needs extra instructions inserted
2265 for mode switching in an optimizing compilation. */
2267 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2268 ix86_optimize_mode_switching[(ENTITY)]
2270 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2271 initializer for an array of integers. Each initializer element N
2272 refers to an entity that needs mode switching, and specifies the
2273 number of different modes that might need to be set for this
2274 entity. The position of the initializer in the initializer -
2275 starting counting at zero - determines the integer that is used to
2276 refer to the mode-switched entity in question. */
2278 #define NUM_MODES_FOR_MODE_SWITCHING \
2279 { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2281 /* ENTITY is an integer specifying a mode-switched entity. If
2282 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2283 return an integer value not larger than the corresponding element
2284 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2285 must be switched into prior to the execution of INSN. */
2287 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2289 /* If this macro is defined, it is evaluated for every INSN during
2290 mode switching. It determines the mode that an insn results in (if
2291 different from the incoming mode). */
2293 #define MODE_AFTER(ENTITY, MODE, I) ix86_mode_after ((ENTITY), (MODE), (I))
2295 /* If this macro is defined, it is evaluated for every ENTITY that
2296 needs mode switching. It should evaluate to an integer, which is
2297 a mode that ENTITY is assumed to be switched to at function entry. */
2299 #define MODE_ENTRY(ENTITY) ix86_mode_entry (ENTITY)
2301 /* If this macro is defined, it is evaluated for every ENTITY that
2302 needs mode switching. It should evaluate to an integer, which is
2303 a mode that ENTITY is assumed to be switched to at function exit. */
2305 #define MODE_EXIT(ENTITY) ix86_mode_exit (ENTITY)
2307 /* This macro specifies the order in which modes for ENTITY are
2308 processed. 0 is the highest priority. */
2310 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2312 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2313 is the set of hard registers live at the point where the insn(s)
2314 are to be inserted. */
2316 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2317 ix86_emit_mode_set ((ENTITY), (MODE), (HARD_REGS_LIVE))
2319 /* Avoid renaming of stack registers, as doing so in combination with
2320 scheduling just increases amount of live registers at time and in
2321 the turn amount of fxch instructions needed.
2323 ??? Maybe Pentium chips benefits from renaming, someone can try....
2325 Don't rename evex to non-evex sse registers. */
2327 #define HARD_REGNO_RENAME_OK(SRC, TARGET) (!STACK_REGNO_P (SRC) && \
2328 (EXT_REX_SSE_REGNO_P (SRC) == \
2329 EXT_REX_SSE_REGNO_P (TARGET)))
2332 #define FASTCALL_PREFIX '@'
2334 /* Machine specific frame tracking during prologue/epilogue generation. */
2336 #ifndef USED_FOR_TARGET
2337 struct GTY(()) machine_frame_state
2339 /* This pair tracks the currently active CFA as reg+offset. When reg
2340 is drap_reg, we don't bother trying to record here the real CFA when
2341 it might really be a DW_CFA_def_cfa_expression. */
2343 HOST_WIDE_INT cfa_offset
;
2345 /* The current offset (canonically from the CFA) of ESP and EBP.
2346 When stack frame re-alignment is active, these may not be relative
2347 to the CFA. However, in all cases they are relative to the offsets
2348 of the saved registers stored in ix86_frame. */
2349 HOST_WIDE_INT sp_offset
;
2350 HOST_WIDE_INT fp_offset
;
2352 /* The size of the red-zone that may be assumed for the purposes of
2353 eliding register restore notes in the epilogue. This may be zero
2354 if no red-zone is in effect, or may be reduced from the real
2355 red-zone value by a maximum runtime stack re-alignment value. */
2356 int red_zone_offset
;
2358 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid
2359 value within the frame. If false then the offset above should be
2360 ignored. Note that DRAP, if valid, *always* points to the CFA and
2361 thus has an offset of zero. */
2362 BOOL_BITFIELD sp_valid
: 1;
2363 BOOL_BITFIELD fp_valid
: 1;
2364 BOOL_BITFIELD drap_valid
: 1;
2366 /* Indicate whether the local stack frame has been re-aligned. When
2367 set, the SP/FP offsets above are relative to the aligned frame
2369 BOOL_BITFIELD realigned
: 1;
2372 /* Private to winnt.c. */
2373 struct seh_frame_state
;
2375 struct GTY(()) machine_function
{
2376 struct stack_local_entry
*stack_locals
;
2377 const char *some_ld_name
;
2378 int varargs_gpr_size
;
2379 int varargs_fpr_size
;
2380 int optimize_mode_switching
[MAX_386_ENTITIES
];
2382 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE
2383 has been computed for. */
2384 int use_fast_prologue_epilogue_nregs
;
2386 /* For -fsplit-stack support: A stack local which holds a pointer to
2387 the stack arguments for a function with a variable number of
2388 arguments. This is set at the start of the function and is used
2389 to initialize the overflow_arg_area field of the va_list
2391 rtx split_stack_varargs_pointer
;
2393 /* This value is used for amd64 targets and specifies the current abi
2394 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2395 ENUM_BITFIELD(calling_abi
) call_abi
: 8;
2397 /* Nonzero if the function accesses a previous frame. */
2398 BOOL_BITFIELD accesses_prev_frame
: 1;
2400 /* Nonzero if the function requires a CLD in the prologue. */
2401 BOOL_BITFIELD needs_cld
: 1;
2403 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2404 expander to determine the style used. */
2405 BOOL_BITFIELD use_fast_prologue_epilogue
: 1;
2407 /* If true, the current function needs the default PIC register, not
2408 an alternate register (on x86) and must not use the red zone (on
2409 x86_64), even if it's a leaf function. We don't want the
2410 function to be regarded as non-leaf because TLS calls need not
2411 affect register allocation. This flag is set when a TLS call
2412 instruction is expanded within a function, and never reset, even
2413 if all such instructions are optimized away. Use the
2414 ix86_current_function_calls_tls_descriptor macro for a better
2416 BOOL_BITFIELD tls_descriptor_call_expanded_p
: 1;
2418 /* If true, the current function has a STATIC_CHAIN is placed on the
2419 stack below the return address. */
2420 BOOL_BITFIELD static_chain_on_stack
: 1;
2422 /* During prologue/epilogue generation, the current frame state.
2423 Otherwise, the frame state at the end of the prologue. */
2424 struct machine_frame_state fs
;
2426 /* During SEH output, this is non-null. */
2427 struct seh_frame_state
* GTY((skip(""))) seh
;
2431 #define ix86_stack_locals (cfun->machine->stack_locals)
2432 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2433 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2434 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2435 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2436 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2437 (cfun->machine->tls_descriptor_call_expanded_p)
2438 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2439 calls are optimized away, we try to detect cases in which it was
2440 optimized away. Since such instructions (use (reg REG_SP)), we can
2441 verify whether there's any such instruction live by testing that
2443 #define ix86_current_function_calls_tls_descriptor \
2444 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2445 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack)
2447 /* Control behavior of x86_file_start. */
2448 #define X86_FILE_START_VERSION_DIRECTIVE false
2449 #define X86_FILE_START_FLTUSED false
2451 /* Flag to mark data that is in the large address area. */
2452 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2453 #define SYMBOL_REF_FAR_ADDR_P(X) \
2454 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2456 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2457 have defined always, to avoid ifdefing. */
2458 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2459 #define SYMBOL_REF_DLLIMPORT_P(X) \
2460 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2462 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2463 #define SYMBOL_REF_DLLEXPORT_P(X) \
2464 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2466 #define SYMBOL_FLAG_STUBVAR (SYMBOL_FLAG_MACH_DEP << 4)
2467 #define SYMBOL_REF_STUBVAR_P(X) \
2468 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_STUBVAR) != 0)
2470 extern void debug_ready_dispatch (void);
2471 extern void debug_dispatch_window (int);
2473 /* The value at zero is only defined for the BMI instructions
2474 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */
2475 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2476 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI)
2477 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2478 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT)
2481 /* Flags returned by ix86_get_callcvt (). */
2482 #define IX86_CALLCVT_CDECL 0x1
2483 #define IX86_CALLCVT_STDCALL 0x2
2484 #define IX86_CALLCVT_FASTCALL 0x4
2485 #define IX86_CALLCVT_THISCALL 0x8
2486 #define IX86_CALLCVT_REGPARM 0x10
2487 #define IX86_CALLCVT_SSEREGPARM 0x20
2489 #define IX86_BASE_CALLCVT(FLAGS) \
2490 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \
2491 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL))
2493 #define RECIP_MASK_NONE 0x00
2494 #define RECIP_MASK_DIV 0x01
2495 #define RECIP_MASK_SQRT 0x02
2496 #define RECIP_MASK_VEC_DIV 0x04
2497 #define RECIP_MASK_VEC_SQRT 0x08
2498 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \
2499 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2500 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT)
2502 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0)
2503 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0)
2504 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
2505 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
2507 #define IX86_HLE_ACQUIRE (1 << 16)
2508 #define IX86_HLE_RELEASE (1 << 17)