1 ; Options for the IA-32 and AMD64 ports of the compiler.
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009,
4 ; 2010, 2011 Free Software Foundation, Inc.
6 ; This file is part of GCC.
8 ; GCC is free software; you can redistribute it and/or modify it under
9 ; the terms of the GNU General Public License as published by the Free
10 ; Software Foundation; either version 3, or (at your option) any later
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 ; You should have received a copy of the GNU General Public License
19 ; along with GCC; see the file COPYING3. If not see
20 ; <http://www.gnu.org/licenses/>.
23 config/i386/i386-opts.h
25 ; Bit flags that specify the ISA we are compiling for.
27 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
29 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
30 ; on the command line.
32 HOST_WIDE_INT ix86_isa_flags_explicit
35 int recip_mask = RECIP_MASK_DEFAULT
38 int recip_mask_explicit
41 int x_recip_mask_explicit
43 ;; Definitions to add to the cl_target_option structure
54 unsigned char schedule
58 unsigned char branch_cost
60 ;; which flags were passed by the user
62 HOST_WIDE_INT x_ix86_isa_flags_explicit
64 ;; which flags were passed by the user
66 int ix86_target_flags_explicit
68 ;; whether -mtune was not specified
70 unsigned char tune_defaulted
72 ;; whether -march was specified
74 unsigned char arch_specified
78 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
79 sizeof(long double) is 16
82 Target Report Mask(80387) Save
86 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
87 sizeof(long double) is 12
89 maccumulate-outgoing-args
90 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
91 Reserve space for outgoing arguments in the function prologue
94 Target Report Mask(ALIGN_DOUBLE) Save
95 Align some doubles on dword boundary
98 Target RejectNegative Joined UInteger
99 Function starts are aligned to this power of 2
102 Target RejectNegative Joined UInteger
103 Jump targets are aligned to this power of 2
106 Target RejectNegative Joined UInteger
107 Loop code aligned to this power of 2
110 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
111 Align destination of the string operations
114 Target RejectNegative Joined Var(ix86_arch_string)
115 Generate code for given CPU
118 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
119 Use given assembler dialect
122 Name(asm_dialect) Type(enum asm_dialect)
123 Known assembler dialects (for use with the -masm-dialect= option):
126 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
129 Enum(asm_dialect) String(att) Value(ASM_ATT)
132 Target RejectNegative Joined UInteger Var(ix86_branch_cost)
133 Branches are this expensive (1-5, arbitrary units)
135 mlarge-data-threshold=
136 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
137 Data greater than given threshold will go into .ldata section in x86-64 medium model
140 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
141 Use given x86-64 code model
144 Name(cmodel) Type(enum cmodel)
145 Known code models (for use with the -mcmodel= option):
148 Enum(cmodel) String(small) Value(CM_SMALL)
151 Enum(cmodel) String(medium) Value(CM_MEDIUM)
154 Enum(cmodel) String(large) Value(CM_LARGE)
157 Enum(cmodel) String(32) Value(CM_32)
160 Enum(cmodel) String(kernel) Value(CM_KERNEL)
163 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
164 Use given address mode
167 Name(pmode) Type(enum pmode)
168 Known address mode (for use with the -maddress-mode= option):
171 Enum(pmode) String(short) Value(PMODE_SI)
174 Enum(pmode) String(long) Value(PMODE_DI)
177 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
180 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
181 Generate sin, cos, sqrt for FPU
184 Target Report Var(ix86_force_drap)
185 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
188 Target Report Mask(FLOAT_RETURNS) Save
189 Return values of functions in FPU registers
192 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
193 Generate floating point mathematics using given instruction set
196 Name(fpmath_unit) Type(enum fpmath_unit)
197 Valid arguments to -mfpmath=:
200 Enum(fpmath_unit) String(387) Value(FPMATH_387)
203 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
206 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
209 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
212 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
215 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
218 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
221 Target RejectNegative Mask(80387) Save
225 Target Report Mask(IEEE_FP) Save
226 Use IEEE math for fp comparisons
228 minline-all-stringops
229 Target Report Mask(INLINE_ALL_STRINGOPS) Save
230 Inline all known string operations
232 minline-stringops-dynamically
233 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
234 Inline memset/memcpy string operations, but perform inline version only for small blocks
237 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
241 Target Report Mask(MS_BITFIELD_LAYOUT) Save
242 Use native (MS) bitfield layout
245 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
248 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
251 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
254 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
256 momit-leaf-frame-pointer
257 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
258 Omit the frame pointer in leaf functions
261 Target RejectNegative Report
262 Set 80387 floating-point precision to 32-bit
265 Target RejectNegative Report
266 Set 80387 floating-point precision to 64-bit
269 Target RejectNegative Report
270 Set 80387 floating-point precision to 80-bit
272 mpreferred-stack-boundary=
273 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
274 Attempt to keep stack aligned to this power of 2
276 mincoming-stack-boundary=
277 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
278 Assume incoming stack aligned to this power of 2
281 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
282 Use push instructions to save outgoing arguments
285 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
286 Use red-zone in the x86-64 code
289 Target RejectNegative Joined UInteger Var(ix86_regparm)
290 Number of registers used to pass integer arguments
293 Target Report Mask(RTD) Save
294 Alternate calling convention
297 Target InverseMask(80387) Save
298 Do not use hardware fp
301 Target RejectNegative Mask(SSEREGPARM) Save
302 Use SSE register passing conventions for SF and DF mode
305 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
306 Realign stack in prologue
309 Target Report Mask(STACK_PROBE) Save
313 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
314 Chose strategy to generate stringop using
317 Name(stringop_alg) Type(enum stringop_alg)
318 Valid arguments to -mstringop-strategy=:
321 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
324 Enum(stringop_alg) String(libcall) Value(libcall)
327 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
330 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
333 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
336 Enum(stringop_alg) String(loop) Value(loop)
339 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
342 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
343 Use given thread-local storage dialect
346 Name(tls_dialect) Type(enum tls_dialect)
347 Known TLS dialects (for use with the -mtls-dialect= option):
350 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
353 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
356 Target Report Mask(TLS_DIRECT_SEG_REFS)
357 Use direct references against %gs when accessing tls data
360 Target RejectNegative Joined Var(ix86_tune_string)
361 Schedule code for given CPU
364 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
365 Generate code that conforms to the given ABI
368 Name(calling_abi) Type(enum calling_abi)
369 Known ABIs (for use with the -mabi= option):
372 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
375 Enum(calling_abi) String(ms) Value(MS_ABI)
378 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
379 Vector library ABI to use
382 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
383 Known vectorization library ABIs (for use with the -mveclibabi= option):
386 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
389 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
392 Target Report Mask(VECT8_RETURNS) Save
393 Return 8-byte vectors in memory
396 Target Report Mask(RECIP) Save
397 Generate reciprocals instead of divss and sqrtss.
400 Target Report RejectNegative Joined Var(ix86_recip_name)
401 Control generation of reciprocal estimates.
404 Target Report Mask(CLD) Save
405 Generate cld instruction in the function prologue.
408 Target Report Mask(VZEROUPPER) Save
409 Generate vzeroupper instruction before a transfer of control flow out of
413 Target RejectNegative Var(flag_dispatch_scheduler)
414 Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
418 Target Report Mask(PREFER_AVX128) SAVE
419 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
424 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
425 Generate 32bit i386 code
428 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
429 Generate 64bit x86-64 code
432 Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
433 Generate 32bit x86-64 code
436 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
437 Support MMX built-in functions
440 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
441 Support 3DNow! built-in functions
444 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
445 Support Athlon 3Dnow! built-in functions
448 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
449 Support MMX and SSE built-in functions and code generation
452 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
453 Support MMX, SSE and SSE2 built-in functions and code generation
456 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
457 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
460 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
461 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
464 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
465 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
468 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
469 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
472 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
473 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
476 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
477 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
480 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
484 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
485 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
488 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
489 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
492 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
493 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
496 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
497 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
500 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
501 Support FMA4 built-in functions and code generation
504 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
505 Support XOP built-in functions and code generation
508 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
509 Support LWP built-in functions and code generation
512 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
513 Support code generation of Advanced Bit Manipulation (ABM) instructions.
516 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
517 Support code generation of popcnt instruction.
520 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
521 Support BMI built-in functions and code generation
524 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
525 Support BMI2 built-in functions and code generation
528 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
529 Support LZCNT built-in function and code generation
532 Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
533 Support Hardware Lock Elision prefixes
536 Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
537 Support PREFETCHW instruction
540 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
541 Support TBM built-in functions and code generation
544 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
545 Support code generation of cmpxchg16b instruction.
548 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
549 Support code generation of sahf instruction in 64bit x86-64 code.
552 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
553 Support code generation of movbe instruction.
556 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
557 Support code generation of crc32 instruction.
560 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
561 Support AES built-in functions and code generation
564 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
565 Support PCLMUL built-in functions and code generation
568 Target Report Var(ix86_sse2avx)
569 Encode SSE instructions with VEX prefix
572 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
573 Support FSGSBASE built-in functions and code generation
576 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
577 Support RDRND built-in functions and code generation
580 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
581 Support F16C built-in functions and code generation
584 Target Report Var(flag_fentry) Init(-1)
585 Emit profiling counter call at function entry before prologue.
588 Target Report Mask(USE_8BIT_IDIV) Save
589 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
591 mavx256-split-unaligned-load
592 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
593 Split 32-byte AVX unaligned load
595 mavx256-split-unaligned-store
596 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
597 Split 32-byte AVX unaligned store
600 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
601 Support RTM built-in functions and code generation