gcc/config/i386/i386.opt

   1 ; Options for the IA-32 and AMD64 ports of the compiler.
   2
   3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009,
   4 ; 2010, 2011, 2012 Free Software Foundation, Inc.
   5 ;
   6 ; This file is part of GCC.
   7 ;
   8 ; GCC is free software; you can redistribute it and/or modify it under
   9 ; the terms of the GNU General Public License as published by the Free
  10 ; Software Foundation; either version 3, or (at your option) any later
  11 ; version.
  12 ;
  13 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 ; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 ; for more details.
  17 ;
  18 ; You should have received a copy of the GNU General Public License
  19 ; along with GCC; see the file COPYING3.  If not see
  20 ; <http://www.gnu.org/licenses/>.
  21
  22 HeaderInclude
  23 config/i386/i386-opts.h
  24
  25 ; Bit flags that specify the ISA we are compiling for.
  26 Variable
  27 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
  28
  29 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
  30 ; on the command line.
  31 Variable
  32 HOST_WIDE_INT ix86_isa_flags_explicit
  33
  34 TargetVariable
  35 int recip_mask = RECIP_MASK_DEFAULT
  36
  37 Variable
  38 int recip_mask_explicit
  39
  40 TargetSave
  41 int x_recip_mask_explicit
  42
  43 ;; Definitions to add to the cl_target_option structure
  44 ;; -march= processor
  45 TargetSave
  46 unsigned char arch
  47
  48 ;; -mtune= processor
  49 TargetSave
  50 unsigned char tune
  51
  52 ;; CPU schedule model
  53 TargetSave
  54 unsigned char schedule
  55
  56 ;; branch cost
  57 TargetSave
  58 unsigned char branch_cost
  59
  60 ;; which flags were passed by the user
  61 TargetSave
  62 HOST_WIDE_INT x_ix86_isa_flags_explicit
  63
  64 ;; which flags were passed by the user
  65 TargetSave
  66 int ix86_target_flags_explicit
  67
  68 ;; whether -mtune was not specified
  69 TargetSave
  70 unsigned char tune_defaulted
  71
  72 ;; whether -march was specified
  73 TargetSave
  74 unsigned char arch_specified
  75
  76 ;; x86 options
  77 m128bit-long-double
  78 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
  79 sizeof(long double) is 16
  80
  81 m80387
  82 Target Report Mask(80387) Save
  83 Use hardware fp
  84
  85 m96bit-long-double
  86 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
  87 sizeof(long double) is 12
  88
  89 mlong-double-80
  90 Target Report RejectNegative InverseMask(LONG_DOUBLE_64) Save
  91 Use 80-bit long double
  92
  93 mlong-double-64
  94 Target Report RejectNegative Mask(LONG_DOUBLE_64) Save
  95 Use 64-bit long double
  96
  97 maccumulate-outgoing-args
  98 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
  99 Reserve space for outgoing arguments in the function prologue
 100
 101 malign-double
 102 Target Report Mask(ALIGN_DOUBLE) Save
 103 Align some doubles on dword boundary
 104
 105 malign-functions=
 106 Target RejectNegative Joined UInteger
 107 Function starts are aligned to this power of 2
 108
 109 malign-jumps=
 110 Target RejectNegative Joined UInteger
 111 Jump targets are aligned to this power of 2
 112
 113 malign-loops=
 114 Target RejectNegative Joined UInteger
 115 Loop code aligned to this power of 2
 116
 117 malign-stringops
 118 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
 119 Align destination of the string operations
 120
 121 march=
 122 Target RejectNegative Joined Var(ix86_arch_string)
 123 Generate code for given CPU
 124
 125 masm=
 126 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
 127 Use given assembler dialect
 128
 129 Enum
 130 Name(asm_dialect) Type(enum asm_dialect)
 131 Known assembler dialects (for use with the -masm-dialect= option):
 132
 133 EnumValue
 134 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
 135
 136 EnumValue
 137 Enum(asm_dialect) String(att) Value(ASM_ATT)
 138
 139 mbranch-cost=
 140 Target RejectNegative Joined UInteger Var(ix86_branch_cost)
 141 Branches are this expensive (1-5, arbitrary units)
 142
 143 mlarge-data-threshold=
 144 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(65536)
 145 Data greater than given threshold will go into .ldata section in x86-64 medium model
 146
 147 mcmodel=
 148 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
 149 Use given x86-64 code model
 150
 151 Enum
 152 Name(cmodel) Type(enum cmodel)
 153 Known code models (for use with the -mcmodel= option):
 154
 155 EnumValue
 156 Enum(cmodel) String(small) Value(CM_SMALL)
 157
 158 EnumValue
 159 Enum(cmodel) String(medium) Value(CM_MEDIUM)
 160
 161 EnumValue
 162 Enum(cmodel) String(large) Value(CM_LARGE)
 163
 164 EnumValue
 165 Enum(cmodel) String(32) Value(CM_32)
 166
 167 EnumValue
 168 Enum(cmodel) String(kernel) Value(CM_KERNEL)
 169
 170 maddress-mode=
 171 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
 172 Use given address mode
 173
 174 Enum
 175 Name(pmode) Type(enum pmode)
 176 Known address mode (for use with the -maddress-mode= option):
 177
 178 EnumValue
 179 Enum(pmode) String(short) Value(PMODE_SI)
 180
 181 EnumValue
 182 Enum(pmode) String(long) Value(PMODE_DI)
 183
 184 mcpu=
 185 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
 186
 187 mfancy-math-387
 188 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
 189 Generate sin, cos, sqrt for FPU
 190
 191 mforce-drap
 192 Target Report Var(ix86_force_drap)
 193 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
 194
 195 mfp-ret-in-387
 196 Target Report Mask(FLOAT_RETURNS) Save
 197 Return values of functions in FPU registers
 198
 199 mfpmath=
 200 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
 201 Generate floating point mathematics using given instruction set
 202
 203 Enum
 204 Name(fpmath_unit) Type(enum fpmath_unit)
 205 Valid arguments to -mfpmath=:
 206
 207 EnumValue
 208 Enum(fpmath_unit) String(387) Value(FPMATH_387)
 209
 210 EnumValue
 211 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
 212
 213 EnumValue
 214 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 215
 216 EnumValue
 217 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 218
 219 EnumValue
 220 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 221
 222 EnumValue
 223 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 224
 225 EnumValue
 226 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
 227
 228 mhard-float
 229 Target RejectNegative Mask(80387) Save
 230 Use hardware fp
 231
 232 mieee-fp
 233 Target Report Mask(IEEE_FP) Save
 234 Use IEEE math for fp comparisons
 235
 236 minline-all-stringops
 237 Target Report Mask(INLINE_ALL_STRINGOPS) Save
 238 Inline all known string operations
 239
 240 minline-stringops-dynamically
 241 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
 242 Inline memset/memcpy string operations, but perform inline version only for small blocks
 243
 244 mintel-syntax
 245 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
 246 ;; Deprecated
 247
 248 mms-bitfields
 249 Target Report Mask(MS_BITFIELD_LAYOUT) Save
 250 Use native (MS) bitfield layout
 251
 252 mno-align-stringops
 253 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
 254
 255 mno-fancy-math-387
 256 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
 257
 258 mno-push-args
 259 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
 260
 261 mno-red-zone
 262 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
 263
 264 momit-leaf-frame-pointer
 265 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
 266 Omit the frame pointer in leaf functions
 267
 268 mpc32
 269 Target RejectNegative Report
 270 Set 80387 floating-point precision to 32-bit
 271
 272 mpc64
 273 Target RejectNegative Report
 274 Set 80387 floating-point precision to 64-bit
 275
 276 mpc80
 277 Target RejectNegative Report
 278 Set 80387 floating-point precision to 80-bit
 279
 280 mpreferred-stack-boundary=
 281 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
 282 Attempt to keep stack aligned to this power of 2
 283
 284 mincoming-stack-boundary=
 285 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
 286 Assume incoming stack aligned to this power of 2
 287
 288 mpush-args
 289 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
 290 Use push instructions to save outgoing arguments
 291
 292 mred-zone
 293 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
 294 Use red-zone in the x86-64 code
 295
 296 mregparm=
 297 Target RejectNegative Joined UInteger Var(ix86_regparm)
 298 Number of registers used to pass integer arguments
 299
 300 mrtd
 301 Target Report Mask(RTD) Save
 302 Alternate calling convention
 303
 304 msoft-float
 305 Target InverseMask(80387) Save
 306 Do not use hardware fp
 307
 308 msseregparm
 309 Target RejectNegative Mask(SSEREGPARM) Save
 310 Use SSE register passing conventions for SF and DF mode
 311
 312 mstackrealign
 313 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
 314 Realign stack in prologue
 315
 316 mstack-arg-probe
 317 Target Report Mask(STACK_PROBE) Save
 318 Enable stack probing
 319
 320 mstringop-strategy=
 321 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
 322 Chose strategy to generate stringop using
 323
 324 Enum
 325 Name(stringop_alg) Type(enum stringop_alg)
 326 Valid arguments to -mstringop-strategy=:
 327
 328 EnumValue
 329 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
 330
 331 EnumValue
 332 Enum(stringop_alg) String(libcall) Value(libcall)
 333
 334 EnumValue
 335 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
 336
 337 EnumValue
 338 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
 339
 340 EnumValue
 341 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
 342
 343 EnumValue
 344 Enum(stringop_alg) String(loop) Value(loop)
 345
 346 EnumValue
 347 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
 348
 349 mtls-dialect=
 350 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
 351 Use given thread-local storage dialect
 352
 353 Enum
 354 Name(tls_dialect) Type(enum tls_dialect)
 355 Known TLS dialects (for use with the -mtls-dialect= option):
 356
 357 EnumValue
 358 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
 359
 360 EnumValue
 361 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
 362
 363 mtls-direct-seg-refs
 364 Target Report Mask(TLS_DIRECT_SEG_REFS)
 365 Use direct references against %gs when accessing tls data
 366
 367 mtune=
 368 Target RejectNegative Joined Var(ix86_tune_string)
 369 Schedule code for given CPU
 370
 371 mabi=
 372 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
 373 Generate code that conforms to the given ABI
 374
 375 Enum
 376 Name(calling_abi) Type(enum calling_abi)
 377 Known ABIs (for use with the -mabi= option):
 378
 379 EnumValue
 380 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
 381
 382 EnumValue
 383 Enum(calling_abi) String(ms) Value(MS_ABI)
 384
 385 mveclibabi=
 386 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
 387 Vector library ABI to use
 388
 389 Enum
 390 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
 391 Known vectorization library ABIs (for use with the -mveclibabi= option):
 392
 393 EnumValue
 394 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
 395
 396 EnumValue
 397 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
 398
 399 mvect8-ret-in-mem
 400 Target Report Mask(VECT8_RETURNS) Save
 401 Return 8-byte vectors in memory
 402
 403 mrecip
 404 Target Report Mask(RECIP) Save
 405 Generate reciprocals instead of divss and sqrtss.
 406
 407 mrecip=
 408 Target Report RejectNegative Joined Var(ix86_recip_name)
 409 Control generation of reciprocal estimates.
 410
 411 mcld
 412 Target Report Mask(CLD) Save
 413 Generate cld instruction in the function prologue.
 414
 415 mvzeroupper
 416 Target Report Mask(VZEROUPPER) Save
 417 Generate vzeroupper instruction before a transfer of control flow out of
 418 the function.
 419
 420 mdispatch-scheduler
 421 Target RejectNegative Var(flag_dispatch_scheduler)
 422 Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling
 423 is selected.
 424
 425 mprefer-avx128
 426 Target Report Mask(PREFER_AVX128) SAVE
 427 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
 428
 429 ;; ISA support
 430
 431 m32
 432 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
 433 Generate 32bit i386 code
 434
 435 m64
 436 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
 437 Generate 64bit x86-64 code
 438
 439 mx32
 440 Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
 441 Generate 32bit x86-64 code
 442
 443 mmmx
 444 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
 445 Support MMX built-in functions
 446
 447 m3dnow
 448 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
 449 Support 3DNow! built-in functions
 450
 451 m3dnowa
 452 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
 453 Support Athlon 3Dnow! built-in functions
 454
 455 msse
 456 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
 457 Support MMX and SSE built-in functions and code generation
 458
 459 msse2
 460 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
 461 Support MMX, SSE and SSE2 built-in functions and code generation
 462
 463 msse3
 464 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
 465 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
 466
 467 mssse3
 468 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
 469 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
 470
 471 msse4.1
 472 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 473 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
 474
 475 msse4.2
 476 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 477 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
 478
 479 msse4
 480 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
 481 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
 482
 483 mno-sse4
 484 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
 485 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
 486
 487 msse5
 488 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
 489 ;; Deprecated
 490
 491 mavx
 492 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
 493 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
 494
 495 mavx2
 496 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
 497 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation
 498
 499 mfma
 500 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
 501 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
 502
 503 msse4a
 504 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
 505 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
 506
 507 mfma4
 508 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
 509 Support FMA4 built-in functions and code generation
 510
 511 mxop
 512 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
 513 Support XOP built-in functions and code generation
 514
 515 mlwp
 516 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
 517 Support LWP built-in functions and code generation
 518
 519 mabm
 520 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
 521 Support code generation of Advanced Bit Manipulation (ABM) instructions.
 522
 523 mpopcnt
 524 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
 525 Support code generation of popcnt instruction.
 526
 527 mbmi
 528 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
 529 Support BMI built-in functions and code generation
 530
 531 mbmi2
 532 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
 533 Support BMI2 built-in functions and code generation
 534
 535 mlzcnt
 536 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
 537 Support LZCNT built-in function and code generation
 538
 539 mhle
 540 Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
 541 Support Hardware Lock Elision prefixes
 542
 543 mrdseed
 544 Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
 545 Support RDSEED instruction
 546
 547 mprfchw
 548 Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
 549 Support PREFETCHW instruction
 550
 551 madx
 552 Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
 553 Support flag-preserving add-carry instructions
 554
 555 mfxsr
 556 Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
 557 Support FXSAVE and FXRSTOR instructions
 558
 559 mxsave
 560 Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
 561 Support XSAVE and XRSTOR instructions
 562
 563 mxsaveopt
 564 Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
 565 Support XSAVEOPT instruction
 566
 567 mtbm
 568 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
 569 Support TBM built-in functions and code generation
 570
 571 mcx16
 572 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save
 573 Support code generation of cmpxchg16b instruction.
 574
 575 msahf
 576 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
 577 Support code generation of sahf instruction in 64bit x86-64 code.
 578
 579 mmovbe
 580 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save
 581 Support code generation of movbe instruction.
 582
 583 mcrc32
 584 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
 585 Support code generation of crc32 instruction.
 586
 587 maes
 588 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
 589 Support AES built-in functions and code generation
 590
 591 mpclmul
 592 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
 593 Support PCLMUL built-in functions and code generation
 594
 595 msse2avx
 596 Target Report Var(ix86_sse2avx)
 597 Encode SSE instructions with VEX prefix
 598
 599 mfsgsbase
 600 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
 601 Support FSGSBASE built-in functions and code generation
 602
 603 mrdrnd
 604 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
 605 Support RDRND built-in functions and code generation
 606
 607 mf16c
 608 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
 609 Support F16C built-in functions and code generation
 610
 611 mfentry
 612 Target Report Var(flag_fentry) Init(-1)
 613 Emit profiling counter call at function entry before prologue.
 614
 615 m8bit-idiv
 616 Target Report Mask(USE_8BIT_IDIV) Save
 617 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check
 618
 619 mavx256-split-unaligned-load
 620 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
 621 Split 32-byte AVX unaligned load
 622
 623 mavx256-split-unaligned-store
 624 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
 625 Split 32-byte AVX unaligned store
 626
 627 mrtm
 628 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
 629 Support RTM built-in functions and code generation