1 ; Options for the IA-32 and AMD64 ports of the compiler.
3 ; Copyright (C) 2005-2019 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
22 config/i386/i386-opts.h
24 ; Bit flags that specify the ISA we are compiling for.
26 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT
29 HOST_WIDE_INT ix86_isa_flags2 = 0
31 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared
32 ; on the command line.
34 HOST_WIDE_INT ix86_isa_flags_explicit
37 HOST_WIDE_INT ix86_isa_flags2_explicit
39 ; Additional target flags
44 int recip_mask = RECIP_MASK_DEFAULT
47 int recip_mask_explicit
50 int x_recip_mask_explicit
52 ;; Definitions to add to the cl_target_option structure
61 ;; -march= processor-string
63 const char *x_ix86_arch_string
65 ;; -mtune= processor-string
67 const char *x_ix86_tune_string
71 unsigned char schedule
73 ;; True if processor has SSE prefetch instruction.
75 unsigned char prefetch_sse
79 unsigned char branch_cost
81 ;; which flags were passed by the user
83 HOST_WIDE_INT x_ix86_isa_flags2_explicit
85 ;; which flags were passed by the user
87 HOST_WIDE_INT x_ix86_isa_flags_explicit
89 ;; whether -mtune was not specified
91 unsigned char tune_defaulted
93 ;; whether -march was specified
95 unsigned char arch_specified
99 enum cmodel x_ix86_cmodel
103 enum calling_abi x_ix86_abi
107 enum asm_dialect x_ix86_asm_dialect
111 int x_ix86_branch_cost
113 ;; -mdump-tune-features=
115 int x_ix86_dump_tunes
119 int x_ix86_force_align_arg_pointer
123 int x_ix86_force_drap
125 ;; -mincoming-stack-boundary=
127 int x_ix86_incoming_stack_boundary_arg
131 enum pmode x_ix86_pmode
133 ;; -mpreferred-stack-boundary=
135 int x_ix86_preferred_stack_boundary_arg
139 const char *x_ix86_recip_name
145 ;; -mlarge-data-threshold=
147 int x_ix86_section_threshold
153 ;; -mstack-protector-guard=
155 enum stack_protector_guard x_ix86_stack_protector_guard
157 ;; -mstringop-strategy=
159 enum stringop_alg x_ix86_stringop_alg
163 enum tls_dialect x_ix86_tls_dialect
167 const char *x_ix86_tune_ctrl_string
169 ;; -mmemcpy-strategy=
171 const char *x_ix86_tune_memcpy_strategy
173 ;; -mmemset-strategy=
175 const char *x_ix86_tune_memset_strategy
179 int x_ix86_tune_no_default
183 enum ix86_veclibabi x_ix86_veclibabi_type
185 ;; -mprefer-vector-width=
187 enum prefer_vector_width x_prefer_vector_width_type
191 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
192 sizeof(long double) is 16.
195 Target Report Mask(80387) Save
199 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
200 sizeof(long double) is 12.
203 Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save
204 Use 80-bit long double.
207 Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save
208 Use 64-bit long double.
211 Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save
212 Use 128-bit long double.
214 maccumulate-outgoing-args
215 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
216 Reserve space for outgoing arguments in the function prologue.
219 Target Report Mask(ALIGN_DOUBLE) Save
220 Align some doubles on dword boundary.
223 Target RejectNegative Joined UInteger
224 Function starts are aligned to this power of 2.
227 Target RejectNegative Joined UInteger
228 Jump targets are aligned to this power of 2.
231 Target RejectNegative Joined UInteger
232 Loop code aligned to this power of 2.
235 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
236 Align destination of the string operations.
239 Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat)
240 Use the given data alignment.
243 Name(ix86_align_data) Type(enum ix86_align_data)
244 Known data alignment choices (for use with the -malign-data= option):
247 Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat)
250 Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi)
253 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)
256 Target RejectNegative Negative(march=) Joined Var(ix86_arch_string)
257 Generate code for given CPU.
260 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT)
261 Use given assembler dialect.
264 Name(asm_dialect) Type(enum asm_dialect)
265 Known assembler dialects (for use with the -masm= option):
268 Enum(asm_dialect) String(intel) Value(ASM_INTEL)
271 Enum(asm_dialect) String(att) Value(ASM_ATT)
274 Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5)
275 Branches are this expensive (arbitrary units).
277 mlarge-data-threshold=
278 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD)
279 -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model.
282 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32)
283 Use given x86-64 code model.
286 Name(cmodel) Type(enum cmodel)
287 Known code models (for use with the -mcmodel= option):
290 Enum(cmodel) String(small) Value(CM_SMALL)
293 Enum(cmodel) String(medium) Value(CM_MEDIUM)
296 Enum(cmodel) String(large) Value(CM_LARGE)
299 Enum(cmodel) String(32) Value(CM_32)
302 Enum(cmodel) String(kernel) Value(CM_KERNEL)
305 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI)
306 Use given address mode.
309 Name(pmode) Type(enum pmode)
310 Known address mode (for use with the -maddress-mode= option):
313 Enum(pmode) String(short) Value(PMODE_SI)
316 Enum(pmode) String(long) Value(PMODE_DI)
319 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead)
322 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
323 Generate sin, cos, sqrt for FPU.
326 Target Report Var(ix86_force_drap)
327 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack.
330 Target Report Mask(FLOAT_RETURNS) Save
331 Return values of functions in FPU registers.
334 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save
335 Generate floating point mathematics using given instruction set.
338 Name(fpmath_unit) Type(enum fpmath_unit)
339 Valid arguments to -mfpmath=:
342 Enum(fpmath_unit) String(387) Value(FPMATH_387)
345 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE)
348 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
351 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
354 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
357 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
360 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)})
363 Target RejectNegative Mask(80387) Save
367 Target Report Mask(IEEE_FP) Save
368 Use IEEE math for fp comparisons.
370 minline-all-stringops
371 Target Report Mask(INLINE_ALL_STRINGOPS) Save
372 Inline all known string operations.
374 minline-stringops-dynamically
375 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
376 Inline memset/memcpy string operations, but perform inline version only for small blocks.
379 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead)
383 Target Report Mask(MS_BITFIELD_LAYOUT) Save
384 Use native (MS) bitfield layout.
387 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
390 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
393 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
396 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
398 momit-leaf-frame-pointer
399 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
400 Omit the frame pointer in leaf functions.
403 Target RejectNegative Report
404 Set 80387 floating-point precision to 32-bit.
407 Target RejectNegative Report
408 Set 80387 floating-point precision to 64-bit.
411 Target RejectNegative Report
412 Set 80387 floating-point precision to 80-bit.
414 mpreferred-stack-boundary=
415 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg)
416 Attempt to keep stack aligned to this power of 2.
418 mincoming-stack-boundary=
419 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg)
420 Assume incoming stack aligned to this power of 2.
423 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
424 Use push instructions to save outgoing arguments.
427 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
428 Use red-zone in the x86-64 code.
431 Target RejectNegative Joined UInteger Var(ix86_regparm)
432 Number of registers used to pass integer arguments.
435 Target Report Mask(RTD) Save
436 Alternate calling convention.
439 Target InverseMask(80387) Save
440 Do not use hardware fp.
443 Target RejectNegative Mask(SSEREGPARM) Save
444 Use SSE register passing conventions for SF and DF mode.
447 Target Report Var(ix86_force_align_arg_pointer)
448 Realign stack in prologue.
451 Target Report Mask(STACK_PROBE) Save
452 Enable stack probing.
455 Target RejectNegative Joined Var(ix86_tune_memcpy_strategy)
456 Specify memcpy expansion strategy when expected size is known.
459 Target RejectNegative Joined Var(ix86_tune_memset_strategy)
460 Specify memset expansion strategy when expected size is known.
463 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop)
464 Chose strategy to generate stringop using.
467 Name(stringop_alg) Type(enum stringop_alg)
468 Valid arguments to -mstringop-strategy=:
471 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte)
474 Enum(stringop_alg) String(libcall) Value(libcall)
477 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte)
480 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte)
483 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte)
486 Enum(stringop_alg) String(loop) Value(loop)
489 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop)
492 Enum(stringop_alg) String(vector_loop) Value(vector_loop)
495 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU)
496 Use given thread-local storage dialect.
499 Name(tls_dialect) Type(enum tls_dialect)
500 Known TLS dialects (for use with the -mtls-dialect= option):
503 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU)
506 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2)
509 Target Report Mask(TLS_DIRECT_SEG_REFS)
510 Use direct references against %gs when accessing tls data.
513 Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string)
514 Schedule code for given CPU.
517 Target RejectNegative Joined Var(ix86_tune_ctrl_string)
518 Fine grain control of tune features.
521 Target RejectNegative Var(ix86_tune_no_default)
522 Clear all tune features.
525 Target RejectNegative Var(ix86_dump_tunes)
528 Target Report Mask(IAMCU)
529 Generate code that conforms to Intel MCU psABI.
532 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI)
533 Generate code that conforms to the given ABI.
536 Name(calling_abi) Type(enum calling_abi)
537 Known ABIs (for use with the -mabi= option):
540 Enum(calling_abi) String(sysv) Value(SYSV_ABI)
543 Enum(calling_abi) String(ms) Value(MS_ABI)
545 mcall-ms2sysv-xlogues
546 Target Report Mask(CALL_MS2SYSV_XLOGUES) Save
547 Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls.
550 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none)
551 Vector library ABI to use.
554 Name(ix86_veclibabi) Type(enum ix86_veclibabi)
555 Known vectorization library ABIs (for use with the -mveclibabi= option):
558 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml)
561 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml)
564 Target Report Mask(VECT8_RETURNS) Save
565 Return 8-byte vectors in memory.
568 Target Report Mask(RECIP) Save
569 Generate reciprocals instead of divss and sqrtss.
572 Target Report RejectNegative Joined Var(ix86_recip_name)
573 Control generation of reciprocal estimates.
576 Target Report Mask(CLD) Save
577 Generate cld instruction in the function prologue.
580 Target Report Mask(VZEROUPPER) Save
581 Generate vzeroupper instruction before a transfer of control flow out of
585 Target Report Mask(STV) Save
586 Disable Scalar to Vector optimization pass transforming 64-bit integer
587 computations into a vector ones.
590 Target RejectNegative Var(flag_dispatch_scheduler)
591 Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
592 or znver1 and Haifa scheduling is selected.
595 Target Alias(mprefer-vector-width=, 128, 256)
596 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
598 mprefer-vector-width=
599 Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
600 Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
603 Name(prefer_vector_width) Type(enum prefer_vector_width)
604 Known preferred register vector length (to use with the -mprefer-vector-width= option):
607 Enum(prefer_vector_width) String(none) Value(PVW_NONE)
610 Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
613 Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
616 Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
621 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
622 Generate 32bit i386 code.
625 Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save
626 Generate 64bit x86-64 code.
629 Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save
630 Generate 32bit x86-64 code.
633 Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save
634 Generate 16bit i386 code.
637 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save
638 Support MMX built-in functions.
641 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save
642 Support 3DNow! built-in functions.
645 Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
646 Support Athlon 3Dnow! built-in functions.
649 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save
650 Support MMX and SSE built-in functions and code generation.
653 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save
654 Support MMX, SSE and SSE2 built-in functions and code generation.
657 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save
658 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
661 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save
662 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation.
665 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save
666 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation.
669 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
670 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
673 Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save
674 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation.
677 Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save
678 Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
681 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed)
685 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save
686 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation.
689 Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save
690 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation.
693 Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save
694 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation.
697 Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save
698 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation.
701 Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save
702 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation.
705 Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save
706 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation.
709 Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save
710 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation.
713 Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save
714 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation.
717 Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save
718 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation.
721 Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save
722 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation.
725 Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save
726 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation.
729 Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save
730 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation.
733 Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save
734 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation.
737 Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save
738 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation.
741 Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save
742 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation.
745 Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save
746 Support AVX512VNNI built-in functions and code generation.
749 Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save
750 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation.
753 Target Report Mask(ISA_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save
754 Support AVX512VP2INTERSECT built-in functions and code generation.
757 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save
758 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation.
761 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save
762 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation.
765 Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save
766 Support FMA4 built-in functions and code generation.
769 Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save
770 Support XOP built-in functions and code generation.
773 Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save
774 Support LWP built-in functions and code generation.
777 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save
778 Support code generation of Advanced Bit Manipulation (ABM) instructions.
781 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save
782 Support code generation of popcnt instruction.
785 Target Report Mask(ISA_PCONFIG) Var(ix86_isa_flags2) Save
786 Support PCONFIG built-in functions and code generation.
789 Target Report Mask(ISA_WBNOINVD) Var(ix86_isa_flags2) Save
790 Support WBNOINVD built-in functions and code generation.
793 Target Report Mask(ISA_PTWRITE) Var(ix86_isa_flags2) Save
794 Support PTWRITE built-in functions and code generation.
797 Target Report Mask(ISA_SGX) Var(ix86_isa_flags2) Save
798 Support SGX built-in functions and code generation.
801 Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save
802 Support RDPID built-in functions and code generation.
805 Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save
806 Support GFNI built-in functions and code generation.
809 Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save
810 Support VAES built-in functions and code generation.
813 Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save
814 Support VPCLMULQDQ built-in functions and code generation.
817 Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save
818 Support BMI built-in functions and code generation.
821 Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save
822 Support BMI2 built-in functions and code generation.
825 Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save
826 Support LZCNT built-in function and code generation.
829 Target Report Mask(ISA_HLE) Var(ix86_isa_flags2) Save
830 Support Hardware Lock Elision prefixes.
833 Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
834 Support RDSEED instruction.
837 Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
838 Support PREFETCHW instruction.
841 Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save
842 Support flag-preserving add-carry instructions.
845 Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save
846 Support CLFLUSHOPT instructions.
849 Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save
850 Support CLWB instruction.
857 Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save
858 Support FXSAVE and FXRSTOR instructions.
861 Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save
862 Support XSAVE and XRSTOR instructions.
865 Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save
866 Support XSAVEOPT instruction.
869 Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save
870 Support XSAVEC instructions.
873 Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save
874 Support XSAVES and XRSTORS instructions.
877 Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save
878 Support TBM built-in functions and code generation.
881 Target Report Mask(ISA_CX16) Var(ix86_isa_flags2) Save
882 Support code generation of cmpxchg16b instruction.
885 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save
886 Support code generation of sahf instruction in 64bit x86-64 code.
889 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags2) Save
890 Support code generation of movbe instruction.
893 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save
894 Support code generation of crc32 instruction.
897 Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save
898 Support AES built-in functions and code generation.
901 Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save
902 Support SHA1 and SHA256 built-in functions and code generation.
905 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save
906 Support PCLMUL built-in functions and code generation.
909 Target Report Var(ix86_sse2avx)
910 Encode SSE instructions with VEX prefix.
913 Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save
914 Support FSGSBASE built-in functions and code generation.
917 Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save
918 Support RDRND built-in functions and code generation.
921 Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save
922 Support F16C built-in functions and code generation.
925 Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save
926 Support PREFETCHWT1 built-in functions and code generation.
929 Target Report Var(flag_fentry)
930 Emit profiling counter call at function entry before prologue.
933 Target Report Var(flag_record_mcount)
934 Generate __mcount_loc section with all mcount or __fentry__ calls.
937 Target Report Var(flag_nop_mcount)
938 Generate mcount/__fentry__ calls as nops. To activate they need to be
942 Target RejectNegative Joined Var(fentry_name)
943 Set name of __fentry__ symbol called at function entry.
946 Target RejectNegative Joined Var(fentry_section)
947 Set name of section to record mrecord-mcount calls.
950 Target Report Var(flag_skip_rax_setup)
951 Skip setting up RAX register when passing variable arguments.
954 Target Report Mask(USE_8BIT_IDIV) Save
955 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check.
957 mavx256-split-unaligned-load
958 Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save
959 Split 32-byte AVX unaligned load.
961 mavx256-split-unaligned-store
962 Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save
963 Split 32-byte AVX unaligned store.
966 Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save
967 Support RTM built-in functions and code generation.
971 Removed in GCC 9. This switch has no effect.
974 Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags2) Save
975 Support MWAITX and MONITORX built-in functions and code generation.
978 Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags2) Save
979 Support CLZERO built-in functions and code generation.
982 Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save
983 Support PKU built-in functions and code generation.
985 mstack-protector-guard=
986 Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS)
987 Use given stack-protector guard.
990 Name(stack_protector_guard) Type(enum stack_protector_guard)
991 Known stack protector guard (for use with the -mstack-protector-guard= option):
994 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
997 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
999 mstack-protector-guard-reg=
1000 Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str)
1001 Use the given base register for addressing the stack-protector guard.
1004 addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC
1006 mstack-protector-guard-offset=
1007 Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str)
1008 Use the given offset for addressing the stack-protector guard.
1011 HOST_WIDE_INT ix86_stack_protector_guard_offset = 0
1013 mstack-protector-guard-symbol=
1014 Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str)
1015 Use the given symbol for addressing the stack-protector guard.
1022 Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
1023 Generate code which uses only the general registers.
1026 Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save
1027 Enable shadow stack built-in functions from Control-flow Enforcement
1031 Target Report Undocumented Var(flag_cet_switch) Init(0)
1032 Turn on CET instrumentation for switch statements that use a jump table and
1036 Target Report Var(flag_manual_endbr) Init(0)
1037 Insert ENDBR instruction at function entry only via cf_check attribute
1038 for CET instrumentation.
1040 mforce-indirect-call
1041 Target Report Var(flag_force_indirect_call) Init(0)
1042 Make all function calls indirect.
1045 Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep)
1046 Convert indirect call and jump to call and return thunks.
1049 Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep)
1050 Convert function return to call and return thunk.
1053 Name(indirect_branch) Type(enum indirect_branch)
1054 Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options):
1057 Enum(indirect_branch) String(keep) Value(indirect_branch_keep)
1060 Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk)
1063 Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline)
1066 Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern)
1068 mindirect-branch-register
1069 Target Report Var(ix86_indirect_branch_register) Init(0)
1070 Force indirect call and jump via register.
1073 Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save
1074 Support MOVDIRI built-in functions and code generation.
1077 Target Report Mask(ISA_MOVDIR64B) Var(ix86_isa_flags2) Save
1078 Support MOVDIR64B built-in functions and code generation.
1081 Target Report Mask(ISA_WAITPKG) Var(ix86_isa_flags2) Save
1082 Support WAITPKG built-in functions and code generation.
1085 Target Report Mask(ISA_CLDEMOTE) Var(ix86_isa_flags2) Save
1086 Support CLDEMOTE built-in functions and code generation.
1089 Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none)
1090 Instrument function exit in instrumented functions with __fentry__.
1093 Name(instrument_return) Type(enum instrument_return)
1094 Known choices for return instrumentation with -minstrument-return=:
1097 Enum(instrument_return) String(none) Value(instrument_return_none)
1100 Enum(instrument_return) String(call) Value(instrument_return_call)
1103 Enum(instrument_return) String(nop5) Value(instrument_return_nop5)
1106 Target Report Var(ix86_flag_record_return) Init(0)
1107 Generate a __return_loc section pointing to all return instrumentation code.
1110 Target Report Mask(ISA_AVX512BF16) Var(ix86_isa_flags2) Save
1111 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and
1112 AVX512BF16 built-in functions and code generation.
1115 Target Report Mask(ISA_ENQCMD) Var(ix86_isa_flags2) Save
1116 Support ENQCMD built-in functions and code generation.