1 ;; GCC machine description for AVX512F instructions
2 ;; Copyright (C) 2013-2016 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Some iterators for extending subst as much as possible
21 ;; All vectors (Use it for destination)
22 (define_mode_iterator SUBST_V
30 (define_mode_iterator SUBST_S
33 (define_mode_iterator SUBST_A
43 (define_subst_attr "mask_name" "mask" "" "_mask")
44 (define_subst_attr "mask_applied" "mask" "false" "true")
45 (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
46 (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
47 (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
48 (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
49 (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
50 (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
51 (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
52 (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
53 (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
54 (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
55 (define_subst_attr "mask_codefor" "mask" "*" "")
56 (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
57 (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
58 (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
59 (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
60 (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
61 (define_subst_attr "store_mask_constraint" "mask" "vm" "v")
62 (define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
63 (define_subst_attr "mask_prefix" "mask" "vex" "evex")
64 (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
65 (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex")
66 (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex")
67 (define_subst_attr "mask_expand_op3" "mask" "3" "5")
70 [(set (match_operand:SUBST_V 0)
71 (match_operand:SUBST_V 1))]
76 (match_operand:SUBST_V 2 "vector_move_operand" "0C")
77 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
79 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
80 (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
81 (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
83 (define_subst "mask_scalar_merge"
84 [(set (match_operand:SUBST_S 0)
85 (match_operand:SUBST_S 1))]
90 (match_operand:SUBST_S 3 "register_operand" "Yk")))])
92 (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
93 (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
94 (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
95 (define_subst_attr "sd_mask_codefor" "sd" "*" "")
96 (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
99 [(set (match_operand:SUBST_V 0)
100 (match_operand:SUBST_V 1))]
105 (match_operand:SUBST_V 2 "const0_operand" "C")
106 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
109 (define_subst_attr "round_name" "round" "" "_round")
110 (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
111 (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
112 (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
113 (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
114 (define_subst_attr "round_op2" "round" "" "%R2")
115 (define_subst_attr "round_op3" "round" "" "%R3")
116 (define_subst_attr "round_op4" "round" "" "%R4")
117 (define_subst_attr "round_op5" "round" "" "%R5")
118 (define_subst_attr "round_op6" "round" "" "%R6")
119 (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
120 (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
121 (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
122 (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
123 (define_subst_attr "round_constraint" "round" "vm" "v")
124 (define_subst_attr "round_constraint2" "round" "m" "v")
125 (define_subst_attr "round_constraint3" "round" "rm" "r")
126 (define_subst_attr "round_nimm_predicate" "round" "nonimmediate_operand" "register_operand")
127 (define_subst_attr "round_prefix" "round" "vex" "evex")
128 (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
129 || <MODE>mode == V8DFmode
130 || <MODE>mode == V8DImode
131 || <MODE>mode == V16SImode)")
132 (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
133 (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
134 (define_subst_attr "round_codefor" "round" "*" "")
135 (define_subst_attr "round_opnum" "round" "5" "6")
137 (define_subst "round"
138 [(set (match_operand:SUBST_A 0)
139 (match_operand:SUBST_A 1))]
144 (unspec [(match_operand:SI 2 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])])
146 (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
147 (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
148 (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
149 (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
150 (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
151 (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
152 (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
153 (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
154 (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
155 (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
156 (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
157 (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
158 (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
159 (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
160 (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
161 (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
162 (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
163 (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
164 (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
165 (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
166 (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
167 || <MODE>mode == V8DFmode
168 || <MODE>mode == V8DImode
169 || <MODE>mode == V16SImode)")
170 (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
172 (define_subst "round_saeonly"
173 [(set (match_operand:SUBST_A 0)
174 (match_operand:SUBST_A 1))]
179 (unspec [(match_operand:SI 2 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])])
181 (define_subst_attr "round_expand_name" "round_expand" "" "_round")
182 (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
183 (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
185 (define_subst "round_expand"
186 [(match_operand:SUBST_V 0)
187 (match_operand:SUBST_V 1)
188 (match_operand:SUBST_V 2)
189 (match_operand:SUBST_V 3)
190 (match_operand:SUBST_S 4)]
197 (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
199 (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
200 (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
201 (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
203 (define_subst "round_saeonly_expand"
204 [(match_operand:SUBST_V 0)
205 (match_operand:SUBST_V 1)
206 (match_operand:SUBST_V 2)
207 (match_operand:SUBST_A 3)
209 (match_operand:SUBST_S 5)]
217 (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
219 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
220 (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
222 (define_subst "mask_expand4"
223 [(match_operand:SUBST_V 0)
224 (match_operand:SUBST_V 1)
225 (match_operand:SUBST_V 2)
226 (match_operand:SI 3)]
232 (match_operand:SUBST_V 4 "vector_move_operand")
233 (match_operand:<avx512fmaskmode> 5 "register_operand")])