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git.ipfire.org Git - thirdparty/gcc.git/blob - gcc/config/i386/x86-tune-sched-atom.c
1 /* Scheduler hooks for IA-32 which implement atom+ specific logic.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #define IN_TARGET_CODE 1
24 #include "coretypes.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
36 #include "sched-int.h"
38 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
39 execution. It is applied if
40 (1) IMUL instruction is on the top of list;
41 (2) There exists the only producer of independent IMUL instruction in
43 Return index of IMUL producer if it was found and -1 otherwise. */
45 do_reorder_for_imul (rtx_insn
**ready
, int n_ready
)
48 rtx set
, insn1
, insn2
;
49 sd_iterator_def sd_it
;
57 /* Check that IMUL instruction is on the top of ready list. */
58 insn
= ready
[n_ready
- 1];
59 set
= single_set (insn
);
62 if (!(GET_CODE (SET_SRC (set
)) == MULT
63 && GET_MODE (SET_SRC (set
)) == SImode
))
66 /* Search for producer of independent IMUL instruction. */
67 for (i
= n_ready
- 2; i
>= 0; i
--)
70 if (!NONDEBUG_INSN_P (insn
))
72 /* Skip IMUL instruction. */
73 insn2
= PATTERN (insn
);
74 if (GET_CODE (insn2
) == PARALLEL
)
75 insn2
= XVECEXP (insn2
, 0, 0);
76 if (GET_CODE (insn2
) == SET
77 && GET_CODE (SET_SRC (insn2
)) == MULT
78 && GET_MODE (SET_SRC (insn2
)) == SImode
)
81 FOR_EACH_DEP (insn
, SD_LIST_FORW
, sd_it
, dep
)
85 if (!NONDEBUG_INSN_P (con
))
87 insn1
= PATTERN (con
);
88 if (GET_CODE (insn1
) == PARALLEL
)
89 insn1
= XVECEXP (insn1
, 0, 0);
91 if (GET_CODE (insn1
) == SET
92 && GET_CODE (SET_SRC (insn1
)) == MULT
93 && GET_MODE (SET_SRC (insn1
)) == SImode
)
95 sd_iterator_def sd_it1
;
97 /* Check if there is no other dependee for IMUL. */
99 FOR_EACH_DEP (con
, SD_LIST_BACK
, sd_it1
, dep1
)
102 pro
= DEP_PRO (dep1
);
103 if (!NONDEBUG_INSN_P (pro
))
118 /* Try to find the best candidate on the top of ready list if two insns
119 have the same priority - candidate is best if its dependees were
120 scheduled earlier. Applied for Silvermont only.
121 Return true if top 2 insns must be interchanged. */
123 swap_top_of_ready_list (rtx_insn
**ready
, int n_ready
)
125 rtx_insn
*top
= ready
[n_ready
- 1];
126 rtx_insn
*next
= ready
[n_ready
- 2];
128 sd_iterator_def sd_it
;
132 #define INSN_TICK(INSN) (HID (INSN)->tick)
134 if (!TARGET_SILVERMONT
&& !TARGET_INTEL
)
137 if (!NONDEBUG_INSN_P (top
))
139 if (!NONJUMP_INSN_P (top
))
141 if (!NONDEBUG_INSN_P (next
))
143 if (!NONJUMP_INSN_P (next
))
145 set
= single_set (top
);
148 set
= single_set (next
);
152 if (INSN_PRIORITY_KNOWN (top
) && INSN_PRIORITY_KNOWN (next
))
154 if (INSN_PRIORITY (top
) != INSN_PRIORITY (next
))
156 /* Determine winner more precise. */
157 FOR_EACH_DEP (top
, SD_LIST_RES_BACK
, sd_it
, dep
)
161 if (!NONDEBUG_INSN_P (pro
))
163 if (INSN_TICK (pro
) > clock1
)
164 clock1
= INSN_TICK (pro
);
166 FOR_EACH_DEP (next
, SD_LIST_RES_BACK
, sd_it
, dep
)
170 if (!NONDEBUG_INSN_P (pro
))
172 if (INSN_TICK (pro
) > clock2
)
173 clock2
= INSN_TICK (pro
);
176 if (clock1
== clock2
)
178 /* Determine winner - load must win. */
179 enum attr_memory memory1
, memory2
;
180 memory1
= get_attr_memory (top
);
181 memory2
= get_attr_memory (next
);
182 if (memory2
== MEMORY_LOAD
&& memory1
!= MEMORY_LOAD
)
185 return (bool) (clock2
< clock1
);
191 /* Perform possible reodering of ready list for Atom/Silvermont only.
192 Return issue rate. */
194 ix86_atom_sched_reorder (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
195 int *pn_ready
, int clock_var
)
198 int n_ready
= *pn_ready
;
203 /* Set up issue rate. */
204 issue_rate
= ix86_issue_rate ();
206 /* Do reodering for BONNELL/SILVERMONT only. */
207 if (!TARGET_BONNELL
&& !TARGET_SILVERMONT
&& !TARGET_INTEL
)
210 /* Nothing to do if ready list contains only 1 instruction. */
214 /* Do reodering for post-reload scheduler only. */
215 if (!reload_completed
)
218 if ((index
= do_reorder_for_imul (ready
, n_ready
)) >= 0)
220 if (sched_verbose
> 1)
221 fprintf (dump
, ";;\tatom sched_reorder: put %d insn on top\n",
222 INSN_UID (ready
[index
]));
224 /* Put IMUL producer (ready[index]) at the top of ready list. */
226 for (i
= index
; i
< n_ready
- 1; i
++)
227 ready
[i
] = ready
[i
+ 1];
228 ready
[n_ready
- 1] = insn
;
232 /* Skip selective scheduling since HID is not populated in it. */
235 && swap_top_of_ready_list (ready
, n_ready
))
237 if (sched_verbose
> 1)
238 fprintf (dump
, ";;\tslm sched_reorder: swap %d and %d insns\n",
239 INSN_UID (ready
[n_ready
- 1]), INSN_UID (ready
[n_ready
- 2]));
240 /* Swap 2 top elements of ready list. */
241 insn
= ready
[n_ready
- 1];
242 ready
[n_ready
- 1] = ready
[n_ready
- 2];
243 ready
[n_ready
- 2] = insn
;