gcc/config/i386/x86-tune.def

   1 /* Definitions of x86 tunable features.
   2    Copyright (C) 2013-2018 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License and
  17 a copy of the GCC Runtime Library Exception along with this program;
  18 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 /* Tuning for a given CPU XXXX consists of:
  22     - adding new CPU into:
  23         - adding PROCESSOR_XXX to processor_type (in i386.h)
  24         - possibly adding XXX into CPU attribute in i386.md
  25         - adding XXX to processor_alias_table (in i386.c)
  26     - introducing ix86_XXX_cost in i386.c
  27         - Stringop generation table can be build based on test_stringop
  28         - script (once rest of tuning is complete)
  29     - designing a scheduler model in
  30         - XXXX.md file
  31         - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
  32         - possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
  33           and ix86_sched_init_global if those tricks are needed.
  34     - Tunning the flags bellow. Those are split into sections and each
  35       section is very roughly ordered by importance.  */
  36
  37 /*****************************************************************************/
  38 /* Scheduling flags.                                                         */
  39 /*****************************************************************************/
  40
  41 /* X86_TUNE_SCHEDULE: Enable scheduling.  */
  42 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
  43           m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  44           | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
  45           | m_GENERIC)
  46
  47 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
  48    on modern chips.  Preffer stores affecting whole integer register
  49    over partial stores.  For example preffer MOVZBL or MOVQ to load 8bit
  50    value over movb.  */
  51 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
  52           m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  53           | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
  54           | m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
  55
  56 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
  57    destinations to be 128bit to allow register renaming on 128bit SSE units,
  58    but usually results in one extra microop on 64bit SSE units.
  59    Experimental results shows that disabling this option on P4 brings over 20%
  60    SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
  61    that can be partly masked by careful scheduling of moves.  */
  62 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
  63           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  64           | m_BDVER | m_ZNVER1 | m_GENERIC)
  65
  66 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
  67    are resolved on SSE register parts instead of whole registers, so we may
  68    maintain just lower part of scalar values in proper format leaving the
  69    upper part undefined.  */
  70 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
  71
  72 /* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of of flags
  73    set by instructions affecting just some flags (in particular shifts).
  74    This is because Core2 resolves dependencies on whole flags register
  75    and such sequences introduce false dependency on previous instruction
  76    setting full flags.
  77
  78    The flags does not affect generation of INC and DEC that is controlled
  79    by X86_TUNE_USE_INCDEC.  */
  80
  81 DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
  82           m_CORE2)
  83
  84 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
  85    partial dependencies.  */
  86 DEF_TUNE (X86_TUNE_MOVX, "movx",
  87           m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  88           | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
  89           | m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
  90
  91 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
  92    full sized loads.  */
  93 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
  94           m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
  95           | m_KNL | m_KNM | m_GOLDMONT | m_AMD_MULTIPLE | m_GENERIC)
  96
  97 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
  98    conditional jump instruction for 32 bit TARGET.  */
  99 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
 100           m_CORE_ALL | m_BDVER | m_ZNVER1 | m_GENERIC)
 101
 102 /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
 103    conditional jump instruction for TARGET_64BIT.  */
 104 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
 105           m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1 | m_GENERIC)
 106
 107 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
 108    subsequent conditional jump instruction when the condition jump
 109    check sign flag (SF) or overflow flag (OF).  */
 110 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
 111           m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_BDVER | m_ZNVER1 | m_GENERIC)
 112
 113 /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
 114    jump instruction when the alu instruction produces the CCFLAG consumed by
 115    the conditional jump instruction. */
 116 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
 117           m_SANDYBRIDGE | m_HASWELL | m_GENERIC)
 118
 119
 120 /*****************************************************************************/
 121 /* Function prologue, epilogue and function calling sequences.               */
 122 /*****************************************************************************/
 123
 124 /* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
 125    arguments in prologue/epilogue instead of separately for each call
 126    by push/pop instructions.
 127    This increase code size by about 5% in 32bit mode, less so in 64bit mode
 128    because parameters are passed in registers.  It is considerable
 129    win for targets without stack engine that prevents multple push operations
 130    to happen in parallel.  */
 131
 132 DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
 133           m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
 134           | m_GOLDMONT | m_ATHLON_K8)
 135
 136 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
 137    considered on critical path.  */
 138 DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
 139           m_PPRO | m_ATHLON_K8)
 140
 141 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
 142    considered on critical path.  */
 143 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
 144           m_PPRO | m_ATHLON_K8)
 145
 146 /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
 147 DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
 148           m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
 149
 150 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
 151    Some chips, like 486 and Pentium works faster with separate load
 152    and push instructions.  */
 153 DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
 154           m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
 155           | m_GENERIC)
 156
 157 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
 158    over esp subtraction.  */
 159 DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
 160           | m_LAKEMONT | m_K6_GEODE)
 161
 162 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
 163    over esp subtraction.  */
 164 DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMONT
 165           | m_K6_GEODE)
 166
 167 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
 168    over esp addition.  */
 169 DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT
 170           | m_LAKEMONT | m_PPRO)
 171
 172 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
 173    over esp addition.  */
 174 DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMONT)
 175
 176 /*****************************************************************************/
 177 /* Branch predictor tuning                                                   */
 178 /*****************************************************************************/
 179
 180 /* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
 181    instructions long.  */
 182 DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
 183
 184 /* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
 185    of conditional jump or directly preceded by other jump instruction.
 186    This is important for AND K8-AMDFAM10 because the branch prediction
 187    architecture expect at most one jump per 2 byte window.  Failing to
 188    pad returns leads to misaligned return stack.  */
 189 DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
 190           m_ATHLON_K8 | m_AMDFAM10)
 191
 192 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
 193    than 4 branch instructions in the 16 byte window.  */
 194 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
 195           m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
 196           | m_GOLDMONT | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
 197
 198 /*****************************************************************************/
 199 /* Integer instruction selection tuning                                      */
 200 /*****************************************************************************/
 201
 202 /* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
 203    at -O3.  For the moment, the prefetching seems badly tuned for Intel
 204    chips.  */
 205 DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
 206           m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
 207
 208 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
 209    on 16-bit immediate moves into memory on Core2 and Corei7.  */
 210 DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
 211
 212 /* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
 213    as "add mem, reg".  */
 214 DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
 215
 216 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
 217
 218    Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
 219    Sandy bridge and Ivy bridge generate extra uop.  On Haswell this extra uop
 220    is output only when the values needs to be really merged, which is not
 221    done by GCC generated code.  */
 222 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
 223           ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
 224             | m_BONNELL | m_SILVERMONT | m_INTEL |  m_KNL | m_KNM | m_GOLDMONT
 225             | m_GENERIC))
 226
 227 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
 228    for DFmode copies */
 229 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
 230           ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 231             | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
 232             | m_GENERIC))
 233
 234 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
 235    will impact LEA instruction selection. */
 236 DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
 237          | m_KNM | m_GOLDMONT | m_INTEL)
 238
 239 /* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation.  */
 240 DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
 241           m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM)
 242
 243 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
 244    vector path on AMD machines.
 245    FIXME: Do we need to enable this for core? */
 246 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
 247           m_K8 | m_AMDFAM10)
 248
 249 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
 250    machines.
 251    FIXME: Do we need to enable this for core? */
 252 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
 253           m_K8 | m_AMDFAM10)
 254
 255 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
 256    a conditional move.  */
 257 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
 258           m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL)
 259
 260 /* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
 261    as MOVS and STOS (without a REP prefix) to move/set sequences of bytes.  */
 262 DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
 263
 264 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
 265    compact prologues and epilogues by issuing a misaligned moves.  This
 266    requires target to handle misaligned moves and partial memory stalls
 267    reasonably well.
 268    FIXME: This may actualy be a win on more targets than listed here.  */
 269 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
 270           "misaligned_move_string_pro_epilogues",
 271           m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC)
 272
 273 /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
 274 DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
 275           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 276           | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
 277           | m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GENERIC)
 278
 279 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
 280 DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
 281           ~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
 282             | m_K6 | m_GOLDMONT))
 283
 284 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions.  */
 285 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
 286           m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
 287           | m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GENERIC)
 288
 289 /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
 290    for bit-manipulation instructions.  */
 291 DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
 292           m_SANDYBRIDGE | m_HASWELL | m_GENERIC)
 293
 294 /* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
 295    on hardware capabilities. Bdver3 hardware has a loop buffer which makes
 296    unrolling small loop less important. For, such architectures we adjust
 297    the unroll factor so that the unrolled loop fits the loop buffer.  */
 298 DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
 299
 300 /* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
 301    if-converted sequence to one.  */
 302 DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
 303           m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
 304           | m_GENERIC)
 305
 306 /*****************************************************************************/
 307 /* 387 instruction selection tuning                                          */
 308 /*****************************************************************************/
 309
 310 /* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
 311    integer operand.
 312    FIXME: Why this is disabled for modern chips?  */
 313 DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
 314           m_386 | m_486 | m_K6_GEODE)
 315
 316 /* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
 317    integer operand.  */
 318 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
 319           ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
 320             | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
 321             | m_GOLDMONT | m_GENERIC))
 322
 323 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
 324 DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
 325
 326 /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
 327 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
 328           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
 329           | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
 330           | m_GENERIC)
 331
 332 /*****************************************************************************/
 333 /* SSE instruction selection tuning                                          */
 334 /*****************************************************************************/
 335
 336 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
 337    regs instead of memory.  */
 338 DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
 339           m_CORE_ALL)
 340
 341 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
 342    of a sequence loading registers by parts.  */
 343 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
 344           m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
 345           | m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_AMDFAM10 | m_BDVER
 346           | m_BTVER | m_ZNVER1 | m_GENERIC)
 347
 348 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
 349    of a sequence loading registers by parts.  */
 350 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
 351           m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
 352           | m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_BDVER | m_ZNVER1
 353           | m_GENERIC)
 354
 355 /* Use packed single precision instructions where posisble.  I.e. movups instead
 356    of movupd.  */
 357 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
 358           m_BDVER | m_ZNVER1)
 359
 360 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 361 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
 362           m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
 363
 364 /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
 365    xorps/xorpd and other variants.  */
 366 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
 367           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER1
 368           | m_GENERIC)
 369
 370 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
 371    to SSE registers.  If disabled, the moves will be done by storing
 372    the value to memory and reloading.  */
 373 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
 374           ~(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC))
 375
 376 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
 377    to integer registers.  If disabled, the moves will be done by storing
 378    the value to memory and reloading.  */
 379 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
 380           ~m_ATHLON_K8)
 381
 382 /* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
 383    to use both SSE and integer registers at a same time.  */
 384 DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
 385           ~(m_AMDFAM10 | m_BDVER))
 386
 387 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
 388    fp converts to destination register.  */
 389 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
 390           m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_INTEL)
 391
 392 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
 393    from FP to FP.  This form of instructions avoids partial write to the
 394    destination.  */
 395 DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
 396           m_AMDFAM10)
 397
 398 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
 399    from integer to FP. */
 400 DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
 401
 402 /* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction.  */
 403 DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
 404           m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_INTEL)
 405
 406 /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes.  */
 407 DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
 408           m_SILVERMONT | m_GOLDMONT | m_INTEL)
 409
 410 /* X86_TUNE_USE_GATHER: Use gather instructions.  */
 411 DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",
 412           ~(m_ZNVER1 | m_GENERIC))
 413
 414 /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
 415    smaller FMA chain.  */
 416 DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER1)
 417
 418 /*****************************************************************************/
 419 /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
 420 /*****************************************************************************/
 421
 422 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
 423    split.  */
 424 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
 425           ~(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC))
 426
 427 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
 428    split.  */
 429 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
 430           ~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1 | m_GENERIC))
 431
 432 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
 433    the auto-vectorizer.  */
 434 DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2
 435           | m_ZNVER1)
 436
 437 /* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
 438    instructions in the auto-vectorizer.  */
 439 DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_SKYLAKE_AVX512)
 440
 441 /*****************************************************************************/
 442 /* Historical relics: tuning flags that helps a specific old CPU designs     */
 443 /*****************************************************************************/
 444
 445 /* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
 446    an integer register.  */
 447 DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
 448
 449 /* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
 450    such as fsqrt, fprem, fsin, fcos, fsincos etc.
 451    Should be enabled for all targets that always has coprocesor.  */
 452 DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
 453           ~(m_386 | m_486 | m_LAKEMONT))
 454
 455 /* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
 456    inline strlen.  This affects only -minline-all-stringops mode. By
 457    default we always dispatch to a library since our internal strlen
 458    is bad.  */
 459 DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
 460
 461 /* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
 462    longer "sal $1, reg".  */
 463 DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
 464
 465 /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
 466    of mozbl/movwl.  */
 467 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
 468           m_486 | m_PENT)
 469
 470 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
 471    and SImode multiply, but 386 and 486 do HImode multiply faster.  */
 472 DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
 473           ~(m_386 | m_486))
 474
 475 /* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
 476    into 16bit/8bit when resulting sequence is shorter.  For example
 477    for "and $-65536, reg" to 16bit store of 0.  */
 478 DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix",
 479           ~(m_386 | m_486 | m_PENT | m_LAKEMONT))
 480
 481 /* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
 482    such as "add $1, mem".  */
 483 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write",
 484           ~(m_PENT | m_LAKEMONT))
 485
 486 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
 487    than a MOV.  */
 488 DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMONT)
 489
 490 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
 491    but one byte longer.  */
 492 DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT)
 493
 494 /* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
 495    use of partial registers by renaming.  This improved performance of 16bit
 496    code where upper halves of registers are not used.  It also leads to
 497    an penalty whenever a 16bit store is followed by 32bit use.  This flag
 498    disables production of such sequences in common cases.
 499    See also X86_TUNE_HIMODE_MATH.
 500
 501    In current implementation the partial register stalls are not eliminated
 502    very well - they can be introduced via subregs synthesized by combine
 503    and can happen in caller/callee saving sequences.  */
 504 DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
 505
 506 /* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
 507    corresponding 32bit arithmetic.  */
 508 DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
 509           ~m_PPRO)
 510
 511 /* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic.  Again we avoid
 512    partial register stalls on PentiumPro targets. */
 513 DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
 514
 515 /* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
 516    On PPro this flag is meant to avoid partial register stalls.  */
 517 DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
 518
 519 /* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
 520    directly to memory.  */
 521 DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
 522
 523 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx.  */
 524 DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
 525
 526 /* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
 527    integer register.  */
 528 DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
 529
 530 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
 531    operand that cannot be represented using a modRM byte.  The XOR
 532    replacement is long decoded, so this split helps here as well.  */
 533 DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
 534
 535 /* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
 536    forms of instructions on K8 targets.  */
 537 DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
 538           m_K8)
 539
 540 /*****************************************************************************/
 541 /* This never worked well before.                                            */
 542 /*****************************************************************************/
 543
 544 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
 545    on simulation result. But after P4 was made, no performance benefit
 546    was observed with branch hints.  It also increases the code size.
 547    As a result, icc never generates branch hints.  */
 548 DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0U)
 549
 550 /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic.  */
 551 DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0U)
 552
 553 /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
 554    arithmetic to 32bit via PROMOTE_MODE macro.  This code generation scheme
 555    is usually used for RISC targets.  */
 556 DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0U)
 557
 558 /* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion
 559    before a transfer of control flow out of the function.  */
 560 DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER, "emit_vzeroupper", ~m_KNL)