gcc/config/i386/x86-tune.def

   1 /* Definitions of x86 tunable features.
   2    Copyright (C) 2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License and
  17 a copy of the GCC Runtime Library Exception along with this program;
  18 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 /* Tuning for a given CPU XXXX consists of:
  22     - adding new CPU into:
  23         - adding PROCESSOR_XXX to processor_type (in i386.h)
  24         - possibly adding XXX into CPU attribute in i386.md
  25         - adding XXX to processor_alias_table (in i386.c)
  26     - introducing ix86_XXX_cost in i386.c
  27         - Stringop generation table can be build based on test_stringop
  28         - script (once rest of tuning is complete)
  29     - designing a scheduler model in
  30         - XXXX.md file
  31         - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
  32         - possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
  33           and ix86_sched_init_global if those tricks are needed.
  34     - Tunning the flags bellow. Those are split into sections and each
  35       section is very roughly ordered by importance.  */
  36
  37 /*****************************************************************************/
  38 /* Scheduling flags.                                                         */
  39 /*****************************************************************************/
  40
  41 /* X86_TUNE_SCHEDULE: Enable scheduling.  */
  42 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
  43           m_PENT | m_PPRO | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
  44           | m_AMD_MULTIPLE | m_GENERIC)
  45
  46 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
  47    on modern chips.  Preffer stores affecting whole integer register
  48    over partial stores.  For example preffer MOVZBL or MOVQ to load 8bit
  49    value over movb.  */
  50 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
  51           m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE
  52           | m_GENERIC)
  53
  54 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
  55    destinations to be 128bit to allow register renaming on 128bit SSE units,
  56    but usually results in one extra microop on 64bit SSE units.
  57    Experimental results shows that disabling this option on P4 brings over 20%
  58    SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
  59    that can be partly masked by careful scheduling of moves.  */
  60 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
  61           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMDFAM10
  62           | m_BDVER | m_GENERIC)
  63
  64 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
  65    are resolved on SSE register parts instead of whole registers, so we may
  66    maintain just lower part of scalar values in proper format leaving the
  67    upper part undefined.  */
  68 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
  69
  70 /* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of of flags
  71    set by instructions affecting just some flags (in particular shifts).
  72    This is because Core2 resolves dependencies on whole flags register
  73    and such sequences introduce false dependency on previous instruction
  74    setting full flags.
  75
  76    The flags does not affect generation of INC and DEC that is controlled
  77    by X86_TUNE_USE_INCDEC.
  78
  79    This flag may be dropped from generic once core2-corei5 machines are
  80    rare enough.  */
  81 DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
  82           m_CORE2 | m_GENERIC)
  83
  84 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
  85    partial dependencies.  */
  86 DEF_TUNE (X86_TUNE_MOVX, "movx",
  87           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GEODE
  88           | m_AMD_MULTIPLE  | m_GENERIC)
  89
  90 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
  91    full sized loads.  */
  92 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
  93           m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
  94
  95 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
  96    conditional jump instruction for 32 bit TARGET.
  97    FIXME: revisit for generic.  */
  98 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
  99           m_CORE_ALL | m_BDVER)
 100
 101 /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
 102    conditional jump instruction for TARGET_64BIT.
 103    FIXME: revisit for generic.  */
 104 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
 105           m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER)
 106
 107 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
 108    subsequent conditional jump instruction when the condition jump
 109    check sign flag (SF) or overflow flag (OF).  */
 110 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
 111           m_COREI7 | m_COREI7_AVX | m_HASWELL | m_BDVER)
 112
 113 /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
 114    jump instruction when the alu instruction produces the CCFLAG consumed by
 115    the conditional jump instruction. */
 116 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
 117           m_COREI7_AVX | m_HASWELL)
 118
 119 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
 120    during reassociation of integer computation.  */
 121 DEF_TUNE (X86_TUNE_REASSOC_INT_TO_PARALLEL, "reassoc_int_to_parallel",
 122           m_ATOM)
 123
 124 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
 125    during reassociation of fp computation.  */
 126 DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
 127           m_ATOM | m_SLM | m_HASWELL | m_BDVER1 | m_BDVER2 | m_GENERIC)
 128
 129 /*****************************************************************************/
 130 /* Function prologue, epilogue and function calling sequences.               */
 131 /*****************************************************************************/
 132
 133 /* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
 134    arguments in prologue/epilogue instead of separately for each call
 135    by push/pop instructions.
 136    This increase code size by about 5% in 32bit mode, less so in 64bit mode
 137    because parameters are passed in registers.  It is considerable
 138    win for targets without stack engine that prevents multple push operations
 139    to happen in parallel.
 140
 141    FIXME: the flags is incorrectly enabled for amdfam10, Bulldozer,
 142    Bobcat and Generic.  This is because disabling it causes large
 143    regression on mgrid due to IRA limitation leading to unecessary
 144    use of the frame pointer in 32bit mode.  */
 145 DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
 146           m_PPRO | m_P4_NOCONA | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
 147
 148 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
 149    considered on critical path.  */
 150 DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
 151           m_PPRO | m_ATHLON_K8)
 152
 153 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
 154    considered on critical path.  */
 155 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
 156           m_PPRO | m_ATHLON_K8)
 157
 158 /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
 159 DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
 160           m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
 161
 162 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
 163    Some chips, like 486 and Pentium works faster with separate load
 164    and push instructions.  */
 165 DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
 166           m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
 167           | m_GENERIC)
 168
 169 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
 170    over esp subtraction.  */
 171 DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
 172           | m_K6_GEODE)
 173
 174 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
 175    over esp subtraction.  */
 176 DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_K6_GEODE)
 177
 178 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
 179    over esp addition.  */
 180 DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT | m_PPRO)
 181
 182 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
 183    over esp addition.  */
 184 DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT)
 185
 186 /*****************************************************************************/
 187 /* Branch predictor tuning                                                   */
 188 /*****************************************************************************/
 189
 190 /* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
 191    instructions long.  */
 192 DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_ATOM)
 193
 194 /* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
 195    of conditional jump or directly preceded by other jump instruction.
 196    This is important for AND K8-AMDFAM10 because the branch prediction
 197    architecture expect at most one jump per 2 byte window.  Failing to
 198    pad returns leads to misaligned return stack.  */
 199 DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
 200           m_ATHLON_K8 | m_AMDFAM10 | m_GENERIC)
 201
 202 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
 203    than 4 branch instructions in the 16 byte window.  */
 204 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
 205           m_PPRO | m_P4_NOCONA | m_ATOM | m_SLM | m_ATHLON_K8 | m_AMDFAM10)
 206
 207 /*****************************************************************************/
 208 /* Integer instruction selection tuning                                      */
 209 /*****************************************************************************/
 210
 211 /* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
 212    at -O3.  For the moment, the prefetching seems badly tuned for Intel
 213    chips.  */
 214 DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
 215           m_K6_GEODE | m_AMD_MULTIPLE)
 216
 217 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
 218    on 16-bit immediate moves into memory on Core2 and Corei7.  */
 219 DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
 220
 221 /* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
 222    as "add mem, reg".  */
 223 DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_PPRO))
 224
 225 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.   */
 226 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
 227           ~(m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GENERIC))
 228
 229 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
 230    for DFmode copies */
 231 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
 232           ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM
 233           | m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
 234
 235 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
 236    will impact LEA instruction selection. */
 237 DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_ATOM | m_SLM)
 238
 239 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
 240    vector path on AMD machines.
 241    FIXME: Do we need to enable this for core? */
 242 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
 243           m_K8 | m_AMDFAM10)
 244
 245 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
 246    machines.
 247    FIXME: Do we need to enable this for core? */
 248 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
 249           m_K8 | m_AMDFAM10)
 250
 251 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
 252    a conditional move.  */
 253 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
 254           m_ATOM | m_SLM)
 255
 256 /* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
 257    as MOVS and STOS (without a REP prefix) to move/set sequences of bytes.  */
 258 DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
 259
 260 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
 261    compact prologues and epilogues by issuing a misaligned moves.  This
 262    requires target to handle misaligned moves and partial memory stalls
 263    reasonably well.
 264    FIXME: This may actualy be a win on more targets than listed here.  */
 265 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
 266           "misaligned_move_string_pro_epilogues",
 267           m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC)
 268
 269 /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
 270 DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
 271           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
 272           | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
 273
 274 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
 275 DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", ~(m_PENT | m_ATOM | m_SLM | m_K6))
 276
 277 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions.  */
 278 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
 279           m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
 280
 281 /*****************************************************************************/
 282 /* 387 instruction selection tuning                                          */
 283 /*****************************************************************************/
 284
 285 /* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
 286    integer operand.
 287    FIXME: Why this is disabled for modern chips?  */
 288 DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
 289           m_386 | m_486 | m_K6_GEODE)
 290
 291 /* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
 292    integer operand.  */
 293 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
 294           ~(m_PENT | m_PPRO | m_CORE_ALL | m_ATOM
 295             | m_SLM | m_AMD_MULTIPLE | m_GENERIC))
 296
 297 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
 298 DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
 299
 300 /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
 301 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
 302           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
 303           | m_ATHLON_K8 | m_GENERIC)
 304
 305 /*****************************************************************************/
 306 /* SSE instruction selection tuning                                          */
 307 /*****************************************************************************/
 308
 309 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
 310    instructions.  */
 311 DEF_TUNE (X86_TUNE_VECTORIZE_DOUBLE, "vectorize_double", ~m_ATOM)
 312
 313 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
 314    regs instead of memory.  */
 315 DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
 316           m_CORE_ALL)
 317
 318 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
 319    of a sequence loading registers by parts.  */
 320 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
 321           m_COREI7 | m_COREI7_AVX | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
 322
 323 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
 324    of a sequence loading registers by parts.  */
 325 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
 326           m_COREI7 | m_COREI7_AVX | m_BDVER | m_SLM | m_GENERIC)
 327
 328 /* Use packed single precision instructions where posisble.  I.e. movups instead
 329    of movupd.  */
 330 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
 331           m_BDVER)
 332
 333 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 334 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
 335           m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC)
 336
 337 /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
 338    xorps/xorpd and other variants.  */
 339 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
 340           m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_GENERIC)
 341
 342 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
 343    to SSE registers.  If disabled, the moves will be done by storing
 344    the value to memory and reloading.  */
 345 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
 346           ~(m_AMD_MULTIPLE | m_GENERIC))
 347
 348 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
 349    to integer registers.  If disabled, the moves will be done by storing
 350    the value to memory and reloading.  */
 351 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
 352           ~m_ATHLON_K8)
 353
 354 /* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
 355    to use both SSE and integer registers at a same time.
 356    FIXME: revisit importance of this for generic.  */
 357 DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
 358           ~(m_AMDFAM10 | m_BDVER))
 359
 360 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
 361    fp converts to destination register.  */
 362 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
 363           m_SLM)
 364
 365 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
 366    from FP to FP.  This form of instructions avoids partial write to the
 367    destination.  */
 368 DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
 369           m_AMDFAM10)
 370
 371 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
 372    from integer to FP. */
 373 DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
 374
 375 /*****************************************************************************/
 376 /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
 377 /*****************************************************************************/
 378
 379 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if true, unaligned loads are
 380    split.  */
 381 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
 382           ~(m_COREI7 | m_GENERIC))
 383
 384 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if true, unaligned loads are
 385    split.  */
 386 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_load_optimal",
 387           ~(m_COREI7 | m_BDVER | m_GENERIC))
 388
 389 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
 390    the auto-vectorizer.  */
 391 DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2)
 392
 393 /*****************************************************************************/
 394 /* Historical relics: tuning flags that helps a specific old CPU designs     */
 395 /*****************************************************************************/
 396
 397 /* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
 398    an integer register.  */
 399 DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
 400
 401 /* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
 402    such as fsqrt, fprem, fsin, fcos, fsincos etc.
 403    Should be enabled for all targets that always has coprocesor.  */
 404 DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
 405           ~(m_386 | m_486))
 406
 407 /* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
 408    inline strlen.  This affects only -minline-all-stringops mode. By
 409    default we always dispatch to a library since our internal strlen
 410    is bad.  */
 411 DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
 412
 413 /* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
 414    longer "sal $1, reg".  */
 415 DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
 416
 417 /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
 418    of mozbl/movwl.  */
 419 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",  m_486 | m_PENT)
 420
 421 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
 422    and SImode multiply, but 386 and 486 do HImode multiply faster.  */
 423 DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
 424           ~(m_386 | m_486))
 425
 426 /* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
 427    into 16bit/8bit when resulting sequence is shorter.  For example
 428    for "and $-65536, reg" to 16bit store of 0.  */
 429 DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix", ~(m_386 | m_486 | m_PENT))
 430
 431 /* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
 432    such as "add $1, mem".  */
 433 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write", ~m_PENT)
 434
 435 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
 436    than a MOV.  */
 437 DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT)
 438
 439 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
 440    but one byte longer.  */
 441 DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT)
 442
 443 /* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
 444    use of partial registers by renaming.  This improved performance of 16bit
 445    code where upper halves of registers are not used.  It also leads to
 446    an penalty whenever a 16bit store is followed by 32bit use.  This flag
 447    disables production of such sequences in common cases.
 448    See also X86_TUNE_HIMODE_MATH.
 449
 450    In current implementation the partial register stalls are not eliminated
 451    very well - they can be introduced via subregs synthesized by combine
 452    and can happen in caller/callee saving sequences.  */
 453 DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
 454
 455 /* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
 456    corresponding 32bit arithmetic.  */
 457 DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
 458           ~m_PPRO)
 459
 460 /* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic.  Again we avoid
 461    partial register stalls on PentiumPro targets. */
 462 DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
 463
 464 /* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
 465    On PPro this flag is meant to avoid partial register stalls.  */
 466 DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
 467
 468 /* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
 469    directly to memory.  */
 470 DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
 471
 472 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx.  */
 473 DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
 474
 475 /* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
 476    integer register.  */
 477 DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
 478
 479 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
 480    operand that cannot be represented using a modRM byte.  The XOR
 481    replacement is long decoded, so this split helps here as well.  */
 482 DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
 483
 484 /* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
 485    forms of instructions on K8 targets.  */
 486 DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
 487           m_K8)
 488
 489 /*****************************************************************************/
 490 /* This never worked well before.                                            */
 491 /*****************************************************************************/
 492
 493 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
 494    on simulation result. But after P4 was made, no performance benefit
 495    was observed with branch hints.  It also increases the code size.
 496    As a result, icc never generates branch hints.  */
 497 DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0)
 498
 499 /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic.  */
 500 DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0)
 501
 502 /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
 503    arithmetic to 32bit via PROMOTE_MODE macro.  This code generation scheme
 504    is usually used for RISC targets.  */
 505 DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0)