1 /* Definitions of x86 tunable features.
2 Copyright (C) 2013-2021 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License and
17 a copy of the GCC Runtime Library Exception along with this program;
18 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
19 <http://www.gnu.org/licenses/>. */
21 /* Tuning for a given CPU XXXX consists of:
22 - adding new CPU into:
23 - adding PROCESSOR_XXX to processor_type (in i386.h)
24 - possibly adding XXX into CPU attribute in i386.md
25 - adding XXX to processor_alias_table (in i386.c)
26 - introducing ix86_XXX_cost in i386.c
27 - Stringop generation table can be build based on test_stringop
28 - script (once rest of tuning is complete)
29 - designing a scheduler model in
31 - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
32 - possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
33 and ix86_sched_init_global if those tricks are needed.
34 - Tunning the flags bellow. Those are split into sections and each
35 section is very roughly ordered by importance. */
37 /*****************************************************************************/
38 /* Scheduling flags. */
39 /*****************************************************************************/
41 /* X86_TUNE_SCHEDULE: Enable scheduling. */
42 DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
43 m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
44 | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
45 | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
47 /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
48 on modern chips. Prefer stores affecting whole integer register
49 over partial stores. For example prefer MOVZBL or MOVQ to load 8bit
51 DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
52 m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
53 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
54 | m_KNL | m_KNM | m_AMD_MULTIPLE | m_TREMONT | m_ALDERLAKE
57 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
58 destinations to be 128bit to allow register renaming on 128bit SSE units,
59 but usually results in one extra microop on 64bit SSE units.
60 Experimental results shows that disabling this option on P4 brings over 20%
61 SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
62 that can be partly masked by careful scheduling of moves. */
63 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
64 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
65 | m_BDVER | m_ZNVER | m_TREMONT | m_ALDERLAKE | m_GENERIC)
67 /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
68 partial write to the destination in scalar SSE conversion from FP
70 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
71 "sse_partial_reg_fp_converts_dependency",
72 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
73 | m_BDVER | m_ZNVER | m_ALDERLAKE | m_GENERIC)
75 /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
76 write to the destination in scalar SSE conversion from integer to FP. */
77 DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
78 "sse_partial_reg_converts_dependency",
79 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
80 | m_BDVER | m_ZNVER | m_ALDERLAKE | m_GENERIC)
82 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
83 are resolved on SSE register parts instead of whole registers, so we may
84 maintain just lower part of scalar values in proper format leaving the
85 upper part undefined. */
86 DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
88 /* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of flags
89 set by instructions affecting just some flags (in particular shifts).
90 This is because Core2 resolves dependencies on whole flags register
91 and such sequences introduce false dependency on previous instruction
94 The flags does not affect generation of INC and DEC that is controlled
95 by X86_TUNE_USE_INCDEC. */
97 DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
100 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
101 partial dependencies. */
102 DEF_TUNE (X86_TUNE_MOVX, "movx",
103 m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
104 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
105 | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE
106 | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
108 /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
110 DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
111 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
112 | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
113 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
115 /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
116 conditional jump instruction for 32 bit TARGET. */
117 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
118 m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
120 /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
121 conditional jump instruction for TARGET_64BIT. */
122 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
123 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
124 | m_ZNVER | m_GENERIC)
126 /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
127 subsequent conditional jump instruction when the condition jump
128 check sign flag (SF) or overflow flag (OF). */
129 DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
130 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
131 | m_ZNVER | m_GENERIC)
133 /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
134 jump instruction when the alu instruction produces the CCFLAG consumed by
135 the conditional jump instruction. */
136 DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
137 m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC)
140 /*****************************************************************************/
141 /* Function prologue, epilogue and function calling sequences. */
142 /*****************************************************************************/
144 /* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
145 arguments in prologue/epilogue instead of separately for each call
146 by push/pop instructions.
147 This increase code size by about 5% in 32bit mode, less so in 64bit mode
148 because parameters are passed in registers. It is considerable
149 win for targets without stack engine that prevents multple push operations
150 to happen in parallel. */
152 DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
153 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
154 | m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8)
156 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
157 considered on critical path. */
158 DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
159 m_PPRO | m_ATHLON_K8)
161 /* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
162 considered on critical path. */
163 DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
164 m_PPRO | m_ATHLON_K8)
166 /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
167 DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
168 m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_TREMONT
169 | m_ALDERLAKE | m_GENERIC)
171 /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
172 Some chips, like 486 and Pentium works faster with separate load
173 and push instructions. */
174 DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
175 m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
176 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
178 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
179 over esp subtraction. */
180 DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
181 | m_LAKEMONT | m_K6_GEODE)
183 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
184 over esp subtraction. */
185 DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMONT
188 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
189 over esp addition. */
190 DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT
191 | m_LAKEMONT | m_PPRO)
193 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
194 over esp addition. */
195 DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMONT)
197 /*****************************************************************************/
198 /* Branch predictor tuning */
199 /*****************************************************************************/
201 /* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
202 instructions long. */
203 DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
205 /* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
206 of conditional jump or directly preceded by other jump instruction.
207 This is important for AND K8-AMDFAM10 because the branch prediction
208 architecture expect at most one jump per 2 byte window. Failing to
209 pad returns leads to misaligned return stack. */
210 DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
211 m_ATHLON_K8 | m_AMDFAM10)
213 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
214 than 4 branch instructions in the 16 byte window. */
215 DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
216 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
217 | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
219 /*****************************************************************************/
220 /* Integer instruction selection tuning */
221 /*****************************************************************************/
223 /* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
224 at -O3. For the moment, the prefetching seems badly tuned for Intel
226 DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
227 m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
229 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
230 on 16-bit immediate moves into memory on Core2 and Corei7. */
231 DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
233 /* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
234 as "add mem, reg". */
235 DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
237 /* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
239 Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
240 Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop
241 is output only when the values needs to be really merged, which is not
242 done by GCC generated code. */
243 DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
244 ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
245 | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
246 | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC))
248 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
250 DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
251 ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
252 | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
253 | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC))
255 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
256 will impact LEA instruction selection. */
257 DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
258 | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
260 /* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
261 DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
262 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS
265 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
266 vector path on AMD machines.
267 FIXME: Do we need to enable this for core? */
268 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
271 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
273 FIXME: Do we need to enable this for core? */
274 DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
277 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
278 a conditional move. */
279 DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
280 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
283 /* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
284 as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
285 DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
287 /* X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB: Enable use of REP MOVSB/STOSB to
288 move/set sequences of bytes with known size. */
289 DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
290 "prefer_known_rep_movsb_stosb",
291 m_SKYLAKE | m_ALDERLAKE | m_TREMONT | m_CORE_AVX512)
293 /* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
294 compact prologues and epilogues by issuing a misaligned moves. This
295 requires target to handle misaligned moves and partial memory stalls
297 FIXME: This may actualy be a win on more targets than listed here. */
298 DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
299 "misaligned_move_string_pro_epilogues",
300 m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_TREMONT
301 | m_ALDERLAKE | m_GENERIC)
303 /* X86_TUNE_USE_SAHF: Controls use of SAHF. */
304 DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
305 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
306 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
307 | m_BTVER | m_ZNVER | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
308 | m_ALDERLAKE | m_GENERIC)
310 /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
311 DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
312 ~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
313 | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS))
315 /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
316 DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
317 m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
318 | m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
319 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
321 /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
322 for bit-manipulation instructions. */
323 DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
324 m_SANDYBRIDGE | m_CORE_AVX2 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
326 /* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
327 on hardware capabilities. Bdver3 hardware has a loop buffer which makes
328 unrolling small loop less important. For, such architectures we adjust
329 the unroll factor so that the unrolled loop fits the loop buffer. */
330 DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
332 /* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
333 if-converted sequence to one. */
334 DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
335 m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
336 | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
338 /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
339 DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
340 m_CORE_ALL | m_BDVER | m_ZNVER | m_TREMONT | m_ALDERLAKE | m_GENERIC)
342 /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
343 generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
344 (signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */
345 DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
346 m_CORE_ALL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
349 /*****************************************************************************/
350 /* 387 instruction selection tuning */
351 /*****************************************************************************/
353 /* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
355 FIXME: Why this is disabled for modern chips? */
356 DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
357 m_386 | m_486 | m_K6_GEODE)
359 /* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
361 DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
362 ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
363 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
364 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
367 /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
368 DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
370 /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
371 DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
372 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
373 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
374 | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC)
376 /*****************************************************************************/
377 /* SSE instruction selection tuning */
378 /*****************************************************************************/
380 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
381 regs instead of memory. */
382 DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
385 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
386 of a sequence loading registers by parts. */
387 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
388 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
389 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
390 | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_GENERIC)
392 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
393 instead of a sequence loading registers by parts. */
394 DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
395 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM
396 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS
397 | m_TREMONT | m_ALDERLAKE | m_BDVER | m_ZNVER | m_GENERIC)
399 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
400 precision 128bit instructions instead of double where possible. */
401 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
404 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
405 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
406 m_AMD_MULTIPLE | m_CORE_ALL | m_TREMONT | m_ALDERLAKE | m_GENERIC)
408 /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
409 xorps/xorpd and other variants. */
410 DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
411 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
412 | m_TREMONT | m_ALDERLAKE | m_GENERIC)
414 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
415 to SSE registers. If disabled, the moves will be done by storing
416 the value to memory and reloading.
417 Enable this flag for generic - the only relevant architecture preferring
418 no inter-unit moves is Buldozer. While this makes small regression on SPECfp
419 scores (sub 0.3%), disabling inter-unit moves penalizes noticeably hand
420 written vectorized code which use i.e. _mm_set_epi16. */
421 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
422 ~(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER))
424 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
425 to integer registers. If disabled, the moves will be done by storing
426 the value to memory and reloading. */
427 DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
430 /* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
431 to use both SSE and integer registers at a same time. */
432 DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
433 ~(m_AMDFAM10 | m_BDVER))
435 /* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
436 fp converts to destination register. */
437 DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
438 m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
441 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
442 from FP to FP. This form of instructions avoids partial write to the
444 DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
447 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
448 from integer to FP. */
449 DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
451 /* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
452 DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
453 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
454 | m_GOLDMONT_PLUS | m_INTEL)
456 /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
457 DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
458 m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE
461 /* X86_TUNE_USE_GATHER: Use gather instructions. */
462 DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",
463 ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_GENERIC))
465 /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
466 smaller FMA chain. */
467 DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER)
469 /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
470 smaller FMA chain. */
471 DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3)
473 /* X86_TUNE_V2DF_REDUCTION_PREFER_PHADDPD: Prefer haddpd
474 for v2df vector reduction. */
475 DEF_TUNE (X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD,
476 "v2df_reduction_prefer_haddpd", m_NONE)
478 /*****************************************************************************/
479 /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
480 /*****************************************************************************/
482 /* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
484 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
485 ~(m_NEHALEM | m_SANDYBRIDGE))
487 /* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
489 DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
490 ~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1))
492 /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX256 ops are split into two AVX128 ops. */
493 DEF_TUNE (X86_TUNE_AVX256_SPLIT_REGS, "avx256_split_regs",m_BDVER | m_BTVER2
496 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
497 the auto-vectorizer. */
498 DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2
501 /* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
502 instructions in the auto-vectorizer. */
503 DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512)
505 /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
507 DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
510 /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
512 DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
515 /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
517 DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
520 /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
522 DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
525 /*****************************************************************************/
526 /*****************************************************************************/
527 /* Historical relics: tuning flags that helps a specific old CPU designs */
528 /*****************************************************************************/
530 /* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
531 an integer register. */
532 DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
534 /* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
535 such as fsqrt, fprem, fsin, fcos, fsincos etc.
536 Should be enabled for all targets that always has coprocesor. */
537 DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
538 ~(m_386 | m_486 | m_LAKEMONT))
540 /* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
541 inline strlen. This affects only -minline-all-stringops mode. By
542 default we always dispatch to a library since our internal strlen
544 DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
546 /* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
547 longer "sal $1, reg". */
548 DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
550 /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
552 DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
555 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
556 and SImode multiply, but 386 and 486 do HImode multiply faster. */
557 DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
560 /* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
561 into 16bit/8bit when resulting sequence is shorter. For example
562 for "and $-65536, reg" to 16bit store of 0. */
563 DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix",
564 ~(m_386 | m_486 | m_PENT | m_LAKEMONT))
566 /* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
567 such as "add $1, mem". */
568 DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write",
569 ~(m_PENT | m_LAKEMONT))
571 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
573 DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMONT)
575 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
576 but one byte longer. */
577 DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT)
579 /* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
580 use of partial registers by renaming. This improved performance of 16bit
581 code where upper halves of registers are not used. It also leads to
582 an penalty whenever a 16bit store is followed by 32bit use. This flag
583 disables production of such sequences in common cases.
584 See also X86_TUNE_HIMODE_MATH.
586 In current implementation the partial register stalls are not eliminated
587 very well - they can be introduced via subregs synthesized by combine
588 and can happen in caller/callee saving sequences. */
589 DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
591 /* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
592 corresponding 32bit arithmetic. */
593 DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
596 /* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid
597 partial register stalls on PentiumPro targets. */
598 DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
600 /* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
601 On PPro this flag is meant to avoid partial register stalls. */
602 DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
604 /* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
605 directly to memory. */
606 DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
608 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
609 DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
611 /* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
613 DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
615 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
616 operand that cannot be represented using a modRM byte. The XOR
617 replacement is long decoded, so this split helps here as well. */
618 DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
620 /* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
621 forms of instructions on K8 targets. */
622 DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
625 /*****************************************************************************/
626 /* This never worked well before. */
627 /*****************************************************************************/
629 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
630 on simulation result. But after P4 was made, no performance benefit
631 was observed with branch hints. It also increases the code size.
632 As a result, icc never generates branch hints. */
633 DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", m_NONE)
635 /* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */
636 DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", m_ALL)
638 /* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
639 arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme
640 is usually used for RISC targets. */
641 DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", m_NONE)
643 /* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion
644 before a transfer of control flow out of the function. */
645 DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER, "emit_vzeroupper", ~m_KNL)