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1 /* Definitions of target machine for GNU compiler, for Intel 860.
2 Copyright (C) 1989, 1991, 1993, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
5 the whims of the System V Release 4 assembler.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 /* Note that some other tm.h files include this one and then override
26 many of the definitions that relate to assembler syntax. */
29 /* Names to predefine in the preprocessor for this target machine. */
30 #define TARGET_CPU_CPP_BUILTINS() \
32 builtin_define ("i860"); \
33 builtin_assert ("cpu=i860"); \
34 builtin_assert ("machine=i860"); \
37 /* Print subsidiary information on the compiler version in use. */
38 #define TARGET_VERSION fprintf (stderr, " (i860)");
40 /* target machine storage layout */
42 /* Define this if most significant bit is lowest numbered
43 in instructions that operate on numbered bit-fields.
44 This is a moot question on the i860 due to the lack of bit-field insns. */
45 #define BITS_BIG_ENDIAN 0
47 /* Define this if most significant byte of a word is the lowest numbered. */
48 /* That is not true on i860 in the mode we will use. */
49 #define BYTES_BIG_ENDIAN 0
51 /* Define this if most significant word of a multiword number is the lowest
53 /* For the i860 this goes with BYTES_BIG_ENDIAN. */
54 /* NOTE: GCC probably cannot support a big-endian i860
55 because GCC fundamentally assumes that the order of words
56 in memory as the same as the order in registers.
57 That's not true for the big-endian i860.
58 The big-endian i860 isn't important enough to
59 justify the trouble of changing this assumption. */
60 #define WORDS_BIG_ENDIAN 0
62 /* Width of a word, in units (bytes). */
63 #define UNITS_PER_WORD 4
65 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
66 #define PARM_BOUNDARY 32
68 /* Boundary (in *bits*) on which stack pointer should be aligned. */
69 #define STACK_BOUNDARY 128
71 /* Allocation boundary (in *bits*) for the code of a function. */
72 #define FUNCTION_BOUNDARY 64
74 /* Alignment of field after `int : 0' in a structure. */
75 #define EMPTY_FIELD_BOUNDARY 32
77 /* Every structure's size must be a multiple of this. */
78 #define STRUCTURE_SIZE_BOUNDARY 8
80 /* Minimum size in bits of the largest boundary to which any
81 and all fundamental data types supported by the hardware
82 might need to be aligned. No data type wants to be aligned
83 rounder than this. The i860 supports 128-bit (long double)
84 floating point quantities, and the System V Release 4 i860
85 ABI requires these to be aligned to 16-byte (128-bit)
87 #define BIGGEST_ALIGNMENT 128
89 /* Set this nonzero if move instructions will actually fail to work
90 when given unaligned data. */
91 #define STRICT_ALIGNMENT 1
93 /* If bit field type is int, don't let it cross an int,
94 and give entire struct the alignment of an int. */
95 #define PCC_BITFIELD_TYPE_MATTERS 1
97 /* Standard register usage. */
99 /* Number of actual hardware registers.
100 The hardware registers are assigned numbers for the compiler
101 from 0 to just below FIRST_PSEUDO_REGISTER.
102 All registers that the compiler knows about must be given numbers,
103 even those that are not normally considered general registers.
105 i860 has 32 fullword registers and 32 floating point registers. */
107 #define FIRST_PSEUDO_REGISTER 64
109 /* 1 for registers that have pervasive standard uses
110 and are not available for the register allocator.
111 On the i860, this includes the always-0 registers
112 and fp, sp, arg pointer, and the return address.
113 Also r31, used for special purposes for constant addresses. */
114 #define FIXED_REGISTERS \
115 {1, 1, 1, 1, 0, 0, 0, 0, \
116 0, 0, 0, 0, 0, 0, 0, 0, \
117 0, 0, 0, 0, 0, 0, 0, 0, \
118 0, 0, 0, 0, 0, 0, 0, 1, \
119 1, 1, 0, 0, 0, 0, 0, 0, \
120 0, 0, 0, 0, 0, 0, 0, 0, \
121 0, 0, 0, 0, 0, 0, 0, 0, \
122 0, 0, 0, 0, 0, 0, 0, 0}
124 /* 1 for registers not available across function calls.
125 These must include the FIXED_REGISTERS and also any
126 registers that can be used without being saved.
127 On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */
128 #define CALL_USED_REGISTERS \
129 {1, 1, 1, 1, 0, 0, 0, 0, \
130 0, 0, 0, 0, 0, 0, 0, 0, \
131 1, 1, 1, 1, 1, 1, 1, 1, \
132 1, 1, 1, 1, 1, 1, 1, 1, \
133 1, 1, 0, 0, 0, 0, 0, 0, \
134 1, 1, 1, 1, 1, 1, 1, 1, \
135 1, 1, 1, 1, 1, 1, 1, 1, \
136 1, 1, 1, 1, 1, 1, 1, 1}
138 /* Try to get a non-preserved register before trying to get one we will
139 have to preserve. Try to get an FP register only *after* trying to
140 get a general register, because it is relatively expensive to move
141 into or out of an FP register. */
143 #define REG_ALLOC_ORDER \
144 {31, 30, 29, 28, 27, 26, 25, 24, \
145 23, 22, 21, 20, 19, 18, 17, 16, \
146 15, 14, 13, 12, 11, 10, 9, 8, \
147 7, 6, 5, 4, 3, 2, 1, 0, \
148 63, 62, 61, 60, 59, 58, 57, 56, \
149 55, 54, 53, 52, 51, 50, 49, 48, \
150 47, 46, 45, 44, 43, 42, 41, 40, \
151 39, 38, 37, 36, 35, 34, 33, 32}
153 /* Return number of consecutive hard regs needed starting at reg REGNO
154 to hold something of mode MODE.
155 This is ordinarily the length in words of a value of mode MODE
156 but can be less for certain modes in special long registers.
158 On the i860, all registers hold 32 bits worth. */
159 #define HARD_REGNO_NREGS(REGNO, MODE) \
160 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
162 #define REGNO_MODE_ALIGNED(REGNO, MODE) \
163 (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
165 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
167 On the i860, we allow anything to go into any registers, but we require
168 any sort of value going into the FP registers to be properly aligned
169 (based on its size) within the FP register set.
171 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
173 || (MODE) == VOIDmode || (MODE) == BLKmode \
174 || REGNO_MODE_ALIGNED (REGNO, MODE))
176 /* Value is 1 if it is a good idea to tie two pseudo registers
177 when one has mode MODE1 and one has mode MODE2.
178 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
179 for any hard reg, then this must be 0 for correct output. */
180 /* I think that is not always true; alignment restrictions for doubles
181 should not prevent tying them with singles. So try allowing that.
182 On the other hand, don't let fixed and floating be tied;
183 this restriction is not necessary, but may make better code. */
184 #define MODES_TIEABLE_P(MODE1, MODE2) \
185 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
186 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
187 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
188 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
190 /* Specify the registers used for certain standard purposes.
191 The values of these macros are register numbers. */
193 /* i860 pc isn't overloaded on a register that the compiler knows about. */
194 /* #define PC_REGNUM */
196 /* Register to use for pushing function arguments. */
197 #define STACK_POINTER_REGNUM 2
199 /* Base register for access to local variables of the function. */
200 #define FRAME_POINTER_REGNUM 3
202 /* Value should be nonzero if functions must have frame pointers.
203 Zero means the frame pointer need not be set up (and parms
204 may be accessed via the stack pointer) in functions that seem suitable.
205 This is computed in `reload', in reload1.c. */
206 #define FRAME_POINTER_REQUIRED 1
208 /* Base register for access to arguments of the function. */
209 #define ARG_POINTER_REGNUM 28
211 /* Register in which static-chain is passed to a function. */
212 #define STATIC_CHAIN_REGNUM 29
214 /* Register in which address to store a structure value
215 is passed to a function. */
216 #define I860_STRUCT_VALUE_REGNUM 16
218 /* Register to use when a source of a floating-point zero is needed. */
221 /* Define the classes of registers for register constraints in the
222 machine description. Also define ranges of constants.
224 One of the classes must always be named ALL_REGS and include all hard regs.
225 If there is more than one class, another class must be named NO_REGS
226 and contain no registers.
228 The name GENERAL_REGS must be the name of a class (or an alias for
229 another name such as ALL_REGS). This is the class of registers
230 that is allowed by "g" or "r" in a register constraint.
231 Also, registers outside this class are allocated only when
232 instructions express preferences for them.
234 The classes must be numbered in nondecreasing order; that is,
235 a larger-numbered class must never be contained completely
236 in a smaller-numbered class.
238 For any two classes, it is very desirable that there be another
239 class that represents their union. */
241 /* The i860 has two kinds of registers, hence four classes. */
243 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
245 #define N_REG_CLASSES (int) LIM_REG_CLASSES
247 /* Give names of register classes as strings for dump file. */
249 #define REG_CLASS_NAMES \
250 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
252 /* Define which registers fit in which classes.
253 This is an initializer for a vector of HARD_REG_SET
254 of length N_REG_CLASSES. */
256 #define REG_CLASS_CONTENTS \
257 {{0, 0}, {0xffffffff, 0}, \
258 {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
260 /* The same information, inverted:
261 Return the class number of the smallest class containing
262 reg number REGNO. This could be a conditional expression
263 or could index an array. */
265 #define REGNO_REG_CLASS(REGNO) \
266 ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
268 /* The class value for index registers, and the one for base regs. */
269 #define INDEX_REG_CLASS GENERAL_REGS
270 #define BASE_REG_CLASS GENERAL_REGS
272 /* Get reg_class from a letter such as appears in the machine description. */
274 #define REG_CLASS_FROM_LETTER(C) \
275 ((C) == 'f' ? FP_REGS : NO_REGS)
277 /* The letters I, J, K, L and M in a register constraint string
278 can be used to stand for particular ranges of immediate operands.
279 This macro defines what the ranges are.
280 C is the letter, and VALUE is a constant value.
281 Return 1 if VALUE is in the range specified by C.
283 For the i860, `I' is used for the range of constants
284 an add/subtract insn can actually contain.
285 But not including -0x8000, since we need
286 to negate the constant sometimes.
287 `J' is used for the range which is just zero (since that is R0).
288 `K' is used for the range allowed in bte.
289 `L' is used for the range allowed in logical insns. */
291 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
293 #define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
295 #define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
297 #define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
299 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
300 ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \
301 : (C) == 'J' ? (VALUE) == 0 \
302 : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \
303 : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \
306 /* Return nonzero if the given VALUE is acceptable for the
307 constraint letter C. For the i860, constraint letter 'G'
308 permits only a floating-point zero value. */
309 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
310 ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \
311 && CONST_DOUBLE_HIGH ((VALUE)) == 0)
313 /* Given an rtx X being reloaded into a reg required to be
314 in class CLASS, return the class of reg to actually use.
315 In general this is just CLASS; but on some machines
316 in some cases it is preferable to use a more restrictive class.
318 If we are trying to put an integer constant into some register, prefer an
319 integer register to an FP register. If we are trying to put a
320 nonzero floating-point constant into some register, use an integer
321 register if the constant is SFmode and GENERAL_REGS is one of our options.
322 Otherwise, put the constant into memory.
324 When reloading something smaller than a word, use a general reg
325 rather than an FP reg. */
327 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
328 ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \
329 : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \
330 && (CLASS) == ALL_REGS) \
332 : (GET_CODE (X) == CONST_DOUBLE \
333 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
334 && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \
335 ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \
336 : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \
340 /* Return the register class of a scratch register needed to copy IN into
341 a register in CLASS in MODE. If it can be done directly, NO_REGS is
344 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
345 ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
347 /* Return the maximum number of consecutive registers
348 needed to represent mode MODE in a register of class CLASS. */
349 /* On the i860, this is the size of MODE in words. */
350 #define CLASS_MAX_NREGS(CLASS, MODE) \
351 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
353 /* Stack layout; function entry, exit and calling. */
355 /* Define this if pushing a word on the stack
356 makes the stack pointer a smaller address. */
357 #define STACK_GROWS_DOWNWARD
359 /* Define this to non-zero if the nominal address of the stack frame
360 is at the high-address end of the local variables;
361 that is, each additional local variable allocated
362 goes at a more negative offset in the frame. */
363 #define FRAME_GROWS_DOWNWARD 1
365 /* Offset within stack frame to start allocating local variables at.
366 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
367 first local allocated. Otherwise, it is the offset to the BEGINNING
368 of the first local allocated. */
369 #define STARTING_FRAME_OFFSET 0
371 /* If we generate an insn to push BYTES bytes,
372 this says how many the stack pointer really advances by.
373 On the i860, don't define this because there are no push insns. */
374 /* #define PUSH_ROUNDING(BYTES) */
376 /* Offset of first parameter from the argument pointer register value. */
377 #define FIRST_PARM_OFFSET(FNDECL) 0
379 /* Value is the number of bytes of arguments automatically
380 popped when returning from a subroutine call.
381 FUNDECL is the declaration node of the function (as a tree),
382 FUNTYPE is the data type of the function (as a tree),
383 or for a library call it is an identifier node for the subroutine name.
384 SIZE is the number of bytes of arguments passed on the stack. */
386 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
388 /* Define how to find the value returned by a function.
389 VALTYPE is the data type of the value (as a tree).
390 If the precise function being called is known, FUNC is its FUNCTION_DECL;
391 otherwise, FUNC is 0. */
393 /* On the i860, the value register depends on the mode. */
395 #define FUNCTION_VALUE(VALTYPE, FUNC) \
396 gen_rtx_REG (TYPE_MODE (VALTYPE), \
397 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
400 /* Define how to find the value returned by a library function
401 assuming the value has mode MODE. */
403 #define LIBCALL_VALUE(MODE) \
405 (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
408 /* 1 if N is a possible register number for a function value
409 as seen by the caller. */
411 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
413 /* 1 if N is a possible register number for function argument passing.
414 On the i860, these are r16-r27 and f8-f15. */
416 #define FUNCTION_ARG_REGNO_P(N) \
417 (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
419 /* Define a data type for recording info about an argument list
420 during the scan of that argument list. This data type should
421 hold all necessary information about the function itself
422 and about the args processed so far, enough to enable macros
423 such as FUNCTION_ARG to determine where the next arg should go.
425 On the i860, we must count separately the number of general registers used
426 and the number of float registers used. */
428 struct cumulative_args
{ int ints
, floats
; };
429 #define CUMULATIVE_ARGS struct cumulative_args
431 /* Initialize a variable CUM of type CUMULATIVE_ARGS
432 for a call to a function whose data type is FNTYPE.
433 For a library call, FNTYPE is 0.
435 On the i860, the general-reg offset normally starts at 0,
436 but starts at 4 bytes
437 when the function gets a structure-value-address as an
438 invisible first argument. */
440 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
441 ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE)), 0) \
445 /* Machine-specific subroutines of the following macros. */
446 #define CEILING(X,Y) (((X) + (Y) - 1) / (Y))
447 #define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y))
449 /* Update the data in CUM to advance over an argument
450 of mode MODE and data type TYPE.
451 (TYPE is null for libcalls where that information may not be available.)
452 Floats, and doubleword ints, are returned in f regs;
453 other ints, in r regs.
454 Aggregates, even short ones, are passed in memory. */
456 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
457 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
458 || TREE_CODE ((TYPE)) == UNION_TYPE) \
460 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
461 ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \
462 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
463 : GET_MODE_CLASS ((MODE)) == MODE_INT \
464 ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
465 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
468 /* Determine where to put an argument to a function.
469 Value is zero to push the argument on the stack,
470 or a hard register in which to store the argument.
472 MODE is the argument's machine mode.
473 TYPE is the data type of the argument (as a tree).
474 This is null for libcalls where that information may
476 CUM is a variable of type CUMULATIVE_ARGS which gives info about
477 the preceding args and about the function being called.
478 NAMED is nonzero if this argument is a named parameter
479 (otherwise it is an extra parameter matching an ellipsis). */
481 /* On the i860, the first 12 words of integer arguments go in r16-r27,
482 and the first 8 words of floating arguments go in f8-f15.
483 DImode values are treated as floats. */
485 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
486 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
487 || TREE_CODE ((TYPE)) == UNION_TYPE) \
489 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
490 ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
491 ? gen_rtx_REG ((MODE), \
492 40 + (ROUNDUP ((CUM).floats, \
493 GET_MODE_SIZE ((MODE))) \
496 : GET_MODE_CLASS ((MODE)) == MODE_INT \
497 ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
498 ? gen_rtx_REG ((MODE), \
499 16 + (ROUNDUP ((CUM).ints, \
500 GET_MODE_SIZE ((MODE))) \
505 /* If defined, a C expression that gives the alignment boundary, in
506 bits, of an argument with the specified mode and type. If it is
507 not defined, `PARM_BOUNDARY' is used for all arguments. */
509 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
511 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
513 : TYPE_ALIGN(TYPE)) \
514 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
516 : GET_MODE_ALIGNMENT(MODE)))
518 /* Output a no-op just before the beginning of the function,
519 to ensure that there does not appear to be a delayed branch there.
520 Such a thing would confuse interrupt recovery. */
521 #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
522 fprintf (FILE, "\tnop\n")
524 /* Output assembler code to FILE to increment profiler label # LABELNO
525 for profiling a function entry. */
527 #define FUNCTION_PROFILER(FILE, LABELNO) \
530 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
531 the stack pointer does not matter. The value is tested only in
532 functions that have frame pointers.
533 No definition is equivalent to always zero. */
535 #define EXIT_IGNORE_STACK 1
537 /* Implement `va_start' for varargs and stdarg. */
538 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
539 i860_va_start (valist, nextarg)
541 /* Store in the variable DEPTH the initial difference between the
542 frame pointer reg contents and the stack pointer reg contents,
543 as of the start of the function body. This depends on the layout
544 of the fixed parts of the stack frame and on how registers are saved.
546 On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
547 macro doesn't matter. But it must be defined. */
549 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
550 do { (DEPTH) = 0; } while (0)
552 /* Output assembler code for a block containing the constant parts
553 of a trampoline, leaving space for the variable parts. */
555 /* On the i860, the trampoline contains five instructions:
556 orh #TOP_OF_FUNCTION,r0,r31
557 or #BOTTOM_OF_FUNCTION,r31,r31
558 orh #TOP_OF_STATIC,r0,r29
560 or #BOTTOM_OF_STATIC,r29,r29 */
561 #define TRAMPOLINE_TEMPLATE(FILE) \
563 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1f0000)); \
564 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7ff0000)); \
565 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1d0000)); \
566 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x4000f800)); \
567 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7bd0000)); \
570 /* Length in units of the trampoline for entering a nested function. */
572 #define TRAMPOLINE_SIZE 20
574 /* Emit RTL insns to initialize the variable parts of a trampoline.
575 FNADDR is an RTX for the address of the function's pure code.
576 CXT is an RTX for the static chain value for the function.
578 Store hi function at +0, low function at +4,
579 hi static at +8, low static at +16 */
581 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
583 rtx cxt = force_reg (Pmode, CXT); \
584 rtx fn = force_reg (Pmode, FNADDR); \
585 rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \
586 size_int (16), 0, 0); \
587 rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \
588 size_int (16), 0, 0); \
589 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 16)), \
590 gen_lowpart (HImode, cxt)); \
591 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 4)), \
592 gen_lowpart (HImode, fn)); \
593 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 8)), \
594 gen_lowpart (HImode, hi_cxt)); \
595 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 0)), \
596 gen_lowpart (HImode, hi_fn)); \
599 /* Addressing modes, and classification of registers for them. */
601 /* #define HAVE_POST_INCREMENT 0 */
602 /* #define HAVE_POST_DECREMENT 0 */
604 /* #define HAVE_PRE_DECREMENT 0 */
605 /* #define HAVE_PRE_INCREMENT 0 */
607 /* Macros to check register numbers against specific register classes. */
609 /* These assume that REGNO is a hard or pseudo reg number.
610 They give nonzero only if REGNO is a hard reg of the suitable class
611 or a pseudo reg currently allocated to a suitable hard reg.
612 Since they use reg_renumber, they are safe only once reg_renumber
613 has been allocated, which happens in local-alloc.c. */
615 #define REGNO_OK_FOR_INDEX_P(REGNO) \
616 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
617 #define REGNO_OK_FOR_BASE_P(REGNO) \
618 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
619 #define REGNO_OK_FOR_FP_P(REGNO) \
620 (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
622 /* Now macros that check whether X is a register and also,
623 strictly, whether it is in a specified class.
625 These macros are specific to the i860, and may be used only
626 in code for printing assembler insns and in conditions for
627 define_optimization. */
629 /* 1 if X is an fp register. */
631 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
633 /* Maximum number of registers that can appear in a valid memory address. */
635 #define MAX_REGS_PER_ADDRESS 2
637 /* Recognize any constant value that is a valid address. */
639 #define CONSTANT_ADDRESS_P(X) \
640 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
641 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
642 || GET_CODE (X) == HIGH)
644 /* Nonzero if the constant value X is a legitimate general operand.
645 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
647 On the Sparc, this is anything but a CONST_DOUBLE.
648 Let's try permitting CONST_DOUBLEs and see what happens. */
650 #define LEGITIMATE_CONSTANT_P(X) 1
652 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
653 and check its validity for a certain class.
654 We have two alternate definitions for each of them.
655 The usual definition accepts all pseudo regs; the other rejects
656 them unless they have been allocated suitable hard regs.
657 The symbol REG_OK_STRICT causes the latter definition to be used.
659 Most source files want to accept pseudo regs in the hope that
660 they will get allocated to the class that the insn wants them to be in.
661 Source files for reload pass need to be strict.
662 After reload, it makes no difference, since pseudo regs have
663 been eliminated by then. */
665 #ifndef REG_OK_STRICT
667 /* Nonzero if X is a hard reg that can be used as an index
668 or if it is a pseudo reg. */
669 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
670 /* Nonzero if X is a hard reg that can be used as a base reg
671 or if it is a pseudo reg. */
672 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
676 /* Nonzero if X is a hard reg that can be used as an index. */
677 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
678 /* Nonzero if X is a hard reg that can be used as a base reg. */
679 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
683 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
684 that is a valid memory address for an instruction.
685 The MODE argument is the machine mode for the MEM expression
686 that wants to use this address.
688 On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
689 But we can treat a SYMBOL_REF as legitimate if it is part of this
690 function's constant-pool, because such addresses can actually
691 be output as REG+SMALLINT.
693 The displacement in an address must be a multiple of the alignment.
695 Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
696 a legitimate address, regardless. Because the only insns which can use
697 memory are load or store insns, the added hair in the machine description
698 is not that bad. It should also speed up the compiler by halving the number
699 of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */
701 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
702 { if (GET_CODE (X) == REG) \
703 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
704 else if (GET_CODE (X) == PLUS) \
706 if (GET_CODE (XEXP (X, 0)) == REG \
707 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
709 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
710 && INTVAL (XEXP (X, 1)) >= -0x8000 \
711 && INTVAL (XEXP (X, 1)) < 0x8000 \
712 && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
715 else if (GET_CODE (XEXP (X, 1)) == REG \
716 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
718 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
719 && INTVAL (XEXP (X, 0)) >= -0x8000 \
720 && INTVAL (XEXP (X, 0)) < 0x8000 \
721 && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
725 else if (CONSTANT_ADDRESS_P (X)) \
729 /* Try machine-dependent ways of modifying an illegitimate address
730 to be legitimate. If we find one, return the new, valid address.
731 This macro is used in only one place: `memory_address' in explow.c.
733 OLDX is the address as it was before break_out_memory_refs was called.
734 In some cases it is useful to look at this to decide what needs to be done.
736 MODE and WIN are passed so that this macro can use
737 GO_IF_LEGITIMATE_ADDRESS.
739 It is always safe for this macro to do nothing. It exists to recognize
740 opportunities to optimize the output. */
742 /* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
743 Also change a symbolic constant to a REG,
744 though that may not be necessary. */
746 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
747 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
748 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
749 force_operand (XEXP (X, 0), 0)); \
750 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
751 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
752 force_operand (XEXP (X, 1), 0)); \
753 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
754 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
755 force_operand (XEXP (X, 0), 0)); \
756 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
757 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
758 force_operand (XEXP (X, 1), 0)); \
759 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
760 && GET_CODE (XEXP (X, 0)) != CONST_INT) \
761 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
762 copy_to_mode_reg (SImode, XEXP (X, 0))); \
763 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
764 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
765 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
766 copy_to_mode_reg (SImode, XEXP (X, 1))); \
767 if (GET_CODE (x) == SYMBOL_REF) \
768 (X) = copy_to_reg (X); \
769 if (GET_CODE (x) == CONST) \
770 (X) = copy_to_reg (X); \
771 if (memory_address_p (MODE, X)) \
774 /* Go to LABEL if ADDR (a legitimate address expression)
775 has an effect that depends on the machine mode it is used for.
776 On the i860 this is never true.
777 There are some addresses that are invalid in wide modes
778 but valid for narrower modes, but they shouldn't affect
779 the places that use this macro. */
781 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
783 /* Specify the machine mode that this machine uses
784 for the index in the tablejump instruction. */
785 #define CASE_VECTOR_MODE SImode
787 /* Define this as 1 if `char' should by default be signed; else as 0. */
788 #define DEFAULT_SIGNED_CHAR 1
790 /* Max number of bytes we can move from memory to memory
791 in one reasonably fast instruction. */
794 /* Nonzero if access to memory by bytes is slow and undesirable. */
795 #define SLOW_BYTE_ACCESS 0
797 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
798 is done just by pretending it is already truncated. */
799 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
801 /* Value is 1 if it generates better code to perform an unsigned comparison
802 on the given literal integer value in the given mode when we are only
803 looking for an equal/non-equal result. */
804 /* For the i860, if the immediate value has its high-order 27 bits zero,
805 then we want to engineer an unsigned comparison for EQ/NE because
806 such values can fit in the 5-bit immediate field of a bte or btne
807 instruction (which gets zero extended before comparing). For all
808 other immediate values on the i860, we will use signed compares
809 because that avoids the need for doing explicit xor's to zero_extend
810 the non-constant operand in cases where it was (mem:QI ...) or a
811 (mem:HI ...) which always gets automatically sign-extended by the
812 hardware upon loading. */
814 #define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \
815 (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
817 /* Specify the machine mode that pointers have.
818 After generation of rtl, the compiler makes no further distinction
819 between pointers and any other objects of this machine mode. */
822 /* A function address in a call instruction
823 is a byte address (for indexing purposes)
824 so give the MEM rtx a byte's mode. */
825 #define FUNCTION_MODE SImode
827 /* Define this if addresses of constant functions
828 shouldn't be put through pseudo regs where they can be cse'd.
829 Desirable on machines where ordinary constants are expensive
830 but a CALL with constant address is cheap. */
831 #define NO_FUNCTION_CSE
833 /* Specify the cost of a branch insn; roughly the number of extra insns that
834 should be added to avoid a branch.
836 Set this to 3 on the i860 since branches may often take three cycles. */
838 #define BRANCH_COST 3
840 /* Tell final.c how to eliminate redundant test instructions. */
842 /* Here we define machine-dependent flags and fields in cc_status
843 (see `conditions.h'). */
845 /* This holds the value sourcing h%r31. We keep this info
846 around so that mem/mem ops, such as increment and decrement,
847 etc, can be performed reasonably. */
848 #define CC_STATUS_MDEP rtx
850 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
852 #define CC_NEGATED 01000
854 /* We use this macro in those places in the i860.md file where we would
855 normally just do a CC_STATUS_INIT (for other machines). This macro
856 differs from CC_STATUS_INIT in that it doesn't mess with the special
857 bits or fields which describe what is currently in the special r31
858 scratch register, but it does clear out everything that actually
859 relates to the condition code bit of the i860. */
861 #define CC_STATUS_PARTIAL_INIT \
862 (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \
863 cc_status.value1 = 0, \
864 cc_status.value2 = 0)
866 /* Nonzero if we know the value of h%r31. */
867 #define CC_KNOW_HI_R31 0100000
869 /* Nonzero if h%r31 is actually ha%something, rather than h%something. */
870 #define CC_HI_R31_ADJ 0200000
872 /* Store in cc_status the expressions
873 that the condition codes will describe
874 after execution of an instruction whose pattern is EXP.
875 Do not alter them if the instruction would not alter the cc's. */
877 /* On the i860, only compare insns set a useful condition code. */
879 #define NOTICE_UPDATE_CC(EXP, INSN) \
880 { cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \
881 cc_status.value1 = 0; cc_status.value2 = 0; }
883 /* Control the assembler format that we output. */
885 /* Assembler pseudos to introduce constants of various size. */
887 #define ASM_DOUBLE "\t.double"
889 /* Output to assembler file text saying following lines
890 may contain character constants, extra white space, comments, etc. */
892 #define ASM_APP_ON ""
894 /* Output to assembler file text saying following lines
895 no longer contain unusual constructs. */
897 #define ASM_APP_OFF ""
899 /* Output before read-only data. */
901 #define TEXT_SECTION_ASM_OP "\t.text"
903 /* Output before writable data. */
905 #define DATA_SECTION_ASM_OP "\t.data"
907 /* How to refer to registers in assembler output.
908 This sequence is indexed by compiler's hard-register-number (see above). */
910 #define REGISTER_NAMES \
911 {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \
912 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
913 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
915 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
916 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
917 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
920 /* This is how to output the definition of a user-level label named NAME,
921 such as the label on a static function or variable NAME. */
923 #define ASM_OUTPUT_LABEL(FILE,NAME) \
924 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
926 /* The prefix to add to user-visible assembler symbols.
928 This definition is overridden in i860/sysv4.h because under System V
929 Release 4, user-level symbols are *not* prefixed with underscores in
930 the generated assembly code. */
932 #define USER_LABEL_PREFIX "_"
934 /* This is how to output an internal numbered label which
935 labels a jump table. */
937 #undef ASM_OUTPUT_CASE_LABEL
938 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
939 do { ASM_OUTPUT_ALIGN ((FILE), 2); \
940 (*targetm.asm_out.internal_label) ((FILE), PREFIX, NUM); \
943 /* Output at the end of a jump table. */
945 #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
946 fprintf (FILE, ".text\n")
948 /* This is how to store into the string LABEL
949 the symbol_ref name of an internal numbered label where
950 PREFIX is the class of label and NUM is the number within the class.
951 This is suitable for output with `assemble_name'. */
953 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
954 sprintf (LABEL, "*.%s%d", PREFIX, NUM)
956 /* This is how to output code to push a register on the stack.
957 It need not be very fast code. */
959 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
960 fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \
961 i860_reg_prefix, i860_reg_prefix, \
962 ((REGNO) < 32 ? "" : "f"), \
963 i860_reg_prefix, reg_names[REGNO], \
966 /* This is how to output an insn to pop a register from the stack.
967 It need not be very fast code. */
969 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
970 fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \
971 ((REGNO) < 32 ? "" : "f"), \
973 i860_reg_prefix, reg_names[REGNO], \
974 i860_reg_prefix, i860_reg_prefix)
976 /* This is how to output an element of a case-vector that is absolute. */
978 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
979 fprintf (FILE, "\t.long .L%d\n", VALUE)
981 /* This is how to output an element of a case-vector that is relative.
982 (The i860 does not use such vectors,
983 but we must define this macro anyway.) */
985 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
986 fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
988 /* This is how to output an assembler line
989 that says to advance the location counter
990 to a multiple of 2**LOG bytes. */
992 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
994 fprintf (FILE, "\t.align %d\n", 1 << (LOG))
996 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
997 fprintf (FILE, "\t.blkb %u\n", (SIZE))
999 /* This says how to output an assembler line
1000 to define a global common symbol. */
1002 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1003 ( fputs (".comm ", (FILE)), \
1004 assemble_name ((FILE), (NAME)), \
1005 fprintf ((FILE), ",%u\n", (ROUNDED)))
1007 /* This says how to output an assembler line
1008 to define a local common symbol. */
1010 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1011 ( fputs (".lcomm ", (FILE)), \
1012 assemble_name ((FILE), (NAME)), \
1013 fprintf ((FILE), ",%u\n", (ROUNDED)))
1015 /* Store in OUTPUT a string (made with alloca) containing
1016 an assembler-name for a local static variable named NAME.
1017 LABELNO is an integer which is different for each call. */
1019 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1020 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1021 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1023 /* Print operand X (an rtx) in assembler syntax to file FILE.
1024 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1025 For `%' followed by punctuation, CODE is the punctuation and X is null.
1027 In the following comments, the term "constant address" is used frequently.
1028 For an exact definition of what constitutes a "constant address" see the
1029 output_addr_const routine in final.c
1031 On the i860, the following target-specific special codes are recognized:
1033 `r' The operand can be anything, but if it is an immediate zero
1034 value (either integer or floating point) then it will be
1035 represented as `r0' or as `f0' (respectively).
1037 `m' The operand is a memory ref (to a constant address) but print
1038 its address as a constant.
1040 `L' The operand is a numeric constant, a constant address, or
1041 a memory ref to a constant address. Print the correct
1042 notation to yield the low part of the given value or
1043 address or the low part of the address of the referred
1046 `H' The operand is a numeric constant, a constant address, or
1047 a memory ref to a constant address. Print the correct
1048 notation to yield the high part of the given value or
1049 address or the high part of the address of the referred
1052 `h' The operand is a numeric constant, a constant address, or
1053 a memory ref to a constant address. Either print the
1054 correct notation to yield the plain high part of the
1055 given value or address (or the plain high part of the
1056 address of the memory object) or else print the correct
1057 notation to yield the "adjusted" high part of the given
1058 address (or of the address of the referred to memory object).
1060 The choice of what to print depends upon whether the address
1061 in question is relocatable or not. If it is relocatable,
1062 print the notation to get the adjusted high part. Otherwise
1063 just print the notation to get the plain high part. Note
1064 that "adjusted" high parts are generally used *only* when
1065 the next following instruction uses the low part of the
1066 address as an offset, as in `offset(reg)'.
1068 `R' The operand is a floating-pointer register. Print the
1069 name of the next following (32-bit) floating-point register.
1070 (This is used when moving a value into just the most
1071 significant part of a floating-point register pair.)
1073 `?' (takes no operand) Substitute the value of i860_reg_prefix
1074 at this point. The value of i860_reg_prefix is typically
1075 a null string for most i860 targets, but for System V
1076 Release 4 the i860 assembler syntax requires that all
1077 names of registers be prefixed with a percent-sign, so
1078 for SVR4, the value of i860_reg_prefix is initialized to
1082 extern const char *i860_reg_prefix
;
1084 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
1086 /* The following macro definition is overridden in i860v4.h
1087 because the svr4 i860 assembler required a different syntax
1088 for getting parts of constant/relocatable values. */
1090 #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
1091 do { fprintf (FILE, "%s%%", PART_CODE); \
1092 output_address (X); \
1095 #define OPERAND_LOW_PART "l"
1096 #define OPERAND_HIGH_PART "h"
1097 /* NOTE: All documentation available for the i860 sez that you must
1098 use "ha" to get the relocated high part of a relocatable, but
1099 reality sez different. */
1100 #define OPERAND_HIGH_ADJ_PART "ha"
1102 #define PRINT_OPERAND(FILE, X, CODE) \
1103 { if ((CODE) == '?') \
1104 fprintf (FILE, "%s", i860_reg_prefix); \
1105 else if (CODE == 'R') \
1106 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \
1107 else if (GET_CODE (X) == REG) \
1108 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \
1109 else if ((CODE) == 'm') \
1110 output_address (XEXP (X, 0)); \
1111 else if ((CODE) == 'L') \
1113 if (GET_CODE (X) == MEM) \
1114 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
1116 PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
1118 else if ((CODE) == 'H') \
1120 if (GET_CODE (X) == MEM) \
1121 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
1123 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
1125 else if ((CODE) == 'h') \
1127 if (GET_CODE (X) == MEM) \
1128 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \
1130 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \
1132 else if (GET_CODE (X) == MEM) \
1133 output_address (XEXP (X, 0)); \
1134 else if ((CODE) == 'r' && (X) == const0_rtx) \
1135 fprintf (FILE, "%sr0", i860_reg_prefix); \
1136 else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
1137 fprintf (FILE, "%sf0", i860_reg_prefix); \
1138 else if (GET_CODE (X) == CONST_DOUBLE) \
1139 fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (X)); \
1141 output_addr_const (FILE, X); }
1143 /* Print a memory address as an operand to reference that memory location. */
1145 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1146 { register rtx addr = ADDR; \
1147 if (GET_CODE (addr) == REG) \
1149 fprintf (FILE, "0(%s%s)", \
1150 i860_reg_prefix, reg_names[REGNO (addr)]); \
1152 else if (GET_CODE (addr) == CONST_DOUBLE \
1153 && GET_MODE (addr) == SFmode) \
1154 fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (addr)); \
1155 else if (GET_CODE (addr) == PLUS) \
1157 if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1158 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1159 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \
1160 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1161 else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1162 && (GET_CODE (XEXP (addr, 0)) == REG)) \
1163 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \
1164 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
1165 else if ((GET_CODE (XEXP (addr, 0)) == REG) \
1166 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1167 fprintf (FILE, "%s%s(%s%s)", \
1168 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \
1169 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1171 output_addr_const (FILE, addr); \
1175 output_addr_const (FILE, addr); \
1179 /* Optionally define this if you have added predicates to
1180 `MACHINE.c'. This macro is called within an initializer of an
1181 array of structures. The first field in the structure is the
1182 name of a predicate and the second field is an array of rtl
1183 codes. For each predicate, list all rtl codes that can be in
1184 expressions matched by the predicate. The list should have a
1185 trailing comma. Here is an example of two entries in the list
1186 for a typical RISC machine:
1188 #define PREDICATE_CODES \
1189 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
1190 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
1192 Defining this macro does not affect the generated code (however,
1193 incorrect definitions that omit an rtl code that may be matched
1194 by the predicate can cause the compiler to malfunction).
1195 Instead, it allows the table built by `genrecog' to be more
1196 compact and efficient, thus speeding up the compiler. The most
1197 important predicates to include in the list specified by this
1198 macro are thoses used in the most insn patterns. */
1200 #define PREDICATE_CODES \
1201 {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
1202 {"arith_operand", {REG, SUBREG, CONST_INT}}, \
1203 {"logic_operand", {REG, SUBREG, CONST_INT}}, \
1204 {"shift_operand", {REG, SUBREG, CONST_INT}}, \
1205 {"compare_operand", {REG, SUBREG, CONST_INT}}, \
1206 {"bte_operand", {REG, SUBREG, CONST_INT}}, \
1207 {"indexed_operand", {MEM}}, \
1208 {"load_operand", {MEM}}, \
1209 {"small_int", {CONST_INT}}, \
1210 {"logic_int", {CONST_INT}}, \
1211 {"call_insn_operand", {MEM}},
1213 /* Define the information needed to generate branch insns. This is stored
1214 from the compare operation. Note that we can't use "rtx" here since it
1215 hasn't been defined! */
1217 extern struct rtx_def
*i860_compare_op0
, *i860_compare_op1
;