1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files may include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 #define MULTILIB_DEFAULTS { "mnumerics" }
29 /* Names to predefine in the preprocessor for this target machine. */
30 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
32 /* Name to predefine in the preprocessor for processor variations. */
33 #define CPP_SPEC "%{mic*:-D__i960\
34 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
35 %{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
37 %{msa:-D__i960SA}%{msb:-D__i960SB}\
39 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
41 %{mka:-D__i960KA__ -D__i960_KA__}\
42 %{mkb:-D__i960KB__ -D__i960_KB__}\
43 %{msa:-D__i960SA__ -D__i960_SA__}\
44 %{msb:-D__i960SB__ -D__i960_SB__}\
45 %{mmc:-D__i960MC__ -D__i960_MC__}\
46 %{mca:-D__i960CA__ -D__i960_CA__}\
47 %{mcc:-D__i960CC__ -D__i960_CC__}\
48 %{mcf:-D__i960CF__ -D__i960_CF__}\
49 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
50 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
51 %{mlong-double-64:-D__LONG_DOUBLE_64__}"
53 /* -mic* options make characters signed by default. */
54 /* Use #if rather than ?: because MIPS C compiler rejects ?: in
56 #if DEFAULT_SIGNED_CHAR
57 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
59 #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
62 /* Specs for the compiler, to handle processor variations.
63 If the user gives an explicit -gstabs or -gcoff option, then do not
64 try to add an implicit one, as this will fail. */
66 "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
67 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
68 %{mcoff:%{g*:-gcoff}}\
69 %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
71 /* Specs for the assembler, to handle processor variations.
72 For compatibility with Intel's gnu960 tool chain, pass -A options to
75 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
76 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
77 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
78 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
79 %{mlink-relax:-linkrelax}"
81 /* Specs for the linker, to handle processor variations.
82 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
85 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
86 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
87 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
88 %{mbout:-Fbout}%{mcoff:-Fcoff}\
89 %{mlink-relax:-relax}"
91 /* Specs for the libraries to link with, to handle processor variations.
92 Compatible with Intel's gnu960 tool chain. */
93 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
94 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
96 /* Show we can debug even without a frame pointer. */
97 #define CAN_DEBUG_WITHOUT_FP
99 /* Do leaf procedure and tail call optimizations for -O2 and higher. */
100 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
104 target_flags |= TARGET_FLAG_LEAFPROC; \
105 target_flags |= TARGET_FLAG_TAILCALL; \
109 /* Print subsidiary information on the compiler version in use. */
110 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
112 /* Generate DBX debugging information. */
113 #define DBX_DEBUGGING_INFO
115 /* Generate SDB style debugging information. */
116 #define SDB_DEBUGGING_INFO
117 #define EXTENDED_SDB_BASIC_TYPES
119 /* Generate DBX_DEBUGGING_INFO by default. */
120 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
122 /* Redefine this to print in hex. No value adjustment is necessary
124 #define PUT_SDB_TYPE(A) \
125 fprintf (asm_out_file, "\t.type\t0x%x;", A)
127 /* Handle pragmas for compatibility with Intel's compilers. */
128 #define HANDLE_PRAGMA(GET, UNGET, NAME) process_pragma (GET, UNGET, NAME)
129 extern int process_pragma ();
131 /* Run-time compilation parameters selecting different hardware subsets. */
133 /* 960 architecture with floating-point. */
134 #define TARGET_FLAG_NUMERICS 0x01
135 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
137 /* 960 architecture with memory management. */
138 /* ??? Not used currently. */
139 #define TARGET_FLAG_PROTECTED 0x02
140 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
142 /* The following three are mainly used to provide a little sanity checking
143 against the -mARCH flags given. The Jx series, for the purposes of
144 gcc, is a Kx with a data cache. */
146 /* Nonzero if we should generate code for the KA and similar processors.
147 No FPU, no microcode instructions. */
148 #define TARGET_FLAG_K_SERIES 0x04
149 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
151 /* Nonzero if we should generate code for the MC processor.
152 Not really different from KB for our purposes. */
153 #define TARGET_FLAG_MC 0x08
154 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
156 /* Nonzero if we should generate code for the CA processor.
157 Enables different optimization strategies. */
158 #define TARGET_FLAG_C_SERIES 0x10
159 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
161 /* Nonzero if we should generate leaf-procedures when we find them.
162 You may not want to do this because leaf-proc entries are
163 slower when not entered via BAL - this would be true when
164 a linker not supporting the optimization is used. */
165 #define TARGET_FLAG_LEAFPROC 0x20
166 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
168 /* Nonzero if we should perform tail-call optimizations when we find them.
169 You may not want to do this because the detection of cases where
170 this is not valid is not totally complete. */
171 #define TARGET_FLAG_TAILCALL 0x40
172 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
174 /* Nonzero if use of a complex addressing mode is a win on this implementation.
175 Complex addressing modes are probably not worthwhile on the K-series,
176 but they definitely are on the C-series. */
177 #define TARGET_FLAG_COMPLEX_ADDR 0x80
178 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
180 /* Align code to 8 byte boundaries for faster fetching. */
181 #define TARGET_FLAG_CODE_ALIGN 0x100
182 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
184 /* Append branch prediction suffixes to branch opcodes. */
185 /* ??? Not used currently. */
186 #define TARGET_FLAG_BRANCH_PREDICT 0x200
187 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
189 /* Forces prototype and return promotions. */
190 /* ??? This does not work. */
191 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
192 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
194 /* For compatibility with iC960 v3.0. */
195 #define TARGET_FLAG_IC_COMPAT3_0 0x800
196 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
198 /* For compatibility with iC960 v2.0. */
199 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
200 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
202 /* If no unaligned accesses are to be permitted. */
203 #define TARGET_FLAG_STRICT_ALIGN 0x2000
204 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
206 /* For compatibility with iC960 assembler. */
207 #define TARGET_FLAG_ASM_COMPAT 0x4000
208 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
210 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
211 alignment rules. Also, turns on STRICT_ALIGNMENT. */
212 #define TARGET_FLAG_OLD_ALIGN 0x8000
213 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
215 /* Nonzero if long doubles are to be 64 bits. Useful for soft-float targets
216 if 80 bit long double support is missing. */
217 #define TARGET_FLAG_LONG_DOUBLE_64 0x10000
218 #define TARGET_LONG_DOUBLE_64 (target_flags & TARGET_FLAG_LONG_DOUBLE_64)
220 extern int target_flags
;
222 /* Macro to define tables used to set the flags.
223 This is a list in braces of pairs in braces,
224 each pair being { "NAME", VALUE }
225 where VALUE is the bits to set or minus the bits to clear.
226 An empty string NAME is used to identify the default VALUE. */
228 /* ??? Not all ten of these architecture variations actually exist, but I
229 am not sure which are real and which aren't. */
231 #define TARGET_SWITCHES \
232 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
233 "Generate SA code"}, \
234 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
235 TARGET_FLAG_COMPLEX_ADDR), \
236 "Generate SB code"}, \
237 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
238 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
239 "Generate SC code"}, */ \
240 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
241 "Generate KA code"}, \
242 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
243 TARGET_FLAG_COMPLEX_ADDR), \
244 "Generate KB code"}, \
245 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
246 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
247 "Generate KC code"}, */ \
248 {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
249 "Generate JA code"}, \
250 {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
251 "Generate JD code"}, \
252 {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
253 TARGET_FLAG_COMPLEX_ADDR), \
254 "Generate JF code"}, \
255 {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
256 "generate RP code"}, \
257 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
258 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
259 "Generate MC code"}, \
260 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
261 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
262 "Generate CA code"}, \
263 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
264 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
265 "Generate CB code"}, \
266 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
267 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
268 TARGET_FLAG_CODE_ALIGN), \
269 "Generate CC code"}, */ \
270 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
271 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
272 "Generate CF code"}, \
273 {"numerics", (TARGET_FLAG_NUMERICS), \
274 "Use hardware floating point instructions"}, \
275 {"soft-float", -(TARGET_FLAG_NUMERICS), \
276 "Use software floating point"}, \
277 {"leaf-procedures", TARGET_FLAG_LEAFPROC, \
278 "Use alternate leaf function entries"}, \
279 {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
280 "Do not use alternate leaf function entries"}, \
281 {"tail-call", TARGET_FLAG_TAILCALL, \
282 "Perform tail call optimization"}, \
283 {"no-tail-call", -(TARGET_FLAG_TAILCALL), \
284 "Do not perform tail call optimization"}, \
285 {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
286 "Use complex addressing modes"}, \
287 {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
288 "Do not use complex addressing modes"}, \
289 {"code-align", TARGET_FLAG_CODE_ALIGN, \
290 "Align code to 8 byte boundary"}, \
291 {"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
292 "Do not align code to 8 byte boundary"}, \
293 /* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
294 "Force use of prototypes"}, \
295 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
296 "Do not force use of prototypes"}, */ \
297 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
298 "Enable compatibility with iC960 v2.0"}, \
299 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
300 "Enable compatibility with iC960 v2.0"}, \
301 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
302 "Enable compatibility with iC960 v3.0"}, \
303 {"asm-compat", TARGET_FLAG_ASM_COMPAT, \
304 "Enable compatibility with ic960 assembler"}, \
305 {"intel-asm", TARGET_FLAG_ASM_COMPAT, \
306 "Enable compatibility with ic960 assembler"}, \
307 {"strict-align", TARGET_FLAG_STRICT_ALIGN, \
308 "Do not permit unaligned accesses"}, \
309 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
310 "Permit unaligned accesses"}, \
311 {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
312 "Layout types like Intel's v1.3 gcc"}, \
313 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
314 "Do not layout types like Intel's v1.3 gcc"}, \
315 {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
316 "Use 64 bit long doubles"}, \
318 "Enable linker relaxation"}, \
319 {"no-link-relax", 0, \
320 "Do not enable linker relaxation"}, \
322 { "", TARGET_DEFAULT, \
325 /* This are meant to be redefined in the host dependent files */
326 #define SUBTARGET_SWITCHES
328 /* Override conflicting target switch options.
329 Doesn't actually detect if more than one -mARCH option is given, but
330 does handle the case of two blatantly conflicting -mARCH options. */
331 #define OVERRIDE_OPTIONS \
333 if (TARGET_K_SERIES && TARGET_C_SERIES) \
335 warning ("conflicting architectures defined - using C series", 0); \
336 target_flags &= ~TARGET_FLAG_K_SERIES; \
338 if (TARGET_K_SERIES && TARGET_MC) \
340 warning ("conflicting architectures defined - using K series", 0); \
341 target_flags &= ~TARGET_FLAG_MC; \
343 if (TARGET_C_SERIES && TARGET_MC) \
345 warning ("conflicting architectures defined - using C series", 0);\
346 target_flags &= ~TARGET_FLAG_MC; \
348 if (TARGET_IC_COMPAT3_0) \
350 flag_short_enums = 1; \
351 flag_signed_char = 1; \
352 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
353 if (TARGET_IC_COMPAT2_0) \
355 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
356 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
359 if (TARGET_IC_COMPAT2_0) \
361 flag_signed_char = 1; \
362 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
364 /* ??? See the LONG_DOUBLE_TYPE_SIZE definition below. */ \
365 if (TARGET_LONG_DOUBLE_64) \
366 warning ("The -mlong-double-64 option does not work yet.", 0);\
367 i960_initialize (); \
370 /* Don't enable anything by default. The user is expected to supply a -mARCH
371 option. If none is given, then -mka is added by CC1_SPEC. */
372 #define TARGET_DEFAULT 0
374 /* Target machine storage layout. */
376 /* Define for cross-compilation from a host with a different float format
377 or endianness, as well as to support 80 bit long doubles on the i960. */
378 #define REAL_ARITHMETIC
380 /* Define this if most significant bit is lowest numbered
381 in instructions that operate on numbered bit-fields. */
382 #define BITS_BIG_ENDIAN 0
384 /* Define this if most significant byte of a word is the lowest numbered.
385 The i960 case be either big endian or little endian. We only support
386 little endian, which is the most common. */
387 #define BYTES_BIG_ENDIAN 0
389 /* Define this if most significant word of a multiword number is lowest
391 #define WORDS_BIG_ENDIAN 0
393 /* Number of bits in an addressable storage unit. */
394 #define BITS_PER_UNIT 8
396 /* Bitfields cannot cross word boundaries. */
397 #define BITFIELD_NBYTES_LIMITED 1
399 /* Width in bits of a "word", which is the contents of a machine register.
400 Note that this is not necessarily the width of data type `int';
401 if using 16-bit ints on a 68000, this would still be 32.
402 But on a machine with 16-bit registers, this would be 16. */
403 #define BITS_PER_WORD 32
405 /* Width of a word, in units (bytes). */
406 #define UNITS_PER_WORD 4
408 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
409 #define POINTER_SIZE 32
411 /* Width in bits of a long double. Define to 96, and let
412 ROUND_TYPE_ALIGN adjust the alignment for speed. */
413 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96)
415 /* ??? This must be a constant, because real.c and real.h test it with #if. */
416 #undef LONG_DOUBLE_TYPE_SIZE
417 #define LONG_DOUBLE_TYPE_SIZE 96
419 /* Define this to set long double type size to use in libgcc2.c, which can
420 not depend on target_flags. */
421 #if defined(__LONG_DOUBLE_64__)
422 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
424 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
427 /* Allocation boundary (in *bits*) for storing pointers in memory. */
428 #define POINTER_BOUNDARY 32
430 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
431 #define PARM_BOUNDARY 32
433 /* Boundary (in *bits*) on which stack pointer should be aligned. */
434 #define STACK_BOUNDARY 128
436 /* Allocation boundary (in *bits*) for the code of a function. */
437 #define FUNCTION_BOUNDARY 128
439 /* Alignment of field after `int : 0' in a structure. */
440 #define EMPTY_FIELD_BOUNDARY 32
442 /* This makes zero-length anonymous fields lay the next field
443 at a word boundary. It also makes the whole struct have
444 at least word alignment if there are any bitfields at all. */
445 #define PCC_BITFIELD_TYPE_MATTERS 1
447 /* Every structure's size must be a multiple of this. */
448 #define STRUCTURE_SIZE_BOUNDARY 8
450 /* No data type wants to be aligned rounder than this.
451 Extended precision floats gets 4-word alignment. */
452 #define BIGGEST_ALIGNMENT 128
454 /* Define this if move instructions will actually fail to work
455 when given unaligned data.
456 80960 will work even with unaligned data, but it is slow. */
457 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
459 /* Specify alignment for string literals (which might be higher than the
460 base type's minimal alignment requirement. This allows strings to be
461 aligned on word boundaries, and optimizes calls to the str* and mem*
462 library functions. */
463 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
464 (TREE_CODE (EXP) == STRING_CST \
465 && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
466 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
469 /* Make XFmode floating point quantities be 128 bit aligned. */
470 #define DATA_ALIGNMENT(TYPE, ALIGN) \
471 (TREE_CODE (TYPE) == ARRAY_TYPE \
472 && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
473 && (ALIGN) < 128 ? 128 : (ALIGN))
475 /* Macros to determine size of aggregates (structures and unions
476 in C). Normally, these may be defined to simply return the maximum
477 alignment and simple rounded-up size, but on some machines (like
478 the i960), the total size of a structure is based on a non-trivial
481 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
482 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
483 ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
484 : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \
485 && TREE_CODE (TYPE) == RECORD_TYPE) \
486 ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
487 : MAX ((COMPUTED), (SPECIFIED))))
489 #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
490 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
491 ? build_int_2 (128, 0) : round_up (COMPUTED, SPECIFIED))
493 /* Standard register usage. */
495 /* Number of actual hardware registers.
496 The hardware registers are assigned numbers for the compiler
497 from 0 to just below FIRST_PSEUDO_REGISTER.
498 All registers that the compiler knows about must be given numbers,
499 even those that are not normally considered general registers.
501 Registers 0-15 are the global registers (g0-g15).
502 Registers 16-31 are the local registers (r0-r15).
503 Register 32-35 are the fp registers (fp0-fp3).
504 Register 36 is the condition code register.
505 Register 37 is unused. */
507 #define FIRST_PSEUDO_REGISTER 38
509 /* 1 for registers that have pervasive standard uses and are not available
510 for the register allocator. On 80960, this includes the frame pointer
511 (g15), the previous FP (r0), the stack pointer (r1), the return
512 instruction pointer (r2), and the argument pointer (g14). */
513 #define FIXED_REGISTERS \
514 {0, 0, 0, 0, 0, 0, 0, 0, \
515 0, 0, 0, 0, 0, 0, 1, 1, \
516 1, 1, 1, 0, 0, 0, 0, 0, \
517 0, 0, 0, 0, 0, 0, 0, 0, \
520 /* 1 for registers not available across function calls.
521 These must include the FIXED_REGISTERS and also any
522 registers that can be used without being saved.
523 The latter must include the registers where values are returned
524 and the register where structure-value addresses are passed.
525 Aside from that, you can include as many other registers as you like. */
527 /* On the 80960, note that:
528 g0..g3 are used for return values,
529 g0..g7 may always be used for parameters,
530 g8..g11 may be used for parameters, but are preserved if they aren't,
531 g12 is always preserved, but otherwise unused,
532 g13 is the struct return ptr if used, or temp, but may be trashed,
533 g14 is the leaf return ptr or the arg block ptr otherwise zero,
534 must be reset to zero before returning if it was used,
535 g15 is the frame pointer,
536 r0 is the previous FP,
537 r1 is the stack pointer,
538 r2 is the return instruction pointer,
539 r3-r15 are always available,
540 r3 is clobbered by calls in functions that use the arg pointer
541 r4-r11 may be clobbered by the mcount call when profiling
542 r4-r15 if otherwise unused may be used for preserving global registers
543 fp0..fp3 are never available. */
544 #define CALL_USED_REGISTERS \
545 {1, 1, 1, 1, 1, 1, 1, 1, \
546 0, 0, 0, 0, 0, 1, 1, 1, \
547 1, 1, 1, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 0, 0, \
551 /* If no fp unit, make all of the fp registers fixed so that they can't
553 #define CONDITIONAL_REGISTER_USAGE \
554 if (! TARGET_NUMERICS) { \
555 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
558 /* Return number of consecutive hard regs needed starting at reg REGNO
559 to hold something of mode MODE.
560 This is ordinarily the length in words of a value of mode MODE
561 but can be less for certain modes in special long registers.
563 On 80960, ordinary registers hold 32 bits worth, but can be ganged
564 together to hold double or extended precision floating point numbers,
565 and the floating point registers hold any size floating point number */
566 #define HARD_REGNO_NREGS(REGNO, MODE) \
568 ? (((MODE) == VOIDmode) \
569 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
570 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
572 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
573 On 80960, the cpu registers can hold any mode but the float registers
574 can only hold SFmode, DFmode, or XFmode. */
575 extern int hard_regno_mode_ok ();
576 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
578 /* Value is 1 if it is a good idea to tie two pseudo registers
579 when one has mode MODE1 and one has mode MODE2.
580 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
581 for any hard reg, then this must be 0 for correct output. */
583 #define MODES_TIEABLE_P(MODE1, MODE2) \
584 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
586 /* Specify the registers used for certain standard purposes.
587 The values of these macros are register numbers. */
589 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
590 /* #define PC_REGNUM */
592 /* Register to use for pushing function arguments. */
593 #define STACK_POINTER_REGNUM 17
595 /* Actual top-of-stack address is same as
596 the contents of the stack pointer register. */
597 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
599 /* Base register for access to local variables of the function. */
600 #define FRAME_POINTER_REGNUM 15
602 /* Value should be nonzero if functions must have frame pointers.
603 Zero means the frame pointer need not be set up (and parms
604 may be accessed via the stack pointer) in functions that seem suitable.
605 This is computed in `reload', in reload1.c. */
606 /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
607 fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
608 caused this to fail. */
609 #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
611 /* C statement to store the difference between the frame pointer
612 and the stack pointer values immediately after the function prologue.
614 Since the stack grows upward on the i960, this must be a negative number.
615 This includes the 64 byte hardware register save area and the size of
618 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
619 do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
621 /* Base register for access to arguments of the function. */
622 #define ARG_POINTER_REGNUM 14
624 /* Register in which static-chain is passed to a function.
625 On i960, we use r3. */
626 #define STATIC_CHAIN_REGNUM 19
628 /* Functions which return large structures get the address
629 to place the wanted value at in g13. */
631 #define STRUCT_VALUE_REGNUM 13
633 /* The order in which to allocate registers. */
635 #define REG_ALLOC_ORDER \
636 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
637 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
638 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
639 11, 12, /* g11, g12 */ \
640 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
641 /* We can't actually allocate these. */ \
642 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
644 /* Define the classes of registers for register constraints in the
645 machine description. Also define ranges of constants.
647 One of the classes must always be named ALL_REGS and include all hard regs.
648 If there is more than one class, another class must be named NO_REGS
649 and contain no registers.
651 The name GENERAL_REGS must be the name of a class (or an alias for
652 another name such as ALL_REGS). This is the class of registers
653 that is allowed by "g" or "r" in a register constraint.
654 Also, registers outside this class are allocated only when
655 instructions express preferences for them.
657 The classes must be numbered in nondecreasing order; that is,
658 a larger-numbered class must never be contained completely
659 in a smaller-numbered class.
661 For any two classes, it is very desirable that there be another
662 class that represents their union. */
664 /* The 80960 has four kinds of registers, global, local, floating point,
665 and condition code. The cc register is never allocated, so no class
666 needs to be defined for it. */
668 enum reg_class
{ NO_REGS
, GLOBAL_REGS
, LOCAL_REGS
, LOCAL_OR_GLOBAL_REGS
,
669 FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
671 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
673 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
675 #define N_REG_CLASSES (int) LIM_REG_CLASSES
677 /* Give names of register classes as strings for dump file. */
679 #define REG_CLASS_NAMES \
680 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
681 "FP_REGS", "ALL_REGS" }
683 /* Define which registers fit in which classes.
684 This is an initializer for a vector of HARD_REG_SET
685 of length N_REG_CLASSES. */
687 #define REG_CLASS_CONTENTS \
688 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
690 /* The same information, inverted:
691 Return the class number of the smallest class containing
692 reg number REGNO. This could be a conditional expression
693 or could index an array. */
695 #define REGNO_REG_CLASS(REGNO) \
696 ((REGNO) < 16 ? GLOBAL_REGS \
697 : (REGNO) < 32 ? LOCAL_REGS \
698 : (REGNO) < 36 ? FP_REGS \
701 /* The class value for index registers, and the one for base regs.
702 There is currently no difference between base and index registers on the
703 i960, but this distinction may one day be useful. */
704 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
705 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
707 /* Get reg_class from a letter such as appears in the machine description.
708 'f' is a floating point register (fp0..fp3)
709 'l' is a local register (r0-r15)
710 'b' is a global register (g0-g15)
711 'd' is any local or global register
712 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
713 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
714 the same thing, since 'r' may include the fp registers. */
715 #define REG_CLASS_FROM_LETTER(C) \
716 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
717 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
719 /* The letters I, J, K, L and M in a register constraint string
720 can be used to stand for particular ranges of immediate operands.
721 This macro defines what the ranges are.
722 C is the letter, and VALUE is a constant value.
723 Return 1 if VALUE is in the range specified by C.
726 'I' is used for literal values 0..31
730 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
731 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
732 : (C) == 'J' ? ((VALUE) == 0) \
733 : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \
734 : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \
737 /* Similar, but for floating constants, and defining letters G and H.
738 Here VALUE is the CONST_DOUBLE rtx itself.
739 For the 80960, G is 0.0 and H is 1.0. */
741 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
742 ((TARGET_NUMERICS) && \
743 (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
744 || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
746 /* Given an rtx X being reloaded into a reg required to be
747 in class CLASS, return the class of reg to actually use.
748 In general this is just CLASS; but on some machines
749 in some cases it is preferable to use a more restrictive class. */
751 /* On 960, can't load constant into floating-point reg except
754 Any hard reg is ok as a src operand of a reload insn. */
756 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
757 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
759 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
760 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
761 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
763 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
765 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
766 secondary_reload_class (CLASS, MODE, IN)
768 /* Return the maximum number of consecutive registers
769 needed to represent mode MODE in a register of class CLASS. */
770 /* On 80960, this is the size of MODE in words,
771 except in the FP regs, where a single reg is always enough. */
772 #define CLASS_MAX_NREGS(CLASS, MODE) \
773 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
775 /* Stack layout; function entry, exit and calling. */
777 /* Define this if pushing a word on the stack
778 makes the stack pointer a smaller address. */
779 /* #define STACK_GROWS_DOWNWARD */
781 /* Define this if the nominal address of the stack frame
782 is at the high-address end of the local variables;
783 that is, each additional local variable allocated
784 goes at a more negative offset in the frame. */
785 /* #define FRAME_GROWS_DOWNWARD */
787 /* Offset within stack frame to start allocating local variables at.
788 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
789 first local allocated. Otherwise, it is the offset to the BEGINNING
790 of the first local allocated.
792 The i960 has a 64 byte register save area, plus possibly some extra
793 bytes allocated for varargs functions. */
794 #define STARTING_FRAME_OFFSET 64
796 /* If we generate an insn to push BYTES bytes,
797 this says how many the stack pointer really advances by.
798 On 80960, don't define this because there are no push insns. */
799 /* #define PUSH_ROUNDING(BYTES) BYTES */
801 /* Offset of first parameter from the argument pointer register value. */
802 #define FIRST_PARM_OFFSET(FNDECL) 0
804 /* When a parameter is passed in a register, no stack space is
805 allocated for it. However, when args are passed in the
806 stack, space is allocated for every register parameter. */
807 #define MAYBE_REG_PARM_STACK_SPACE 48
808 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
809 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
810 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
811 #define OUTGOING_REG_PARM_STACK_SPACE
813 /* Keep the stack pointer constant throughout the function. */
814 #define ACCUMULATE_OUTGOING_ARGS
816 /* Value is 1 if returning from a function call automatically
817 pops the arguments described by the number-of-args field in the call.
818 FUNDECL is the declaration node of the function (as a tree),
819 FUNTYPE is the data type of the function (as a tree),
820 or for a library call it is an identifier node for the subroutine name. */
822 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
824 /* Define how to find the value returned by a library function
825 assuming the value has mode MODE. */
827 #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
829 /* 1 if N is a possible register number for a function value
830 as seen by the caller.
831 On 80960, returns are in g0..g3 */
833 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
835 /* 1 if N is a possible register number for function argument passing.
836 On 80960, parameters are passed in g0..g11 */
838 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
840 /* Perform any needed actions needed for a function that is receiving a
841 variable number of arguments.
845 MODE and TYPE are the mode and type of the current parameter.
847 PRETEND_SIZE is a variable that should be set to the amount of stack
848 that must be pushed by the prolog to pretend that our caller pushed
851 Normally, this macro will push all remaining incoming registers on the
852 stack and set PRETEND_SIZE to the length of the registers pushed. */
854 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
855 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
857 /* Define a data type for recording info about an argument list
858 during the scan of that argument list. This data type should
859 hold all necessary information about the function itself
860 and about the args processed so far, enough to enable macros
861 such as FUNCTION_ARG to determine where the next arg should go.
863 On 80960, this is two integers, which count the number of register
864 parameters and the number of stack parameters seen so far. */
866 struct cum_args
{ int ca_nregparms
; int ca_nstackparms
; };
868 #define CUMULATIVE_ARGS struct cum_args
870 /* Define the number of registers that can hold parameters.
871 This macro is used only in macro definitions below and/or i960.c. */
872 #define NPARM_REGS 12
874 /* Define how to round to the next parameter boundary.
875 This macro is used only in macro definitions below and/or i960.c. */
876 #define ROUND_PARM(X, MULTIPLE_OF) \
877 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
879 /* Initialize a variable CUM of type CUMULATIVE_ARGS
880 for a call to a function whose data type is FNTYPE.
881 For a library call, FNTYPE is 0.
883 On 80960, the offset always starts at 0; the first parm reg is g0. */
885 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
886 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
888 /* Update the data in CUM to advance over an argument
889 of mode MODE and data type TYPE.
890 CUM should be advanced to align with the data type accessed and
891 also the size of that data type in # of regs.
892 (TYPE is null for libcalls where that information may not be available.) */
894 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
895 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
897 /* Indicate the alignment boundary for an argument of the specified mode and
899 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
901 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
903 : TYPE_ALIGN (TYPE)) \
904 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
906 : GET_MODE_ALIGNMENT (MODE)))
908 /* Determine where to put an argument to a function.
909 Value is zero to push the argument on the stack,
910 or a hard register in which to store the argument.
912 MODE is the argument's machine mode.
913 TYPE is the data type of the argument (as a tree).
914 This is null for libcalls where that information may
916 CUM is a variable of type CUMULATIVE_ARGS which gives info about
917 the preceding args and about the function being called.
918 NAMED is nonzero if this argument is a named parameter
919 (otherwise it is an extra parameter matching an ellipsis). */
921 extern struct rtx_def
*i960_function_arg ();
922 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
923 i960_function_arg(&CUM, MODE, TYPE, NAMED)
925 /* Define how to find the value returned by a function.
926 VALTYPE is the data type of the value (as a tree).
927 If the precise function being called is known, FUNC is its FUNCTION_DECL;
928 otherwise, FUNC is 0. */
930 #define FUNCTION_VALUE(TYPE, FUNC) \
931 gen_rtx (REG, TYPE_MODE (TYPE), 0)
933 /* Force aggregates and objects larger than 16 bytes to be returned in memory,
934 since we only have 4 registers available for return values. */
936 #define RETURN_IN_MEMORY(TYPE) \
937 (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
939 /* Don't default to pcc-struct-return, because we have already specified
940 exactly how to return structures in the RETURN_IN_MEMORY macro. */
941 #define DEFAULT_PCC_STRUCT_RETURN 0
943 /* For an arg passed partly in registers and partly in memory,
944 this is the number of registers used.
945 This never happens on 80960. */
947 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
949 /* Output the label for a function definition.
950 This handles leaf functions and a few other things for the i960. */
952 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
953 i960_function_name_declare (FILE, NAME, DECL)
955 /* This macro generates the assembly code for function entry.
956 FILE is a stdio stream to output the code to.
957 SIZE is an int: how many units of temporary storage to allocate.
958 Refer to the array `regs_ever_live' to determine which registers
959 to save; `regs_ever_live[I]' is nonzero if register number I
960 is ever used in the function. This macro is responsible for
961 knowing which registers should not be saved even if used. */
963 #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
965 /* Output assembler code to FILE to increment profiler label # LABELNO
966 for profiling a function entry. */
968 #define FUNCTION_PROFILER(FILE, LABELNO) \
969 output_function_profiler ((FILE), (LABELNO));
971 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
972 the stack pointer does not matter. The value is tested only in
973 functions that have frame pointers.
974 No definition is equivalent to always zero. */
976 #define EXIT_IGNORE_STACK 1
978 /* This macro generates the assembly code for function exit,
979 on machines that need it. If FUNCTION_EPILOGUE is not defined
980 then individual return instructions are generated for each
981 return statement. Args are same as for FUNCTION_PROLOGUE.
983 The function epilogue should not depend on the current stack pointer!
984 It should use the frame pointer only. This is mandatory because
985 of alloca; we also take advantage of it to omit stack adjustments
988 #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
990 /* Addressing modes, and classification of registers for them. */
992 /* #define HAVE_POST_INCREMENT 0 */
993 /* #define HAVE_POST_DECREMENT 0 */
995 /* #define HAVE_PRE_DECREMENT 0 */
996 /* #define HAVE_PRE_INCREMENT 0 */
998 /* Macros to check register numbers against specific register classes. */
1000 /* These assume that REGNO is a hard or pseudo reg number.
1001 They give nonzero only if REGNO is a hard reg of the suitable class
1002 or a pseudo reg currently allocated to a suitable hard reg.
1003 Since they use reg_renumber, they are safe only once reg_renumber
1004 has been allocated, which happens in local-alloc.c. */
1006 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1007 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
1008 #define REGNO_OK_FOR_BASE_P(REGNO) \
1009 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
1010 #define REGNO_OK_FOR_FP_P(REGNO) \
1011 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
1013 /* Now macros that check whether X is a register and also,
1014 strictly, whether it is in a specified class.
1016 These macros are specific to the 960, and may be used only
1017 in code for printing assembler insns and in conditions for
1018 define_optimization. */
1020 /* 1 if X is an fp register. */
1022 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
1024 /* Maximum number of registers that can appear in a valid memory address. */
1025 #define MAX_REGS_PER_ADDRESS 2
1027 #define CONSTANT_ADDRESS_P(X) \
1028 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1029 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1030 || GET_CODE (X) == HIGH)
1032 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
1033 is a legitimate general operand.
1034 It is given that X satisfies CONSTANT_P.
1036 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
1038 ??? This probably should be defined to 1. */
1040 #define LEGITIMATE_CONSTANT_P(X) \
1041 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
1043 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1044 and check its validity for a certain class.
1045 We have two alternate definitions for each of them.
1046 The usual definition accepts all pseudo regs; the other rejects
1047 them unless they have been allocated suitable hard regs.
1048 The symbol REG_OK_STRICT causes the latter definition to be used.
1050 Most source files want to accept pseudo regs in the hope that
1051 they will get allocated to the class that the insn wants them to be in.
1052 Source files for reload pass need to be strict.
1053 After reload, it makes no difference, since pseudo regs have
1054 been eliminated by then. */
1056 #ifndef REG_OK_STRICT
1058 /* Nonzero if X is a hard reg that can be used as an index
1059 or if it is a pseudo reg. */
1060 #define REG_OK_FOR_INDEX_P(X) \
1061 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1062 /* Nonzero if X is a hard reg that can be used as a base reg
1063 or if it is a pseudo reg. */
1064 #define REG_OK_FOR_BASE_P(X) \
1065 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1067 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1068 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1072 /* Nonzero if X is a hard reg that can be used as an index. */
1073 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1074 /* Nonzero if X is a hard reg that can be used as a base reg. */
1075 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1079 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1080 that is a valid memory address for an instruction.
1081 The MODE argument is the machine mode for the MEM expression
1082 that wants to use this address.
1084 On 80960, legitimate addresses are:
1086 disp (12 or 32 bit) ld foo,r0
1087 base + index ld (g0)[g1*1],r0
1088 base + displ ld 0xf00(g0),r0
1089 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1090 index*scale + base ld (g0)[g1*4],r0
1091 index*scale + displ ld 0xf00[g1*4],r0
1092 index*scale ld [g1*4],r0
1093 index + base + displ ld 0xf00(g0)[g1*1],r0
1095 In each case, scale can be 1, 2, 4, 8, or 16. */
1097 /* Returns 1 if the scale factor of an index term is valid. */
1098 #define SCALE_TERM_P(X) \
1099 (GET_CODE (X) == CONST_INT \
1100 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1101 || INTVAL(X) == 8 || INTVAL (X) == 16))
1104 #ifdef REG_OK_STRICT
1105 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1106 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1108 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1109 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1112 /* Try machine-dependent ways of modifying an illegitimate address
1113 to be legitimate. If we find one, return the new, valid address.
1114 This macro is used in only one place: `memory_address' in explow.c.
1116 OLDX is the address as it was before break_out_memory_refs was called.
1117 In some cases it is useful to look at this to decide what needs to be done.
1119 MODE and WIN are passed so that this macro can use
1120 GO_IF_LEGITIMATE_ADDRESS.
1122 It is always safe for this macro to do nothing. It exists to recognize
1123 opportunities to optimize the output. */
1125 /* On 80960, convert non-canonical addresses to canonical form. */
1127 extern struct rtx_def
*legitimize_address ();
1128 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1129 { rtx orig_x = (X); \
1130 (X) = legitimize_address (X, OLDX, MODE); \
1131 if ((X) != orig_x && memory_address_p (MODE, X)) \
1134 /* Go to LABEL if ADDR (a legitimate address expression)
1135 has an effect that depends on the machine mode it is used for.
1136 On the 960 this is never true. */
1138 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1140 /* Specify the machine mode that this machine uses
1141 for the index in the tablejump instruction. */
1142 #define CASE_VECTOR_MODE SImode
1144 /* Define as C expression which evaluates to nonzero if the tablejump
1145 instruction expects the table to contain offsets from the address of the
1147 Do not define this if the table should contain absolute addresses. */
1148 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1150 /* Specify the tree operation to be used to convert reals to integers. */
1151 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1153 /* This is the kind of divide that is easiest to do in the general case. */
1154 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1156 /* Define this as 1 if `char' should by default be signed; else as 0. */
1157 #define DEFAULT_SIGNED_CHAR 0
1159 /* Allow and ignore #sccs directives. */
1160 #define SCCS_DIRECTIVE
1162 /* Max number of bytes we can move from memory to memory
1163 in one reasonably fast instruction. */
1166 /* Define if operations between registers always perform the operation
1167 on the full register even if a narrower mode is specified. */
1168 #define WORD_REGISTER_OPERATIONS
1170 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1171 will either zero-extend or sign-extend. The value of this macro should
1172 be the code that says which one of the two operations is implicitly
1173 done, NIL if none. */
1174 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1176 /* Nonzero if access to memory by bytes is no faster than for words.
1177 Value changed to 1 after reports of poor bitfield code with g++.
1178 Indications are that code is usually as good, sometimes better. */
1180 #define SLOW_BYTE_ACCESS 1
1182 /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
1183 change in SLOW_BYTE_ACCESS would have changed it to 4. */
1185 #define BOOL_TYPE_SIZE CHAR_TYPE_SIZE
1187 /* We assume that the store-condition-codes instructions store 0 for false
1188 and some other value for true. This is the value stored for true. */
1190 #define STORE_FLAG_VALUE 1
1192 /* Define this to be nonzero if shift instructions ignore all but the low-order
1194 #define SHIFT_COUNT_TRUNCATED 0
1196 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1197 is done just by pretending it is already truncated. */
1198 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1200 /* Specify the machine mode that pointers have.
1201 After generation of rtl, the compiler makes no further distinction
1202 between pointers and any other objects of this machine mode. */
1203 #define Pmode SImode
1205 /* Specify the widest mode that BLKmode objects can be promoted to */
1206 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1208 /* These global variables are used to pass information between
1209 cc setter and cc user at insn emit time. */
1211 extern struct rtx_def
*i960_compare_op0
, *i960_compare_op1
;
1213 /* Define the function that build the compare insn for scc and bcc. */
1215 extern struct rtx_def
*gen_compare_reg ();
1217 /* Add any extra modes needed to represent the condition code.
1219 Also, signed and unsigned comparisons are distinguished, as
1220 are operations which are compatible with chkbit insns. */
1221 #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1223 /* Define the names for the modes specified above. */
1224 #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1226 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1227 return the mode to be used for the comparison. For floating-point, CCFPmode
1228 should be used. CC_NOOVmode should be used when the first operand is a
1229 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1231 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1233 /* A function address in a call instruction is a byte address
1234 (for indexing purposes) so give the MEM rtx a byte's mode. */
1235 #define FUNCTION_MODE SImode
1237 /* Define this if addresses of constant functions
1238 shouldn't be put through pseudo regs where they can be cse'd.
1239 Desirable on machines where ordinary constants are expensive
1240 but a CALL with constant address is cheap. */
1241 #define NO_FUNCTION_CSE
1243 /* Use memcpy, etc. instead of bcopy. */
1246 #define TARGET_MEM_FUNCTIONS 1
1249 /* Compute the cost of computing a constant rtl expression RTX
1250 whose rtx-code is CODE. The body of this macro is a portion
1251 of a switch statement. If the code is computed here,
1252 return it with a return statement. Otherwise, break from the switch. */
1254 /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1255 that can be non-ldconst operands in rare cases are cost 1. Other constants
1256 have higher costs. */
1258 /* Must check for OUTER_CODE of SET for power2_operand, because
1259 reload_cse_move2add calls us with OUTER_CODE of PLUS to decide when
1260 to replace set with add. */
1262 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1264 if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1265 || (OUTER_CODE == SET && power2_operand (RTX, VOIDmode))) \
1267 else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1272 return (TARGET_C_SERIES ? 6 : 8); \
1273 case CONST_DOUBLE: \
1274 if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1275 || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1279 /* The i960 offers addressing modes which are "as cheap as a register".
1280 See i960.c (or gcc.texinfo) for details. */
1282 #define ADDRESS_COST(RTX) \
1283 (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1285 /* Control the assembler format that we output. */
1287 /* Output at beginning of assembler file. */
1289 #define ASM_FILE_START(file)
1291 /* Output to assembler file text saying following lines
1292 may contain character constants, extra white space, comments, etc. */
1294 #define ASM_APP_ON ""
1296 /* Output to assembler file text saying following lines
1297 no longer contain unusual constructs. */
1299 #define ASM_APP_OFF ""
1301 /* Output before read-only data. */
1303 #define TEXT_SECTION_ASM_OP ".text"
1305 /* Output before writable data. */
1307 #define DATA_SECTION_ASM_OP ".data"
1309 /* How to refer to registers in assembler output.
1310 This sequence is indexed by compiler's hard-register-number (see above). */
1312 #define REGISTER_NAMES { \
1313 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1314 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1315 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1316 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1317 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1319 /* How to renumber registers for dbx and gdb.
1320 In the 960 encoding, g0..g15 are registers 16..31. */
1322 #define DBX_REGISTER_NUMBER(REGNO) \
1323 (((REGNO) < 16) ? (REGNO) + 16 \
1324 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1326 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1327 #define DBX_CONTIN_LENGTH 1500
1329 /* This is how to output a note to DBX telling it the line number
1330 to which the following sequence of instructions corresponds. */
1332 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1333 { if (write_symbols == SDB_DEBUG) { \
1334 fprintf ((FILE), "\t.ln %d\n", \
1335 (sdb_begin_function_line \
1336 ? (LINE) - sdb_begin_function_line : 1)); \
1337 } else if (write_symbols == DBX_DEBUG) { \
1338 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1341 /* This is how to output the definition of a user-level label named NAME,
1342 such as the label on a static function or variable NAME. */
1344 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1345 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1347 /* This is how to output a command to make the user-level label named NAME
1348 defined for reference from other files. */
1350 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1351 { fputs ("\t.globl ", FILE); \
1352 assemble_name (FILE, NAME); \
1353 fputs ("\n", FILE); }
1355 /* The prefix to add to user-visible assembler symbols. */
1357 #define USER_LABEL_PREFIX "_"
1359 /* This is how to output an internal numbered label where
1360 PREFIX is the class of label and NUM is the number within the class. */
1362 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1363 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1365 /* This is how to store into the string LABEL
1366 the symbol_ref name of an internal numbered label where
1367 PREFIX is the class of label and NUM is the number within the class.
1368 This is suitable for output with `assemble_name'. */
1370 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1371 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1373 /* This is how to output an assembler line defining a `long double'
1376 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
1378 /* This is how to output an assembler line defining a `double' constant. */
1380 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1382 /* This is how to output an assembler line defining a `float' constant. */
1384 #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1386 /* This is how to output an assembler line defining an `int' constant. */
1388 #define ASM_OUTPUT_INT(FILE,VALUE) \
1389 ( fprintf (FILE, "\t.word "), \
1390 output_addr_const (FILE, (VALUE)), \
1391 fprintf (FILE, "\n"))
1393 /* Likewise for `char' and `short' constants. */
1395 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1396 ( fprintf (FILE, "\t.short "), \
1397 output_addr_const (FILE, (VALUE)), \
1398 fprintf (FILE, "\n"))
1400 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1401 ( fprintf (FILE, "\t.byte "), \
1402 output_addr_const (FILE, (VALUE)), \
1403 fprintf (FILE, "\n"))
1405 /* This is how to output an assembler line for a numeric constant byte. */
1407 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1408 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1410 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1411 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1413 /* This is how to output an insn to pop a register from the stack.
1414 It need not be very fast code. */
1416 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1417 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1419 /* This is how to output an element of a case-vector that is absolute. */
1421 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1422 fprintf (FILE, "\t.word L%d\n", VALUE)
1424 /* This is how to output an element of a case-vector that is relative. */
1426 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1427 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1429 /* This is how to output an assembler line that says to advance the
1430 location counter to a multiple of 2**LOG bytes. */
1432 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1433 fprintf (FILE, "\t.align %d\n", (LOG))
1435 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1436 fprintf (FILE, "\t.space %d\n", (SIZE))
1438 /* This says how to output an assembler line
1439 to define a global common symbol. */
1441 /* For common objects, output unpadded size... gld960 & lnk960 both
1442 have code to align each common object at link time. Also, if size
1443 is 0, treat this as a declaration, not a definition - i.e.,
1444 do nothing at all. */
1446 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1447 { if ((SIZE) != 0) \
1449 fputs (".globl ", (FILE)), \
1450 assemble_name ((FILE), (NAME)), \
1451 fputs ("\n.comm ", (FILE)), \
1452 assemble_name ((FILE), (NAME)), \
1453 fprintf ((FILE), ",%d\n", (SIZE)); \
1457 /* This says how to output an assembler line to define a local common symbol.
1458 Output unpadded size, with request to linker to align as requested.
1459 0 size should not be possible here. */
1461 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1462 ( fputs (".bss\t", (FILE)), \
1463 assemble_name ((FILE), (NAME)), \
1464 fprintf ((FILE), ",%d,%d\n", (SIZE), \
1465 (floor_log2 ((ALIGN) / BITS_PER_UNIT))))
1467 /* A C statement (sans semicolon) to output to the stdio stream
1468 FILE the assembler definition of uninitialized global DECL named
1469 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1470 Try to use asm_output_aligned_bss to implement this macro. */
1472 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1474 fputs (".globl ", (FILE)); \
1475 assemble_name ((FILE), (NAME)); \
1476 fputs ("\n", (FILE)); \
1477 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1480 /* Output text for an #ident directive. */
1481 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1483 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1485 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
1487 /* Store in OUTPUT a string (made with alloca) containing
1488 an assembler-name for a local static variable named NAME.
1489 LABELNO is an integer which is different for each call. */
1491 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1492 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1493 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1495 /* Define the parentheses used to group arithmetic operations
1496 in assembler code. */
1498 #define ASM_OPEN_PAREN "("
1499 #define ASM_CLOSE_PAREN ")"
1501 /* Define results of standard character escape sequences. */
1502 #define TARGET_BELL 007
1503 #define TARGET_BS 010
1504 #define TARGET_TAB 011
1505 #define TARGET_NEWLINE 012
1506 #define TARGET_VT 013
1507 #define TARGET_FF 014
1508 #define TARGET_CR 015
1510 /* Output assembler code to FILE to initialize this source file's
1511 basic block profiling info, if that has not already been done. */
1513 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1514 { fprintf (FILE, "\tld LPBX0,g12\n"); \
1515 fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1516 fprintf (FILE, "\tlda LPBX0,g12\n"); \
1517 fprintf (FILE, "\tcall ___bb_init_func\n"); \
1518 fprintf (FILE, "LPY%d:\n",LABELNO); }
1520 /* Output assembler code to FILE to increment the entry-count for
1521 the BLOCKNO'th basic block in this source file. */
1523 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1524 { int blockn = (BLOCKNO); \
1525 fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1526 fprintf (FILE, "\taddo g12,1,g12\n"); \
1527 fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1529 /* Print operand X (an rtx) in assembler syntax to file FILE.
1530 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1531 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1533 #define PRINT_OPERAND(FILE, X, CODE) \
1534 i960_print_operand (FILE, X, CODE);
1536 /* Print a memory address as an operand to reference that memory location. */
1538 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1539 i960_print_operand_addr (FILE, ADDR)
1541 /* Output assembler code for a block containing the constant parts
1542 of a trampoline, leaving space for the variable parts. */
1544 /* On the i960, the trampoline contains three instructions:
1545 ldconst _function, r4
1546 ldconst static addr, r3
1549 #define TRAMPOLINE_TEMPLATE(FILE) \
1551 ASM_OUTPUT_INT (FILE, GEN_INT (0x8C203000)); \
1552 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1553 ASM_OUTPUT_INT (FILE, GEN_INT (0x8C183000)); \
1554 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1555 ASM_OUTPUT_INT (FILE, GEN_INT (0x84212000)); \
1558 /* Length in units of the trampoline for entering a nested function. */
1560 #define TRAMPOLINE_SIZE 20
1562 /* Emit RTL insns to initialize the variable parts of a trampoline.
1563 FNADDR is an RTX for the address of the function's pure code.
1564 CXT is an RTX for the static chain value for the function. */
1566 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1568 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1570 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1574 /* Generate RTL to flush the register windows so as to make arbitrary frames
1576 #define SETUP_FRAME_ADDRESSES() \
1577 emit_insn (gen_flush_register_windows ())
1579 #define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx
1582 /* Promote char and short arguments to ints, when want compatibility with
1583 the iC960 compilers. */
1585 /* ??? In order for this to work, all users would need to be changed
1586 to test the value of the macro at run time. */
1587 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1588 /* ??? This does not exist. */
1589 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1592 /* Instruction type definitions. Used to alternate instructions types for
1593 better performance on the C series chips. */
1595 enum insn_types
{ I_TYPE_REG
, I_TYPE_MEM
, I_TYPE_CTRL
};
1597 /* Holds the insn type of the last insn output to the assembly file. */
1599 extern enum insn_types i960_last_insn_type
;
1601 /* Parse opcodes, and set the insn last insn type based on them. */
1603 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1605 /* Table listing what rtl codes each predicate in i960.c will accept. */
1607 #define PREDICATE_CODES \
1608 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1609 LABEL_REF, SUBREG, REG, MEM}}, \
1610 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1611 {"logic_operand", {SUBREG, REG, CONST_INT}}, \
1612 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1613 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1614 {"literal", {CONST_INT}}, \
1615 {"fp_literal_one", {CONST_DOUBLE}}, \
1616 {"fp_literal_double", {CONST_DOUBLE}}, \
1617 {"fp_literal", {CONST_DOUBLE}}, \
1618 {"signed_literal", {CONST_INT}}, \
1619 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1620 {"eq_or_neq", {EQ, NE}}, \
1621 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1622 CONST_DOUBLE, CONST}}, \
1623 {"power2_operand", {CONST_INT}}, \
1624 {"cmplpower2_operand", {CONST_INT}},
1626 /* Define functions in i960.c and used in insn-output.c. */
1628 extern char *i960_output_ldconst ();
1629 extern char *i960_output_call_insn ();
1630 extern char *i960_output_ret_insn ();
1631 extern char *i960_output_move_double ();
1632 extern char *i960_output_move_double_zero ();
1633 extern char *i960_output_move_quad ();
1634 extern char *i960_output_move_quad_zero ();
1636 /* Defined in reload.c, and used in insn-recog.c. */
1638 extern int rtx_equal_function_value_matters
;
1640 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1641 Used for C++ multiple inheritance. */
1642 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1645 if (d < 0 && d > -32) \
1646 fprintf (FILE, "\tsubo %d,g0,g0\n", -d); \
1647 else if (d > 0 && d < 32) \
1648 fprintf (FILE, "\taddo %d,g0,g0\n", d); \
1651 fprintf (FILE, "\tldconst %d,r5\n", d); \
1652 fprintf (FILE, "\taddo r5,g0,g0\n"); \
1654 fprintf (FILE, "\tbx "); \
1655 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1656 fprintf (FILE, "\n"); \