1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files may include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Names to predefine in the preprocessor for this target machine. */
28 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
30 /* Name to predefine in the preprocessor for processor variations. */
31 #define CPP_SPEC "%{mic*:-D__i960\
32 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
33 %{msa:-D__i960SA}%{msb:-D__i960SB}\
35 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
37 %{mka:-D__i960KA__ -D__i960_KA__}\
38 %{mkb:-D__i960KB__ -D__i960_KB__}\
39 %{msa:-D__i960SA__ -D__i960_SA__}\
40 %{msb:-D__i960SB__ -D__i960_SB__}\
41 %{mmc:-D__i960MC__ -D__i960_MC__}\
42 %{mca:-D__i960CA__ -D__i960_CA__}\
43 %{mcc:-D__i960CC__ -D__i960_CC__}\
44 %{mcf:-D__i960CF__ -D__i960_CF__}\
45 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
46 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
48 /* -mic* options make characters signed by default. */
49 /* Use #if rather than ?: because MIPS C compiler rejects ?: in
51 #if DEFAULT_SIGNED_CHAR
52 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
54 #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
57 /* Specs for the compiler, to handle processor variations.
58 If the user gives an explicit -gstabs or -gcoff option, then do not
59 try to add an implicit one, as this will fail. */
61 "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\
62 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
63 %{mcoff:%{g*:-gcoff}}\
64 %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
66 /* Specs for the assembler, to handle processor variations.
67 For compatibility with Intel's gnu960 tool chain, pass -A options to
70 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
71 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
72 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
73 %{mlink-relax:-linkrelax}"
75 /* Specs for the linker, to handle processor variations.
76 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
79 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
80 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
81 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
82 %{mbout:-Fbout}%{mcoff:-Fcoff}\
83 %{mlink-relax:-relax}"
85 /* Specs for the libraries to link with, to handle processor variations.
86 Compatible with Intel's gnu960 tool chain. */
87 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
88 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
90 /* Show we can debug even without a frame pointer. */
91 #define CAN_DEBUG_WITHOUT_FP
93 /* Do leaf procedure and tail call optimizations for -O2 and higher. */
94 #define OPTIMIZATION_OPTIONS(LEVEL) \
98 target_flags |= TARGET_FLAG_LEAFPROC; \
99 target_flags |= TARGET_FLAG_TAILCALL; \
103 /* Print subsidiary information on the compiler version in use. */
104 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
106 /* Generate DBX debugging information. */
107 #define DBX_DEBUGGING_INFO
109 /* Generate SDB style debugging information. */
110 #define SDB_DEBUGGING_INFO
112 /* Generate DBX_DEBUGGING_INFO by default. */
113 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
115 /* Redefine this to print in hex and adjust values like GNU960. The extra
116 bit is used to handle the type long double. Gcc does not support long
117 double in sdb output, but we do support the non-standard format. */
118 #define PUT_SDB_TYPE(A) \
119 fprintf (asm_out_file, "\t.type\t0x%x;", (A & 0xf) + 2 * (A & ~0xf))
121 /* Handle pragmas for compatibility with Intel's compilers. */
122 #define HANDLE_PRAGMA(FILE, CH) process_pragma (FILE, CH)
124 /* Run-time compilation parameters selecting different hardware subsets. */
126 /* 960 architecture with floating-point. */
127 #define TARGET_FLAG_NUMERICS 0x01
128 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
130 /* 960 architecture with memory management. */
131 /* ??? Not used currently. */
132 #define TARGET_FLAG_PROTECTED 0x02
133 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
135 /* The following three are mainly used to provide a little sanity checking
136 against the -mARCH flags given. */
138 /* Nonzero if we should generate code for the KA and similar processors.
139 No FPU, no microcode instructions. */
140 #define TARGET_FLAG_K_SERIES 0x04
141 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
143 /* Nonzero if we should generate code for the MC processor.
144 Not really different from KB for our purposes. */
145 #define TARGET_FLAG_MC 0x08
146 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
148 /* Nonzero if we should generate code for the CA processor.
149 Enables different optimization strategies. */
150 #define TARGET_FLAG_C_SERIES 0x10
151 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
153 /* Nonzero if we should generate leaf-procedures when we find them.
154 You may not want to do this because leaf-proc entries are
155 slower when not entered via BAL - this would be true when
156 a linker not supporting the optimization is used. */
157 #define TARGET_FLAG_LEAFPROC 0x20
158 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
160 /* Nonzero if we should perform tail-call optimizations when we find them.
161 You may not want to do this because the detection of cases where
162 this is not valid is not totally complete. */
163 #define TARGET_FLAG_TAILCALL 0x40
164 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
166 /* Nonzero if use of a complex addressing mode is a win on this implementation.
167 Complex addressing modes are probably not worthwhile on the K-series,
168 but they definitely are on the C-series. */
169 #define TARGET_FLAG_COMPLEX_ADDR 0x80
170 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
172 /* Align code to 8 byte boundaries for faster fetching. */
173 #define TARGET_FLAG_CODE_ALIGN 0x100
174 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
176 /* Append branch prediction suffixes to branch opcodes. */
177 /* ??? Not used currently. */
178 #define TARGET_FLAG_BRANCH_PREDICT 0x200
179 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
181 /* Forces prototype and return promotions. */
182 /* ??? This does not work. */
183 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
184 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
186 /* For compatibility with iC960 v3.0. */
187 #define TARGET_FLAG_IC_COMPAT3_0 0x800
188 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
190 /* For compatibility with iC960 v2.0. */
191 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
192 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
194 /* If no unaligned accesses are to be permitted. */
195 #define TARGET_FLAG_STRICT_ALIGN 0x2000
196 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
198 /* For compatibility with iC960 assembler. */
199 #define TARGET_FLAG_ASM_COMPAT 0x4000
200 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
202 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
203 alignment rules. Also, turns on STRICT_ALIGNMENT. */
204 #define TARGET_FLAG_OLD_ALIGN 0x8000
205 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
207 extern int target_flags
;
209 /* Macro to define tables used to set the flags.
210 This is a list in braces of pairs in braces,
211 each pair being { "NAME", VALUE }
212 where VALUE is the bits to set or minus the bits to clear.
213 An empty string NAME is used to identify the default VALUE. */
215 /* ??? Not all ten of these architecture variations actually exist, but I
216 am not sure which are real and which aren't. */
218 #define TARGET_SWITCHES \
219 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
220 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
221 TARGET_FLAG_COMPLEX_ADDR)},\
222 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
223 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
224 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
225 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
226 TARGET_FLAG_COMPLEX_ADDR)},\
227 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
228 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
229 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
230 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
231 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
232 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
233 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
234 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
235 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
236 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
237 TARGET_FLAG_CODE_ALIGN)}, */ \
238 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
239 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
240 {"numerics", (TARGET_FLAG_NUMERICS)}, \
241 {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
242 {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
243 {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
244 {"tail-call",TARGET_FLAG_TAILCALL}, \
245 {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
246 {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
247 {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
248 {"code-align",TARGET_FLAG_CODE_ALIGN}, \
249 {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
250 {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
251 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
252 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
253 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
254 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
255 {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
256 {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
257 {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
258 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
259 {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
260 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
262 {"no-link-relax", 0}, \
263 { "", TARGET_DEFAULT}}
265 /* Override conflicting target switch options.
266 Doesn't actually detect if more than one -mARCH option is given, but
267 does handle the case of two blatantly conflicting -mARCH options. */
268 #define OVERRIDE_OPTIONS \
270 if (TARGET_K_SERIES && TARGET_C_SERIES) \
272 warning ("conflicting architectures defined - using C series", 0); \
273 target_flags &= ~TARGET_FLAG_K_SERIES; \
275 if (TARGET_K_SERIES && TARGET_MC) \
277 warning ("conflicting architectures defined - using K series", 0); \
278 target_flags &= ~TARGET_FLAG_MC; \
280 if (TARGET_C_SERIES && TARGET_MC) \
282 warning ("conflicting architectures defined - using C series", 0);\
283 target_flags &= ~TARGET_FLAG_MC; \
285 if (TARGET_IC_COMPAT3_0) \
287 flag_short_enums = 1; \
288 flag_signed_char = 1; \
289 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
290 if (TARGET_IC_COMPAT2_0) \
292 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
293 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
296 if (TARGET_IC_COMPAT2_0) \
298 flag_signed_char = 1; \
299 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
301 i960_initialize (); \
304 /* Don't enable anything by default. The user is expected to supply a -mARCH
305 option. If none is given, then -mkb is added by CC1_SPEC. */
306 #define TARGET_DEFAULT 0
308 /* Target machine storage layout. */
310 /* Define for cross-compilation from a host with a different float format
311 or endianness, as well as to support 80 bit long doubles on the i960. */
312 #define REAL_ARITHMETIC
314 /* Define this if most significant bit is lowest numbered
315 in instructions that operate on numbered bit-fields. */
316 #define BITS_BIG_ENDIAN 0
318 /* Define this if most significant byte of a word is the lowest numbered.
319 The i960 case be either big endian or little endian. We only support
320 little endian, which is the most common. */
321 #define BYTES_BIG_ENDIAN 0
323 /* Define this if most significant word of a multiword number is lowest
325 #define WORDS_BIG_ENDIAN 0
327 /* Number of bits in an addressable storage unit. */
328 #define BITS_PER_UNIT 8
330 /* Bitfields cannot cross word boundaries. */
331 #define BITFIELD_NBYTES_LIMITED 1
333 /* Width in bits of a "word", which is the contents of a machine register.
334 Note that this is not necessarily the width of data type `int';
335 if using 16-bit ints on a 68000, this would still be 32.
336 But on a machine with 16-bit registers, this would be 16. */
337 #define BITS_PER_WORD 32
339 /* Width of a word, in units (bytes). */
340 #define UNITS_PER_WORD 4
342 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
343 #define POINTER_SIZE 32
345 /* Width in bits of a long double. Identical to double for now. */
346 #define LONG_DOUBLE_TYPE_SIZE 64
348 /* Allocation boundary (in *bits*) for storing pointers in memory. */
349 #define POINTER_BOUNDARY 32
351 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
352 #define PARM_BOUNDARY 32
354 /* Boundary (in *bits*) on which stack pointer should be aligned. */
355 #define STACK_BOUNDARY 128
357 /* Allocation boundary (in *bits*) for the code of a function. */
358 #define FUNCTION_BOUNDARY 128
360 /* Alignment of field after `int : 0' in a structure. */
361 #define EMPTY_FIELD_BOUNDARY 32
363 /* This makes zero-length anonymous fields lay the next field
364 at a word boundary. It also makes the whole struct have
365 at least word alignment if there are any bitfields at all. */
366 #define PCC_BITFIELD_TYPE_MATTERS 1
368 /* Every structure's size must be a multiple of this. */
369 #define STRUCTURE_SIZE_BOUNDARY 8
371 /* No data type wants to be aligned rounder than this.
372 Extended precision floats gets 4-word alignment. */
373 #define BIGGEST_ALIGNMENT 128
375 /* Define this if move instructions will actually fail to work
376 when given unaligned data.
377 80960 will work even with unaligned data, but it is slow. */
378 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
380 /* Specify alignment for string literals (which might be higher than the
381 base type's minimal alignment requirement. This allows strings to be
382 aligned on word boundaries, and optimizes calls to the str* and mem*
383 library functions. */
384 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
385 (TREE_CODE (EXP) == STRING_CST \
386 && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
387 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
390 /* Make XFmode floating point quantities be 128 bit aligned. */
391 #define DATA_ALIGNMENT(TYPE, ALIGN) \
392 (TREE_CODE (TYPE) == ARRAY_TYPE \
393 && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
394 && (ALIGN) < 128 ? 128 : (ALIGN))
396 /* Macros to determine size of aggregates (structures and unions
397 in C). Normally, these may be defined to simply return the maximum
398 alignment and simple rounded-up size, but on some machines (like
399 the i960), the total size of a structure is based on a non-trivial
402 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
403 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
404 ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
405 : ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
406 ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
407 : MAX ((COMPUTED), (SPECIFIED))))
409 #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
410 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
411 ? build_int_2 (128, 0) : (COMPUTED))
413 /* Standard register usage. */
415 /* Number of actual hardware registers.
416 The hardware registers are assigned numbers for the compiler
417 from 0 to just below FIRST_PSEUDO_REGISTER.
418 All registers that the compiler knows about must be given numbers,
419 even those that are not normally considered general registers.
421 Registers 0-15 are the global registers (g0-g15).
422 Registers 16-31 are the local registers (r0-r15).
423 Register 32-35 are the fp registers (fp0-fp3).
424 Register 36 is the condition code register.
425 Register 37 is unused. */
427 #define FIRST_PSEUDO_REGISTER 38
429 /* 1 for registers that have pervasive standard uses and are not available
430 for the register allocator. On 80960, this includes the frame pointer
431 (g15), the previous FP (r0), the stack pointer (r1), the return
432 instruction pointer (r2), and the argument pointer (g14). */
433 #define FIXED_REGISTERS \
434 {0, 0, 0, 0, 0, 0, 0, 0, \
435 0, 0, 0, 0, 0, 0, 1, 1, \
436 1, 1, 1, 0, 0, 0, 0, 0, \
437 0, 0, 0, 0, 0, 0, 0, 0, \
440 /* 1 for registers not available across function calls.
441 These must include the FIXED_REGISTERS and also any
442 registers that can be used without being saved.
443 The latter must include the registers where values are returned
444 and the register where structure-value addresses are passed.
445 Aside from that, you can include as many other registers as you like. */
447 /* On the 80960, note that:
448 g0..g3 are used for return values,
449 g0..g7 may always be used for parameters,
450 g8..g11 may be used for parameters, but are preserved if they aren't,
451 g12 is always preserved, but otherwise unused,
452 g13 is the struct return ptr if used, or temp, but may be trashed,
453 g14 is the leaf return ptr or the arg block ptr otherwise zero,
454 must be reset to zero before returning if it was used,
455 g15 is the frame pointer,
456 r0 is the previous FP,
457 r1 is the stack pointer,
458 r2 is the return instruction pointer,
459 r3-r15 are always available,
460 r3 is clobbered by calls in functions that use the arg pointer
461 r4-r11 may be clobbered by the mcount call when profiling
462 r4-r15 if otherwise unused may be used for preserving global registers
463 fp0..fp3 are never available. */
464 #define CALL_USED_REGISTERS \
465 {1, 1, 1, 1, 1, 1, 1, 1, \
466 0, 0, 0, 0, 0, 1, 1, 1, \
467 1, 1, 1, 0, 0, 0, 0, 0, \
468 0, 0, 0, 0, 0, 0, 0, 0, \
471 /* If no fp unit, make all of the fp registers fixed so that they can't
473 #define CONDITIONAL_REGISTER_USAGE \
474 if (! TARGET_NUMERICS) { \
475 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
478 /* Return number of consecutive hard regs needed starting at reg REGNO
479 to hold something of mode MODE.
480 This is ordinarily the length in words of a value of mode MODE
481 but can be less for certain modes in special long registers.
483 On 80960, ordinary registers hold 32 bits worth, but can be ganged
484 together to hold double or extended precision floating point numbers,
485 and the floating point registers hold any size floating point number */
486 #define HARD_REGNO_NREGS(REGNO, MODE) \
488 ? (((MODE) == VOIDmode) \
489 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
490 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
492 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
493 On 80960, the cpu registers can hold any mode but the float registers
494 can only hold SFmode, DFmode, or XFmode. */
495 extern unsigned int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
496 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
497 ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
499 /* Value is 1 if it is a good idea to tie two pseudo registers
500 when one has mode MODE1 and one has mode MODE2.
501 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
502 for any hard reg, then this must be 0 for correct output. */
504 #define MODES_TIEABLE_P(MODE1, MODE2) \
505 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
507 /* Specify the registers used for certain standard purposes.
508 The values of these macros are register numbers. */
510 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
511 /* #define PC_REGNUM */
513 /* Register to use for pushing function arguments. */
514 #define STACK_POINTER_REGNUM 17
516 /* Actual top-of-stack address is same as
517 the contents of the stack pointer register. */
518 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
520 /* Base register for access to local variables of the function. */
521 #define FRAME_POINTER_REGNUM 15
523 /* Value should be nonzero if functions must have frame pointers.
524 Zero means the frame pointer need not be set up (and parms
525 may be accessed via the stack pointer) in functions that seem suitable.
526 This is computed in `reload', in reload1.c. */
527 /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
528 fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
529 caused this to fail. */
530 #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
532 /* C statement to store the difference between the frame pointer
533 and the stack pointer values immediately after the function prologue.
535 Since the stack grows upward on the i960, this must be a negative number.
536 This includes the 64 byte hardware register save area and the size of
539 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
540 do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
542 /* Base register for access to arguments of the function. */
543 #define ARG_POINTER_REGNUM 14
545 /* Register in which static-chain is passed to a function.
546 On i960, we use r3. */
547 #define STATIC_CHAIN_REGNUM 19
549 /* Functions which return large structures get the address
550 to place the wanted value at in g13. */
552 #define STRUCT_VALUE_REGNUM 13
554 /* The order in which to allocate registers. */
556 #define REG_ALLOC_ORDER \
557 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
558 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
559 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
560 11, 12, /* g11, g12 */ \
561 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
562 /* We can't actually allocate these. */ \
563 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
565 /* Define the classes of registers for register constraints in the
566 machine description. Also define ranges of constants.
568 One of the classes must always be named ALL_REGS and include all hard regs.
569 If there is more than one class, another class must be named NO_REGS
570 and contain no registers.
572 The name GENERAL_REGS must be the name of a class (or an alias for
573 another name such as ALL_REGS). This is the class of registers
574 that is allowed by "g" or "r" in a register constraint.
575 Also, registers outside this class are allocated only when
576 instructions express preferences for them.
578 The classes must be numbered in nondecreasing order; that is,
579 a larger-numbered class must never be contained completely
580 in a smaller-numbered class.
582 For any two classes, it is very desirable that there be another
583 class that represents their union. */
585 /* The 80960 has four kinds of registers, global, local, floating point,
586 and condition code. The cc register is never allocated, so no class
587 needs to be defined for it. */
589 enum reg_class
{ NO_REGS
, GLOBAL_REGS
, LOCAL_REGS
, LOCAL_OR_GLOBAL_REGS
,
590 FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
592 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
594 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
596 #define N_REG_CLASSES (int) LIM_REG_CLASSES
598 /* Give names of register classes as strings for dump file. */
600 #define REG_CLASS_NAMES \
601 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
602 "FP_REGS", "ALL_REGS" }
604 /* Define which registers fit in which classes.
605 This is an initializer for a vector of HARD_REG_SET
606 of length N_REG_CLASSES. */
608 #define REG_CLASS_CONTENTS \
609 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
611 /* The same information, inverted:
612 Return the class number of the smallest class containing
613 reg number REGNO. This could be a conditional expression
614 or could index an array. */
616 #define REGNO_REG_CLASS(REGNO) \
617 ((REGNO) < 16 ? GLOBAL_REGS \
618 : (REGNO) < 32 ? LOCAL_REGS \
619 : (REGNO) < 36 ? FP_REGS \
622 /* The class value for index registers, and the one for base regs.
623 There is currently no difference between base and index registers on the
624 i960, but this distinction may one day be useful. */
625 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
626 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
628 /* Get reg_class from a letter such as appears in the machine description.
629 'f' is a floating point register (fp0..fp3)
630 'l' is a local register (r0-r15)
631 'b' is a global register (g0-g15)
632 'd' is any local or global register
633 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
634 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
635 the same thing, since 'r' may include the fp registers. */
636 #define REG_CLASS_FROM_LETTER(C) \
637 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
638 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
640 /* The letters I, J, K, L and M in a register constraint string
641 can be used to stand for particular ranges of immediate operands.
642 This macro defines what the ranges are.
643 C is the letter, and VALUE is a constant value.
644 Return 1 if VALUE is in the range specified by C.
647 'I' is used for literal values 0..31
651 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
652 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
653 : (C) == 'J' ? ((VALUE) == 0) \
654 : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \
655 : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \
658 /* Similar, but for floating constants, and defining letters G and H.
659 Here VALUE is the CONST_DOUBLE rtx itself.
660 For the 80960, G is 0.0 and H is 1.0. */
662 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
663 ((TARGET_NUMERICS) && \
664 (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
665 || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
667 /* Given an rtx X being reloaded into a reg required to be
668 in class CLASS, return the class of reg to actually use.
669 In general this is just CLASS; but on some machines
670 in some cases it is preferable to use a more restrictive class. */
672 /* On 960, can't load constant into floating-point reg except
675 Any hard reg is ok as a src operand of a reload insn. */
677 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
678 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
680 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
681 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
682 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
684 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
686 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
687 secondary_reload_class (CLASS, MODE, IN)
689 /* Return the maximum number of consecutive registers
690 needed to represent mode MODE in a register of class CLASS. */
691 /* On 80960, this is the size of MODE in words,
692 except in the FP regs, where a single reg is always enough. */
693 #define CLASS_MAX_NREGS(CLASS, MODE) \
694 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
696 /* Stack layout; function entry, exit and calling. */
698 /* Define this if pushing a word on the stack
699 makes the stack pointer a smaller address. */
700 /* #define STACK_GROWS_DOWNWARD */
702 /* Define this if the nominal address of the stack frame
703 is at the high-address end of the local variables;
704 that is, each additional local variable allocated
705 goes at a more negative offset in the frame. */
706 /* #define FRAME_GROWS_DOWNWARD */
708 /* Offset within stack frame to start allocating local variables at.
709 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
710 first local allocated. Otherwise, it is the offset to the BEGINNING
711 of the first local allocated.
713 The i960 has a 64 byte register save area, plus possibly some extra
714 bytes allocated for varargs functions. */
715 #define STARTING_FRAME_OFFSET 64
717 /* If we generate an insn to push BYTES bytes,
718 this says how many the stack pointer really advances by.
719 On 80960, don't define this because there are no push insns. */
720 /* #define PUSH_ROUNDING(BYTES) BYTES */
722 /* Offset of first parameter from the argument pointer register value. */
723 #define FIRST_PARM_OFFSET(FNDECL) 0
725 /* When a parameter is passed in a register, no stack space is
726 allocated for it. However, when args are passed in the
727 stack, space is allocated for every register parameter. */
728 #define MAYBE_REG_PARM_STACK_SPACE 48
729 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
730 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
731 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
732 #define OUTGOING_REG_PARM_STACK_SPACE
734 /* Keep the stack pointer constant throughout the function. */
735 #define ACCUMULATE_OUTGOING_ARGS
737 /* Value is 1 if returning from a function call automatically
738 pops the arguments described by the number-of-args field in the call.
739 FUNDECL is the declaration node of the function (as a tree),
740 FUNTYPE is the data type of the function (as a tree),
741 or for a library call it is an identifier node for the subroutine name. */
743 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
745 /* Define how to find the value returned by a library function
746 assuming the value has mode MODE. */
748 #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
750 /* 1 if N is a possible register number for a function value
751 as seen by the caller.
752 On 80960, returns are in g0..g3 */
754 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
756 /* 1 if N is a possible register number for function argument passing.
757 On 80960, parameters are passed in g0..g11 */
759 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
761 /* Perform any needed actions needed for a function that is receiving a
762 variable number of arguments.
766 MODE and TYPE are the mode and type of the current parameter.
768 PRETEND_SIZE is a variable that should be set to the amount of stack
769 that must be pushed by the prolog to pretend that our caller pushed
772 Normally, this macro will push all remaining incoming registers on the
773 stack and set PRETEND_SIZE to the length of the registers pushed. */
775 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
776 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
778 /* Define a data type for recording info about an argument list
779 during the scan of that argument list. This data type should
780 hold all necessary information about the function itself
781 and about the args processed so far, enough to enable macros
782 such as FUNCTION_ARG to determine where the next arg should go.
784 On 80960, this is two integers, which count the number of register
785 parameters and the number of stack parameters seen so far. */
787 struct cum_args
{ int ca_nregparms
; int ca_nstackparms
; };
789 #define CUMULATIVE_ARGS struct cum_args
791 /* Define the number of registers that can hold parameters.
792 This macro is used only in macro definitions below and/or i960.c. */
793 #define NPARM_REGS 12
795 /* Define how to round to the next parameter boundary.
796 This macro is used only in macro definitions below and/or i960.c. */
797 #define ROUND_PARM(X, MULTIPLE_OF) \
798 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
800 /* Initialize a variable CUM of type CUMULATIVE_ARGS
801 for a call to a function whose data type is FNTYPE.
802 For a library call, FNTYPE is 0.
804 On 80960, the offset always starts at 0; the first parm reg is g0. */
806 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
807 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
809 /* Update the data in CUM to advance over an argument
810 of mode MODE and data type TYPE.
811 CUM should be advanced to align with the data type accessed and
812 also the size of that data type in # of regs.
813 (TYPE is null for libcalls where that information may not be available.) */
815 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
816 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
818 /* Indicate the alignment boundary for an argument of the specified mode and
820 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
822 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
824 : TYPE_ALIGN (TYPE)) \
825 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
827 : GET_MODE_ALIGNMENT (MODE)))
829 /* Determine where to put an argument to a function.
830 Value is zero to push the argument on the stack,
831 or a hard register in which to store the argument.
833 MODE is the argument's machine mode.
834 TYPE is the data type of the argument (as a tree).
835 This is null for libcalls where that information may
837 CUM is a variable of type CUMULATIVE_ARGS which gives info about
838 the preceding args and about the function being called.
839 NAMED is nonzero if this argument is a named parameter
840 (otherwise it is an extra parameter matching an ellipsis). */
842 extern struct rtx_def
*i960_function_arg ();
843 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
844 i960_function_arg(&CUM, MODE, TYPE, NAMED)
846 /* Define how to find the value returned by a function.
847 VALTYPE is the data type of the value (as a tree).
848 If the precise function being called is known, FUNC is its FUNCTION_DECL;
849 otherwise, FUNC is 0. */
851 #define FUNCTION_VALUE(TYPE, FUNC) \
852 gen_rtx (REG, TYPE_MODE (TYPE), 0)
854 /* Force aggregates and objects larger than 16 bytes to be returned in memory,
855 since we only have 4 registers available for return values. */
857 #define RETURN_IN_MEMORY(TYPE) \
858 (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
860 /* Don't default to pcc-struct-return, because we have already specified
861 exactly how to return structures in the RETURN_IN_MEMORY macro. */
862 #define DEFAULT_PCC_STRUCT_RETURN 0
864 /* For an arg passed partly in registers and partly in memory,
865 this is the number of registers used.
866 This never happens on 80960. */
868 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
870 /* Output the label for a function definition.
871 This handles leaf functions and a few other things for the i960. */
873 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
874 i960_function_name_declare (FILE, NAME, DECL)
876 /* This macro generates the assembly code for function entry.
877 FILE is a stdio stream to output the code to.
878 SIZE is an int: how many units of temporary storage to allocate.
879 Refer to the array `regs_ever_live' to determine which registers
880 to save; `regs_ever_live[I]' is nonzero if register number I
881 is ever used in the function. This macro is responsible for
882 knowing which registers should not be saved even if used. */
884 #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
886 /* Output assembler code to FILE to increment profiler label # LABELNO
887 for profiling a function entry. */
889 #define FUNCTION_PROFILER(FILE, LABELNO) \
890 output_function_profiler ((FILE), (LABELNO));
892 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
893 the stack pointer does not matter. The value is tested only in
894 functions that have frame pointers.
895 No definition is equivalent to always zero. */
897 #define EXIT_IGNORE_STACK 1
899 /* This macro generates the assembly code for function exit,
900 on machines that need it. If FUNCTION_EPILOGUE is not defined
901 then individual return instructions are generated for each
902 return statement. Args are same as for FUNCTION_PROLOGUE.
904 The function epilogue should not depend on the current stack pointer!
905 It should use the frame pointer only. This is mandatory because
906 of alloca; we also take advantage of it to omit stack adjustments
909 #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
911 /* Addressing modes, and classification of registers for them. */
913 /* #define HAVE_POST_INCREMENT */
914 /* #define HAVE_POST_DECREMENT */
916 /* #define HAVE_PRE_DECREMENT */
917 /* #define HAVE_PRE_INCREMENT */
919 /* Macros to check register numbers against specific register classes. */
921 /* These assume that REGNO is a hard or pseudo reg number.
922 They give nonzero only if REGNO is a hard reg of the suitable class
923 or a pseudo reg currently allocated to a suitable hard reg.
924 Since they use reg_renumber, they are safe only once reg_renumber
925 has been allocated, which happens in local-alloc.c. */
927 #define REGNO_OK_FOR_INDEX_P(REGNO) \
928 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
929 #define REGNO_OK_FOR_BASE_P(REGNO) \
930 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
931 #define REGNO_OK_FOR_FP_P(REGNO) \
932 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
934 /* Now macros that check whether X is a register and also,
935 strictly, whether it is in a specified class.
937 These macros are specific to the 960, and may be used only
938 in code for printing assembler insns and in conditions for
939 define_optimization. */
941 /* 1 if X is an fp register. */
943 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
945 /* Maximum number of registers that can appear in a valid memory address. */
946 #define MAX_REGS_PER_ADDRESS 2
948 #define CONSTANT_ADDRESS_P(X) \
949 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
950 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
951 || GET_CODE (X) == HIGH)
953 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
954 is a legitimate general operand.
955 It is given that X satisfies CONSTANT_P.
957 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
959 ??? This probably should be defined to 1. */
961 #define LEGITIMATE_CONSTANT_P(X) \
962 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
964 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
965 and check its validity for a certain class.
966 We have two alternate definitions for each of them.
967 The usual definition accepts all pseudo regs; the other rejects
968 them unless they have been allocated suitable hard regs.
969 The symbol REG_OK_STRICT causes the latter definition to be used.
971 Most source files want to accept pseudo regs in the hope that
972 they will get allocated to the class that the insn wants them to be in.
973 Source files for reload pass need to be strict.
974 After reload, it makes no difference, since pseudo regs have
975 been eliminated by then. */
977 #ifndef REG_OK_STRICT
979 /* Nonzero if X is a hard reg that can be used as an index
980 or if it is a pseudo reg. */
981 #define REG_OK_FOR_INDEX_P(X) \
982 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
983 /* Nonzero if X is a hard reg that can be used as a base reg
984 or if it is a pseudo reg. */
985 #define REG_OK_FOR_BASE_P(X) \
986 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
988 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
989 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
993 /* Nonzero if X is a hard reg that can be used as an index. */
994 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
995 /* Nonzero if X is a hard reg that can be used as a base reg. */
996 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1000 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1001 that is a valid memory address for an instruction.
1002 The MODE argument is the machine mode for the MEM expression
1003 that wants to use this address.
1005 On 80960, legitimate addresses are:
1007 disp (12 or 32 bit) ld foo,r0
1008 base + index ld (g0)[g1*1],r0
1009 base + displ ld 0xf00(g0),r0
1010 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1011 index*scale + base ld (g0)[g1*4],r0
1012 index*scale + displ ld 0xf00[g1*4],r0
1013 index*scale ld [g1*4],r0
1014 index + base + displ ld 0xf00(g0)[g1*1],r0
1016 In each case, scale can be 1, 2, 4, 8, or 16. */
1018 /* Returns 1 if the scale factor of an index term is valid. */
1019 #define SCALE_TERM_P(X) \
1020 (GET_CODE (X) == CONST_INT \
1021 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1022 || INTVAL(X) == 8 || INTVAL (X) == 16))
1025 #ifdef REG_OK_STRICT
1026 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1027 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1029 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1030 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1033 /* Try machine-dependent ways of modifying an illegitimate address
1034 to be legitimate. If we find one, return the new, valid address.
1035 This macro is used in only one place: `memory_address' in explow.c.
1037 OLDX is the address as it was before break_out_memory_refs was called.
1038 In some cases it is useful to look at this to decide what needs to be done.
1040 MODE and WIN are passed so that this macro can use
1041 GO_IF_LEGITIMATE_ADDRESS.
1043 It is always safe for this macro to do nothing. It exists to recognize
1044 opportunities to optimize the output. */
1046 /* On 80960, convert non-canonical addresses to canonical form. */
1048 extern struct rtx_def
*legitimize_address ();
1049 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1050 { rtx orig_x = (X); \
1051 (X) = legitimize_address (X, OLDX, MODE); \
1052 if ((X) != orig_x && memory_address_p (MODE, X)) \
1055 /* Go to LABEL if ADDR (a legitimate address expression)
1056 has an effect that depends on the machine mode it is used for.
1057 On the 960 this is never true. */
1059 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1061 /* Specify the machine mode that this machine uses
1062 for the index in the tablejump instruction. */
1063 #define CASE_VECTOR_MODE SImode
1065 /* Define this if the tablejump instruction expects the table
1066 to contain offsets from the address of the table.
1067 Do not define this if the table should contain absolute addresses. */
1068 /* #define CASE_VECTOR_PC_RELATIVE */
1070 /* Specify the tree operation to be used to convert reals to integers. */
1071 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1073 /* This is the kind of divide that is easiest to do in the general case. */
1074 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1076 /* Define this as 1 if `char' should by default be signed; else as 0. */
1077 #define DEFAULT_SIGNED_CHAR 0
1079 /* Allow and ignore #sccs directives. */
1080 #define SCCS_DIRECTIVE
1082 /* Max number of bytes we can move from memory to memory
1083 in one reasonably fast instruction. */
1086 /* Define if operations between registers always perform the operation
1087 on the full register even if a narrower mode is specified. */
1088 #define WORD_REGISTER_OPERATIONS
1090 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1091 will either zero-extend or sign-extend. The value of this macro should
1092 be the code that says which one of the two operations is implicitly
1093 done, NIL if none. */
1094 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1096 /* Nonzero if access to memory by bytes is no faster than for words.
1097 Defining this results in worse code on the i960. */
1099 #define SLOW_BYTE_ACCESS 0
1101 /* We assume that the store-condition-codes instructions store 0 for false
1102 and some other value for true. This is the value stored for true. */
1104 #define STORE_FLAG_VALUE 1
1106 /* Define this to be nonzero if shift instructions ignore all but the low-order
1108 #define SHIFT_COUNT_TRUNCATED 0
1110 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1111 is done just by pretending it is already truncated. */
1112 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1114 /* Specify the machine mode that pointers have.
1115 After generation of rtl, the compiler makes no further distinction
1116 between pointers and any other objects of this machine mode. */
1117 #define Pmode SImode
1119 /* Specify the widest mode that BLKmode objects can be promoted to */
1120 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1122 /* These global variables are used to pass information between
1123 cc setter and cc user at insn emit time. */
1125 extern struct rtx_def
*i960_compare_op0
, *i960_compare_op1
;
1127 /* Define the function that build the compare insn for scc and bcc. */
1129 extern struct rtx_def
*gen_compare_reg ();
1131 /* Add any extra modes needed to represent the condition code.
1133 Also, signed and unsigned comparisons are distinguished, as
1134 are operations which are compatible with chkbit insns. */
1135 #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1137 /* Define the names for the modes specified above. */
1138 #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1140 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1141 return the mode to be used for the comparison. For floating-point, CCFPmode
1142 should be used. CC_NOOVmode should be used when the first operand is a
1143 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1145 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1147 /* A function address in a call instruction is a byte address
1148 (for indexing purposes) so give the MEM rtx a byte's mode. */
1149 #define FUNCTION_MODE SImode
1151 /* Define this if addresses of constant functions
1152 shouldn't be put through pseudo regs where they can be cse'd.
1153 Desirable on machines where ordinary constants are expensive
1154 but a CALL with constant address is cheap. */
1155 #define NO_FUNCTION_CSE
1157 /* Use memcpy, etc. instead of bcopy. */
1160 #define TARGET_MEM_FUNCTIONS 1
1163 /* Compute the cost of computing a constant rtl expression RTX
1164 whose rtx-code is CODE. The body of this macro is a portion
1165 of a switch statement. If the code is computed here,
1166 return it with a return statement. Otherwise, break from the switch. */
1168 /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1169 that can be non-ldconst operands in rare cases are cost 1. Other constants
1170 have higher costs. */
1172 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1174 if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1175 || power2_operand (RTX, VOIDmode)) \
1177 else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1182 return (TARGET_FLAG_C_SERIES ? 6 : 8); \
1183 case CONST_DOUBLE: \
1184 if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1185 || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1189 /* The i960 offers addressing modes which are "as cheap as a register".
1190 See i960.c (or gcc.texinfo) for details. */
1192 #define ADDRESS_COST(RTX) \
1193 (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1195 /* Control the assembler format that we output. */
1197 /* Output at beginning of assembler file. */
1199 #define ASM_FILE_START(file)
1201 /* Output to assembler file text saying following lines
1202 may contain character constants, extra white space, comments, etc. */
1204 #define ASM_APP_ON ""
1206 /* Output to assembler file text saying following lines
1207 no longer contain unusual constructs. */
1209 #define ASM_APP_OFF ""
1211 /* Output before read-only data. */
1213 #define TEXT_SECTION_ASM_OP ".text"
1215 /* Output before writable data. */
1217 #define DATA_SECTION_ASM_OP ".data"
1219 /* How to refer to registers in assembler output.
1220 This sequence is indexed by compiler's hard-register-number (see above). */
1222 #define REGISTER_NAMES { \
1223 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1224 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1225 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1226 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1227 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1229 /* How to renumber registers for dbx and gdb.
1230 In the 960 encoding, g0..g15 are registers 16..31. */
1232 #define DBX_REGISTER_NUMBER(REGNO) \
1233 (((REGNO) < 16) ? (REGNO) + 16 \
1234 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1236 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1237 #define DBX_CONTIN_LENGTH 1500
1239 /* This is how to output a note to DBX telling it the line number
1240 to which the following sequence of instructions corresponds. */
1242 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1243 { if (write_symbols == SDB_DEBUG) { \
1244 fprintf ((FILE), "\t.ln %d\n", \
1245 (sdb_begin_function_line \
1246 ? (LINE) - sdb_begin_function_line : 1)); \
1247 } else if (write_symbols == DBX_DEBUG) { \
1248 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1251 /* This is how to output the definition of a user-level label named NAME,
1252 such as the label on a static function or variable NAME. */
1254 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1255 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1257 /* This is how to output a command to make the user-level label named NAME
1258 defined for reference from other files. */
1260 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1261 { fputs ("\t.globl ", FILE); \
1262 assemble_name (FILE, NAME); \
1263 fputs ("\n", FILE); }
1265 /* This is how to output a reference to a user-level label named NAME.
1266 `assemble_name' uses this. */
1268 #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME)
1270 /* This is how to output an internal numbered label where
1271 PREFIX is the class of label and NUM is the number within the class. */
1273 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1274 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1276 /* This is how to store into the string LABEL
1277 the symbol_ref name of an internal numbered label where
1278 PREFIX is the class of label and NUM is the number within the class.
1279 This is suitable for output with `assemble_name'. */
1281 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1282 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1284 /* This is how to output an assembler line defining a `long double'
1287 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
1289 /* This is how to output an assembler line defining a `double' constant. */
1291 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1293 /* This is how to output an assembler line defining a `float' constant. */
1295 #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1297 /* This is how to output an assembler line defining an `int' constant. */
1299 #define ASM_OUTPUT_INT(FILE,VALUE) \
1300 ( fprintf (FILE, "\t.word "), \
1301 output_addr_const (FILE, (VALUE)), \
1302 fprintf (FILE, "\n"))
1304 /* Likewise for `char' and `short' constants. */
1306 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1307 ( fprintf (FILE, "\t.short "), \
1308 output_addr_const (FILE, (VALUE)), \
1309 fprintf (FILE, "\n"))
1311 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1312 ( fprintf (FILE, "\t.byte "), \
1313 output_addr_const (FILE, (VALUE)), \
1314 fprintf (FILE, "\n"))
1316 /* This is how to output an assembler line for a numeric constant byte. */
1318 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1319 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1321 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1322 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1324 /* This is how to output an insn to pop a register from the stack.
1325 It need not be very fast code. */
1327 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1328 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1330 /* This is how to output an element of a case-vector that is absolute. */
1332 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1333 fprintf (FILE, "\t.word L%d\n", VALUE)
1335 /* This is how to output an element of a case-vector that is relative. */
1337 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1338 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1340 /* This is how to output an assembler line that says to advance the
1341 location counter to a multiple of 2**LOG bytes. */
1343 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1344 fprintf (FILE, "\t.align %d\n", (LOG))
1346 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1347 fprintf (FILE, "\t.space %d\n", (SIZE))
1349 /* This says how to output an assembler line
1350 to define a global common symbol. */
1352 /* For common objects, output unpadded size... gld960 & lnk960 both
1353 have code to align each common object at link time. Also, if size
1354 is 0, treat this as a declaration, not a definition - i.e.,
1355 do nothing at all. */
1357 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1358 { if ((SIZE) != 0) \
1360 fputs (".globl ", (FILE)), \
1361 assemble_name ((FILE), (NAME)), \
1362 fputs ("\n.comm ", (FILE)), \
1363 assemble_name ((FILE), (NAME)), \
1364 fprintf ((FILE), ",%d\n", (SIZE)); \
1368 /* This says how to output an assembler line to define a local common symbol.
1369 Output unpadded size, with request to linker to align as requested.
1370 0 size should not be possible here. */
1372 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1373 ( fputs (".bss\t", (FILE)), \
1374 assemble_name ((FILE), (NAME)), \
1375 fprintf ((FILE), ",%d,%d\n", (SIZE), \
1377 : ((ALIGN) <= 16 ? 1 \
1378 : ((ALIGN) <= 32 ? 2 \
1379 : ((ALIGN <= 64 ? 3 : 4)))))))
1381 /* Output text for an #ident directive. */
1382 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1384 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1386 #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1387 { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); }
1389 /* Store in OUTPUT a string (made with alloca) containing
1390 an assembler-name for a local static variable named NAME.
1391 LABELNO is an integer which is different for each call. */
1393 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1394 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1395 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1397 /* Define the parentheses used to group arithmetic operations
1398 in assembler code. */
1400 #define ASM_OPEN_PAREN "("
1401 #define ASM_CLOSE_PAREN ")"
1403 /* Define results of standard character escape sequences. */
1404 #define TARGET_BELL 007
1405 #define TARGET_BS 010
1406 #define TARGET_TAB 011
1407 #define TARGET_NEWLINE 012
1408 #define TARGET_VT 013
1409 #define TARGET_FF 014
1410 #define TARGET_CR 015
1412 /* Output assembler code to FILE to initialize this source file's
1413 basic block profiling info, if that has not already been done. */
1415 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1416 { fprintf (FILE, "\tld LPBX0,g12\n"); \
1417 fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1418 fprintf (FILE, "\tlda LPBX0,g12\n"); \
1419 fprintf (FILE, "\tcall ___bb_init_func\n"); \
1420 fprintf (FILE, "LPY%d:\n",LABELNO); }
1422 /* Output assembler code to FILE to increment the entry-count for
1423 the BLOCKNO'th basic block in this source file. */
1425 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1426 { int blockn = (BLOCKNO); \
1427 fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1428 fprintf (FILE, "\taddo g12,1,g12\n"); \
1429 fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1431 /* Print operand X (an rtx) in assembler syntax to file FILE.
1432 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1433 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1435 #define PRINT_OPERAND(FILE, X, CODE) \
1436 i960_print_operand (FILE, X, CODE);
1438 /* Print a memory address as an operand to reference that memory location. */
1440 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1441 i960_print_operand_addr (FILE, ADDR)
1443 /* Output assembler code for a block containing the constant parts
1444 of a trampoline, leaving space for the variable parts. */
1446 /* On the i960, the trampoline contains three instructions:
1447 ldconst _function, r4
1448 ldconst static addr, r3
1451 #define TRAMPOLINE_TEMPLATE(FILE) \
1453 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \
1454 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1455 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \
1456 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1457 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \
1460 /* Length in units of the trampoline for entering a nested function. */
1462 #define TRAMPOLINE_SIZE 20
1464 /* Emit RTL insns to initialize the variable parts of a trampoline.
1465 FNADDR is an RTX for the address of the function's pure code.
1466 CXT is an RTX for the static chain value for the function. */
1468 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1470 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1472 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1477 /* Promote char and short arguments to ints, when want compatibility with
1478 the iC960 compilers. */
1480 /* ??? In order for this to work, all users would need to be changed
1481 to test the value of the macro at run time. */
1482 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1483 /* ??? This does not exist. */
1484 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1487 /* Instruction type definitions. Used to alternate instructions types for
1488 better performance on the C series chips. */
1490 enum insn_types
{ I_TYPE_REG
, I_TYPE_MEM
, I_TYPE_CTRL
};
1492 /* Holds the insn type of the last insn output to the assembly file. */
1494 extern enum insn_types i960_last_insn_type
;
1496 /* Parse opcodes, and set the insn last insn type based on them. */
1498 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1500 /* Table listing what rtl codes each predicate in i960.c will accept. */
1502 #define PREDICATE_CODES \
1503 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1504 LABEL_REF, SUBREG, REG, MEM}}, \
1505 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1506 {"logic_operand", {SUBREG, REG, CONST_INT}}, \
1507 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1508 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1509 {"literal", {CONST_INT}}, \
1510 {"fp_literal_one", {CONST_DOUBLE}}, \
1511 {"fp_literal_double", {CONST_DOUBLE}}, \
1512 {"fp_literal", {CONST_DOUBLE}}, \
1513 {"signed_literal", {CONST_INT}}, \
1514 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1515 {"eq_or_neq", {EQ, NE}}, \
1516 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1517 CONST_DOUBLE, CONST}}, \
1518 {"power2_operand", {CONST_INT}}, \
1519 {"cmplpower2_operand", {CONST_INT}},
1521 /* Define functions in i960.c and used in insn-output.c. */
1523 extern char *i960_output_ldconst ();
1524 extern char *i960_output_call_insn ();
1525 extern char *i960_output_ret_insn ();
1527 /* Defined in reload.c, and used in insn-recog.c. */
1529 extern int rtx_equal_function_value_matters
;