1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
52 #include "cfglayout.h"
54 /* This is used for communication between ASM_OUTPUT_LABEL and
55 ASM_OUTPUT_LABELREF. */
56 int ia64_asm_output_label
= 0;
58 /* Define the information needed to generate branch and scc insns. This is
59 stored from the compare operation. */
60 struct rtx_def
* ia64_compare_op0
;
61 struct rtx_def
* ia64_compare_op1
;
63 /* Register names for ia64_expand_prologue. */
64 static const char * const ia64_reg_numbers
[96] =
65 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
66 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
67 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
68 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
69 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
70 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
71 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
72 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
73 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
74 "r104","r105","r106","r107","r108","r109","r110","r111",
75 "r112","r113","r114","r115","r116","r117","r118","r119",
76 "r120","r121","r122","r123","r124","r125","r126","r127"};
78 /* ??? These strings could be shared with REGISTER_NAMES. */
79 static const char * const ia64_input_reg_names
[8] =
80 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
82 /* ??? These strings could be shared with REGISTER_NAMES. */
83 static const char * const ia64_local_reg_names
[80] =
84 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
85 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
86 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
87 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
88 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
89 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
90 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
91 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
92 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
93 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
95 /* ??? These strings could be shared with REGISTER_NAMES. */
96 static const char * const ia64_output_reg_names
[8] =
97 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
99 /* String used with the -mfixed-range= option. */
100 const char *ia64_fixed_range_string
;
102 /* Determines whether we use adds, addl, or movl to generate our
103 TLS immediate offsets. */
104 int ia64_tls_size
= 22;
106 /* String used with the -mtls-size= option. */
107 const char *ia64_tls_size_string
;
109 /* Which cpu are we scheduling for. */
110 enum processor_type ia64_tune
;
112 /* String used with the -tune= option. */
113 const char *ia64_tune_string
;
115 /* Determines whether we run our final scheduling pass or not. We always
116 avoid the normal second scheduling pass. */
117 static int ia64_flag_schedule_insns2
;
119 /* Variables which are this size or smaller are put in the sdata/sbss
122 unsigned int ia64_section_threshold
;
124 /* The following variable is used by the DFA insn scheduler. The value is
125 TRUE if we do insn bundling instead of insn scheduling. */
128 /* Structure to be filled in by ia64_compute_frame_size with register
129 save masks and offsets for the current function. */
131 struct ia64_frame_info
133 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
134 the caller's scratch area. */
135 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
136 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
137 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
138 HARD_REG_SET mask
; /* mask of saved registers. */
139 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
140 registers or long-term scratches. */
141 int n_spilled
; /* number of spilled registers. */
142 int reg_fp
; /* register for fp. */
143 int reg_save_b0
; /* save register for b0. */
144 int reg_save_pr
; /* save register for prs. */
145 int reg_save_ar_pfs
; /* save register for ar.pfs. */
146 int reg_save_ar_unat
; /* save register for ar.unat. */
147 int reg_save_ar_lc
; /* save register for ar.lc. */
148 int reg_save_gp
; /* save register for gp. */
149 int n_input_regs
; /* number of input registers used. */
150 int n_local_regs
; /* number of local registers used. */
151 int n_output_regs
; /* number of output registers used. */
152 int n_rotate_regs
; /* number of rotating registers used. */
154 char need_regstk
; /* true if a .regstk directive needed. */
155 char initialized
; /* true if the data is finalized. */
158 /* Current frame information calculated by ia64_compute_frame_size. */
159 static struct ia64_frame_info current_frame_info
;
161 static int ia64_use_dfa_pipeline_interface (void);
162 static int ia64_first_cycle_multipass_dfa_lookahead (void);
163 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
164 static void ia64_init_dfa_pre_cycle_insn (void);
165 static rtx
ia64_dfa_pre_cycle_insn (void);
166 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
167 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
168 static rtx
gen_tls_get_addr (void);
169 static rtx
gen_thread_pointer (void);
170 static rtx
ia64_expand_tls_address (enum tls_model
, rtx
, rtx
);
171 static int find_gr_spill (int);
172 static int next_scratch_gr_reg (void);
173 static void mark_reg_gr_used_mask (rtx
, void *);
174 static void ia64_compute_frame_size (HOST_WIDE_INT
);
175 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
176 static void finish_spill_pointers (void);
177 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
178 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
179 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
180 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
181 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
182 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
184 static enum machine_mode
hfa_element_mode (tree
, int);
185 static bool ia64_function_ok_for_sibcall (tree
, tree
);
186 static bool ia64_rtx_costs (rtx
, int, int, int *);
187 static void fix_range (const char *);
188 static struct machine_function
* ia64_init_machine_status (void);
189 static void emit_insn_group_barriers (FILE *);
190 static void emit_all_insn_group_barriers (FILE *);
191 static void final_emit_insn_group_barriers (FILE *);
192 static void emit_predicate_relation_info (void);
193 static void ia64_reorg (void);
194 static bool ia64_in_small_data_p (tree
);
195 static void process_epilogue (void);
196 static int process_set (FILE *, rtx
);
198 static rtx
ia64_expand_fetch_and_op (optab
, enum machine_mode
, tree
, rtx
);
199 static rtx
ia64_expand_op_and_fetch (optab
, enum machine_mode
, tree
, rtx
);
200 static rtx
ia64_expand_compare_and_swap (enum machine_mode
, enum machine_mode
,
202 static rtx
ia64_expand_lock_test_and_set (enum machine_mode
, tree
, rtx
);
203 static rtx
ia64_expand_lock_release (enum machine_mode
, tree
, rtx
);
204 static bool ia64_assemble_integer (rtx
, unsigned int, int);
205 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
206 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
207 static void ia64_output_function_end_prologue (FILE *);
209 static int ia64_issue_rate (void);
210 static int ia64_adjust_cost (rtx
, rtx
, rtx
, int);
211 static void ia64_sched_init (FILE *, int, int);
212 static void ia64_sched_finish (FILE *, int);
213 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
214 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
215 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
216 static int ia64_variable_issue (FILE *, int, rtx
, int);
218 static struct bundle_state
*get_free_bundle_state (void);
219 static void free_bundle_state (struct bundle_state
*);
220 static void initiate_bundle_states (void);
221 static void finish_bundle_states (void);
222 static unsigned bundle_state_hash (const void *);
223 static int bundle_state_eq_p (const void *, const void *);
224 static int insert_bundle_state (struct bundle_state
*);
225 static void initiate_bundle_state_table (void);
226 static void finish_bundle_state_table (void);
227 static int try_issue_nops (struct bundle_state
*, int);
228 static int try_issue_insn (struct bundle_state
*, rtx
);
229 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
230 static int get_max_pos (state_t
);
231 static int get_template (state_t
, int);
233 static rtx
get_next_important_insn (rtx
, rtx
);
234 static void bundling (FILE *, int, rtx
, rtx
);
236 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
237 HOST_WIDE_INT
, tree
);
238 static void ia64_file_start (void);
240 static void ia64_select_rtx_section (enum machine_mode
, rtx
,
241 unsigned HOST_WIDE_INT
);
242 static void ia64_rwreloc_select_section (tree
, int, unsigned HOST_WIDE_INT
)
244 static void ia64_rwreloc_unique_section (tree
, int)
246 static void ia64_rwreloc_select_rtx_section (enum machine_mode
, rtx
,
247 unsigned HOST_WIDE_INT
)
249 static unsigned int ia64_rwreloc_section_type_flags (tree
, const char *, int)
252 static void ia64_hpux_add_extern_decl (const char *name
)
254 static void ia64_hpux_file_end (void)
256 static void ia64_hpux_init_libfuncs (void)
258 static void ia64_vms_init_libfuncs (void)
261 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
262 static void ia64_encode_section_info (tree
, rtx
, int);
265 /* Table of valid machine attributes. */
266 static const struct attribute_spec ia64_attribute_table
[] =
268 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
269 { "syscall_linkage", 0, 0, false, true, true, NULL
},
270 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
271 { NULL
, 0, 0, false, false, false, NULL
}
274 /* Initialize the GCC target structure. */
275 #undef TARGET_ATTRIBUTE_TABLE
276 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
278 #undef TARGET_INIT_BUILTINS
279 #define TARGET_INIT_BUILTINS ia64_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
284 #undef TARGET_ASM_BYTE_OP
285 #define TARGET_ASM_BYTE_OP "\tdata1\t"
286 #undef TARGET_ASM_ALIGNED_HI_OP
287 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
288 #undef TARGET_ASM_ALIGNED_SI_OP
289 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
292 #undef TARGET_ASM_UNALIGNED_HI_OP
293 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
294 #undef TARGET_ASM_UNALIGNED_SI_OP
295 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
296 #undef TARGET_ASM_UNALIGNED_DI_OP
297 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
298 #undef TARGET_ASM_INTEGER
299 #define TARGET_ASM_INTEGER ia64_assemble_integer
301 #undef TARGET_ASM_FUNCTION_PROLOGUE
302 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
303 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
304 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
305 #undef TARGET_ASM_FUNCTION_EPILOGUE
306 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
308 #undef TARGET_IN_SMALL_DATA_P
309 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
311 #undef TARGET_SCHED_ADJUST_COST
312 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
315 #undef TARGET_SCHED_VARIABLE_ISSUE
316 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
317 #undef TARGET_SCHED_INIT
318 #define TARGET_SCHED_INIT ia64_sched_init
319 #undef TARGET_SCHED_FINISH
320 #define TARGET_SCHED_FINISH ia64_sched_finish
321 #undef TARGET_SCHED_REORDER
322 #define TARGET_SCHED_REORDER ia64_sched_reorder
323 #undef TARGET_SCHED_REORDER2
324 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
326 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
327 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
329 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
330 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
332 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
333 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
335 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
336 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
337 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
338 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
340 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
341 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
342 ia64_first_cycle_multipass_dfa_lookahead_guard
344 #undef TARGET_SCHED_DFA_NEW_CYCLE
345 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
347 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
348 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
350 #undef TARGET_ASM_OUTPUT_MI_THUNK
351 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
352 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
353 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
355 #undef TARGET_ASM_FILE_START
356 #define TARGET_ASM_FILE_START ia64_file_start
358 #undef TARGET_RTX_COSTS
359 #define TARGET_RTX_COSTS ia64_rtx_costs
360 #undef TARGET_ADDRESS_COST
361 #define TARGET_ADDRESS_COST hook_int_rtx_0
363 #undef TARGET_MACHINE_DEPENDENT_REORG
364 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
366 #undef TARGET_ENCODE_SECTION_INFO
367 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
369 struct gcc_target targetm
= TARGET_INITIALIZER
;
371 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
374 call_operand (rtx op
, enum machine_mode mode
)
376 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
379 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
380 || (GET_CODE (op
) == SUBREG
&& GET_CODE (XEXP (op
, 0)) == REG
));
383 /* Return 1 if OP refers to a symbol in the sdata section. */
386 sdata_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
388 switch (GET_CODE (op
))
391 if (GET_CODE (XEXP (op
, 0)) != PLUS
392 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
)
394 op
= XEXP (XEXP (op
, 0), 0);
398 if (CONSTANT_POOL_ADDRESS_P (op
))
399 return GET_MODE_SIZE (get_pool_mode (op
)) <= ia64_section_threshold
;
401 return SYMBOL_REF_LOCAL_P (op
) && SYMBOL_REF_SMALL_P (op
);
411 small_addr_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
413 return SYMBOL_REF_SMALL_ADDR_P (op
);
416 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
419 got_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
421 switch (GET_CODE (op
))
425 if (GET_CODE (op
) != PLUS
)
427 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
430 if (GET_CODE (op
) != CONST_INT
)
435 /* Ok if we're not using GOT entries at all. */
436 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
439 /* "Ok" while emitting rtl, since otherwise we won't be provided
440 with the entire offset during emission, which makes it very
441 hard to split the offset into high and low parts. */
442 if (rtx_equal_function_value_matters
)
445 /* Force the low 14 bits of the constant to zero so that we do not
446 use up so many GOT entries. */
447 return (INTVAL (op
) & 0x3fff) == 0;
450 if (SYMBOL_REF_SMALL_ADDR_P (op
))
461 /* Return 1 if OP refers to a symbol. */
464 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
466 switch (GET_CODE (op
))
479 /* Return tls_model if OP refers to a TLS symbol. */
482 tls_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
484 if (GET_CODE (op
) != SYMBOL_REF
)
486 return SYMBOL_REF_TLS_MODEL (op
);
490 /* Return 1 if OP refers to a function. */
493 function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
495 if (GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (op
))
501 /* Return 1 if OP is setjmp or a similar function. */
503 /* ??? This is an unsatisfying solution. Should rethink. */
506 setjmp_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
511 if (GET_CODE (op
) != SYMBOL_REF
)
516 /* The following code is borrowed from special_function_p in calls.c. */
518 /* Disregard prefix _, __ or __x. */
521 if (name
[1] == '_' && name
[2] == 'x')
523 else if (name
[1] == '_')
533 && (! strcmp (name
, "setjmp")
534 || ! strcmp (name
, "setjmp_syscall")))
536 && ! strcmp (name
, "sigsetjmp"))
538 && ! strcmp (name
, "savectx")));
540 else if ((name
[0] == 'q' && name
[1] == 's'
541 && ! strcmp (name
, "qsetjmp"))
542 || (name
[0] == 'v' && name
[1] == 'f'
543 && ! strcmp (name
, "vfork")))
549 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
552 move_operand (rtx op
, enum machine_mode mode
)
554 return general_operand (op
, mode
) && !tls_symbolic_operand (op
, mode
);
557 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
560 gr_register_operand (rtx op
, enum machine_mode mode
)
562 if (! register_operand (op
, mode
))
564 if (GET_CODE (op
) == SUBREG
)
565 op
= SUBREG_REG (op
);
566 if (GET_CODE (op
) == REG
)
568 unsigned int regno
= REGNO (op
);
569 if (regno
< FIRST_PSEUDO_REGISTER
)
570 return GENERAL_REGNO_P (regno
);
575 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
578 fr_register_operand (rtx op
, enum machine_mode mode
)
580 if (! register_operand (op
, mode
))
582 if (GET_CODE (op
) == SUBREG
)
583 op
= SUBREG_REG (op
);
584 if (GET_CODE (op
) == REG
)
586 unsigned int regno
= REGNO (op
);
587 if (regno
< FIRST_PSEUDO_REGISTER
)
588 return FR_REGNO_P (regno
);
593 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
596 grfr_register_operand (rtx op
, enum machine_mode mode
)
598 if (! register_operand (op
, mode
))
600 if (GET_CODE (op
) == SUBREG
)
601 op
= SUBREG_REG (op
);
602 if (GET_CODE (op
) == REG
)
604 unsigned int regno
= REGNO (op
);
605 if (regno
< FIRST_PSEUDO_REGISTER
)
606 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
611 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
614 gr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
616 if (! nonimmediate_operand (op
, mode
))
618 if (GET_CODE (op
) == SUBREG
)
619 op
= SUBREG_REG (op
);
620 if (GET_CODE (op
) == REG
)
622 unsigned int regno
= REGNO (op
);
623 if (regno
< FIRST_PSEUDO_REGISTER
)
624 return GENERAL_REGNO_P (regno
);
629 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
632 fr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
634 if (! nonimmediate_operand (op
, mode
))
636 if (GET_CODE (op
) == SUBREG
)
637 op
= SUBREG_REG (op
);
638 if (GET_CODE (op
) == REG
)
640 unsigned int regno
= REGNO (op
);
641 if (regno
< FIRST_PSEUDO_REGISTER
)
642 return FR_REGNO_P (regno
);
647 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
650 grfr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
652 if (! nonimmediate_operand (op
, mode
))
654 if (GET_CODE (op
) == SUBREG
)
655 op
= SUBREG_REG (op
);
656 if (GET_CODE (op
) == REG
)
658 unsigned int regno
= REGNO (op
);
659 if (regno
< FIRST_PSEUDO_REGISTER
)
660 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
665 /* Return 1 if OP is a GR register operand, or zero. */
668 gr_reg_or_0_operand (rtx op
, enum machine_mode mode
)
670 return (op
== const0_rtx
|| gr_register_operand (op
, mode
));
673 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
676 gr_reg_or_5bit_operand (rtx op
, enum machine_mode mode
)
678 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0 && INTVAL (op
) < 32)
679 || GET_CODE (op
) == CONSTANT_P_RTX
680 || gr_register_operand (op
, mode
));
683 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
686 gr_reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
688 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
689 || GET_CODE (op
) == CONSTANT_P_RTX
690 || gr_register_operand (op
, mode
));
693 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
696 gr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
698 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
699 || GET_CODE (op
) == CONSTANT_P_RTX
700 || gr_register_operand (op
, mode
));
703 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
706 grfr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
708 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
709 || GET_CODE (op
) == CONSTANT_P_RTX
710 || grfr_register_operand (op
, mode
));
713 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
717 gr_reg_or_8bit_adjusted_operand (rtx op
, enum machine_mode mode
)
719 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
720 || GET_CODE (op
) == CONSTANT_P_RTX
721 || gr_register_operand (op
, mode
));
724 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
725 immediate and an 8 bit adjusted immediate operand. This is necessary
726 because when we emit a compare, we don't know what the condition will be,
727 so we need the union of the immediates accepted by GT and LT. */
730 gr_reg_or_8bit_and_adjusted_operand (rtx op
, enum machine_mode mode
)
732 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
))
733 && CONST_OK_FOR_L (INTVAL (op
)))
734 || GET_CODE (op
) == CONSTANT_P_RTX
735 || gr_register_operand (op
, mode
));
738 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
741 gr_reg_or_14bit_operand (rtx op
, enum machine_mode mode
)
743 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
744 || GET_CODE (op
) == CONSTANT_P_RTX
745 || gr_register_operand (op
, mode
));
748 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
751 gr_reg_or_22bit_operand (rtx op
, enum machine_mode mode
)
753 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
754 || GET_CODE (op
) == CONSTANT_P_RTX
755 || gr_register_operand (op
, mode
));
758 /* Return 1 if OP is a 6 bit immediate operand. */
761 shift_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
763 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
764 || GET_CODE (op
) == CONSTANT_P_RTX
);
767 /* Return 1 if OP is a 5 bit immediate operand. */
770 shift_32bit_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
772 return ((GET_CODE (op
) == CONST_INT
773 && (INTVAL (op
) >= 0 && INTVAL (op
) < 32))
774 || GET_CODE (op
) == CONSTANT_P_RTX
);
777 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
780 shladd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
782 return (GET_CODE (op
) == CONST_INT
783 && (INTVAL (op
) == 2 || INTVAL (op
) == 4
784 || INTVAL (op
) == 8 || INTVAL (op
) == 16));
787 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
790 fetchadd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
792 return (GET_CODE (op
) == CONST_INT
793 && (INTVAL (op
) == -16 || INTVAL (op
) == -8 ||
794 INTVAL (op
) == -4 || INTVAL (op
) == -1 ||
795 INTVAL (op
) == 1 || INTVAL (op
) == 4 ||
796 INTVAL (op
) == 8 || INTVAL (op
) == 16));
799 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
802 fr_reg_or_fp01_operand (rtx op
, enum machine_mode mode
)
804 return ((GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (op
))
805 || fr_register_operand (op
, mode
));
808 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
809 POST_MODIFY with a REG as displacement. */
812 destination_operand (rtx op
, enum machine_mode mode
)
814 if (! nonimmediate_operand (op
, mode
))
816 if (GET_CODE (op
) == MEM
817 && GET_CODE (XEXP (op
, 0)) == POST_MODIFY
818 && GET_CODE (XEXP (XEXP (XEXP (op
, 0), 1), 1)) == REG
)
823 /* Like memory_operand, but don't allow post-increments. */
826 not_postinc_memory_operand (rtx op
, enum machine_mode mode
)
828 return (memory_operand (op
, mode
)
829 && GET_RTX_CLASS (GET_CODE (XEXP (op
, 0))) != 'a');
832 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
833 signed immediate operand. */
836 normal_comparison_operator (register rtx op
, enum machine_mode mode
)
838 enum rtx_code code
= GET_CODE (op
);
839 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
840 && (code
== EQ
|| code
== NE
841 || code
== GT
|| code
== LE
|| code
== GTU
|| code
== LEU
));
844 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
845 signed immediate operand. */
848 adjusted_comparison_operator (register rtx op
, enum machine_mode mode
)
850 enum rtx_code code
= GET_CODE (op
);
851 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
852 && (code
== LT
|| code
== GE
|| code
== LTU
|| code
== GEU
));
855 /* Return 1 if this is a signed inequality operator. */
858 signed_inequality_operator (register rtx op
, enum machine_mode mode
)
860 enum rtx_code code
= GET_CODE (op
);
861 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
862 && (code
== GE
|| code
== GT
863 || code
== LE
|| code
== LT
));
866 /* Return 1 if this operator is valid for predication. */
869 predicate_operator (register rtx op
, enum machine_mode mode
)
871 enum rtx_code code
= GET_CODE (op
);
872 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
873 && (code
== EQ
|| code
== NE
));
876 /* Return 1 if this operator can be used in a conditional operation. */
879 condop_operator (register rtx op
, enum machine_mode mode
)
881 enum rtx_code code
= GET_CODE (op
);
882 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
883 && (code
== PLUS
|| code
== MINUS
|| code
== AND
884 || code
== IOR
|| code
== XOR
));
887 /* Return 1 if this is the ar.lc register. */
890 ar_lc_reg_operand (register rtx op
, enum machine_mode mode
)
892 return (GET_MODE (op
) == DImode
893 && (mode
== DImode
|| mode
== VOIDmode
)
894 && GET_CODE (op
) == REG
895 && REGNO (op
) == AR_LC_REGNUM
);
898 /* Return 1 if this is the ar.ccv register. */
901 ar_ccv_reg_operand (register rtx op
, enum machine_mode mode
)
903 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
904 && GET_CODE (op
) == REG
905 && REGNO (op
) == AR_CCV_REGNUM
);
908 /* Return 1 if this is the ar.pfs register. */
911 ar_pfs_reg_operand (register rtx op
, enum machine_mode mode
)
913 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
914 && GET_CODE (op
) == REG
915 && REGNO (op
) == AR_PFS_REGNUM
);
918 /* Like general_operand, but don't allow (mem (addressof)). */
921 general_xfmode_operand (rtx op
, enum machine_mode mode
)
923 if (! general_operand (op
, mode
))
925 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
933 destination_xfmode_operand (rtx op
, enum machine_mode mode
)
935 if (! destination_operand (op
, mode
))
937 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
945 xfreg_or_fp01_operand (rtx op
, enum machine_mode mode
)
947 if (GET_CODE (op
) == SUBREG
)
949 return fr_reg_or_fp01_operand (op
, mode
);
952 /* Return 1 if OP is valid as a base register in a reg + offset address. */
955 basereg_operand (rtx op
, enum machine_mode mode
)
957 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
958 checks from pa.c basereg_operand as well? Seems to be OK without them
961 return (register_operand (op
, mode
) &&
962 REG_POINTER ((GET_CODE (op
) == SUBREG
) ? SUBREG_REG (op
) : op
));
967 ADDR_AREA_NORMAL
, /* normal address area */
968 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
972 static GTY(()) tree small_ident1
;
973 static GTY(()) tree small_ident2
;
978 if (small_ident1
== 0)
980 small_ident1
= get_identifier ("small");
981 small_ident2
= get_identifier ("__small__");
985 /* Retrieve the address area that has been chosen for the given decl. */
987 static ia64_addr_area
988 ia64_get_addr_area (tree decl
)
992 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
998 id
= TREE_VALUE (TREE_VALUE (model_attr
));
999 if (id
== small_ident1
|| id
== small_ident2
)
1000 return ADDR_AREA_SMALL
;
1002 return ADDR_AREA_NORMAL
;
1006 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
, int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1008 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
1009 ia64_addr_area area
;
1010 tree arg
, decl
= *node
;
1013 arg
= TREE_VALUE (args
);
1014 if (arg
== small_ident1
|| arg
== small_ident2
)
1016 addr_area
= ADDR_AREA_SMALL
;
1020 warning ("invalid argument of `%s' attribute",
1021 IDENTIFIER_POINTER (name
));
1022 *no_add_attrs
= true;
1025 switch (TREE_CODE (decl
))
1028 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
1030 && !TREE_STATIC (decl
))
1032 error ("%Jan address area attribute cannot be specified for "
1033 "local variables", decl
, decl
);
1034 *no_add_attrs
= true;
1036 area
= ia64_get_addr_area (decl
);
1037 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
1039 error ("%Jaddress area of '%s' conflicts with previous "
1040 "declaration", decl
, decl
);
1041 *no_add_attrs
= true;
1046 error ("%Jaddress area attribute cannot be specified for functions",
1048 *no_add_attrs
= true;
1052 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1053 *no_add_attrs
= true;
1061 ia64_encode_addr_area (tree decl
, rtx symbol
)
1065 flags
= SYMBOL_REF_FLAGS (symbol
);
1066 switch (ia64_get_addr_area (decl
))
1068 case ADDR_AREA_NORMAL
: break;
1069 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
1072 SYMBOL_REF_FLAGS (symbol
) = flags
;
1076 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
1078 default_encode_section_info (decl
, rtl
, first
);
1080 if (TREE_CODE (decl
) == VAR_DECL
1081 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
1082 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
1085 /* Return 1 if the operands of a move are ok. */
1088 ia64_move_ok (rtx dst
, rtx src
)
1090 /* If we're under init_recog_no_volatile, we'll not be able to use
1091 memory_operand. So check the code directly and don't worry about
1092 the validity of the underlying address, which should have been
1093 checked elsewhere anyway. */
1094 if (GET_CODE (dst
) != MEM
)
1096 if (GET_CODE (src
) == MEM
)
1098 if (register_operand (src
, VOIDmode
))
1101 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1102 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
1103 return src
== const0_rtx
;
1105 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
1109 addp4_optimize_ok (rtx op1
, rtx op2
)
1111 return (basereg_operand (op1
, GET_MODE(op1
)) !=
1112 basereg_operand (op2
, GET_MODE(op2
)));
1115 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1116 Return the length of the field, or <= 0 on failure. */
1119 ia64_depz_field_mask (rtx rop
, rtx rshift
)
1121 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
1122 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
1124 /* Get rid of the zero bits we're shifting in. */
1127 /* We must now have a solid block of 1's at bit 0. */
1128 return exact_log2 (op
+ 1);
1131 /* Expand a symbolic constant load. */
1134 ia64_expand_load_address (rtx dest
, rtx src
)
1136 if (tls_symbolic_operand (src
, VOIDmode
))
1138 if (GET_CODE (dest
) != REG
)
1141 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1142 having to pointer-extend the value afterward. Other forms of address
1143 computation below are also more natural to compute as 64-bit quantities.
1144 If we've been given an SImode destination register, change it. */
1145 if (GET_MODE (dest
) != Pmode
)
1146 dest
= gen_rtx_REG (Pmode
, REGNO (dest
));
1148 if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_ADDR_P (src
))
1150 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
1153 else if (TARGET_AUTO_PIC
)
1155 emit_insn (gen_load_gprel64 (dest
, src
));
1158 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1160 emit_insn (gen_load_fptr (dest
, src
));
1163 else if (sdata_symbolic_operand (src
, VOIDmode
))
1165 emit_insn (gen_load_gprel (dest
, src
));
1169 if (GET_CODE (src
) == CONST
1170 && GET_CODE (XEXP (src
, 0)) == PLUS
1171 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
1172 && (INTVAL (XEXP (XEXP (src
, 0), 1)) & 0x1fff) != 0)
1174 rtx sym
= XEXP (XEXP (src
, 0), 0);
1175 HOST_WIDE_INT ofs
, hi
, lo
;
1177 /* Split the offset into a sign extended 14-bit low part
1178 and a complementary high part. */
1179 ofs
= INTVAL (XEXP (XEXP (src
, 0), 1));
1180 lo
= ((ofs
& 0x3fff) ^ 0x2000) - 0x2000;
1183 ia64_expand_load_address (dest
, plus_constant (sym
, hi
));
1184 emit_insn (gen_adddi3 (dest
, dest
, GEN_INT (lo
)));
1190 tmp
= gen_rtx_HIGH (Pmode
, src
);
1191 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1192 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1194 tmp
= gen_rtx_LO_SUM (GET_MODE (dest
), dest
, src
);
1195 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1199 static GTY(()) rtx gen_tls_tga
;
1201 gen_tls_get_addr (void)
1204 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1208 static GTY(()) rtx thread_pointer_rtx
;
1210 gen_thread_pointer (void)
1212 if (!thread_pointer_rtx
)
1214 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1215 RTX_UNCHANGING_P (thread_pointer_rtx
) = 1;
1217 return thread_pointer_rtx
;
1221 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
)
1223 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1228 case TLS_MODEL_GLOBAL_DYNAMIC
:
1231 tga_op1
= gen_reg_rtx (Pmode
);
1232 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1233 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1234 RTX_UNCHANGING_P (tga_op1
) = 1;
1236 tga_op2
= gen_reg_rtx (Pmode
);
1237 emit_insn (gen_load_ltoff_dtprel (tga_op2
, op1
));
1238 tga_op2
= gen_rtx_MEM (Pmode
, tga_op2
);
1239 RTX_UNCHANGING_P (tga_op2
) = 1;
1241 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1242 LCT_CONST
, Pmode
, 2, tga_op1
,
1243 Pmode
, tga_op2
, Pmode
);
1245 insns
= get_insns ();
1248 if (GET_MODE (op0
) != Pmode
)
1250 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1253 case TLS_MODEL_LOCAL_DYNAMIC
:
1254 /* ??? This isn't the completely proper way to do local-dynamic
1255 If the call to __tls_get_addr is used only by a single symbol,
1256 then we should (somehow) move the dtprel to the second arg
1257 to avoid the extra add. */
1260 tga_op1
= gen_reg_rtx (Pmode
);
1261 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1262 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1263 RTX_UNCHANGING_P (tga_op1
) = 1;
1265 tga_op2
= const0_rtx
;
1267 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1268 LCT_CONST
, Pmode
, 2, tga_op1
,
1269 Pmode
, tga_op2
, Pmode
);
1271 insns
= get_insns ();
1274 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1276 tmp
= gen_reg_rtx (Pmode
);
1277 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1279 if (!register_operand (op0
, Pmode
))
1280 op0
= gen_reg_rtx (Pmode
);
1283 emit_insn (gen_load_dtprel (op0
, op1
));
1284 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1287 emit_insn (gen_add_dtprel (op0
, tmp
, op1
));
1290 case TLS_MODEL_INITIAL_EXEC
:
1291 tmp
= gen_reg_rtx (Pmode
);
1292 emit_insn (gen_load_ltoff_tprel (tmp
, op1
));
1293 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1294 RTX_UNCHANGING_P (tmp
) = 1;
1295 tmp
= force_reg (Pmode
, tmp
);
1297 if (!register_operand (op0
, Pmode
))
1298 op0
= gen_reg_rtx (Pmode
);
1299 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1302 case TLS_MODEL_LOCAL_EXEC
:
1303 if (!register_operand (op0
, Pmode
))
1304 op0
= gen_reg_rtx (Pmode
);
1307 emit_insn (gen_load_tprel (op0
, op1
));
1308 emit_insn (gen_adddi3 (op0
, gen_thread_pointer (), op0
));
1311 emit_insn (gen_add_tprel (op0
, gen_thread_pointer (), op1
));
1318 if (orig_op0
== op0
)
1320 if (GET_MODE (orig_op0
) == Pmode
)
1322 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1326 ia64_expand_move (rtx op0
, rtx op1
)
1328 enum machine_mode mode
= GET_MODE (op0
);
1330 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1331 op1
= force_reg (mode
, op1
);
1333 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1335 enum tls_model tls_kind
;
1336 if ((tls_kind
= tls_symbolic_operand (op1
, VOIDmode
)))
1337 return ia64_expand_tls_address (tls_kind
, op0
, op1
);
1339 if (!TARGET_NO_PIC
&& reload_completed
)
1341 ia64_expand_load_address (op0
, op1
);
1349 /* Split a move from OP1 to OP0 conditional on COND. */
1352 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1354 rtx insn
, first
= get_last_insn ();
1356 emit_move_insn (op0
, op1
);
1358 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1360 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1364 /* Split a post-reload TImode reference into two DImode components. */
1367 ia64_split_timode (rtx out
[2], rtx in
, rtx scratch
)
1369 switch (GET_CODE (in
))
1372 out
[0] = gen_rtx_REG (DImode
, REGNO (in
));
1373 out
[1] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1378 rtx base
= XEXP (in
, 0);
1380 switch (GET_CODE (base
))
1383 out
[0] = adjust_address (in
, DImode
, 0);
1386 base
= XEXP (base
, 0);
1387 out
[0] = adjust_address (in
, DImode
, 0);
1390 /* Since we're changing the mode, we need to change to POST_MODIFY
1391 as well to preserve the size of the increment. Either that or
1392 do the update in two steps, but we've already got this scratch
1393 register handy so let's use it. */
1395 base
= XEXP (base
, 0);
1397 = change_address (in
, DImode
,
1399 (Pmode
, base
, plus_constant (base
, 16)));
1402 base
= XEXP (base
, 0);
1404 = change_address (in
, DImode
,
1406 (Pmode
, base
, plus_constant (base
, -16)));
1412 if (scratch
== NULL_RTX
)
1414 out
[1] = change_address (in
, DImode
, scratch
);
1415 return gen_adddi3 (scratch
, base
, GEN_INT (8));
1420 split_double (in
, &out
[0], &out
[1]);
1428 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1429 through memory plus an extra GR scratch register. Except that you can
1430 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1431 SECONDARY_RELOAD_CLASS, but not both.
1433 We got into problems in the first place by allowing a construct like
1434 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1435 This solution attempts to prevent this situation from occurring. When
1436 we see something like the above, we spill the inner register to memory. */
1439 spill_xfmode_operand (rtx in
, int force
)
1441 if (GET_CODE (in
) == SUBREG
1442 && GET_MODE (SUBREG_REG (in
)) == TImode
1443 && GET_CODE (SUBREG_REG (in
)) == REG
)
1445 rtx mem
= gen_mem_addressof (SUBREG_REG (in
), NULL_TREE
, /*rescan=*/true);
1446 return gen_rtx_MEM (XFmode
, copy_to_reg (XEXP (mem
, 0)));
1448 else if (force
&& GET_CODE (in
) == REG
)
1450 rtx mem
= gen_mem_addressof (in
, NULL_TREE
, /*rescan=*/true);
1451 return gen_rtx_MEM (XFmode
, copy_to_reg (XEXP (mem
, 0)));
1453 else if (GET_CODE (in
) == MEM
1454 && GET_CODE (XEXP (in
, 0)) == ADDRESSOF
)
1455 return change_address (in
, XFmode
, copy_to_reg (XEXP (in
, 0)));
1460 /* Emit comparison instruction if necessary, returning the expression
1461 that holds the compare result in the proper mode. */
1463 static GTY(()) rtx cmptf_libfunc
;
1466 ia64_expand_compare (enum rtx_code code
, enum machine_mode mode
)
1468 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1471 /* If we have a BImode input, then we already have a compare result, and
1472 do not need to emit another comparison. */
1473 if (GET_MODE (op0
) == BImode
)
1475 if ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1480 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1481 magic number as its third argument, that indicates what to do.
1482 The return value is an integer to be compared against zero. */
1483 else if (TARGET_HPUX
&& GET_MODE (op0
) == TFmode
)
1486 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1492 enum rtx_code ncode
;
1494 if (GET_MODE (op1
) != TFmode
)
1498 /* 1 = equal, 0 = not equal. Equality operators do
1499 not raise FP_INVALID when given an SNaN operand. */
1500 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1501 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1502 /* isunordered() from C99. */
1503 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1504 /* Relational operators raise FP_INVALID when given
1506 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1507 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1508 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1509 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1510 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1511 Expanders for buneq etc. weuld have to be added to ia64.md
1512 for this to be useful. */
1518 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1519 op0
, TFmode
, op1
, TFmode
,
1520 GEN_INT (magic
), DImode
);
1521 cmp
= gen_reg_rtx (BImode
);
1522 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1523 gen_rtx_fmt_ee (ncode
, BImode
,
1526 insns
= get_insns ();
1529 emit_libcall_block (insns
, cmp
, cmp
,
1530 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
));
1535 cmp
= gen_reg_rtx (BImode
);
1536 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1537 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1541 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1544 /* Emit the appropriate sequence for a call. */
1547 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
1552 addr
= XEXP (addr
, 0);
1553 addr
= convert_memory_address (DImode
, addr
);
1554 b0
= gen_rtx_REG (DImode
, R_BR (0));
1556 /* ??? Should do this for functions known to bind local too. */
1557 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1560 insn
= gen_sibcall_nogp (addr
);
1562 insn
= gen_call_nogp (addr
, b0
);
1564 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1565 insn
= emit_call_insn (insn
);
1570 insn
= gen_sibcall_gp (addr
);
1572 insn
= gen_call_gp (addr
, b0
);
1574 insn
= gen_call_value_gp (retval
, addr
, b0
);
1575 insn
= emit_call_insn (insn
);
1577 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1581 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1585 ia64_reload_gp (void)
1589 if (current_frame_info
.reg_save_gp
)
1590 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1593 HOST_WIDE_INT offset
;
1595 offset
= (current_frame_info
.spill_cfa_off
1596 + current_frame_info
.spill_size
);
1597 if (frame_pointer_needed
)
1599 tmp
= hard_frame_pointer_rtx
;
1604 tmp
= stack_pointer_rtx
;
1605 offset
= current_frame_info
.total_size
- offset
;
1608 if (CONST_OK_FOR_I (offset
))
1609 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1610 tmp
, GEN_INT (offset
)));
1613 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1614 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1615 pic_offset_table_rtx
, tmp
));
1618 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1621 emit_move_insn (pic_offset_table_rtx
, tmp
);
1625 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
1626 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
1629 bool is_desc
= false;
1631 /* If we find we're calling through a register, then we're actually
1632 calling through a descriptor, so load up the values. */
1633 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
1638 /* ??? We are currently constrained to *not* use peep2, because
1639 we can legitimately change the global lifetime of the GP
1640 (in the form of killing where previously live). This is
1641 because a call through a descriptor doesn't use the previous
1642 value of the GP, while a direct call does, and we do not
1643 commit to either form until the split here.
1645 That said, this means that we lack precise life info for
1646 whether ADDR is dead after this call. This is not terribly
1647 important, since we can fix things up essentially for free
1648 with the POST_DEC below, but it's nice to not use it when we
1649 can immediately tell it's not necessary. */
1650 addr_dead_p
= ((noreturn_p
|| sibcall_p
1651 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1653 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1655 /* Load the code address into scratch_b. */
1656 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1657 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1658 emit_move_insn (scratch_r
, tmp
);
1659 emit_move_insn (scratch_b
, scratch_r
);
1661 /* Load the GP address. If ADDR is not dead here, then we must
1662 revert the change made above via the POST_INCREMENT. */
1664 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1667 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1668 emit_move_insn (pic_offset_table_rtx
, tmp
);
1675 insn
= gen_sibcall_nogp (addr
);
1677 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1679 insn
= gen_call_nogp (addr
, retaddr
);
1680 emit_call_insn (insn
);
1682 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1686 /* Begin the assembly file. */
1689 ia64_file_start (void)
1691 default_file_start ();
1692 emit_safe_across_calls ();
1696 emit_safe_across_calls (void)
1698 unsigned int rs
, re
;
1705 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1709 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1713 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
1717 fputc (',', asm_out_file
);
1719 fprintf (asm_out_file
, "p%u", rs
);
1721 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
1725 fputc ('\n', asm_out_file
);
1728 /* Helper function for ia64_compute_frame_size: find an appropriate general
1729 register to spill some special register to. SPECIAL_SPILL_MASK contains
1730 bits in GR0 to GR31 that have already been allocated by this routine.
1731 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1734 find_gr_spill (int try_locals
)
1738 /* If this is a leaf function, first try an otherwise unused
1739 call-clobbered register. */
1740 if (current_function_is_leaf
)
1742 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1743 if (! regs_ever_live
[regno
]
1744 && call_used_regs
[regno
]
1745 && ! fixed_regs
[regno
]
1746 && ! global_regs
[regno
]
1747 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1749 current_frame_info
.gr_used_mask
|= 1 << regno
;
1756 regno
= current_frame_info
.n_local_regs
;
1757 /* If there is a frame pointer, then we can't use loc79, because
1758 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1759 reg_name switching code in ia64_expand_prologue. */
1760 if (regno
< (80 - frame_pointer_needed
))
1762 current_frame_info
.n_local_regs
= regno
+ 1;
1763 return LOC_REG (0) + regno
;
1767 /* Failed to find a general register to spill to. Must use stack. */
1771 /* In order to make for nice schedules, we try to allocate every temporary
1772 to a different register. We must of course stay away from call-saved,
1773 fixed, and global registers. We must also stay away from registers
1774 allocated in current_frame_info.gr_used_mask, since those include regs
1775 used all through the prologue.
1777 Any register allocated here must be used immediately. The idea is to
1778 aid scheduling, not to solve data flow problems. */
1780 static int last_scratch_gr_reg
;
1783 next_scratch_gr_reg (void)
1787 for (i
= 0; i
< 32; ++i
)
1789 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
1790 if (call_used_regs
[regno
]
1791 && ! fixed_regs
[regno
]
1792 && ! global_regs
[regno
]
1793 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1795 last_scratch_gr_reg
= regno
;
1800 /* There must be _something_ available. */
1804 /* Helper function for ia64_compute_frame_size, called through
1805 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1808 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
1810 unsigned int regno
= REGNO (reg
);
1813 unsigned int i
, n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1814 for (i
= 0; i
< n
; ++i
)
1815 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
1819 /* Returns the number of bytes offset between the frame pointer and the stack
1820 pointer for the current function. SIZE is the number of bytes of space
1821 needed for local variables. */
1824 ia64_compute_frame_size (HOST_WIDE_INT size
)
1826 HOST_WIDE_INT total_size
;
1827 HOST_WIDE_INT spill_size
= 0;
1828 HOST_WIDE_INT extra_spill_size
= 0;
1829 HOST_WIDE_INT pretend_args_size
;
1832 int spilled_gr_p
= 0;
1833 int spilled_fr_p
= 0;
1837 if (current_frame_info
.initialized
)
1840 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
1841 CLEAR_HARD_REG_SET (mask
);
1843 /* Don't allocate scratches to the return register. */
1844 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
1846 /* Don't allocate scratches to the EH scratch registers. */
1847 if (cfun
->machine
->ia64_eh_epilogue_sp
)
1848 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
1849 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
1850 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
1852 /* Find the size of the register stack frame. We have only 80 local
1853 registers, because we reserve 8 for the inputs and 8 for the
1856 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1857 since we'll be adjusting that down later. */
1858 regno
= LOC_REG (78) + ! frame_pointer_needed
;
1859 for (; regno
>= LOC_REG (0); regno
--)
1860 if (regs_ever_live
[regno
])
1862 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
1864 /* For functions marked with the syscall_linkage attribute, we must mark
1865 all eight input registers as in use, so that locals aren't visible to
1868 if (cfun
->machine
->n_varargs
> 0
1869 || lookup_attribute ("syscall_linkage",
1870 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
1871 current_frame_info
.n_input_regs
= 8;
1874 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
1875 if (regs_ever_live
[regno
])
1877 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
1880 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
1881 if (regs_ever_live
[regno
])
1883 i
= regno
- OUT_REG (0) + 1;
1885 /* When -p profiling, we need one output register for the mcount argument.
1886 Likewise for -a profiling for the bb_init_func argument. For -ax
1887 profiling, we need two output registers for the two bb_init_trace_func
1889 if (current_function_profile
)
1891 current_frame_info
.n_output_regs
= i
;
1893 /* ??? No rotating register support yet. */
1894 current_frame_info
.n_rotate_regs
= 0;
1896 /* Discover which registers need spilling, and how much room that
1897 will take. Begin with floating point and general registers,
1898 which will always wind up on the stack. */
1900 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
1901 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1903 SET_HARD_REG_BIT (mask
, regno
);
1909 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1910 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1912 SET_HARD_REG_BIT (mask
, regno
);
1918 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
1919 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
1921 SET_HARD_REG_BIT (mask
, regno
);
1926 /* Now come all special registers that might get saved in other
1927 general registers. */
1929 if (frame_pointer_needed
)
1931 current_frame_info
.reg_fp
= find_gr_spill (1);
1932 /* If we did not get a register, then we take LOC79. This is guaranteed
1933 to be free, even if regs_ever_live is already set, because this is
1934 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1935 as we don't count loc79 above. */
1936 if (current_frame_info
.reg_fp
== 0)
1938 current_frame_info
.reg_fp
= LOC_REG (79);
1939 current_frame_info
.n_local_regs
++;
1943 if (! current_function_is_leaf
)
1945 /* Emit a save of BR0 if we call other functions. Do this even
1946 if this function doesn't return, as EH depends on this to be
1947 able to unwind the stack. */
1948 SET_HARD_REG_BIT (mask
, BR_REG (0));
1950 current_frame_info
.reg_save_b0
= find_gr_spill (1);
1951 if (current_frame_info
.reg_save_b0
== 0)
1957 /* Similarly for ar.pfs. */
1958 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1959 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1960 if (current_frame_info
.reg_save_ar_pfs
== 0)
1962 extra_spill_size
+= 8;
1966 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1967 registers are clobbered, so we fall back to the stack. */
1968 current_frame_info
.reg_save_gp
1969 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
1970 if (current_frame_info
.reg_save_gp
== 0)
1972 SET_HARD_REG_BIT (mask
, GR_REG (1));
1979 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
1981 SET_HARD_REG_BIT (mask
, BR_REG (0));
1986 if (regs_ever_live
[AR_PFS_REGNUM
])
1988 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
1989 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
1990 if (current_frame_info
.reg_save_ar_pfs
== 0)
1992 extra_spill_size
+= 8;
1998 /* Unwind descriptor hackery: things are most efficient if we allocate
1999 consecutive GR save registers for RP, PFS, FP in that order. However,
2000 it is absolutely critical that FP get the only hard register that's
2001 guaranteed to be free, so we allocated it first. If all three did
2002 happen to be allocated hard regs, and are consecutive, rearrange them
2003 into the preferred order now. */
2004 if (current_frame_info
.reg_fp
!= 0
2005 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
2006 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
2008 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
2009 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
2010 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
2013 /* See if we need to store the predicate register block. */
2014 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2015 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2017 if (regno
<= PR_REG (63))
2019 SET_HARD_REG_BIT (mask
, PR_REG (0));
2020 current_frame_info
.reg_save_pr
= find_gr_spill (1);
2021 if (current_frame_info
.reg_save_pr
== 0)
2023 extra_spill_size
+= 8;
2027 /* ??? Mark them all as used so that register renaming and such
2028 are free to use them. */
2029 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2030 regs_ever_live
[regno
] = 1;
2033 /* If we're forced to use st8.spill, we're forced to save and restore
2034 ar.unat as well. The check for existing liveness allows inline asm
2035 to touch ar.unat. */
2036 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2037 || regs_ever_live
[AR_UNAT_REGNUM
])
2039 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
2040 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2041 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
2042 if (current_frame_info
.reg_save_ar_unat
== 0)
2044 extra_spill_size
+= 8;
2049 if (regs_ever_live
[AR_LC_REGNUM
])
2051 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2052 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
2053 if (current_frame_info
.reg_save_ar_lc
== 0)
2055 extra_spill_size
+= 8;
2060 /* If we have an odd number of words of pretend arguments written to
2061 the stack, then the FR save area will be unaligned. We round the
2062 size of this area up to keep things 16 byte aligned. */
2064 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
2066 pretend_args_size
= current_function_pretend_args_size
;
2068 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2069 + current_function_outgoing_args_size
);
2070 total_size
= IA64_STACK_ALIGN (total_size
);
2072 /* We always use the 16-byte scratch area provided by the caller, but
2073 if we are a leaf function, there's no one to which we need to provide
2075 if (current_function_is_leaf
)
2076 total_size
= MAX (0, total_size
- 16);
2078 current_frame_info
.total_size
= total_size
;
2079 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2080 current_frame_info
.spill_size
= spill_size
;
2081 current_frame_info
.extra_spill_size
= extra_spill_size
;
2082 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2083 current_frame_info
.n_spilled
= n_spilled
;
2084 current_frame_info
.initialized
= reload_completed
;
2087 /* Compute the initial difference between the specified pair of registers. */
2090 ia64_initial_elimination_offset (int from
, int to
)
2092 HOST_WIDE_INT offset
;
2094 ia64_compute_frame_size (get_frame_size ());
2097 case FRAME_POINTER_REGNUM
:
2098 if (to
== HARD_FRAME_POINTER_REGNUM
)
2100 if (current_function_is_leaf
)
2101 offset
= -current_frame_info
.total_size
;
2103 offset
= -(current_frame_info
.total_size
2104 - current_function_outgoing_args_size
- 16);
2106 else if (to
== STACK_POINTER_REGNUM
)
2108 if (current_function_is_leaf
)
2111 offset
= 16 + current_function_outgoing_args_size
;
2117 case ARG_POINTER_REGNUM
:
2118 /* Arguments start above the 16 byte save area, unless stdarg
2119 in which case we store through the 16 byte save area. */
2120 if (to
== HARD_FRAME_POINTER_REGNUM
)
2121 offset
= 16 - current_function_pretend_args_size
;
2122 else if (to
== STACK_POINTER_REGNUM
)
2123 offset
= (current_frame_info
.total_size
2124 + 16 - current_function_pretend_args_size
);
2136 /* If there are more than a trivial number of register spills, we use
2137 two interleaved iterators so that we can get two memory references
2140 In order to simplify things in the prologue and epilogue expanders,
2141 we use helper functions to fix up the memory references after the
2142 fact with the appropriate offsets to a POST_MODIFY memory mode.
2143 The following data structure tracks the state of the two iterators
2144 while insns are being emitted. */
2146 struct spill_fill_data
2148 rtx init_after
; /* point at which to emit initializations */
2149 rtx init_reg
[2]; /* initial base register */
2150 rtx iter_reg
[2]; /* the iterator registers */
2151 rtx
*prev_addr
[2]; /* address of last memory use */
2152 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2153 HOST_WIDE_INT prev_off
[2]; /* last offset */
2154 int n_iter
; /* number of iterators in use */
2155 int next_iter
; /* next iterator to use */
2156 unsigned int save_gr_used_mask
;
2159 static struct spill_fill_data spill_fill_data
;
2162 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2166 spill_fill_data
.init_after
= get_last_insn ();
2167 spill_fill_data
.init_reg
[0] = init_reg
;
2168 spill_fill_data
.init_reg
[1] = init_reg
;
2169 spill_fill_data
.prev_addr
[0] = NULL
;
2170 spill_fill_data
.prev_addr
[1] = NULL
;
2171 spill_fill_data
.prev_insn
[0] = NULL
;
2172 spill_fill_data
.prev_insn
[1] = NULL
;
2173 spill_fill_data
.prev_off
[0] = cfa_off
;
2174 spill_fill_data
.prev_off
[1] = cfa_off
;
2175 spill_fill_data
.next_iter
= 0;
2176 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2178 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2179 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2181 int regno
= next_scratch_gr_reg ();
2182 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2183 current_frame_info
.gr_used_mask
|= 1 << regno
;
2188 finish_spill_pointers (void)
2190 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2194 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2196 int iter
= spill_fill_data
.next_iter
;
2197 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2198 rtx disp_rtx
= GEN_INT (disp
);
2201 if (spill_fill_data
.prev_addr
[iter
])
2203 if (CONST_OK_FOR_N (disp
))
2205 *spill_fill_data
.prev_addr
[iter
]
2206 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2207 gen_rtx_PLUS (DImode
,
2208 spill_fill_data
.iter_reg
[iter
],
2210 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2211 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2212 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2216 /* ??? Could use register post_modify for loads. */
2217 if (! CONST_OK_FOR_I (disp
))
2219 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2220 emit_move_insn (tmp
, disp_rtx
);
2223 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2224 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2227 /* Micro-optimization: if we've created a frame pointer, it's at
2228 CFA 0, which may allow the real iterator to be initialized lower,
2229 slightly increasing parallelism. Also, if there are few saves
2230 it may eliminate the iterator entirely. */
2232 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2233 && frame_pointer_needed
)
2235 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2236 set_mem_alias_set (mem
, get_varargs_alias_set ());
2244 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2245 spill_fill_data
.init_reg
[iter
]);
2250 if (! CONST_OK_FOR_I (disp
))
2252 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2253 emit_move_insn (tmp
, disp_rtx
);
2257 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2258 spill_fill_data
.init_reg
[iter
],
2265 /* Careful for being the first insn in a sequence. */
2266 if (spill_fill_data
.init_after
)
2267 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2270 rtx first
= get_insns ();
2272 insn
= emit_insn_before (seq
, first
);
2274 insn
= emit_insn (seq
);
2276 spill_fill_data
.init_after
= insn
;
2278 /* If DISP is 0, we may or may not have a further adjustment
2279 afterward. If we do, then the load/store insn may be modified
2280 to be a post-modify. If we don't, then this copy may be
2281 eliminated by copyprop_hardreg_forward, which makes this
2282 insn garbage, which runs afoul of the sanity check in
2283 propagate_one_insn. So mark this insn as legal to delete. */
2285 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2289 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2291 /* ??? Not all of the spills are for varargs, but some of them are.
2292 The rest of the spills belong in an alias set of their own. But
2293 it doesn't actually hurt to include them here. */
2294 set_mem_alias_set (mem
, get_varargs_alias_set ());
2296 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2297 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2299 if (++iter
>= spill_fill_data
.n_iter
)
2301 spill_fill_data
.next_iter
= iter
;
2307 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
2310 int iter
= spill_fill_data
.next_iter
;
2313 mem
= spill_restore_mem (reg
, cfa_off
);
2314 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2315 spill_fill_data
.prev_insn
[iter
] = insn
;
2322 RTX_FRAME_RELATED_P (insn
) = 1;
2324 /* Don't even pretend that the unwind code can intuit its way
2325 through a pair of interleaved post_modify iterators. Just
2326 provide the correct answer. */
2328 if (frame_pointer_needed
)
2330 base
= hard_frame_pointer_rtx
;
2335 base
= stack_pointer_rtx
;
2336 off
= current_frame_info
.total_size
- cfa_off
;
2340 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2341 gen_rtx_SET (VOIDmode
,
2342 gen_rtx_MEM (GET_MODE (reg
),
2343 plus_constant (base
, off
)),
2350 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
2352 int iter
= spill_fill_data
.next_iter
;
2355 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2356 GEN_INT (cfa_off
)));
2357 spill_fill_data
.prev_insn
[iter
] = insn
;
2360 /* Wrapper functions that discards the CONST_INT spill offset. These
2361 exist so that we can give gr_spill/gr_fill the offset they need and
2362 use a consistent function interface. */
2365 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2367 return gen_movdi (dest
, src
);
2371 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2373 return gen_fr_spill (dest
, src
);
2377 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2379 return gen_fr_restore (dest
, src
);
2382 /* Called after register allocation to add any instructions needed for the
2383 prologue. Using a prologue insn is favored compared to putting all of the
2384 instructions in output_function_prologue(), since it allows the scheduler
2385 to intermix instructions with the saves of the caller saved registers. In
2386 some cases, it might be necessary to emit a barrier instruction as the last
2387 insn to prevent such scheduling.
2389 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2390 so that the debug info generation code can handle them properly.
2392 The register save area is layed out like so:
2394 [ varargs spill area ]
2395 [ fr register spill area ]
2396 [ br register spill area ]
2397 [ ar register spill area ]
2398 [ pr register spill area ]
2399 [ gr register spill area ] */
2401 /* ??? Get inefficient code when the frame size is larger than can fit in an
2402 adds instruction. */
2405 ia64_expand_prologue (void)
2407 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2408 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2411 ia64_compute_frame_size (get_frame_size ());
2412 last_scratch_gr_reg
= 15;
2414 /* If there is no epilogue, then we don't need some prologue insns.
2415 We need to avoid emitting the dead prologue insns, because flow
2416 will complain about them. */
2421 for (e
= EXIT_BLOCK_PTR
->pred
; e
; e
= e
->pred_next
)
2422 if ((e
->flags
& EDGE_FAKE
) == 0
2423 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2425 epilogue_p
= (e
!= NULL
);
2430 /* Set the local, input, and output register names. We need to do this
2431 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2432 half. If we use in/loc/out register names, then we get assembler errors
2433 in crtn.S because there is no alloc insn or regstk directive in there. */
2434 if (! TARGET_REG_NAMES
)
2436 int inputs
= current_frame_info
.n_input_regs
;
2437 int locals
= current_frame_info
.n_local_regs
;
2438 int outputs
= current_frame_info
.n_output_regs
;
2440 for (i
= 0; i
< inputs
; i
++)
2441 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2442 for (i
= 0; i
< locals
; i
++)
2443 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2444 for (i
= 0; i
< outputs
; i
++)
2445 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2448 /* Set the frame pointer register name. The regnum is logically loc79,
2449 but of course we'll not have allocated that many locals. Rather than
2450 worrying about renumbering the existing rtxs, we adjust the name. */
2451 /* ??? This code means that we can never use one local register when
2452 there is a frame pointer. loc79 gets wasted in this case, as it is
2453 renamed to a register that will never be used. See also the try_locals
2454 code in find_gr_spill. */
2455 if (current_frame_info
.reg_fp
)
2457 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2458 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2459 = reg_names
[current_frame_info
.reg_fp
];
2460 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2463 /* We don't need an alloc instruction if we've used no outputs or locals. */
2464 if (current_frame_info
.n_local_regs
== 0
2465 && current_frame_info
.n_output_regs
== 0
2466 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2467 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2469 /* If there is no alloc, but there are input registers used, then we
2470 need a .regstk directive. */
2471 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2472 ar_pfs_save_reg
= NULL_RTX
;
2476 current_frame_info
.need_regstk
= 0;
2478 if (current_frame_info
.reg_save_ar_pfs
)
2479 regno
= current_frame_info
.reg_save_ar_pfs
;
2481 regno
= next_scratch_gr_reg ();
2482 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2484 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2485 GEN_INT (current_frame_info
.n_input_regs
),
2486 GEN_INT (current_frame_info
.n_local_regs
),
2487 GEN_INT (current_frame_info
.n_output_regs
),
2488 GEN_INT (current_frame_info
.n_rotate_regs
)));
2489 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2492 /* Set up frame pointer, stack pointer, and spill iterators. */
2494 n_varargs
= cfun
->machine
->n_varargs
;
2495 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2496 stack_pointer_rtx
, 0);
2498 if (frame_pointer_needed
)
2500 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2501 RTX_FRAME_RELATED_P (insn
) = 1;
2504 if (current_frame_info
.total_size
!= 0)
2506 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2509 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2510 offset
= frame_size_rtx
;
2513 regno
= next_scratch_gr_reg ();
2514 offset
= gen_rtx_REG (DImode
, regno
);
2515 emit_move_insn (offset
, frame_size_rtx
);
2518 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2519 stack_pointer_rtx
, offset
));
2521 if (! frame_pointer_needed
)
2523 RTX_FRAME_RELATED_P (insn
) = 1;
2524 if (GET_CODE (offset
) != CONST_INT
)
2527 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2528 gen_rtx_SET (VOIDmode
,
2530 gen_rtx_PLUS (DImode
,
2537 /* ??? At this point we must generate a magic insn that appears to
2538 modify the stack pointer, the frame pointer, and all spill
2539 iterators. This would allow the most scheduling freedom. For
2540 now, just hard stop. */
2541 emit_insn (gen_blockage ());
2544 /* Must copy out ar.unat before doing any integer spills. */
2545 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2547 if (current_frame_info
.reg_save_ar_unat
)
2549 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2552 alt_regno
= next_scratch_gr_reg ();
2553 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2554 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2557 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2558 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2559 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2561 /* Even if we're not going to generate an epilogue, we still
2562 need to save the register so that EH works. */
2563 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2564 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2567 ar_unat_save_reg
= NULL_RTX
;
2569 /* Spill all varargs registers. Do this before spilling any GR registers,
2570 since we want the UNAT bits for the GR registers to override the UNAT
2571 bits from varargs, which we don't care about. */
2574 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2576 reg
= gen_rtx_REG (DImode
, regno
);
2577 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2580 /* Locate the bottom of the register save area. */
2581 cfa_off
= (current_frame_info
.spill_cfa_off
2582 + current_frame_info
.spill_size
2583 + current_frame_info
.extra_spill_size
);
2585 /* Save the predicate register block either in a register or in memory. */
2586 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2588 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2589 if (current_frame_info
.reg_save_pr
!= 0)
2591 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2592 insn
= emit_move_insn (alt_reg
, reg
);
2594 /* ??? Denote pr spill/fill by a DImode move that modifies all
2595 64 hard registers. */
2596 RTX_FRAME_RELATED_P (insn
) = 1;
2598 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2599 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2602 /* Even if we're not going to generate an epilogue, we still
2603 need to save the register so that EH works. */
2605 emit_insn (gen_prologue_use (alt_reg
));
2609 alt_regno
= next_scratch_gr_reg ();
2610 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2611 insn
= emit_move_insn (alt_reg
, reg
);
2612 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2617 /* Handle AR regs in numerical order. All of them get special handling. */
2618 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2619 && current_frame_info
.reg_save_ar_unat
== 0)
2621 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2622 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2626 /* The alloc insn already copied ar.pfs into a general register. The
2627 only thing we have to do now is copy that register to a stack slot
2628 if we'd not allocated a local register for the job. */
2629 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2630 && current_frame_info
.reg_save_ar_pfs
== 0)
2632 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2633 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2637 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2639 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2640 if (current_frame_info
.reg_save_ar_lc
!= 0)
2642 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2643 insn
= emit_move_insn (alt_reg
, reg
);
2644 RTX_FRAME_RELATED_P (insn
) = 1;
2646 /* Even if we're not going to generate an epilogue, we still
2647 need to save the register so that EH works. */
2649 emit_insn (gen_prologue_use (alt_reg
));
2653 alt_regno
= next_scratch_gr_reg ();
2654 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2655 emit_move_insn (alt_reg
, reg
);
2656 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2661 if (current_frame_info
.reg_save_gp
)
2663 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2664 current_frame_info
.reg_save_gp
),
2665 pic_offset_table_rtx
);
2666 /* We don't know for sure yet if this is actually needed, since
2667 we've not split the PIC call patterns. If all of the calls
2668 are indirect, and not followed by any uses of the gp, then
2669 this save is dead. Allow it to go away. */
2671 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2674 /* We should now be at the base of the gr/br/fr spill area. */
2675 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2676 + current_frame_info
.spill_size
))
2679 /* Spill all general registers. */
2680 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2681 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2683 reg
= gen_rtx_REG (DImode
, regno
);
2684 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2688 /* Handle BR0 specially -- it may be getting stored permanently in
2689 some GR register. */
2690 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2692 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2693 if (current_frame_info
.reg_save_b0
!= 0)
2695 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2696 insn
= emit_move_insn (alt_reg
, reg
);
2697 RTX_FRAME_RELATED_P (insn
) = 1;
2699 /* Even if we're not going to generate an epilogue, we still
2700 need to save the register so that EH works. */
2702 emit_insn (gen_prologue_use (alt_reg
));
2706 alt_regno
= next_scratch_gr_reg ();
2707 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2708 emit_move_insn (alt_reg
, reg
);
2709 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2714 /* Spill the rest of the BR registers. */
2715 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2716 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2718 alt_regno
= next_scratch_gr_reg ();
2719 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2720 reg
= gen_rtx_REG (DImode
, regno
);
2721 emit_move_insn (alt_reg
, reg
);
2722 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2726 /* Align the frame and spill all FR registers. */
2727 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2728 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2732 reg
= gen_rtx_REG (XFmode
, regno
);
2733 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2737 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2740 finish_spill_pointers ();
2743 /* Called after register allocation to add any instructions needed for the
2744 epilogue. Using an epilogue insn is favored compared to putting all of the
2745 instructions in output_function_prologue(), since it allows the scheduler
2746 to intermix instructions with the saves of the caller saved registers. In
2747 some cases, it might be necessary to emit a barrier instruction as the last
2748 insn to prevent such scheduling. */
2751 ia64_expand_epilogue (int sibcall_p
)
2753 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2754 int regno
, alt_regno
, cfa_off
;
2756 ia64_compute_frame_size (get_frame_size ());
2758 /* If there is a frame pointer, then we use it instead of the stack
2759 pointer, so that the stack pointer does not need to be valid when
2760 the epilogue starts. See EXIT_IGNORE_STACK. */
2761 if (frame_pointer_needed
)
2762 setup_spill_pointers (current_frame_info
.n_spilled
,
2763 hard_frame_pointer_rtx
, 0);
2765 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2766 current_frame_info
.total_size
);
2768 if (current_frame_info
.total_size
!= 0)
2770 /* ??? At this point we must generate a magic insn that appears to
2771 modify the spill iterators and the frame pointer. This would
2772 allow the most scheduling freedom. For now, just hard stop. */
2773 emit_insn (gen_blockage ());
2776 /* Locate the bottom of the register save area. */
2777 cfa_off
= (current_frame_info
.spill_cfa_off
2778 + current_frame_info
.spill_size
2779 + current_frame_info
.extra_spill_size
);
2781 /* Restore the predicate registers. */
2782 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2784 if (current_frame_info
.reg_save_pr
!= 0)
2785 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2788 alt_regno
= next_scratch_gr_reg ();
2789 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2790 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2793 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2794 emit_move_insn (reg
, alt_reg
);
2797 /* Restore the application registers. */
2799 /* Load the saved unat from the stack, but do not restore it until
2800 after the GRs have been restored. */
2801 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2803 if (current_frame_info
.reg_save_ar_unat
!= 0)
2805 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2808 alt_regno
= next_scratch_gr_reg ();
2809 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2810 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2811 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
2816 ar_unat_save_reg
= NULL_RTX
;
2818 if (current_frame_info
.reg_save_ar_pfs
!= 0)
2820 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
2821 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2822 emit_move_insn (reg
, alt_reg
);
2824 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2826 alt_regno
= next_scratch_gr_reg ();
2827 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2828 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2830 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2831 emit_move_insn (reg
, alt_reg
);
2834 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2836 if (current_frame_info
.reg_save_ar_lc
!= 0)
2837 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2840 alt_regno
= next_scratch_gr_reg ();
2841 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2842 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2845 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2846 emit_move_insn (reg
, alt_reg
);
2849 /* We should now be at the base of the gr/br/fr spill area. */
2850 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2851 + current_frame_info
.spill_size
))
2854 /* The GP may be stored on the stack in the prologue, but it's
2855 never restored in the epilogue. Skip the stack slot. */
2856 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
2859 /* Restore all general registers. */
2860 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
2861 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2863 reg
= gen_rtx_REG (DImode
, regno
);
2864 do_restore (gen_gr_restore
, reg
, cfa_off
);
2868 /* Restore the branch registers. Handle B0 specially, as it may
2869 have gotten stored in some GR register. */
2870 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2872 if (current_frame_info
.reg_save_b0
!= 0)
2873 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2876 alt_regno
= next_scratch_gr_reg ();
2877 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2878 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2881 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2882 emit_move_insn (reg
, alt_reg
);
2885 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2886 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2888 alt_regno
= next_scratch_gr_reg ();
2889 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2890 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2892 reg
= gen_rtx_REG (DImode
, regno
);
2893 emit_move_insn (reg
, alt_reg
);
2896 /* Restore floating point registers. */
2897 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2898 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2902 reg
= gen_rtx_REG (XFmode
, regno
);
2903 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
2907 /* Restore ar.unat for real. */
2908 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2910 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2911 emit_move_insn (reg
, ar_unat_save_reg
);
2914 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2917 finish_spill_pointers ();
2919 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
2921 /* ??? At this point we must generate a magic insn that appears to
2922 modify the spill iterators, the stack pointer, and the frame
2923 pointer. This would allow the most scheduling freedom. For now,
2925 emit_insn (gen_blockage ());
2928 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2929 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
2930 else if (frame_pointer_needed
)
2932 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
2933 RTX_FRAME_RELATED_P (insn
) = 1;
2935 else if (current_frame_info
.total_size
)
2937 rtx offset
, frame_size_rtx
;
2939 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
2940 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
2941 offset
= frame_size_rtx
;
2944 regno
= next_scratch_gr_reg ();
2945 offset
= gen_rtx_REG (DImode
, regno
);
2946 emit_move_insn (offset
, frame_size_rtx
);
2949 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
2952 RTX_FRAME_RELATED_P (insn
) = 1;
2953 if (GET_CODE (offset
) != CONST_INT
)
2956 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2957 gen_rtx_SET (VOIDmode
,
2959 gen_rtx_PLUS (DImode
,
2966 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2967 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
2970 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
2973 int fp
= GR_REG (2);
2974 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2975 first available call clobbered register. If there was a frame_pointer
2976 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2977 so we have to make sure we're using the string "r2" when emitting
2978 the register name for the assembler. */
2979 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
2980 fp
= HARD_FRAME_POINTER_REGNUM
;
2982 /* We must emit an alloc to force the input registers to become output
2983 registers. Otherwise, if the callee tries to pass its parameters
2984 through to another call without an intervening alloc, then these
2986 /* ??? We don't need to preserve all input registers. We only need to
2987 preserve those input registers used as arguments to the sibling call.
2988 It is unclear how to compute that number here. */
2989 if (current_frame_info
.n_input_regs
!= 0)
2990 emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
2991 GEN_INT (0), GEN_INT (0),
2992 GEN_INT (current_frame_info
.n_input_regs
),
2997 /* Return 1 if br.ret can do all the work required to return from a
3001 ia64_direct_return (void)
3003 if (reload_completed
&& ! frame_pointer_needed
)
3005 ia64_compute_frame_size (get_frame_size ());
3007 return (current_frame_info
.total_size
== 0
3008 && current_frame_info
.n_spilled
== 0
3009 && current_frame_info
.reg_save_b0
== 0
3010 && current_frame_info
.reg_save_pr
== 0
3011 && current_frame_info
.reg_save_ar_pfs
== 0
3012 && current_frame_info
.reg_save_ar_unat
== 0
3013 && current_frame_info
.reg_save_ar_lc
== 0);
3018 /* Return the magic cookie that we use to hold the return address
3019 during early compilation. */
3022 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3026 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3029 /* Split this value after reload, now that we know where the return
3030 address is saved. */
3033 ia64_split_return_addr_rtx (rtx dest
)
3037 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3039 if (current_frame_info
.reg_save_b0
!= 0)
3040 src
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3046 /* Compute offset from CFA for BR0. */
3047 /* ??? Must be kept in sync with ia64_expand_prologue. */
3048 off
= (current_frame_info
.spill_cfa_off
3049 + current_frame_info
.spill_size
);
3050 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3051 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3054 /* Convert CFA offset to a register based offset. */
3055 if (frame_pointer_needed
)
3056 src
= hard_frame_pointer_rtx
;
3059 src
= stack_pointer_rtx
;
3060 off
+= current_frame_info
.total_size
;
3063 /* Load address into scratch register. */
3064 if (CONST_OK_FOR_I (off
))
3065 emit_insn (gen_adddi3 (dest
, src
, GEN_INT (off
)));
3068 emit_move_insn (dest
, GEN_INT (off
));
3069 emit_insn (gen_adddi3 (dest
, src
, dest
));
3072 src
= gen_rtx_MEM (Pmode
, dest
);
3076 src
= gen_rtx_REG (DImode
, BR_REG (0));
3078 emit_move_insn (dest
, src
);
3082 ia64_hard_regno_rename_ok (int from
, int to
)
3084 /* Don't clobber any of the registers we reserved for the prologue. */
3085 if (to
== current_frame_info
.reg_fp
3086 || to
== current_frame_info
.reg_save_b0
3087 || to
== current_frame_info
.reg_save_pr
3088 || to
== current_frame_info
.reg_save_ar_pfs
3089 || to
== current_frame_info
.reg_save_ar_unat
3090 || to
== current_frame_info
.reg_save_ar_lc
)
3093 if (from
== current_frame_info
.reg_fp
3094 || from
== current_frame_info
.reg_save_b0
3095 || from
== current_frame_info
.reg_save_pr
3096 || from
== current_frame_info
.reg_save_ar_pfs
3097 || from
== current_frame_info
.reg_save_ar_unat
3098 || from
== current_frame_info
.reg_save_ar_lc
)
3101 /* Don't use output registers outside the register frame. */
3102 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3105 /* Retain even/oddness on predicate register pairs. */
3106 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3107 return (from
& 1) == (to
& 1);
3112 /* Target hook for assembling integer objects. Handle word-sized
3113 aligned objects and detect the cases when @fptr is needed. */
3116 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3118 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3120 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3121 && GET_CODE (x
) == SYMBOL_REF
3122 && SYMBOL_REF_FUNCTION_P (x
))
3124 if (POINTER_SIZE
== 32)
3125 fputs ("\tdata4\t@fptr(", asm_out_file
);
3127 fputs ("\tdata8\t@fptr(", asm_out_file
);
3128 output_addr_const (asm_out_file
, x
);
3129 fputs (")\n", asm_out_file
);
3132 return default_assemble_integer (x
, size
, aligned_p
);
3135 /* Emit the function prologue. */
3138 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3140 int mask
, grsave
, grsave_prev
;
3142 if (current_frame_info
.need_regstk
)
3143 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3144 current_frame_info
.n_input_regs
,
3145 current_frame_info
.n_local_regs
,
3146 current_frame_info
.n_output_regs
,
3147 current_frame_info
.n_rotate_regs
);
3149 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3152 /* Emit the .prologue directive. */
3155 grsave
= grsave_prev
= 0;
3156 if (current_frame_info
.reg_save_b0
!= 0)
3159 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3161 if (current_frame_info
.reg_save_ar_pfs
!= 0
3162 && (grsave_prev
== 0
3163 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3166 if (grsave_prev
== 0)
3167 grsave
= current_frame_info
.reg_save_ar_pfs
;
3168 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3170 if (current_frame_info
.reg_fp
!= 0
3171 && (grsave_prev
== 0
3172 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3175 if (grsave_prev
== 0)
3176 grsave
= HARD_FRAME_POINTER_REGNUM
;
3177 grsave_prev
= current_frame_info
.reg_fp
;
3179 if (current_frame_info
.reg_save_pr
!= 0
3180 && (grsave_prev
== 0
3181 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3184 if (grsave_prev
== 0)
3185 grsave
= current_frame_info
.reg_save_pr
;
3188 if (mask
&& TARGET_GNU_AS
)
3189 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3190 ia64_dbx_register_number (grsave
));
3192 fputs ("\t.prologue\n", file
);
3194 /* Emit a .spill directive, if necessary, to relocate the base of
3195 the register spill area. */
3196 if (current_frame_info
.spill_cfa_off
!= -16)
3197 fprintf (file
, "\t.spill %ld\n",
3198 (long) (current_frame_info
.spill_cfa_off
3199 + current_frame_info
.spill_size
));
3202 /* Emit the .body directive at the scheduled end of the prologue. */
3205 ia64_output_function_end_prologue (FILE *file
)
3207 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3210 fputs ("\t.body\n", file
);
3213 /* Emit the function epilogue. */
3216 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3217 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3221 if (current_frame_info
.reg_fp
)
3223 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3224 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3225 = reg_names
[current_frame_info
.reg_fp
];
3226 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3228 if (! TARGET_REG_NAMES
)
3230 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3231 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3232 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3233 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3234 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3235 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3238 current_frame_info
.initialized
= 0;
3242 ia64_dbx_register_number (int regno
)
3244 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3245 from its home at loc79 to something inside the register frame. We
3246 must perform the same renumbering here for the debug info. */
3247 if (current_frame_info
.reg_fp
)
3249 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3250 regno
= current_frame_info
.reg_fp
;
3251 else if (regno
== current_frame_info
.reg_fp
)
3252 regno
= HARD_FRAME_POINTER_REGNUM
;
3255 if (IN_REGNO_P (regno
))
3256 return 32 + regno
- IN_REG (0);
3257 else if (LOC_REGNO_P (regno
))
3258 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3259 else if (OUT_REGNO_P (regno
))
3260 return (32 + current_frame_info
.n_input_regs
3261 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3267 ia64_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
3269 rtx addr_reg
, eight
= GEN_INT (8);
3271 /* The Intel assembler requires that the global __ia64_trampoline symbol
3272 be declared explicitly */
3275 static bool declared_ia64_trampoline
= false;
3277 if (!declared_ia64_trampoline
)
3279 declared_ia64_trampoline
= true;
3280 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
3281 "__ia64_trampoline");
3285 /* Load up our iterator. */
3286 addr_reg
= gen_reg_rtx (Pmode
);
3287 emit_move_insn (addr_reg
, addr
);
3289 /* The first two words are the fake descriptor:
3290 __ia64_trampoline, ADDR+16. */
3291 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3292 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3293 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3295 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3296 copy_to_reg (plus_constant (addr
, 16)));
3297 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3299 /* The third word is the target descriptor. */
3300 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3301 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3303 /* The fourth word is the static chain. */
3304 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3307 /* Do any needed setup for a variadic function. CUM has not been updated
3308 for the last named argument which has type TYPE and mode MODE.
3310 We generate the actual spill instructions during prologue generation. */
3313 ia64_setup_incoming_varargs (CUMULATIVE_ARGS cum
, int int_mode
, tree type
,
3315 int second_time ATTRIBUTE_UNUSED
)
3317 /* Skip the current argument. */
3318 ia64_function_arg_advance (&cum
, int_mode
, type
, 1);
3320 if (cum
.words
< MAX_ARGUMENT_SLOTS
)
3322 int n
= MAX_ARGUMENT_SLOTS
- cum
.words
;
3323 *pretend_size
= n
* UNITS_PER_WORD
;
3324 cfun
->machine
->n_varargs
= n
;
3328 /* Check whether TYPE is a homogeneous floating point aggregate. If
3329 it is, return the mode of the floating point type that appears
3330 in all leafs. If it is not, return VOIDmode.
3332 An aggregate is a homogeneous floating point aggregate is if all
3333 fields/elements in it have the same floating point type (e.g,
3334 SFmode). 128-bit quad-precision floats are excluded. */
3336 static enum machine_mode
3337 hfa_element_mode (tree type
, int nested
)
3339 enum machine_mode element_mode
= VOIDmode
;
3340 enum machine_mode mode
;
3341 enum tree_code code
= TREE_CODE (type
);
3342 int know_element_mode
= 0;
3347 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3348 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3349 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3350 case FILE_TYPE
: case SET_TYPE
: case LANG_TYPE
:
3354 /* Fortran complex types are supposed to be HFAs, so we need to handle
3355 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3358 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3359 && TYPE_MODE (type
) != TCmode
)
3360 return GET_MODE_INNER (TYPE_MODE (type
));
3365 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3366 mode if this is contained within an aggregate. */
3367 if (nested
&& TYPE_MODE (type
) != TFmode
)
3368 return TYPE_MODE (type
);
3373 return hfa_element_mode (TREE_TYPE (type
), 1);
3377 case QUAL_UNION_TYPE
:
3378 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3380 if (TREE_CODE (t
) != FIELD_DECL
)
3383 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3384 if (know_element_mode
)
3386 if (mode
!= element_mode
)
3389 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3393 know_element_mode
= 1;
3394 element_mode
= mode
;
3397 return element_mode
;
3400 /* If we reach here, we probably have some front-end specific type
3401 that the backend doesn't know about. This can happen via the
3402 aggregate_value_p call in init_function_start. All we can do is
3403 ignore unknown tree types. */
3410 /* Return rtx for register where argument is passed, or zero if it is passed
3413 /* ??? 128-bit quad-precision floats are always passed in general
3417 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
3418 int named
, int incoming
)
3420 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3421 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3422 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3425 enum machine_mode hfa_mode
= VOIDmode
;
3427 /* Integer and float arguments larger than 8 bytes start at the next even
3428 boundary. Aggregates larger than 8 bytes start at the next even boundary
3429 if the aggregate has 16 byte alignment. Net effect is that types with
3430 alignment greater than 8 start at the next even boundary. */
3431 /* ??? The ABI does not specify how to handle aggregates with alignment from
3432 9 to 15 bytes, or greater than 16. We handle them all as if they had
3433 16 byte alignment. Such aggregates can occur only if gcc extensions are
3435 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3437 && (cum
->words
& 1))
3440 /* If all argument slots are used, then it must go on the stack. */
3441 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3444 /* Check for and handle homogeneous FP aggregates. */
3446 hfa_mode
= hfa_element_mode (type
, 0);
3448 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3449 and unprototyped hfas are passed specially. */
3450 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3454 int fp_regs
= cum
->fp_regs
;
3455 int int_regs
= cum
->words
+ offset
;
3456 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3460 /* If prototyped, pass it in FR regs then GR regs.
3461 If not prototyped, pass it in both FR and GR regs.
3463 If this is an SFmode aggregate, then it is possible to run out of
3464 FR regs while GR regs are still left. In that case, we pass the
3465 remaining part in the GR regs. */
3467 /* Fill the FP regs. We do this always. We stop if we reach the end
3468 of the argument, the last FP register, or the last argument slot. */
3470 byte_size
= ((mode
== BLKmode
)
3471 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3472 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3474 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3475 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3477 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3478 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3482 args_byte_size
+= hfa_size
;
3486 /* If no prototype, then the whole thing must go in GR regs. */
3487 if (! cum
->prototype
)
3489 /* If this is an SFmode aggregate, then we might have some left over
3490 that needs to go in GR regs. */
3491 else if (byte_size
!= offset
)
3492 int_regs
+= offset
/ UNITS_PER_WORD
;
3494 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3496 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3498 enum machine_mode gr_mode
= DImode
;
3500 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3501 then this goes in a GR reg left adjusted/little endian, right
3502 adjusted/big endian. */
3503 /* ??? Currently this is handled wrong, because 4-byte hunks are
3504 always right adjusted/little endian. */
3507 /* If we have an even 4 byte hunk because the aggregate is a
3508 multiple of 4 bytes in size, then this goes in a GR reg right
3509 adjusted/little endian. */
3510 else if (byte_size
- offset
== 4)
3512 /* Complex floats need to have float mode. */
3513 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3516 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3517 gen_rtx_REG (gr_mode
, (basereg
3520 offset
+= GET_MODE_SIZE (gr_mode
);
3521 int_regs
+= GET_MODE_SIZE (gr_mode
) <= UNITS_PER_WORD
3522 ? 1 : GET_MODE_SIZE (gr_mode
) / UNITS_PER_WORD
;
3525 /* If we ended up using just one location, just return that one loc, but
3526 change the mode back to the argument mode. */
3528 return gen_rtx_REG (mode
, REGNO (XEXP (loc
[0], 0)));
3530 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3533 /* Integral and aggregates go in general registers. If we have run out of
3534 FR registers, then FP values must also go in general registers. This can
3535 happen when we have a SFmode HFA. */
3536 else if (mode
== TFmode
|| mode
== TCmode
3537 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3539 int byte_size
= ((mode
== BLKmode
)
3540 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3541 if (BYTES_BIG_ENDIAN
3542 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3543 && byte_size
< UNITS_PER_WORD
3546 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3547 gen_rtx_REG (DImode
,
3548 (basereg
+ cum
->words
3551 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3554 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3558 /* If there is a prototype, then FP values go in a FR register when
3559 named, and in a GR register when unnamed. */
3560 else if (cum
->prototype
)
3563 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3565 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3567 /* If there is no prototype, then FP values go in both FR and GR
3571 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3572 gen_rtx_REG (mode
, (FR_ARG_FIRST
3575 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3577 (basereg
+ cum
->words
3581 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3585 /* Return number of words, at the beginning of the argument, that must be
3586 put in registers. 0 is the argument is entirely in registers or entirely
3590 ia64_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3591 tree type
, int named ATTRIBUTE_UNUSED
)
3593 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3594 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3598 /* Arguments with alignment larger than 8 bytes start at the next even
3600 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3602 && (cum
->words
& 1))
3605 /* If all argument slots are used, then it must go on the stack. */
3606 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3609 /* It doesn't matter whether the argument goes in FR or GR regs. If
3610 it fits within the 8 argument slots, then it goes entirely in
3611 registers. If it extends past the last argument slot, then the rest
3612 goes on the stack. */
3614 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3617 return MAX_ARGUMENT_SLOTS
- cum
->words
- offset
;
3620 /* Update CUM to point after this argument. This is patterned after
3621 ia64_function_arg. */
3624 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3625 tree type
, int named
)
3627 int words
= (((mode
== BLKmode
? int_size_in_bytes (type
)
3628 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
3631 enum machine_mode hfa_mode
= VOIDmode
;
3633 /* If all arg slots are already full, then there is nothing to do. */
3634 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3637 /* Arguments with alignment larger than 8 bytes start at the next even
3639 if ((type
? (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3641 && (cum
->words
& 1))
3644 cum
->words
+= words
+ offset
;
3646 /* Check for and handle homogeneous FP aggregates. */
3648 hfa_mode
= hfa_element_mode (type
, 0);
3650 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3651 and unprototyped hfas are passed specially. */
3652 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3654 int fp_regs
= cum
->fp_regs
;
3655 /* This is the original value of cum->words + offset. */
3656 int int_regs
= cum
->words
- words
;
3657 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3661 /* If prototyped, pass it in FR regs then GR regs.
3662 If not prototyped, pass it in both FR and GR regs.
3664 If this is an SFmode aggregate, then it is possible to run out of
3665 FR regs while GR regs are still left. In that case, we pass the
3666 remaining part in the GR regs. */
3668 /* Fill the FP regs. We do this always. We stop if we reach the end
3669 of the argument, the last FP register, or the last argument slot. */
3671 byte_size
= ((mode
== BLKmode
)
3672 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3673 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3675 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3676 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3679 args_byte_size
+= hfa_size
;
3683 cum
->fp_regs
= fp_regs
;
3686 /* Integral and aggregates go in general registers. If we have run out of
3687 FR registers, then FP values must also go in general registers. This can
3688 happen when we have a SFmode HFA. */
3689 else if (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
)
3690 cum
->int_regs
= cum
->words
;
3692 /* If there is a prototype, then FP values go in a FR register when
3693 named, and in a GR register when unnamed. */
3694 else if (cum
->prototype
)
3697 cum
->int_regs
= cum
->words
;
3699 /* ??? Complex types should not reach here. */
3700 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3702 /* If there is no prototype, then FP values go in both FR and GR
3706 /* ??? Complex types should not reach here. */
3707 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3708 cum
->int_regs
= cum
->words
;
3712 /* Variable sized types are passed by reference. */
3713 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3716 ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3717 enum machine_mode mode ATTRIBUTE_UNUSED
,
3718 tree type
, int named ATTRIBUTE_UNUSED
)
3720 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
3723 /* True if it is OK to do sibling call optimization for the specified
3724 call expression EXP. DECL will be the called function, or NULL if
3725 this is an indirect call. */
3727 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3729 /* We must always return with our current GP. This means we can
3730 only sibcall to functions defined in the current module. */
3731 return decl
&& (*targetm
.binds_local_p
) (decl
);
3735 /* Implement va_arg. */
3738 ia64_va_arg (tree valist
, tree type
)
3742 /* Variable sized types are passed by reference. */
3743 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
3745 rtx addr
= std_expand_builtin_va_arg (valist
, build_pointer_type (type
));
3746 return gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, addr
));
3749 /* Arguments with alignment larger than 8 bytes start at the next even
3751 if (TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3753 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
3754 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
3755 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3756 build_int_2 (-2 * UNITS_PER_WORD
, -1));
3757 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
3758 TREE_SIDE_EFFECTS (t
) = 1;
3759 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
3762 return std_expand_builtin_va_arg (valist
, type
);
3765 /* Return 1 if function return value returned in memory. Return 0 if it is
3769 ia64_return_in_memory (tree valtype
)
3771 enum machine_mode mode
;
3772 enum machine_mode hfa_mode
;
3773 HOST_WIDE_INT byte_size
;
3775 mode
= TYPE_MODE (valtype
);
3776 byte_size
= GET_MODE_SIZE (mode
);
3777 if (mode
== BLKmode
)
3779 byte_size
= int_size_in_bytes (valtype
);
3784 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3786 hfa_mode
= hfa_element_mode (valtype
, 0);
3787 if (hfa_mode
!= VOIDmode
)
3789 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3791 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
3796 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
3802 /* Return rtx for register that holds the function return value. */
3805 ia64_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
3807 enum machine_mode mode
;
3808 enum machine_mode hfa_mode
;
3810 mode
= TYPE_MODE (valtype
);
3811 hfa_mode
= hfa_element_mode (valtype
, 0);
3813 if (hfa_mode
!= VOIDmode
)
3821 hfa_size
= GET_MODE_SIZE (hfa_mode
);
3822 byte_size
= ((mode
== BLKmode
)
3823 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
3825 for (i
= 0; offset
< byte_size
; i
++)
3827 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3828 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
3834 return XEXP (loc
[0], 0);
3836 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3838 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
)
3839 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
3842 if (BYTES_BIG_ENDIAN
3843 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
3851 bytesize
= int_size_in_bytes (valtype
);
3852 for (i
= 0; offset
< bytesize
; i
++)
3854 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3855 gen_rtx_REG (DImode
,
3858 offset
+= UNITS_PER_WORD
;
3860 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3863 return gen_rtx_REG (mode
, GR_RET_FIRST
);
3867 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3868 We need to emit DTP-relative relocations. */
3871 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
3875 fputs ("\tdata8.ua\t@dtprel(", file
);
3876 output_addr_const (file
, x
);
3880 /* Print a memory address as an operand to reference that memory location. */
3882 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3883 also call this from ia64_print_operand for memory addresses. */
3886 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
3887 rtx address ATTRIBUTE_UNUSED
)
3891 /* Print an operand to an assembler instruction.
3892 C Swap and print a comparison operator.
3893 D Print an FP comparison operator.
3894 E Print 32 - constant, for SImode shifts as extract.
3895 e Print 64 - constant, for DImode rotates.
3896 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3897 a floating point register emitted normally.
3898 I Invert a predicate register by adding 1.
3899 J Select the proper predicate register for a condition.
3900 j Select the inverse predicate register for a condition.
3901 O Append .acq for volatile load.
3902 P Postincrement of a MEM.
3903 Q Append .rel for volatile store.
3904 S Shift amount for shladd instruction.
3905 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3906 for Intel assembler.
3907 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3908 for Intel assembler.
3909 r Print register name, or constant 0 as r0. HP compatibility for
3912 ia64_print_operand (FILE * file
, rtx x
, int code
)
3919 /* Handled below. */
3924 enum rtx_code c
= swap_condition (GET_CODE (x
));
3925 fputs (GET_RTX_NAME (c
), file
);
3930 switch (GET_CODE (x
))
3942 str
= GET_RTX_NAME (GET_CODE (x
));
3949 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
3953 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
3957 if (x
== CONST0_RTX (GET_MODE (x
)))
3958 str
= reg_names
[FR_REG (0)];
3959 else if (x
== CONST1_RTX (GET_MODE (x
)))
3960 str
= reg_names
[FR_REG (1)];
3961 else if (GET_CODE (x
) == REG
)
3962 str
= reg_names
[REGNO (x
)];
3969 fputs (reg_names
[REGNO (x
) + 1], file
);
3975 unsigned int regno
= REGNO (XEXP (x
, 0));
3976 if (GET_CODE (x
) == EQ
)
3980 fputs (reg_names
[regno
], file
);
3985 if (MEM_VOLATILE_P (x
))
3986 fputs(".acq", file
);
3991 HOST_WIDE_INT value
;
3993 switch (GET_CODE (XEXP (x
, 0)))
3999 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
4000 if (GET_CODE (x
) == CONST_INT
)
4002 else if (GET_CODE (x
) == REG
)
4004 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
4012 value
= GET_MODE_SIZE (GET_MODE (x
));
4016 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
4020 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
4025 if (MEM_VOLATILE_P (x
))
4026 fputs(".rel", file
);
4030 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4034 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4036 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
4042 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4044 const char *prefix
= "0x";
4045 if (INTVAL (x
) & 0x80000000)
4047 fprintf (file
, "0xffffffff");
4050 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
4056 /* If this operand is the constant zero, write it as register zero.
4057 Any register, zero, or CONST_INT value is OK here. */
4058 if (GET_CODE (x
) == REG
)
4059 fputs (reg_names
[REGNO (x
)], file
);
4060 else if (x
== CONST0_RTX (GET_MODE (x
)))
4062 else if (GET_CODE (x
) == CONST_INT
)
4063 output_addr_const (file
, x
);
4065 output_operand_lossage ("invalid %%r value");
4072 /* For conditional branches, returns or calls, substitute
4073 sptk, dptk, dpnt, or spnt for %s. */
4074 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4077 int pred_val
= INTVAL (XEXP (x
, 0));
4079 /* Guess top and bottom 10% statically predicted. */
4080 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4082 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4084 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4089 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4094 fputs (which
, file
);
4099 x
= current_insn_predicate
;
4102 unsigned int regno
= REGNO (XEXP (x
, 0));
4103 if (GET_CODE (x
) == EQ
)
4105 fprintf (file
, "(%s) ", reg_names
[regno
]);
4110 output_operand_lossage ("ia64_print_operand: unknown code");
4114 switch (GET_CODE (x
))
4116 /* This happens for the spill/restore instructions. */
4121 /* ... fall through ... */
4124 fputs (reg_names
[REGNO (x
)], file
);
4129 rtx addr
= XEXP (x
, 0);
4130 if (GET_RTX_CLASS (GET_CODE (addr
)) == 'a')
4131 addr
= XEXP (addr
, 0);
4132 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4137 output_addr_const (file
, x
);
4144 /* Compute a (partial) cost for rtx X. Return true if the complete
4145 cost has been computed, and false if subexpressions should be
4146 scanned. In either case, *TOTAL contains the cost result. */
4147 /* ??? This is incomplete. */
4150 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4158 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4161 if (CONST_OK_FOR_I (INTVAL (x
)))
4163 else if (CONST_OK_FOR_J (INTVAL (x
)))
4166 *total
= COSTS_N_INSNS (1);
4169 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4172 *total
= COSTS_N_INSNS (1);
4177 *total
= COSTS_N_INSNS (1);
4183 *total
= COSTS_N_INSNS (3);
4187 /* For multiplies wider than HImode, we have to go to the FPU,
4188 which normally involves copies. Plus there's the latency
4189 of the multiply itself, and the latency of the instructions to
4190 transfer integer regs to FP regs. */
4191 /* ??? Check for FP mode. */
4192 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4193 *total
= COSTS_N_INSNS (10);
4195 *total
= COSTS_N_INSNS (2);
4203 *total
= COSTS_N_INSNS (1);
4210 /* We make divide expensive, so that divide-by-constant will be
4211 optimized to a multiply. */
4212 *total
= COSTS_N_INSNS (60);
4220 /* Calculate the cost of moving data from a register in class FROM to
4221 one in class TO, using MODE. */
4224 ia64_register_move_cost (enum machine_mode mode
, enum reg_class from
,
4227 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4228 if (to
== ADDL_REGS
)
4230 if (from
== ADDL_REGS
)
4233 /* All costs are symmetric, so reduce cases by putting the
4234 lower number class as the destination. */
4237 enum reg_class tmp
= to
;
4238 to
= from
, from
= tmp
;
4241 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4242 so that we get secondary memory reloads. Between FR_REGS,
4243 we have to make this at least as expensive as MEMORY_MOVE_COST
4244 to avoid spectacularly poor register class preferencing. */
4247 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4248 return MEMORY_MOVE_COST (mode
, to
, 0);
4256 /* Moving between PR registers takes two insns. */
4257 if (from
== PR_REGS
)
4259 /* Moving between PR and anything but GR is impossible. */
4260 if (from
!= GR_REGS
)
4261 return MEMORY_MOVE_COST (mode
, to
, 0);
4265 /* Moving between BR and anything but GR is impossible. */
4266 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4267 return MEMORY_MOVE_COST (mode
, to
, 0);
4272 /* Moving between AR and anything but GR is impossible. */
4273 if (from
!= GR_REGS
)
4274 return MEMORY_MOVE_COST (mode
, to
, 0);
4279 case GR_AND_FR_REGS
:
4280 case GR_AND_BR_REGS
:
4291 /* This function returns the register class required for a secondary
4292 register when copying between one of the registers in CLASS, and X,
4293 using MODE. A return value of NO_REGS means that no secondary register
4297 ia64_secondary_reload_class (enum reg_class
class,
4298 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4302 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4303 regno
= true_regnum (x
);
4310 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4311 interaction. We end up with two pseudos with overlapping lifetimes
4312 both of which are equiv to the same constant, and both which need
4313 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4314 changes depending on the path length, which means the qty_first_reg
4315 check in make_regs_eqv can give different answers at different times.
4316 At some point I'll probably need a reload_indi pattern to handle
4319 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4320 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4321 non-general registers for good measure. */
4322 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4325 /* This is needed if a pseudo used as a call_operand gets spilled to a
4327 if (GET_CODE (x
) == MEM
)
4332 /* Need to go through general registers to get to other class regs. */
4333 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4336 /* This can happen when a paradoxical subreg is an operand to the
4338 /* ??? This shouldn't be necessary after instruction scheduling is
4339 enabled, because paradoxical subregs are not accepted by
4340 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4341 stop the paradoxical subreg stupidity in the *_operand functions
4343 if (GET_CODE (x
) == MEM
4344 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4345 || GET_MODE (x
) == QImode
))
4348 /* This can happen because of the ior/and/etc patterns that accept FP
4349 registers as operands. If the third operand is a constant, then it
4350 needs to be reloaded into a FP register. */
4351 if (GET_CODE (x
) == CONST_INT
)
4354 /* This can happen because of register elimination in a muldi3 insn.
4355 E.g. `26107 * (unsigned long)&u'. */
4356 if (GET_CODE (x
) == PLUS
)
4361 /* ??? This happens if we cse/gcse a BImode value across a call,
4362 and the function has a nonlocal goto. This is because global
4363 does not allocate call crossing pseudos to hard registers when
4364 current_function_has_nonlocal_goto is true. This is relatively
4365 common for C++ programs that use exceptions. To reproduce,
4366 return NO_REGS and compile libstdc++. */
4367 if (GET_CODE (x
) == MEM
)
4370 /* This can happen when we take a BImode subreg of a DImode value,
4371 and that DImode value winds up in some non-GR register. */
4372 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4377 /* Since we have no offsettable memory addresses, we need a temporary
4378 to hold the address of the second word. */
4391 /* Emit text to declare externally defined variables and functions, because
4392 the Intel assembler does not support undefined externals. */
4395 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
4397 int save_referenced
;
4399 /* GNU as does not need anything here, but the HP linker does need
4400 something for external functions. */
4404 || TREE_CODE (decl
) != FUNCTION_DECL
4405 || strstr (name
, "__builtin_") == name
))
4408 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4409 the linker when we do this, so we need to be careful not to do this for
4410 builtin functions which have no library equivalent. Unfortunately, we
4411 can't tell here whether or not a function will actually be called by
4412 expand_expr, so we pull in library functions even if we may not need
4414 if (! strcmp (name
, "__builtin_next_arg")
4415 || ! strcmp (name
, "alloca")
4416 || ! strcmp (name
, "__builtin_constant_p")
4417 || ! strcmp (name
, "__builtin_args_info"))
4421 ia64_hpux_add_extern_decl (name
);
4424 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4426 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4427 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4428 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4429 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4430 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4434 /* Parse the -mfixed-range= option string. */
4437 fix_range (const char *const_str
)
4440 char *str
, *dash
, *comma
;
4442 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4443 REG2 are either register names or register numbers. The effect
4444 of this option is to mark the registers in the range from REG1 to
4445 REG2 as ``fixed'' so they won't be used by the compiler. This is
4446 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4448 i
= strlen (const_str
);
4449 str
= (char *) alloca (i
+ 1);
4450 memcpy (str
, const_str
, i
+ 1);
4454 dash
= strchr (str
, '-');
4457 warning ("value of -mfixed-range must have form REG1-REG2");
4462 comma
= strchr (dash
+ 1, ',');
4466 first
= decode_reg_name (str
);
4469 warning ("unknown register name: %s", str
);
4473 last
= decode_reg_name (dash
+ 1);
4476 warning ("unknown register name: %s", dash
+ 1);
4484 warning ("%s-%s is an empty range", str
, dash
+ 1);
4488 for (i
= first
; i
<= last
; ++i
)
4489 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4499 static struct machine_function
*
4500 ia64_init_machine_status (void)
4502 return ggc_alloc_cleared (sizeof (struct machine_function
));
4505 /* Handle TARGET_OPTIONS switches. */
4508 ia64_override_options (void)
4512 const char *const name
; /* processor name or nickname. */
4513 const enum processor_type processor
;
4515 const processor_alias_table
[] =
4517 {"itanium", PROCESSOR_ITANIUM
},
4518 {"itanium1", PROCESSOR_ITANIUM
},
4519 {"merced", PROCESSOR_ITANIUM
},
4520 {"itanium2", PROCESSOR_ITANIUM2
},
4521 {"mckinley", PROCESSOR_ITANIUM2
},
4524 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4527 if (TARGET_AUTO_PIC
)
4528 target_flags
|= MASK_CONST_GP
;
4530 if (TARGET_INLINE_FLOAT_DIV_LAT
&& TARGET_INLINE_FLOAT_DIV_THR
)
4532 warning ("cannot optimize floating point division for both latency and throughput");
4533 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4536 if (TARGET_INLINE_INT_DIV_LAT
&& TARGET_INLINE_INT_DIV_THR
)
4538 warning ("cannot optimize integer division for both latency and throughput");
4539 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4542 if (TARGET_INLINE_SQRT_LAT
&& TARGET_INLINE_SQRT_THR
)
4544 warning ("cannot optimize square root for both latency and throughput");
4545 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4548 if (TARGET_INLINE_SQRT_LAT
)
4550 warning ("not yet implemented: latency-optimized inline square root");
4551 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4554 if (ia64_fixed_range_string
)
4555 fix_range (ia64_fixed_range_string
);
4557 if (ia64_tls_size_string
)
4560 unsigned long tmp
= strtoul (ia64_tls_size_string
, &end
, 10);
4561 if (*end
|| (tmp
!= 14 && tmp
!= 22 && tmp
!= 64))
4562 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string
);
4564 ia64_tls_size
= tmp
;
4567 if (!ia64_tune_string
)
4568 ia64_tune_string
= "itanium2";
4570 for (i
= 0; i
< pta_size
; i
++)
4571 if (! strcmp (ia64_tune_string
, processor_alias_table
[i
].name
))
4573 ia64_tune
= processor_alias_table
[i
].processor
;
4578 error ("bad value (%s) for -tune= switch", ia64_tune_string
);
4580 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4581 flag_schedule_insns_after_reload
= 0;
4583 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4585 init_machine_status
= ia64_init_machine_status
;
4588 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
4589 static enum attr_type
ia64_safe_type (rtx
);
4591 static enum attr_itanium_class
4592 ia64_safe_itanium_class (rtx insn
)
4594 if (recog_memoized (insn
) >= 0)
4595 return get_attr_itanium_class (insn
);
4597 return ITANIUM_CLASS_UNKNOWN
;
4600 static enum attr_type
4601 ia64_safe_type (rtx insn
)
4603 if (recog_memoized (insn
) >= 0)
4604 return get_attr_type (insn
);
4606 return TYPE_UNKNOWN
;
4609 /* The following collection of routines emit instruction group stop bits as
4610 necessary to avoid dependencies. */
4612 /* Need to track some additional registers as far as serialization is
4613 concerned so we can properly handle br.call and br.ret. We could
4614 make these registers visible to gcc, but since these registers are
4615 never explicitly used in gcc generated code, it seems wasteful to
4616 do so (plus it would make the call and return patterns needlessly
4618 #define REG_GP (GR_REG (1))
4619 #define REG_RP (BR_REG (0))
4620 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4621 /* This is used for volatile asms which may require a stop bit immediately
4622 before and after them. */
4623 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4624 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4625 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4627 /* For each register, we keep track of how it has been written in the
4628 current instruction group.
4630 If a register is written unconditionally (no qualifying predicate),
4631 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4633 If a register is written if its qualifying predicate P is true, we
4634 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4635 may be written again by the complement of P (P^1) and when this happens,
4636 WRITE_COUNT gets set to 2.
4638 The result of this is that whenever an insn attempts to write a register
4639 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4641 If a predicate register is written by a floating-point insn, we set
4642 WRITTEN_BY_FP to true.
4644 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4645 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4647 struct reg_write_state
4649 unsigned int write_count
: 2;
4650 unsigned int first_pred
: 16;
4651 unsigned int written_by_fp
: 1;
4652 unsigned int written_by_and
: 1;
4653 unsigned int written_by_or
: 1;
4656 /* Cumulative info for the current instruction group. */
4657 struct reg_write_state rws_sum
[NUM_REGS
];
4658 /* Info for the current instruction. This gets copied to rws_sum after a
4659 stop bit is emitted. */
4660 struct reg_write_state rws_insn
[NUM_REGS
];
4662 /* Indicates whether this is the first instruction after a stop bit,
4663 in which case we don't need another stop bit. Without this, we hit
4664 the abort in ia64_variable_issue when scheduling an alloc. */
4665 static int first_instruction
;
4667 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4668 RTL for one instruction. */
4671 unsigned int is_write
: 1; /* Is register being written? */
4672 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
4673 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
4674 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
4675 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
4676 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
4679 static void rws_update (struct reg_write_state
*, int, struct reg_flags
, int);
4680 static int rws_access_regno (int, struct reg_flags
, int);
4681 static int rws_access_reg (rtx
, struct reg_flags
, int);
4682 static void update_set_flags (rtx
, struct reg_flags
*, int *, rtx
*);
4683 static int set_src_needs_barrier (rtx
, struct reg_flags
, int, rtx
);
4684 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
4685 static void init_insn_group_barriers (void);
4686 static int group_barrier_needed_p (rtx
);
4687 static int safe_group_barrier_needed_p (rtx
);
4689 /* Update *RWS for REGNO, which is being written by the current instruction,
4690 with predicate PRED, and associated register flags in FLAGS. */
4693 rws_update (struct reg_write_state
*rws
, int regno
, struct reg_flags flags
, int pred
)
4696 rws
[regno
].write_count
++;
4698 rws
[regno
].write_count
= 2;
4699 rws
[regno
].written_by_fp
|= flags
.is_fp
;
4700 /* ??? Not tracking and/or across differing predicates. */
4701 rws
[regno
].written_by_and
= flags
.is_and
;
4702 rws
[regno
].written_by_or
= flags
.is_or
;
4703 rws
[regno
].first_pred
= pred
;
4706 /* Handle an access to register REGNO of type FLAGS using predicate register
4707 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4708 a dependency with an earlier instruction in the same group. */
4711 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
4713 int need_barrier
= 0;
4715 if (regno
>= NUM_REGS
)
4718 if (! PR_REGNO_P (regno
))
4719 flags
.is_and
= flags
.is_or
= 0;
4725 /* One insn writes same reg multiple times? */
4726 if (rws_insn
[regno
].write_count
> 0)
4729 /* Update info for current instruction. */
4730 rws_update (rws_insn
, regno
, flags
, pred
);
4731 write_count
= rws_sum
[regno
].write_count
;
4733 switch (write_count
)
4736 /* The register has not been written yet. */
4737 rws_update (rws_sum
, regno
, flags
, pred
);
4741 /* The register has been written via a predicate. If this is
4742 not a complementary predicate, then we need a barrier. */
4743 /* ??? This assumes that P and P+1 are always complementary
4744 predicates for P even. */
4745 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4747 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4749 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4751 rws_update (rws_sum
, regno
, flags
, pred
);
4755 /* The register has been unconditionally written already. We
4757 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4759 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4763 rws_sum
[regno
].written_by_and
= flags
.is_and
;
4764 rws_sum
[regno
].written_by_or
= flags
.is_or
;
4773 if (flags
.is_branch
)
4775 /* Branches have several RAW exceptions that allow to avoid
4778 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
4779 /* RAW dependencies on branch regs are permissible as long
4780 as the writer is a non-branch instruction. Since we
4781 never generate code that uses a branch register written
4782 by a branch instruction, handling this case is
4786 if (REGNO_REG_CLASS (regno
) == PR_REGS
4787 && ! rws_sum
[regno
].written_by_fp
)
4788 /* The predicates of a branch are available within the
4789 same insn group as long as the predicate was written by
4790 something other than a floating-point instruction. */
4794 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
4796 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
4799 switch (rws_sum
[regno
].write_count
)
4802 /* The register has not been written yet. */
4806 /* The register has been written via a predicate. If this is
4807 not a complementary predicate, then we need a barrier. */
4808 /* ??? This assumes that P and P+1 are always complementary
4809 predicates for P even. */
4810 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
4815 /* The register has been unconditionally written already. We
4825 return need_barrier
;
4829 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
4831 int regno
= REGNO (reg
);
4832 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
4835 return rws_access_regno (regno
, flags
, pred
);
4838 int need_barrier
= 0;
4840 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
4841 return need_barrier
;
4845 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4846 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4849 update_set_flags (rtx x
, struct reg_flags
*pflags
, int *ppred
, rtx
*pcond
)
4851 rtx src
= SET_SRC (x
);
4855 switch (GET_CODE (src
))
4861 if (SET_DEST (x
) == pc_rtx
)
4862 /* X is a conditional branch. */
4866 int is_complemented
= 0;
4868 /* X is a conditional move. */
4869 rtx cond
= XEXP (src
, 0);
4870 if (GET_CODE (cond
) == EQ
)
4871 is_complemented
= 1;
4872 cond
= XEXP (cond
, 0);
4873 if (GET_CODE (cond
) != REG
4874 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
4877 if (XEXP (src
, 1) == SET_DEST (x
)
4878 || XEXP (src
, 2) == SET_DEST (x
))
4880 /* X is a conditional move that conditionally writes the
4883 /* We need another complement in this case. */
4884 if (XEXP (src
, 1) == SET_DEST (x
))
4885 is_complemented
= ! is_complemented
;
4887 *ppred
= REGNO (cond
);
4888 if (is_complemented
)
4892 /* ??? If this is a conditional write to the dest, then this
4893 instruction does not actually read one source. This probably
4894 doesn't matter, because that source is also the dest. */
4895 /* ??? Multiple writes to predicate registers are allowed
4896 if they are all AND type compares, or if they are all OR
4897 type compares. We do not generate such instructions
4900 /* ... fall through ... */
4903 if (GET_RTX_CLASS (GET_CODE (src
)) == '<'
4904 && GET_MODE_CLASS (GET_MODE (XEXP (src
, 0))) == MODE_FLOAT
)
4905 /* Set pflags->is_fp to 1 so that we know we're dealing
4906 with a floating point comparison when processing the
4907 destination of the SET. */
4910 /* Discover if this is a parallel comparison. We only handle
4911 and.orcm and or.andcm at present, since we must retain a
4912 strict inverse on the predicate pair. */
4913 else if (GET_CODE (src
) == AND
)
4915 else if (GET_CODE (src
) == IOR
)
4922 /* Subroutine of rtx_needs_barrier; this function determines whether the
4923 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
4924 are as in rtx_needs_barrier. COND is an rtx that holds the condition
4928 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
, rtx cond
)
4930 int need_barrier
= 0;
4932 rtx src
= SET_SRC (x
);
4934 if (GET_CODE (src
) == CALL
)
4935 /* We don't need to worry about the result registers that
4936 get written by subroutine call. */
4937 return rtx_needs_barrier (src
, flags
, pred
);
4938 else if (SET_DEST (x
) == pc_rtx
)
4940 /* X is a conditional branch. */
4941 /* ??? This seems redundant, as the caller sets this bit for
4943 flags
.is_branch
= 1;
4944 return rtx_needs_barrier (src
, flags
, pred
);
4947 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
4949 /* This instruction unconditionally uses a predicate register. */
4951 need_barrier
|= rws_access_reg (cond
, flags
, 0);
4954 if (GET_CODE (dst
) == ZERO_EXTRACT
)
4956 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
4957 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
4958 dst
= XEXP (dst
, 0);
4960 return need_barrier
;
4963 /* Handle an access to rtx X of type FLAGS using predicate register
4964 PRED. Return 1 if this access creates a dependency with an earlier
4965 instruction in the same group. */
4968 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
4971 int is_complemented
= 0;
4972 int need_barrier
= 0;
4973 const char *format_ptr
;
4974 struct reg_flags new_flags
;
4982 switch (GET_CODE (x
))
4985 update_set_flags (x
, &new_flags
, &pred
, &cond
);
4986 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
, cond
);
4987 if (GET_CODE (SET_SRC (x
)) != CALL
)
4989 new_flags
.is_write
= 1;
4990 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
4995 new_flags
.is_write
= 0;
4996 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
4998 /* Avoid multiple register writes, in case this is a pattern with
4999 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5000 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
5002 new_flags
.is_write
= 1;
5003 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
5004 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
5005 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5010 /* X is a predicated instruction. */
5012 cond
= COND_EXEC_TEST (x
);
5015 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
5017 if (GET_CODE (cond
) == EQ
)
5018 is_complemented
= 1;
5019 cond
= XEXP (cond
, 0);
5020 if (GET_CODE (cond
) != REG
5021 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5023 pred
= REGNO (cond
);
5024 if (is_complemented
)
5027 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
5028 return need_barrier
;
5032 /* Clobber & use are for earlier compiler-phases only. */
5037 /* We always emit stop bits for traditional asms. We emit stop bits
5038 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5039 if (GET_CODE (x
) != ASM_OPERANDS
5040 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
5042 /* Avoid writing the register multiple times if we have multiple
5043 asm outputs. This avoids an abort in rws_access_reg. */
5044 if (! rws_insn
[REG_VOLATILE
].write_count
)
5046 new_flags
.is_write
= 1;
5047 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5052 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5053 We can not just fall through here since then we would be confused
5054 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5055 traditional asms unlike their normal usage. */
5057 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5058 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5063 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5065 rtx pat
= XVECEXP (x
, 0, i
);
5066 if (GET_CODE (pat
) == SET
)
5068 update_set_flags (pat
, &new_flags
, &pred
, &cond
);
5069 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
, cond
);
5071 else if (GET_CODE (pat
) == USE
5072 || GET_CODE (pat
) == CALL
5073 || GET_CODE (pat
) == ASM_OPERANDS
)
5074 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5075 else if (GET_CODE (pat
) != CLOBBER
&& GET_CODE (pat
) != RETURN
)
5078 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5080 rtx pat
= XVECEXP (x
, 0, i
);
5081 if (GET_CODE (pat
) == SET
)
5083 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5085 new_flags
.is_write
= 1;
5086 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5090 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5091 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5099 if (REGNO (x
) == AR_UNAT_REGNUM
)
5101 for (i
= 0; i
< 64; ++i
)
5102 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5105 need_barrier
= rws_access_reg (x
, flags
, pred
);
5109 /* Find the regs used in memory address computation. */
5110 new_flags
.is_write
= 0;
5111 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5114 case CONST_INT
: case CONST_DOUBLE
:
5115 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5118 /* Operators with side-effects. */
5119 case POST_INC
: case POST_DEC
:
5120 if (GET_CODE (XEXP (x
, 0)) != REG
)
5123 new_flags
.is_write
= 0;
5124 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5125 new_flags
.is_write
= 1;
5126 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5130 if (GET_CODE (XEXP (x
, 0)) != REG
)
5133 new_flags
.is_write
= 0;
5134 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5135 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5136 new_flags
.is_write
= 1;
5137 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5140 /* Handle common unary and binary ops for efficiency. */
5141 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5142 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5143 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5144 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5145 case NE
: case EQ
: case GE
: case GT
: case LE
:
5146 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5147 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5148 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5151 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5152 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5153 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5154 case SQRT
: case FFS
: case POPCOUNT
:
5155 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5159 switch (XINT (x
, 1))
5161 case UNSPEC_LTOFF_DTPMOD
:
5162 case UNSPEC_LTOFF_DTPREL
:
5164 case UNSPEC_LTOFF_TPREL
:
5166 case UNSPEC_PRED_REL_MUTEX
:
5167 case UNSPEC_PIC_CALL
:
5169 case UNSPEC_FETCHADD_ACQ
:
5170 case UNSPEC_BSP_VALUE
:
5171 case UNSPEC_FLUSHRS
:
5172 case UNSPEC_BUNDLE_SELECTOR
:
5175 case UNSPEC_GR_SPILL
:
5176 case UNSPEC_GR_RESTORE
:
5178 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5179 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5181 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5182 new_flags
.is_write
= (XINT (x
, 1) == 1);
5183 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5188 case UNSPEC_FR_SPILL
:
5189 case UNSPEC_FR_RESTORE
:
5190 case UNSPEC_GETF_EXP
:
5191 case UNSPEC_SETF_EXP
:
5193 case UNSPEC_FR_SQRT_RECIP_APPROX
:
5194 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5197 case UNSPEC_FR_RECIP_APPROX
:
5198 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5199 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5202 case UNSPEC_CMPXCHG_ACQ
:
5203 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5204 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5212 case UNSPEC_VOLATILE
:
5213 switch (XINT (x
, 1))
5216 /* Alloc must always be the first instruction of a group.
5217 We force this by always returning true. */
5218 /* ??? We might get better scheduling if we explicitly check for
5219 input/local/output register dependencies, and modify the
5220 scheduler so that alloc is always reordered to the start of
5221 the current group. We could then eliminate all of the
5222 first_instruction code. */
5223 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5225 new_flags
.is_write
= 1;
5226 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5229 case UNSPECV_SET_BSP
:
5233 case UNSPECV_BLOCKAGE
:
5234 case UNSPECV_INSN_GROUP_BARRIER
:
5236 case UNSPECV_PSAC_ALL
:
5237 case UNSPECV_PSAC_NORMAL
:
5246 new_flags
.is_write
= 0;
5247 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5248 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5250 new_flags
.is_write
= 1;
5251 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5252 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5256 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5257 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5258 switch (format_ptr
[i
])
5260 case '0': /* unused field */
5261 case 'i': /* integer */
5262 case 'n': /* note */
5263 case 'w': /* wide integer */
5264 case 's': /* pointer to string */
5265 case 'S': /* optional pointer to string */
5269 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5274 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5275 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5284 return need_barrier
;
5287 /* Clear out the state for group_barrier_needed_p at the start of a
5288 sequence of insns. */
5291 init_insn_group_barriers (void)
5293 memset (rws_sum
, 0, sizeof (rws_sum
));
5294 first_instruction
= 1;
5297 /* Given the current state, recorded by previous calls to this function,
5298 determine whether a group barrier (a stop bit) is necessary before INSN.
5299 Return nonzero if so. */
5302 group_barrier_needed_p (rtx insn
)
5305 int need_barrier
= 0;
5306 struct reg_flags flags
;
5308 memset (&flags
, 0, sizeof (flags
));
5309 switch (GET_CODE (insn
))
5315 /* A barrier doesn't imply an instruction group boundary. */
5319 memset (rws_insn
, 0, sizeof (rws_insn
));
5323 flags
.is_branch
= 1;
5324 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5325 memset (rws_insn
, 0, sizeof (rws_insn
));
5327 /* Don't bundle a call following another call. */
5328 if ((pat
= prev_active_insn (insn
))
5329 && GET_CODE (pat
) == CALL_INSN
)
5335 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5339 flags
.is_branch
= 1;
5341 /* Don't bundle a jump following a call. */
5342 if ((pat
= prev_active_insn (insn
))
5343 && GET_CODE (pat
) == CALL_INSN
)
5351 if (GET_CODE (PATTERN (insn
)) == USE
5352 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5353 /* Don't care about USE and CLOBBER "insns"---those are used to
5354 indicate to the optimizer that it shouldn't get rid of
5355 certain operations. */
5358 pat
= PATTERN (insn
);
5360 /* Ug. Hack hacks hacked elsewhere. */
5361 switch (recog_memoized (insn
))
5363 /* We play dependency tricks with the epilogue in order
5364 to get proper schedules. Undo this for dv analysis. */
5365 case CODE_FOR_epilogue_deallocate_stack
:
5366 case CODE_FOR_prologue_allocate_stack
:
5367 pat
= XVECEXP (pat
, 0, 0);
5370 /* The pattern we use for br.cloop confuses the code above.
5371 The second element of the vector is representative. */
5372 case CODE_FOR_doloop_end_internal
:
5373 pat
= XVECEXP (pat
, 0, 1);
5376 /* Doesn't generate code. */
5377 case CODE_FOR_pred_rel_mutex
:
5378 case CODE_FOR_prologue_use
:
5385 memset (rws_insn
, 0, sizeof (rws_insn
));
5386 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5388 /* Check to see if the previous instruction was a volatile
5391 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5398 if (first_instruction
&& INSN_P (insn
)
5399 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5400 && GET_CODE (PATTERN (insn
)) != USE
5401 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5404 first_instruction
= 0;
5407 return need_barrier
;
5410 /* Like group_barrier_needed_p, but do not clobber the current state. */
5413 safe_group_barrier_needed_p (rtx insn
)
5415 struct reg_write_state rws_saved
[NUM_REGS
];
5416 int saved_first_instruction
;
5419 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5420 saved_first_instruction
= first_instruction
;
5422 t
= group_barrier_needed_p (insn
);
5424 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5425 first_instruction
= saved_first_instruction
;
5430 /* Scan the current function and insert stop bits as necessary to
5431 eliminate dependencies. This function assumes that a final
5432 instruction scheduling pass has been run which has already
5433 inserted most of the necessary stop bits. This function only
5434 inserts new ones at basic block boundaries, since these are
5435 invisible to the scheduler. */
5438 emit_insn_group_barriers (FILE *dump
)
5442 int insns_since_last_label
= 0;
5444 init_insn_group_barriers ();
5446 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5448 if (GET_CODE (insn
) == CODE_LABEL
)
5450 if (insns_since_last_label
)
5452 insns_since_last_label
= 0;
5454 else if (GET_CODE (insn
) == NOTE
5455 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5457 if (insns_since_last_label
)
5459 insns_since_last_label
= 0;
5461 else if (GET_CODE (insn
) == INSN
5462 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5463 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5465 init_insn_group_barriers ();
5468 else if (INSN_P (insn
))
5470 insns_since_last_label
= 1;
5472 if (group_barrier_needed_p (insn
))
5477 fprintf (dump
, "Emitting stop before label %d\n",
5478 INSN_UID (last_label
));
5479 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5482 init_insn_group_barriers ();
5490 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5491 This function has to emit all necessary group barriers. */
5494 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
5498 init_insn_group_barriers ();
5500 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5502 if (GET_CODE (insn
) == BARRIER
)
5504 rtx last
= prev_active_insn (insn
);
5508 if (GET_CODE (last
) == JUMP_INSN
5509 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5510 last
= prev_active_insn (last
);
5511 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5512 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5514 init_insn_group_barriers ();
5516 else if (INSN_P (insn
))
5518 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5519 init_insn_group_barriers ();
5520 else if (group_barrier_needed_p (insn
))
5522 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5523 init_insn_group_barriers ();
5524 group_barrier_needed_p (insn
);
5531 static int errata_find_address_regs (rtx
*, void *);
5532 static void errata_emit_nops (rtx
);
5533 static void fixup_errata (void);
5535 /* This structure is used to track some details about the previous insns
5536 groups so we can determine if it may be necessary to insert NOPs to
5537 workaround hardware errata. */
5540 HARD_REG_SET p_reg_set
;
5541 HARD_REG_SET gr_reg_conditionally_set
;
5544 /* Index into the last_group array. */
5545 static int group_idx
;
5547 /* Called through for_each_rtx; determines if a hard register that was
5548 conditionally set in the previous group is used as an address register.
5549 It ensures that for_each_rtx returns 1 in that case. */
5551 errata_find_address_regs (rtx
*xp
, void *data ATTRIBUTE_UNUSED
)
5554 if (GET_CODE (x
) != MEM
)
5557 if (GET_CODE (x
) == POST_MODIFY
)
5559 if (GET_CODE (x
) == REG
)
5561 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5562 if (TEST_HARD_REG_BIT (prev_group
->gr_reg_conditionally_set
,
5570 /* Called for each insn; this function keeps track of the state in
5571 last_group and emits additional NOPs if necessary to work around
5572 an Itanium A/B step erratum. */
5574 errata_emit_nops (rtx insn
)
5576 struct group
*this_group
= last_group
+ group_idx
;
5577 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5578 rtx pat
= PATTERN (insn
);
5579 rtx cond
= GET_CODE (pat
) == COND_EXEC
? COND_EXEC_TEST (pat
) : 0;
5580 rtx real_pat
= cond
? COND_EXEC_CODE (pat
) : pat
;
5581 enum attr_type type
;
5584 if (GET_CODE (real_pat
) == USE
5585 || GET_CODE (real_pat
) == CLOBBER
5586 || GET_CODE (real_pat
) == ASM_INPUT
5587 || GET_CODE (real_pat
) == ADDR_VEC
5588 || GET_CODE (real_pat
) == ADDR_DIFF_VEC
5589 || asm_noperands (PATTERN (insn
)) >= 0)
5592 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5595 if (GET_CODE (set
) == PARALLEL
)
5598 set
= XVECEXP (real_pat
, 0, 0);
5599 for (i
= 1; i
< XVECLEN (real_pat
, 0); i
++)
5600 if (GET_CODE (XVECEXP (real_pat
, 0, i
)) != USE
5601 && GET_CODE (XVECEXP (real_pat
, 0, i
)) != CLOBBER
)
5608 if (set
&& GET_CODE (set
) != SET
)
5611 type
= get_attr_type (insn
);
5614 && set
&& REG_P (SET_DEST (set
)) && PR_REGNO_P (REGNO (SET_DEST (set
))))
5615 SET_HARD_REG_BIT (this_group
->p_reg_set
, REGNO (SET_DEST (set
)));
5617 if ((type
== TYPE_M
|| type
== TYPE_A
) && cond
&& set
5618 && REG_P (SET_DEST (set
))
5619 && GET_CODE (SET_SRC (set
)) != PLUS
5620 && GET_CODE (SET_SRC (set
)) != MINUS
5621 && (GET_CODE (SET_SRC (set
)) != ASHIFT
5622 || !shladd_operand (XEXP (SET_SRC (set
), 1), VOIDmode
))
5623 && (GET_CODE (SET_SRC (set
)) != MEM
5624 || GET_CODE (XEXP (SET_SRC (set
), 0)) != POST_MODIFY
)
5625 && GENERAL_REGNO_P (REGNO (SET_DEST (set
))))
5627 if (GET_RTX_CLASS (GET_CODE (cond
)) != '<'
5628 || ! REG_P (XEXP (cond
, 0)))
5631 if (TEST_HARD_REG_BIT (prev_group
->p_reg_set
, REGNO (XEXP (cond
, 0))))
5632 SET_HARD_REG_BIT (this_group
->gr_reg_conditionally_set
, REGNO (SET_DEST (set
)));
5634 if (for_each_rtx (&real_pat
, errata_find_address_regs
, NULL
))
5636 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5637 emit_insn_before (gen_nop (), insn
);
5638 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5640 memset (last_group
, 0, sizeof last_group
);
5644 /* Emit extra nops if they are required to work around hardware errata. */
5651 if (! TARGET_B_STEP
)
5655 memset (last_group
, 0, sizeof last_group
);
5657 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5662 if (ia64_safe_type (insn
) == TYPE_S
)
5665 memset (last_group
+ group_idx
, 0, sizeof last_group
[group_idx
]);
5668 errata_emit_nops (insn
);
5673 /* Instruction scheduling support. */
5675 #define NR_BUNDLES 10
5677 /* A list of names of all available bundles. */
5679 static const char *bundle_name
[NR_BUNDLES
] =
5685 #if NR_BUNDLES == 10
5695 /* Nonzero if we should insert stop bits into the schedule. */
5697 int ia64_final_schedule
= 0;
5699 /* Codes of the corresponding quieryied units: */
5701 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5702 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5704 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5705 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5707 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5709 /* The following variable value is an insn group barrier. */
5711 static rtx dfa_stop_insn
;
5713 /* The following variable value is the last issued insn. */
5715 static rtx last_scheduled_insn
;
5717 /* The following variable value is size of the DFA state. */
5719 static size_t dfa_state_size
;
5721 /* The following variable value is pointer to a DFA state used as
5722 temporary variable. */
5724 static state_t temp_dfa_state
= NULL
;
5726 /* The following variable value is DFA state after issuing the last
5729 static state_t prev_cycle_state
= NULL
;
5731 /* The following array element values are TRUE if the corresponding
5732 insn requires to add stop bits before it. */
5734 static char *stops_p
;
5736 /* The following variable is used to set up the mentioned above array. */
5738 static int stop_before_p
= 0;
5740 /* The following variable value is length of the arrays `clocks' and
5743 static int clocks_length
;
5745 /* The following array element values are cycles on which the
5746 corresponding insn will be issued. The array is used only for
5751 /* The following array element values are numbers of cycles should be
5752 added to improve insn scheduling for MM_insns for Itanium1. */
5754 static int *add_cycles
;
5756 static rtx
ia64_single_set (rtx
);
5757 static void ia64_emit_insn_before (rtx
, rtx
);
5759 /* Map a bundle number to its pseudo-op. */
5762 get_bundle_name (int b
)
5764 return bundle_name
[b
];
5768 /* Return the maximum number of instructions a cpu can issue. */
5771 ia64_issue_rate (void)
5776 /* Helper function - like single_set, but look inside COND_EXEC. */
5779 ia64_single_set (rtx insn
)
5781 rtx x
= PATTERN (insn
), ret
;
5782 if (GET_CODE (x
) == COND_EXEC
)
5783 x
= COND_EXEC_CODE (x
);
5784 if (GET_CODE (x
) == SET
)
5787 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5788 Although they are not classical single set, the second set is there just
5789 to protect it from moving past FP-relative stack accesses. */
5790 switch (recog_memoized (insn
))
5792 case CODE_FOR_prologue_allocate_stack
:
5793 case CODE_FOR_epilogue_deallocate_stack
:
5794 ret
= XVECEXP (x
, 0, 0);
5798 ret
= single_set_2 (insn
, x
);
5805 /* Adjust the cost of a scheduling dependency. Return the new cost of
5806 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5809 ia64_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
5811 enum attr_itanium_class dep_class
;
5812 enum attr_itanium_class insn_class
;
5814 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
5817 insn_class
= ia64_safe_itanium_class (insn
);
5818 dep_class
= ia64_safe_itanium_class (dep_insn
);
5819 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
5820 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
5826 /* Like emit_insn_before, but skip cycle_display notes.
5827 ??? When cycle display notes are implemented, update this. */
5830 ia64_emit_insn_before (rtx insn
, rtx before
)
5832 emit_insn_before (insn
, before
);
5835 /* The following function marks insns who produce addresses for load
5836 and store insns. Such insns will be placed into M slots because it
5837 decrease latency time for Itanium1 (see function
5838 `ia64_produce_address_p' and the DFA descriptions). */
5841 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
5843 rtx insn
, link
, next
, next_tail
;
5845 next_tail
= NEXT_INSN (tail
);
5846 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5849 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
5851 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
5853 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
5855 next
= XEXP (link
, 0);
5856 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
5857 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
5858 && ia64_st_address_bypass_p (insn
, next
))
5860 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
5861 || ia64_safe_itanium_class (next
)
5862 == ITANIUM_CLASS_FLD
)
5863 && ia64_ld_address_bypass_p (insn
, next
))
5866 insn
->call
= link
!= 0;
5870 /* We're beginning a new block. Initialize data structures as necessary. */
5873 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
5874 int sched_verbose ATTRIBUTE_UNUSED
,
5875 int max_ready ATTRIBUTE_UNUSED
)
5877 #ifdef ENABLE_CHECKING
5880 if (reload_completed
)
5881 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
5882 insn
!= current_sched_info
->next_tail
;
5883 insn
= NEXT_INSN (insn
))
5884 if (SCHED_GROUP_P (insn
))
5887 last_scheduled_insn
= NULL_RTX
;
5888 init_insn_group_barriers ();
5891 /* We are about to being issuing insns for this clock cycle.
5892 Override the default sort algorithm to better slot instructions. */
5895 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
5896 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
,
5900 int n_ready
= *pn_ready
;
5901 rtx
*e_ready
= ready
+ n_ready
;
5905 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
5907 if (reorder_type
== 0)
5909 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5911 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5912 if (insnp
< e_ready
)
5915 enum attr_type t
= ia64_safe_type (insn
);
5916 if (t
== TYPE_UNKNOWN
)
5918 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
5919 || asm_noperands (PATTERN (insn
)) >= 0)
5921 rtx lowest
= ready
[n_asms
];
5922 ready
[n_asms
] = insn
;
5928 rtx highest
= ready
[n_ready
- 1];
5929 ready
[n_ready
- 1] = insn
;
5936 if (n_asms
< n_ready
)
5938 /* Some normal insns to process. Skip the asms. */
5942 else if (n_ready
> 0)
5946 if (ia64_final_schedule
)
5949 int nr_need_stop
= 0;
5951 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
5952 if (safe_group_barrier_needed_p (*insnp
))
5955 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
5957 if (reorder_type
== 0)
5960 /* Move down everything that needs a stop bit, preserving
5962 while (insnp
-- > ready
+ deleted
)
5963 while (insnp
>= ready
+ deleted
)
5966 if (! safe_group_barrier_needed_p (insn
))
5968 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
5979 /* We are about to being issuing insns for this clock cycle. Override
5980 the default sort algorithm to better slot instructions. */
5983 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
5986 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
5987 pn_ready
, clock_var
, 0);
5990 /* Like ia64_sched_reorder, but called after issuing each insn.
5991 Override the default sort algorithm to better slot instructions. */
5994 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
5995 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
5996 int *pn_ready
, int clock_var
)
5998 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
5999 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
6000 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
6004 /* We are about to issue INSN. Return the number of insns left on the
6005 ready queue that can be issued this cycle. */
6008 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
6009 int sched_verbose ATTRIBUTE_UNUSED
,
6010 rtx insn ATTRIBUTE_UNUSED
,
6011 int can_issue_more ATTRIBUTE_UNUSED
)
6013 last_scheduled_insn
= insn
;
6014 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
6015 if (reload_completed
)
6017 if (group_barrier_needed_p (insn
))
6019 if (GET_CODE (insn
) == CALL_INSN
)
6020 init_insn_group_barriers ();
6021 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6027 /* We are choosing insn from the ready queue. Return nonzero if INSN
6031 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
6033 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6035 return (!reload_completed
6036 || !safe_group_barrier_needed_p (insn
));
6039 /* The following variable value is pseudo-insn used by the DFA insn
6040 scheduler to change the DFA state when the simulated clock is
6043 static rtx dfa_pre_cycle_insn
;
6045 /* We are about to being issuing INSN. Return nonzero if we can not
6046 issue it on given cycle CLOCK and return zero if we should not sort
6047 the ready queue on the next clock start. */
6050 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
6051 int clock
, int *sort_p
)
6053 int setup_clocks_p
= FALSE
;
6055 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6057 if ((reload_completed
&& safe_group_barrier_needed_p (insn
))
6058 || (last_scheduled_insn
6059 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6060 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6061 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6063 init_insn_group_barriers ();
6064 if (verbose
&& dump
)
6065 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6066 last_clock
== clock
? " + cycle advance" : "");
6068 if (last_clock
== clock
)
6070 state_transition (curr_state
, dfa_stop_insn
);
6071 if (TARGET_EARLY_STOP_BITS
)
6072 *sort_p
= (last_scheduled_insn
== NULL_RTX
6073 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6078 else if (reload_completed
)
6079 setup_clocks_p
= TRUE
;
6080 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6081 state_transition (curr_state
, dfa_stop_insn
);
6082 state_transition (curr_state
, dfa_pre_cycle_insn
);
6083 state_transition (curr_state
, NULL
);
6085 else if (reload_completed
)
6086 setup_clocks_p
= TRUE
;
6087 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
)
6089 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6091 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6096 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6097 if (REG_NOTE_KIND (link
) == 0)
6099 enum attr_itanium_class dep_class
;
6100 rtx dep_insn
= XEXP (link
, 0);
6102 dep_class
= ia64_safe_itanium_class (dep_insn
);
6103 if ((dep_class
== ITANIUM_CLASS_MMMUL
6104 || dep_class
== ITANIUM_CLASS_MMSHF
)
6105 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6107 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6108 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6111 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6119 /* The following page contains abstract data `bundle states' which are
6120 used for bundling insns (inserting nops and template generation). */
6122 /* The following describes state of insn bundling. */
6126 /* Unique bundle state number to identify them in the debugging
6129 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6130 /* number nops before and after the insn */
6131 short before_nops_num
, after_nops_num
;
6132 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6134 int cost
; /* cost of the state in cycles */
6135 int accumulated_insns_num
; /* number of all previous insns including
6136 nops. L is considered as 2 insns */
6137 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6138 struct bundle_state
*next
; /* next state with the same insn_num */
6139 struct bundle_state
*originator
; /* originator (previous insn state) */
6140 /* All bundle states are in the following chain. */
6141 struct bundle_state
*allocated_states_chain
;
6142 /* The DFA State after issuing the insn and the nops. */
6146 /* The following is map insn number to the corresponding bundle state. */
6148 static struct bundle_state
**index_to_bundle_states
;
6150 /* The unique number of next bundle state. */
6152 static int bundle_states_num
;
6154 /* All allocated bundle states are in the following chain. */
6156 static struct bundle_state
*allocated_bundle_states_chain
;
6158 /* All allocated but not used bundle states are in the following
6161 static struct bundle_state
*free_bundle_state_chain
;
6164 /* The following function returns a free bundle state. */
6166 static struct bundle_state
*
6167 get_free_bundle_state (void)
6169 struct bundle_state
*result
;
6171 if (free_bundle_state_chain
!= NULL
)
6173 result
= free_bundle_state_chain
;
6174 free_bundle_state_chain
= result
->next
;
6178 result
= xmalloc (sizeof (struct bundle_state
));
6179 result
->dfa_state
= xmalloc (dfa_state_size
);
6180 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6181 allocated_bundle_states_chain
= result
;
6183 result
->unique_num
= bundle_states_num
++;
6188 /* The following function frees given bundle state. */
6191 free_bundle_state (struct bundle_state
*state
)
6193 state
->next
= free_bundle_state_chain
;
6194 free_bundle_state_chain
= state
;
6197 /* Start work with abstract data `bundle states'. */
6200 initiate_bundle_states (void)
6202 bundle_states_num
= 0;
6203 free_bundle_state_chain
= NULL
;
6204 allocated_bundle_states_chain
= NULL
;
6207 /* Finish work with abstract data `bundle states'. */
6210 finish_bundle_states (void)
6212 struct bundle_state
*curr_state
, *next_state
;
6214 for (curr_state
= allocated_bundle_states_chain
;
6216 curr_state
= next_state
)
6218 next_state
= curr_state
->allocated_states_chain
;
6219 free (curr_state
->dfa_state
);
6224 /* Hash table of the bundle states. The key is dfa_state and insn_num
6225 of the bundle states. */
6227 static htab_t bundle_state_table
;
6229 /* The function returns hash of BUNDLE_STATE. */
6232 bundle_state_hash (const void *bundle_state
)
6234 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6237 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6238 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6239 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6240 return result
+ state
->insn_num
;
6243 /* The function returns nonzero if the bundle state keys are equal. */
6246 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
6248 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6249 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6251 return (state1
->insn_num
== state2
->insn_num
6252 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6253 dfa_state_size
) == 0);
6256 /* The function inserts the BUNDLE_STATE into the hash table. The
6257 function returns nonzero if the bundle has been inserted into the
6258 table. The table contains the best bundle state with given key. */
6261 insert_bundle_state (struct bundle_state
*bundle_state
)
6265 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6266 if (*entry_ptr
== NULL
)
6268 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6269 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6270 *entry_ptr
= (void *) bundle_state
;
6273 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6274 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6275 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6276 > bundle_state
->accumulated_insns_num
6277 || (((struct bundle_state
*)
6278 *entry_ptr
)->accumulated_insns_num
6279 == bundle_state
->accumulated_insns_num
6280 && ((struct bundle_state
*)
6281 *entry_ptr
)->branch_deviation
6282 > bundle_state
->branch_deviation
))))
6285 struct bundle_state temp
;
6287 temp
= *(struct bundle_state
*) *entry_ptr
;
6288 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6289 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6290 *bundle_state
= temp
;
6295 /* Start work with the hash table. */
6298 initiate_bundle_state_table (void)
6300 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6304 /* Finish work with the hash table. */
6307 finish_bundle_state_table (void)
6309 htab_delete (bundle_state_table
);
6314 /* The following variable is a insn `nop' used to check bundle states
6315 with different number of inserted nops. */
6317 static rtx ia64_nop
;
6319 /* The following function tries to issue NOPS_NUM nops for the current
6320 state without advancing processor cycle. If it failed, the
6321 function returns FALSE and frees the current state. */
6324 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
6328 for (i
= 0; i
< nops_num
; i
++)
6329 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6331 free_bundle_state (curr_state
);
6337 /* The following function tries to issue INSN for the current
6338 state without advancing processor cycle. If it failed, the
6339 function returns FALSE and frees the current state. */
6342 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
6344 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6346 free_bundle_state (curr_state
);
6352 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6353 starting with ORIGINATOR without advancing processor cycle. If
6354 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6355 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6356 If it was successful, the function creates new bundle state and
6357 insert into the hash table and into `index_to_bundle_states'. */
6360 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
6361 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
6363 struct bundle_state
*curr_state
;
6365 curr_state
= get_free_bundle_state ();
6366 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6367 curr_state
->insn
= insn
;
6368 curr_state
->insn_num
= originator
->insn_num
+ 1;
6369 curr_state
->cost
= originator
->cost
;
6370 curr_state
->originator
= originator
;
6371 curr_state
->before_nops_num
= before_nops_num
;
6372 curr_state
->after_nops_num
= 0;
6373 curr_state
->accumulated_insns_num
6374 = originator
->accumulated_insns_num
+ before_nops_num
;
6375 curr_state
->branch_deviation
= originator
->branch_deviation
;
6376 if (insn
== NULL_RTX
)
6378 else if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6380 if (GET_MODE (insn
) == TImode
)
6382 if (!try_issue_nops (curr_state
, before_nops_num
))
6384 if (!try_issue_insn (curr_state
, insn
))
6386 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6387 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6388 && curr_state
->accumulated_insns_num
% 3 != 0)
6390 free_bundle_state (curr_state
);
6394 else if (GET_MODE (insn
) != TImode
)
6396 if (!try_issue_nops (curr_state
, before_nops_num
))
6398 if (!try_issue_insn (curr_state
, insn
))
6400 curr_state
->accumulated_insns_num
++;
6401 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6402 || asm_noperands (PATTERN (insn
)) >= 0)
6404 if (ia64_safe_type (insn
) == TYPE_L
)
6405 curr_state
->accumulated_insns_num
++;
6409 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6410 state_transition (curr_state
->dfa_state
, NULL
);
6412 if (!try_issue_nops (curr_state
, before_nops_num
))
6414 if (!try_issue_insn (curr_state
, insn
))
6416 curr_state
->accumulated_insns_num
++;
6417 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6418 || asm_noperands (PATTERN (insn
)) >= 0)
6420 /* Finish bundle containing asm insn. */
6421 curr_state
->after_nops_num
6422 = 3 - curr_state
->accumulated_insns_num
% 3;
6423 curr_state
->accumulated_insns_num
6424 += 3 - curr_state
->accumulated_insns_num
% 3;
6426 else if (ia64_safe_type (insn
) == TYPE_L
)
6427 curr_state
->accumulated_insns_num
++;
6429 if (ia64_safe_type (insn
) == TYPE_B
)
6430 curr_state
->branch_deviation
6431 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6432 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6434 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6437 struct bundle_state
*curr_state1
;
6438 struct bundle_state
*allocated_states_chain
;
6440 curr_state1
= get_free_bundle_state ();
6441 dfa_state
= curr_state1
->dfa_state
;
6442 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6443 *curr_state1
= *curr_state
;
6444 curr_state1
->dfa_state
= dfa_state
;
6445 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6446 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6448 curr_state
= curr_state1
;
6450 if (!try_issue_nops (curr_state
,
6451 3 - curr_state
->accumulated_insns_num
% 3))
6453 curr_state
->after_nops_num
6454 = 3 - curr_state
->accumulated_insns_num
% 3;
6455 curr_state
->accumulated_insns_num
6456 += 3 - curr_state
->accumulated_insns_num
% 3;
6458 if (!insert_bundle_state (curr_state
))
6459 free_bundle_state (curr_state
);
6463 /* The following function returns position in the two window bundle
6467 get_max_pos (state_t state
)
6469 if (cpu_unit_reservation_p (state
, pos_6
))
6471 else if (cpu_unit_reservation_p (state
, pos_5
))
6473 else if (cpu_unit_reservation_p (state
, pos_4
))
6475 else if (cpu_unit_reservation_p (state
, pos_3
))
6477 else if (cpu_unit_reservation_p (state
, pos_2
))
6479 else if (cpu_unit_reservation_p (state
, pos_1
))
6485 /* The function returns code of a possible template for given position
6486 and state. The function should be called only with 2 values of
6487 position equal to 3 or 6. */
6490 get_template (state_t state
, int pos
)
6495 if (cpu_unit_reservation_p (state
, _0mii_
))
6497 else if (cpu_unit_reservation_p (state
, _0mmi_
))
6499 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6501 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6503 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6505 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6507 else if (cpu_unit_reservation_p (state
, _0mib_
))
6509 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6511 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6513 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6518 if (cpu_unit_reservation_p (state
, _1mii_
))
6520 else if (cpu_unit_reservation_p (state
, _1mmi_
))
6522 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6524 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6526 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6528 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6530 else if (cpu_unit_reservation_p (state
, _1mib_
))
6532 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6534 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6536 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6545 /* The following function returns an insn important for insn bundling
6546 followed by INSN and before TAIL. */
6549 get_next_important_insn (rtx insn
, rtx tail
)
6551 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6553 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6554 && GET_CODE (PATTERN (insn
)) != USE
6555 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6560 /* The following function does insn bundling. Bundling algorithm is
6561 based on dynamic programming. It tries to insert different number of
6562 nop insns before/after the real insns. At the end of EBB, it chooses the
6563 best alternative and then, moving back in EBB, inserts templates for
6564 the best alternative. The algorithm is directed by information
6565 (changes of simulated processor cycle) created by the 2nd insn
6569 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
6571 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6572 rtx insn
, next_insn
;
6574 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6575 int pos
= 0, max_pos
, template0
, template1
;
6578 enum attr_type type
;
6581 for (insn
= NEXT_INSN (prev_head_insn
);
6582 insn
&& insn
!= tail
;
6583 insn
= NEXT_INSN (insn
))
6589 dfa_clean_insn_cache ();
6590 initiate_bundle_state_table ();
6591 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6592 * sizeof (struct bundle_state
*));
6593 /* First (forward) pass -- generates states. */
6594 curr_state
= get_free_bundle_state ();
6595 curr_state
->insn
= NULL
;
6596 curr_state
->before_nops_num
= 0;
6597 curr_state
->after_nops_num
= 0;
6598 curr_state
->insn_num
= 0;
6599 curr_state
->cost
= 0;
6600 curr_state
->accumulated_insns_num
= 0;
6601 curr_state
->branch_deviation
= 0;
6602 curr_state
->next
= NULL
;
6603 curr_state
->originator
= NULL
;
6604 state_reset (curr_state
->dfa_state
);
6605 index_to_bundle_states
[0] = curr_state
;
6607 for (insn
= NEXT_INSN (prev_head_insn
);
6609 insn
= NEXT_INSN (insn
))
6611 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6612 || GET_CODE (PATTERN (insn
)) == USE
6613 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6614 && GET_MODE (insn
) == TImode
)
6616 PUT_MODE (insn
, VOIDmode
);
6617 for (next_insn
= NEXT_INSN (insn
);
6619 next_insn
= NEXT_INSN (next_insn
))
6620 if (INSN_P (next_insn
)
6621 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6622 && GET_CODE (PATTERN (next_insn
)) != USE
6623 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6625 PUT_MODE (next_insn
, TImode
);
6629 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6634 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6635 || GET_CODE (PATTERN (insn
)) == USE
6636 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6638 type
= ia64_safe_type (insn
);
6639 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6641 index_to_bundle_states
[insn_num
] = NULL
;
6642 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6644 curr_state
= next_state
)
6646 pos
= curr_state
->accumulated_insns_num
% 3;
6647 next_state
= curr_state
->next
;
6648 /* Finish the current bundle in order to start a subsequent
6649 asm insn in a new bundle. */
6651 = (next_insn
!= NULL_RTX
6652 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6653 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6655 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6656 || (GET_MODE (next_insn
) == TImode
6657 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6658 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6660 /* We need to insert 2 Nops for cases like M_MII. */
6661 || (type
== TYPE_M
&& ia64_tune
== PROCESSOR_ITANIUM
6662 && !bundle_end_p
&& pos
== 1))
6663 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6665 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6667 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6670 if (index_to_bundle_states
[insn_num
] == NULL
)
6672 for (curr_state
= index_to_bundle_states
[insn_num
];
6674 curr_state
= curr_state
->next
)
6675 if (verbose
>= 2 && dump
)
6679 unsigned short one_automaton_state
;
6680 unsigned short oneb_automaton_state
;
6681 unsigned short two_automaton_state
;
6682 unsigned short twob_automaton_state
;
6687 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6688 curr_state
->unique_num
,
6689 (curr_state
->originator
== NULL
6690 ? -1 : curr_state
->originator
->unique_num
),
6692 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6693 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6694 (ia64_tune
== PROCESSOR_ITANIUM
6695 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6696 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6700 if (index_to_bundle_states
[insn_num
] == NULL
)
6702 /* Finding state with a minimal cost: */
6704 for (curr_state
= index_to_bundle_states
[insn_num
];
6706 curr_state
= curr_state
->next
)
6707 if (curr_state
->accumulated_insns_num
% 3 == 0
6708 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
6709 || (best_state
->cost
== curr_state
->cost
6710 && (curr_state
->accumulated_insns_num
6711 < best_state
->accumulated_insns_num
6712 || (curr_state
->accumulated_insns_num
6713 == best_state
->accumulated_insns_num
6714 && curr_state
->branch_deviation
6715 < best_state
->branch_deviation
)))))
6716 best_state
= curr_state
;
6717 /* Second (backward) pass: adding nops and templates: */
6718 insn_num
= best_state
->before_nops_num
;
6719 template0
= template1
= -1;
6720 for (curr_state
= best_state
;
6721 curr_state
->originator
!= NULL
;
6722 curr_state
= curr_state
->originator
)
6724 insn
= curr_state
->insn
;
6725 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6726 || asm_noperands (PATTERN (insn
)) >= 0);
6728 if (verbose
>= 2 && dump
)
6732 unsigned short one_automaton_state
;
6733 unsigned short oneb_automaton_state
;
6734 unsigned short two_automaton_state
;
6735 unsigned short twob_automaton_state
;
6740 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6741 curr_state
->unique_num
,
6742 (curr_state
->originator
== NULL
6743 ? -1 : curr_state
->originator
->unique_num
),
6745 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6746 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6747 (ia64_tune
== PROCESSOR_ITANIUM
6748 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6749 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
6752 max_pos
= get_max_pos (curr_state
->dfa_state
);
6753 if (max_pos
== 6 || (max_pos
== 3 && template0
< 0))
6757 template0
= get_template (curr_state
->dfa_state
, 3);
6760 template1
= get_template (curr_state
->dfa_state
, 3);
6761 template0
= get_template (curr_state
->dfa_state
, 6);
6764 if (max_pos
> 3 && template1
< 0)
6768 template1
= get_template (curr_state
->dfa_state
, 3);
6772 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
6775 emit_insn_after (nop
, insn
);
6783 b
= gen_bundle_selector (GEN_INT (template0
));
6784 ia64_emit_insn_before (b
, nop
);
6785 template0
= template1
;
6789 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6790 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6791 && asm_noperands (PATTERN (insn
)) < 0)
6793 if (ia64_safe_type (insn
) == TYPE_L
)
6798 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
6799 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6800 && asm_noperands (PATTERN (insn
)) < 0)
6804 b
= gen_bundle_selector (GEN_INT (template0
));
6805 ia64_emit_insn_before (b
, insn
);
6806 b
= PREV_INSN (insn
);
6808 template0
= template1
;
6811 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
6814 ia64_emit_insn_before (nop
, insn
);
6815 nop
= PREV_INSN (insn
);
6824 b
= gen_bundle_selector (GEN_INT (template0
));
6825 ia64_emit_insn_before (b
, insn
);
6826 b
= PREV_INSN (insn
);
6828 template0
= template1
;
6833 if (ia64_tune
== PROCESSOR_ITANIUM
)
6834 /* Insert additional cycles for MM-insns: */
6835 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6840 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6841 || GET_CODE (PATTERN (insn
)) == USE
6842 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6844 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6845 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
6851 last
= prev_active_insn (insn
);
6852 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
6854 last
= prev_active_insn (last
);
6856 for (;; last
= prev_active_insn (last
))
6857 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
6859 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
6862 = gen_bundle_selector (GEN_INT (2)); /* -> MFI */
6865 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6867 if ((pred_stop_p
&& n
== 0) || n
> 2
6868 || (template0
== 9 && n
!= 0))
6870 for (j
= 3 - n
; j
> 0; j
--)
6871 ia64_emit_insn_before (gen_nop (), insn
);
6872 add_cycles
[INSN_UID (insn
)]--;
6873 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
6874 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6877 add_cycles
[INSN_UID (insn
)]--;
6878 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
6880 /* Insert .MII bundle. */
6881 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
6883 ia64_emit_insn_before (gen_nop (), insn
);
6884 ia64_emit_insn_before (gen_nop (), insn
);
6887 ia64_emit_insn_before
6888 (gen_insn_group_barrier (GEN_INT (3)), insn
);
6891 ia64_emit_insn_before (gen_nop (), insn
);
6892 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6895 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
6897 for (j
= n
; j
> 0; j
--)
6898 ia64_emit_insn_before (gen_nop (), insn
);
6900 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6904 free (index_to_bundle_states
);
6905 finish_bundle_state_table ();
6907 dfa_clean_insn_cache ();
6910 /* The following function is called at the end of scheduling BB or
6911 EBB. After reload, it inserts stop bits and does insn bundling. */
6914 ia64_sched_finish (FILE *dump
, int sched_verbose
)
6917 fprintf (dump
, "// Finishing schedule.\n");
6918 if (!reload_completed
)
6920 if (reload_completed
)
6922 final_emit_insn_group_barriers (dump
);
6923 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
6924 current_sched_info
->next_tail
);
6925 if (sched_verbose
&& dump
)
6926 fprintf (dump
, "// finishing %d-%d\n",
6927 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
6928 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
6934 /* The following function inserts stop bits in scheduled BB or EBB. */
6937 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
6940 int need_barrier_p
= 0;
6941 rtx prev_insn
= NULL_RTX
;
6943 init_insn_group_barriers ();
6945 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6946 insn
!= current_sched_info
->next_tail
;
6947 insn
= NEXT_INSN (insn
))
6949 if (GET_CODE (insn
) == BARRIER
)
6951 rtx last
= prev_active_insn (insn
);
6955 if (GET_CODE (last
) == JUMP_INSN
6956 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
6957 last
= prev_active_insn (last
);
6958 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6959 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
6961 init_insn_group_barriers ();
6963 prev_insn
= NULL_RTX
;
6965 else if (INSN_P (insn
))
6967 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
6969 init_insn_group_barriers ();
6971 prev_insn
= NULL_RTX
;
6973 else if (need_barrier_p
|| group_barrier_needed_p (insn
))
6975 if (TARGET_EARLY_STOP_BITS
)
6980 last
!= current_sched_info
->prev_head
;
6981 last
= PREV_INSN (last
))
6982 if (INSN_P (last
) && GET_MODE (last
) == TImode
6983 && stops_p
[INSN_UID (last
)])
6985 if (last
== current_sched_info
->prev_head
)
6987 last
= prev_active_insn (last
);
6989 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
6990 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
6992 init_insn_group_barriers ();
6993 for (last
= NEXT_INSN (last
);
6995 last
= NEXT_INSN (last
))
6997 group_barrier_needed_p (last
);
7001 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7003 init_insn_group_barriers ();
7005 group_barrier_needed_p (insn
);
7006 prev_insn
= NULL_RTX
;
7008 else if (recog_memoized (insn
) >= 0)
7010 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7011 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7012 || asm_noperands (PATTERN (insn
)) >= 0);
7019 /* If the following function returns TRUE, we will use the the DFA
7023 ia64_use_dfa_pipeline_interface (void)
7028 /* If the following function returns TRUE, we will use the the DFA
7032 ia64_first_cycle_multipass_dfa_lookahead (void)
7034 return (reload_completed
? 6 : 4);
7037 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7040 ia64_init_dfa_pre_cycle_insn (void)
7042 if (temp_dfa_state
== NULL
)
7044 dfa_state_size
= state_size ();
7045 temp_dfa_state
= xmalloc (dfa_state_size
);
7046 prev_cycle_state
= xmalloc (dfa_state_size
);
7048 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7049 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7050 recog_memoized (dfa_pre_cycle_insn
);
7051 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7052 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7053 recog_memoized (dfa_stop_insn
);
7056 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7057 used by the DFA insn scheduler. */
7060 ia64_dfa_pre_cycle_insn (void)
7062 return dfa_pre_cycle_insn
;
7065 /* The following function returns TRUE if PRODUCER (of type ilog or
7066 ld) produces address for CONSUMER (of type st or stf). */
7069 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
7073 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7075 dest
= ia64_single_set (producer
);
7076 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7077 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7079 if (GET_CODE (reg
) == SUBREG
)
7080 reg
= SUBREG_REG (reg
);
7081 dest
= ia64_single_set (consumer
);
7082 if (dest
== NULL_RTX
|| (mem
= SET_DEST (dest
)) == NULL_RTX
7083 || GET_CODE (mem
) != MEM
)
7085 return reg_mentioned_p (reg
, mem
);
7088 /* The following function returns TRUE if PRODUCER (of type ilog or
7089 ld) produces address for CONSUMER (of type ld or fld). */
7092 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
7094 rtx dest
, src
, reg
, mem
;
7096 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7098 dest
= ia64_single_set (producer
);
7099 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7100 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7102 if (GET_CODE (reg
) == SUBREG
)
7103 reg
= SUBREG_REG (reg
);
7104 src
= ia64_single_set (consumer
);
7105 if (src
== NULL_RTX
|| (mem
= SET_SRC (src
)) == NULL_RTX
)
7107 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7108 mem
= XVECEXP (mem
, 0, 0);
7109 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7110 mem
= XEXP (mem
, 0);
7112 /* Note that LO_SUM is used for GOT loads. */
7113 if (GET_CODE (mem
) != LO_SUM
&& GET_CODE (mem
) != MEM
)
7116 return reg_mentioned_p (reg
, mem
);
7119 /* The following function returns TRUE if INSN produces address for a
7120 load/store insn. We will place such insns into M slot because it
7121 decreases its latency time. */
7124 ia64_produce_address_p (rtx insn
)
7130 /* Emit pseudo-ops for the assembler to describe predicate relations.
7131 At present this assumes that we only consider predicate pairs to
7132 be mutex, and that the assembler can deduce proper values from
7133 straight-line code. */
7136 emit_predicate_relation_info (void)
7140 FOR_EACH_BB_REVERSE (bb
)
7143 rtx head
= BB_HEAD (bb
);
7145 /* We only need such notes at code labels. */
7146 if (GET_CODE (head
) != CODE_LABEL
)
7148 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7149 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7150 head
= NEXT_INSN (head
);
7152 for (r
= PR_REG (0); r
< PR_REG (64); r
+= 2)
7153 if (REGNO_REG_SET_P (bb
->global_live_at_start
, r
))
7155 rtx p
= gen_rtx_REG (BImode
, r
);
7156 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7157 if (head
== BB_END (bb
))
7163 /* Look for conditional calls that do not return, and protect predicate
7164 relations around them. Otherwise the assembler will assume the call
7165 returns, and complain about uses of call-clobbered predicates after
7167 FOR_EACH_BB_REVERSE (bb
)
7169 rtx insn
= BB_HEAD (bb
);
7173 if (GET_CODE (insn
) == CALL_INSN
7174 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7175 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7177 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7178 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7179 if (BB_HEAD (bb
) == insn
)
7181 if (BB_END (bb
) == insn
)
7185 if (insn
== BB_END (bb
))
7187 insn
= NEXT_INSN (insn
);
7192 /* Perform machine dependent operations on the rtl chain INSNS. */
7197 /* We are freeing block_for_insn in the toplev to keep compatibility
7198 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7199 compute_bb_for_insn ();
7201 /* If optimizing, we'll have split before scheduling. */
7203 split_all_insns (0);
7205 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7206 non-optimizing bootstrap. */
7207 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7209 if (ia64_flag_schedule_insns2
)
7211 timevar_push (TV_SCHED2
);
7212 ia64_final_schedule
= 1;
7214 initiate_bundle_states ();
7215 ia64_nop
= make_insn_raw (gen_nop ());
7216 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7217 recog_memoized (ia64_nop
);
7218 clocks_length
= get_max_uid () + 1;
7219 stops_p
= xcalloc (1, clocks_length
);
7220 if (ia64_tune
== PROCESSOR_ITANIUM
)
7222 clocks
= xcalloc (clocks_length
, sizeof (int));
7223 add_cycles
= xcalloc (clocks_length
, sizeof (int));
7225 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7227 pos_1
= get_cpu_unit_code ("2_1");
7228 pos_2
= get_cpu_unit_code ("2_2");
7229 pos_3
= get_cpu_unit_code ("2_3");
7230 pos_4
= get_cpu_unit_code ("2_4");
7231 pos_5
= get_cpu_unit_code ("2_5");
7232 pos_6
= get_cpu_unit_code ("2_6");
7233 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7234 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7235 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7236 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7237 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7238 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7239 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7240 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7241 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7242 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7243 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7244 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7245 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7246 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7247 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7248 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7249 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7250 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7251 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7252 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7256 pos_1
= get_cpu_unit_code ("1_1");
7257 pos_2
= get_cpu_unit_code ("1_2");
7258 pos_3
= get_cpu_unit_code ("1_3");
7259 pos_4
= get_cpu_unit_code ("1_4");
7260 pos_5
= get_cpu_unit_code ("1_5");
7261 pos_6
= get_cpu_unit_code ("1_6");
7262 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7263 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7264 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7265 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7266 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7267 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7268 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7269 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7270 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7271 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7272 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7273 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7274 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7275 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7276 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7277 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7278 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7279 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7280 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7281 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7283 schedule_ebbs (rtl_dump_file
);
7284 finish_bundle_states ();
7285 if (ia64_tune
== PROCESSOR_ITANIUM
)
7291 emit_insn_group_barriers (rtl_dump_file
);
7293 ia64_final_schedule
= 0;
7294 timevar_pop (TV_SCHED2
);
7297 emit_all_insn_group_barriers (rtl_dump_file
);
7299 /* A call must not be the last instruction in a function, so that the
7300 return address is still within the function, so that unwinding works
7301 properly. Note that IA-64 differs from dwarf2 on this point. */
7302 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7307 insn
= get_last_insn ();
7308 if (! INSN_P (insn
))
7309 insn
= prev_active_insn (insn
);
7310 if (GET_CODE (insn
) == INSN
7311 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7312 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7315 insn
= prev_active_insn (insn
);
7317 if (GET_CODE (insn
) == CALL_INSN
)
7320 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7321 emit_insn (gen_break_f ());
7322 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7327 emit_predicate_relation_info ();
7330 /* Return true if REGNO is used by the epilogue. */
7333 ia64_epilogue_uses (int regno
)
7338 /* With a call to a function in another module, we will write a new
7339 value to "gp". After returning from such a call, we need to make
7340 sure the function restores the original gp-value, even if the
7341 function itself does not use the gp anymore. */
7342 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
7344 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7345 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7346 /* For functions defined with the syscall_linkage attribute, all
7347 input registers are marked as live at all function exits. This
7348 prevents the register allocator from using the input registers,
7349 which in turn makes it possible to restart a system call after
7350 an interrupt without having to save/restore the input registers.
7351 This also prevents kernel data from leaking to application code. */
7352 return lookup_attribute ("syscall_linkage",
7353 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7356 /* Conditional return patterns can't represent the use of `b0' as
7357 the return address, so we force the value live this way. */
7361 /* Likewise for ar.pfs, which is used by br.ret. */
7369 /* Return true if REGNO is used by the frame unwinder. */
7372 ia64_eh_uses (int regno
)
7374 if (! reload_completed
)
7377 if (current_frame_info
.reg_save_b0
7378 && regno
== current_frame_info
.reg_save_b0
)
7380 if (current_frame_info
.reg_save_pr
7381 && regno
== current_frame_info
.reg_save_pr
)
7383 if (current_frame_info
.reg_save_ar_pfs
7384 && regno
== current_frame_info
.reg_save_ar_pfs
)
7386 if (current_frame_info
.reg_save_ar_unat
7387 && regno
== current_frame_info
.reg_save_ar_unat
)
7389 if (current_frame_info
.reg_save_ar_lc
7390 && regno
== current_frame_info
.reg_save_ar_lc
)
7396 /* Return true if this goes in small data/bss. */
7398 /* ??? We could also support own long data here. Generating movl/add/ld8
7399 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7400 code faster because there is one less load. This also includes incomplete
7401 types which can't go in sdata/sbss. */
7404 ia64_in_small_data_p (tree exp
)
7406 if (TARGET_NO_SDATA
)
7409 /* We want to merge strings, so we never consider them small data. */
7410 if (TREE_CODE (exp
) == STRING_CST
)
7413 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7415 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7416 if (strcmp (section
, ".sdata") == 0
7417 || strcmp (section
, ".sbss") == 0)
7422 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7424 /* If this is an incomplete type with size 0, then we can't put it
7425 in sdata because it might be too big when completed. */
7426 if (size
> 0 && size
<= ia64_section_threshold
)
7433 /* Output assembly directives for prologue regions. */
7435 /* The current basic block number. */
7437 static bool last_block
;
7439 /* True if we need a copy_state command at the start of the next block. */
7441 static bool need_copy_state
;
7443 /* The function emits unwind directives for the start of an epilogue. */
7446 process_epilogue (void)
7448 /* If this isn't the last block of the function, then we need to label the
7449 current state, and copy it back in at the start of the next block. */
7453 fprintf (asm_out_file
, "\t.label_state 1\n");
7454 need_copy_state
= true;
7457 fprintf (asm_out_file
, "\t.restore sp\n");
7460 /* This function processes a SET pattern looking for specific patterns
7461 which result in emitting an assembly directive required for unwinding. */
7464 process_set (FILE *asm_out_file
, rtx pat
)
7466 rtx src
= SET_SRC (pat
);
7467 rtx dest
= SET_DEST (pat
);
7468 int src_regno
, dest_regno
;
7470 /* Look for the ALLOC insn. */
7471 if (GET_CODE (src
) == UNSPEC_VOLATILE
7472 && XINT (src
, 1) == UNSPECV_ALLOC
7473 && GET_CODE (dest
) == REG
)
7475 dest_regno
= REGNO (dest
);
7477 /* If this isn't the final destination for ar.pfs, the alloc
7478 shouldn't have been marked frame related. */
7479 if (dest_regno
!= current_frame_info
.reg_save_ar_pfs
)
7482 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7483 ia64_dbx_register_number (dest_regno
));
7487 /* Look for SP = .... */
7488 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7490 if (GET_CODE (src
) == PLUS
)
7492 rtx op0
= XEXP (src
, 0);
7493 rtx op1
= XEXP (src
, 1);
7494 if (op0
== dest
&& GET_CODE (op1
) == CONST_INT
)
7496 if (INTVAL (op1
) < 0)
7497 fprintf (asm_out_file
, "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
7500 process_epilogue ();
7505 else if (GET_CODE (src
) == REG
7506 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
7507 process_epilogue ();
7514 /* Register move we need to look at. */
7515 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7517 src_regno
= REGNO (src
);
7518 dest_regno
= REGNO (dest
);
7523 /* Saving return address pointer. */
7524 if (dest_regno
!= current_frame_info
.reg_save_b0
)
7526 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7527 ia64_dbx_register_number (dest_regno
));
7531 if (dest_regno
!= current_frame_info
.reg_save_pr
)
7533 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7534 ia64_dbx_register_number (dest_regno
));
7537 case AR_UNAT_REGNUM
:
7538 if (dest_regno
!= current_frame_info
.reg_save_ar_unat
)
7540 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7541 ia64_dbx_register_number (dest_regno
));
7545 if (dest_regno
!= current_frame_info
.reg_save_ar_lc
)
7547 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7548 ia64_dbx_register_number (dest_regno
));
7551 case STACK_POINTER_REGNUM
:
7552 if (dest_regno
!= HARD_FRAME_POINTER_REGNUM
7553 || ! frame_pointer_needed
)
7555 fprintf (asm_out_file
, "\t.vframe r%d\n",
7556 ia64_dbx_register_number (dest_regno
));
7560 /* Everything else should indicate being stored to memory. */
7565 /* Memory store we need to look at. */
7566 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7572 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7574 base
= XEXP (dest
, 0);
7577 else if (GET_CODE (XEXP (dest
, 0)) == PLUS
7578 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
)
7580 base
= XEXP (XEXP (dest
, 0), 0);
7581 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7586 if (base
== hard_frame_pointer_rtx
)
7588 saveop
= ".savepsp";
7591 else if (base
== stack_pointer_rtx
)
7596 src_regno
= REGNO (src
);
7600 if (current_frame_info
.reg_save_b0
!= 0)
7602 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7606 if (current_frame_info
.reg_save_pr
!= 0)
7608 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7612 if (current_frame_info
.reg_save_ar_lc
!= 0)
7614 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7618 if (current_frame_info
.reg_save_ar_pfs
!= 0)
7620 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7623 case AR_UNAT_REGNUM
:
7624 if (current_frame_info
.reg_save_ar_unat
!= 0)
7626 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
7633 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
7634 1 << (src_regno
- GR_REG (4)));
7642 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
7643 1 << (src_regno
- BR_REG (1)));
7650 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
7651 1 << (src_regno
- FR_REG (2)));
7654 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7655 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7656 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7657 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7658 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
7659 1 << (src_regno
- FR_REG (12)));
7671 /* This function looks at a single insn and emits any directives
7672 required to unwind this insn. */
7674 process_for_unwind_directive (FILE *asm_out_file
, rtx insn
)
7676 if (flag_unwind_tables
7677 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7681 if (GET_CODE (insn
) == NOTE
7682 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
7684 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
7686 /* Restore unwind state from immediately before the epilogue. */
7687 if (need_copy_state
)
7689 fprintf (asm_out_file
, "\t.body\n");
7690 fprintf (asm_out_file
, "\t.copy_state 1\n");
7691 need_copy_state
= false;
7695 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
7698 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
7700 pat
= XEXP (pat
, 0);
7702 pat
= PATTERN (insn
);
7704 switch (GET_CODE (pat
))
7707 process_set (asm_out_file
, pat
);
7713 int limit
= XVECLEN (pat
, 0);
7714 for (par_index
= 0; par_index
< limit
; par_index
++)
7716 rtx x
= XVECEXP (pat
, 0, par_index
);
7717 if (GET_CODE (x
) == SET
)
7718 process_set (asm_out_file
, x
);
7731 ia64_init_builtins (void)
7733 tree psi_type_node
= build_pointer_type (integer_type_node
);
7734 tree pdi_type_node
= build_pointer_type (long_integer_type_node
);
7736 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7737 tree si_ftype_psi_si_si
7738 = build_function_type_list (integer_type_node
,
7739 psi_type_node
, integer_type_node
,
7740 integer_type_node
, NULL_TREE
);
7742 /* __sync_val_compare_and_swap_di */
7743 tree di_ftype_pdi_di_di
7744 = build_function_type_list (long_integer_type_node
,
7745 pdi_type_node
, long_integer_type_node
,
7746 long_integer_type_node
, NULL_TREE
);
7747 /* __sync_bool_compare_and_swap_di */
7748 tree si_ftype_pdi_di_di
7749 = build_function_type_list (integer_type_node
,
7750 pdi_type_node
, long_integer_type_node
,
7751 long_integer_type_node
, NULL_TREE
);
7752 /* __sync_synchronize */
7753 tree void_ftype_void
7754 = build_function_type (void_type_node
, void_list_node
);
7756 /* __sync_lock_test_and_set_si */
7757 tree si_ftype_psi_si
7758 = build_function_type_list (integer_type_node
,
7759 psi_type_node
, integer_type_node
, NULL_TREE
);
7761 /* __sync_lock_test_and_set_di */
7762 tree di_ftype_pdi_di
7763 = build_function_type_list (long_integer_type_node
,
7764 pdi_type_node
, long_integer_type_node
,
7767 /* __sync_lock_release_si */
7769 = build_function_type_list (void_type_node
, psi_type_node
, NULL_TREE
);
7771 /* __sync_lock_release_di */
7773 = build_function_type_list (void_type_node
, pdi_type_node
, NULL_TREE
);
7778 /* The __fpreg type. */
7779 fpreg_type
= make_node (REAL_TYPE
);
7780 /* ??? The back end should know to load/save __fpreg variables using
7781 the ldf.fill and stf.spill instructions. */
7782 TYPE_PRECISION (fpreg_type
) = 96;
7783 layout_type (fpreg_type
);
7784 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
7786 /* The __float80 type. */
7787 float80_type
= make_node (REAL_TYPE
);
7788 TYPE_PRECISION (float80_type
) = 96;
7789 layout_type (float80_type
);
7790 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
7792 /* The __float128 type. */
7795 tree float128_type
= make_node (REAL_TYPE
);
7796 TYPE_PRECISION (float128_type
) = 128;
7797 layout_type (float128_type
);
7798 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
7801 /* Under HPUX, this is a synonym for "long double". */
7802 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
7805 #define def_builtin(name, type, code) \
7806 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
7808 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si
,
7809 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
);
7810 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di
,
7811 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
);
7812 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si
,
7813 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
);
7814 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di
,
7815 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
);
7817 def_builtin ("__sync_synchronize", void_ftype_void
,
7818 IA64_BUILTIN_SYNCHRONIZE
);
7820 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si
,
7821 IA64_BUILTIN_LOCK_TEST_AND_SET_SI
);
7822 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di
,
7823 IA64_BUILTIN_LOCK_TEST_AND_SET_DI
);
7824 def_builtin ("__sync_lock_release_si", void_ftype_psi
,
7825 IA64_BUILTIN_LOCK_RELEASE_SI
);
7826 def_builtin ("__sync_lock_release_di", void_ftype_pdi
,
7827 IA64_BUILTIN_LOCK_RELEASE_DI
);
7829 def_builtin ("__builtin_ia64_bsp",
7830 build_function_type (ptr_type_node
, void_list_node
),
7833 def_builtin ("__builtin_ia64_flushrs",
7834 build_function_type (void_type_node
, void_list_node
),
7835 IA64_BUILTIN_FLUSHRS
);
7837 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si
,
7838 IA64_BUILTIN_FETCH_AND_ADD_SI
);
7839 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si
,
7840 IA64_BUILTIN_FETCH_AND_SUB_SI
);
7841 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si
,
7842 IA64_BUILTIN_FETCH_AND_OR_SI
);
7843 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si
,
7844 IA64_BUILTIN_FETCH_AND_AND_SI
);
7845 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si
,
7846 IA64_BUILTIN_FETCH_AND_XOR_SI
);
7847 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si
,
7848 IA64_BUILTIN_FETCH_AND_NAND_SI
);
7850 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si
,
7851 IA64_BUILTIN_ADD_AND_FETCH_SI
);
7852 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si
,
7853 IA64_BUILTIN_SUB_AND_FETCH_SI
);
7854 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si
,
7855 IA64_BUILTIN_OR_AND_FETCH_SI
);
7856 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si
,
7857 IA64_BUILTIN_AND_AND_FETCH_SI
);
7858 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si
,
7859 IA64_BUILTIN_XOR_AND_FETCH_SI
);
7860 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si
,
7861 IA64_BUILTIN_NAND_AND_FETCH_SI
);
7863 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di
,
7864 IA64_BUILTIN_FETCH_AND_ADD_DI
);
7865 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di
,
7866 IA64_BUILTIN_FETCH_AND_SUB_DI
);
7867 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di
,
7868 IA64_BUILTIN_FETCH_AND_OR_DI
);
7869 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di
,
7870 IA64_BUILTIN_FETCH_AND_AND_DI
);
7871 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di
,
7872 IA64_BUILTIN_FETCH_AND_XOR_DI
);
7873 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di
,
7874 IA64_BUILTIN_FETCH_AND_NAND_DI
);
7876 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di
,
7877 IA64_BUILTIN_ADD_AND_FETCH_DI
);
7878 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di
,
7879 IA64_BUILTIN_SUB_AND_FETCH_DI
);
7880 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di
,
7881 IA64_BUILTIN_OR_AND_FETCH_DI
);
7882 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di
,
7883 IA64_BUILTIN_AND_AND_FETCH_DI
);
7884 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di
,
7885 IA64_BUILTIN_XOR_AND_FETCH_DI
);
7886 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di
,
7887 IA64_BUILTIN_NAND_AND_FETCH_DI
);
7892 /* Expand fetch_and_op intrinsics. The basic code sequence is:
7900 cmpxchgsz.acq tmp = [ptr], tmp
7901 } while (tmp != ret)
7905 ia64_expand_fetch_and_op (optab binoptab
, enum machine_mode mode
,
7906 tree arglist
, rtx target
)
7908 rtx ret
, label
, tmp
, ccv
, insn
, mem
, value
;
7911 arg0
= TREE_VALUE (arglist
);
7912 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7913 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
7914 #ifdef POINTERS_EXTEND_UNSIGNED
7915 if (GET_MODE(mem
) != Pmode
)
7916 mem
= convert_memory_address (Pmode
, mem
);
7918 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
7920 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
7921 MEM_VOLATILE_P (mem
) = 1;
7923 if (target
&& register_operand (target
, mode
))
7926 ret
= gen_reg_rtx (mode
);
7928 emit_insn (gen_mf ());
7930 /* Special case for fetchadd instructions. */
7931 if (binoptab
== add_optab
&& fetchadd_operand (value
, VOIDmode
))
7934 insn
= gen_fetchadd_acq_si (ret
, mem
, value
);
7936 insn
= gen_fetchadd_acq_di (ret
, mem
, value
);
7941 tmp
= gen_reg_rtx (mode
);
7942 /* ar.ccv must always be loaded with a zero-extended DImode value. */
7943 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
7944 emit_move_insn (tmp
, mem
);
7946 label
= gen_label_rtx ();
7948 emit_move_insn (ret
, tmp
);
7949 convert_move (ccv
, tmp
, /*unsignedp=*/1);
7951 /* Perform the specific operation. Special case NAND by noticing
7952 one_cmpl_optab instead. */
7953 if (binoptab
== one_cmpl_optab
)
7955 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
7956 binoptab
= and_optab
;
7958 tmp
= expand_binop (mode
, binoptab
, tmp
, value
, tmp
, 1, OPTAB_WIDEN
);
7961 insn
= gen_cmpxchg_acq_si (tmp
, mem
, tmp
, ccv
);
7963 insn
= gen_cmpxchg_acq_di (tmp
, mem
, tmp
, ccv
);
7966 emit_cmp_and_jump_insns (tmp
, ret
, NE
, 0, mode
, 1, label
);
7971 /* Expand op_and_fetch intrinsics. The basic code sequence is:
7978 ret = tmp <op> value;
7979 cmpxchgsz.acq tmp = [ptr], ret
7980 } while (tmp != old)
7984 ia64_expand_op_and_fetch (optab binoptab
, enum machine_mode mode
,
7985 tree arglist
, rtx target
)
7987 rtx old
, label
, tmp
, ret
, ccv
, insn
, mem
, value
;
7990 arg0
= TREE_VALUE (arglist
);
7991 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
7992 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
7993 #ifdef POINTERS_EXTEND_UNSIGNED
7994 if (GET_MODE(mem
) != Pmode
)
7995 mem
= convert_memory_address (Pmode
, mem
);
7998 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8000 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8001 MEM_VOLATILE_P (mem
) = 1;
8003 if (target
&& ! register_operand (target
, mode
))
8006 emit_insn (gen_mf ());
8007 tmp
= gen_reg_rtx (mode
);
8008 old
= gen_reg_rtx (mode
);
8009 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8010 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8012 emit_move_insn (tmp
, mem
);
8014 label
= gen_label_rtx ();
8016 emit_move_insn (old
, tmp
);
8017 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8019 /* Perform the specific operation. Special case NAND by noticing
8020 one_cmpl_optab instead. */
8021 if (binoptab
== one_cmpl_optab
)
8023 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8024 binoptab
= and_optab
;
8026 ret
= expand_binop (mode
, binoptab
, tmp
, value
, target
, 1, OPTAB_WIDEN
);
8029 insn
= gen_cmpxchg_acq_si (tmp
, mem
, ret
, ccv
);
8031 insn
= gen_cmpxchg_acq_di (tmp
, mem
, ret
, ccv
);
8034 emit_cmp_and_jump_insns (tmp
, old
, NE
, 0, mode
, 1, label
);
8039 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8043 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8046 For bool_ it's the same except return ret == oldval.
8050 ia64_expand_compare_and_swap (enum machine_mode rmode
, enum machine_mode mode
,
8051 int boolp
, tree arglist
, rtx target
)
8053 tree arg0
, arg1
, arg2
;
8054 rtx mem
, old
, new, ccv
, tmp
, insn
;
8056 arg0
= TREE_VALUE (arglist
);
8057 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8058 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8059 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8060 old
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8061 new = expand_expr (arg2
, NULL_RTX
, mode
, 0);
8063 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8064 MEM_VOLATILE_P (mem
) = 1;
8066 if (GET_MODE (old
) != mode
)
8067 old
= convert_to_mode (mode
, old
, /*unsignedp=*/1);
8068 if (GET_MODE (new) != mode
)
8069 new = convert_to_mode (mode
, new, /*unsignedp=*/1);
8071 if (! register_operand (old
, mode
))
8072 old
= copy_to_mode_reg (mode
, old
);
8073 if (! register_operand (new, mode
))
8074 new = copy_to_mode_reg (mode
, new);
8076 if (! boolp
&& target
&& register_operand (target
, mode
))
8079 tmp
= gen_reg_rtx (mode
);
8081 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8082 convert_move (ccv
, old
, /*unsignedp=*/1);
8083 emit_insn (gen_mf ());
8085 insn
= gen_cmpxchg_acq_si (tmp
, mem
, new, ccv
);
8087 insn
= gen_cmpxchg_acq_di (tmp
, mem
, new, ccv
);
8093 target
= gen_reg_rtx (rmode
);
8094 return emit_store_flag_force (target
, EQ
, tmp
, old
, mode
, 1, 1);
8100 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8103 ia64_expand_lock_test_and_set (enum machine_mode mode
, tree arglist
,
8107 rtx mem
, new, ret
, insn
;
8109 arg0
= TREE_VALUE (arglist
);
8110 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8111 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8112 new = expand_expr (arg1
, NULL_RTX
, mode
, 0);
8114 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8115 MEM_VOLATILE_P (mem
) = 1;
8116 if (! register_operand (new, mode
))
8117 new = copy_to_mode_reg (mode
, new);
8119 if (target
&& register_operand (target
, mode
))
8122 ret
= gen_reg_rtx (mode
);
8125 insn
= gen_xchgsi (ret
, mem
, new);
8127 insn
= gen_xchgdi (ret
, mem
, new);
8133 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8136 ia64_expand_lock_release (enum machine_mode mode
, tree arglist
,
8137 rtx target ATTRIBUTE_UNUSED
)
8142 arg0
= TREE_VALUE (arglist
);
8143 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8145 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8146 MEM_VOLATILE_P (mem
) = 1;
8148 emit_move_insn (mem
, const0_rtx
);
8154 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8155 enum machine_mode mode ATTRIBUTE_UNUSED
,
8156 int ignore ATTRIBUTE_UNUSED
)
8158 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8159 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8160 tree arglist
= TREE_OPERAND (exp
, 1);
8161 enum machine_mode rmode
= VOIDmode
;
8165 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8166 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8171 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8172 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8173 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8174 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8175 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8176 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8177 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8178 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8179 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8180 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8181 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8182 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8183 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8184 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8188 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8193 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8198 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8199 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8200 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8201 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8202 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8203 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8204 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8205 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8206 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8207 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8208 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8209 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8210 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8211 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8221 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8222 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8223 return ia64_expand_compare_and_swap (rmode
, mode
, 1, arglist
,
8226 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8227 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8228 return ia64_expand_compare_and_swap (rmode
, mode
, 0, arglist
,
8231 case IA64_BUILTIN_SYNCHRONIZE
:
8232 emit_insn (gen_mf ());
8235 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8236 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8237 return ia64_expand_lock_test_and_set (mode
, arglist
, target
);
8239 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8240 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8241 return ia64_expand_lock_release (mode
, arglist
, target
);
8243 case IA64_BUILTIN_BSP
:
8244 if (! target
|| ! register_operand (target
, DImode
))
8245 target
= gen_reg_rtx (DImode
);
8246 emit_insn (gen_bsp_value (target
));
8247 #ifdef POINTERS_EXTEND_UNSIGNED
8248 target
= convert_memory_address (ptr_mode
, target
);
8252 case IA64_BUILTIN_FLUSHRS
:
8253 emit_insn (gen_flushrs ());
8256 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8257 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8258 return ia64_expand_fetch_and_op (add_optab
, mode
, arglist
, target
);
8260 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8261 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8262 return ia64_expand_fetch_and_op (sub_optab
, mode
, arglist
, target
);
8264 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8265 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8266 return ia64_expand_fetch_and_op (ior_optab
, mode
, arglist
, target
);
8268 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8269 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8270 return ia64_expand_fetch_and_op (and_optab
, mode
, arglist
, target
);
8272 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8273 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8274 return ia64_expand_fetch_and_op (xor_optab
, mode
, arglist
, target
);
8276 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8277 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8278 return ia64_expand_fetch_and_op (one_cmpl_optab
, mode
, arglist
, target
);
8280 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8281 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8282 return ia64_expand_op_and_fetch (add_optab
, mode
, arglist
, target
);
8284 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8285 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8286 return ia64_expand_op_and_fetch (sub_optab
, mode
, arglist
, target
);
8288 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8289 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8290 return ia64_expand_op_and_fetch (ior_optab
, mode
, arglist
, target
);
8292 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8293 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8294 return ia64_expand_op_and_fetch (and_optab
, mode
, arglist
, target
);
8296 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8297 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8298 return ia64_expand_op_and_fetch (xor_optab
, mode
, arglist
, target
);
8300 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8301 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8302 return ia64_expand_op_and_fetch (one_cmpl_optab
, mode
, arglist
, target
);
8311 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8312 most significant bits of the stack slot. */
8315 ia64_hpux_function_arg_padding (enum machine_mode mode
, tree type
)
8317 /* Exception to normal case for structures/unions/etc. */
8319 if (type
&& AGGREGATE_TYPE_P (type
)
8320 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8323 /* Fall back to the default. */
8324 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8327 /* Linked list of all external functions that are to be emitted by GCC.
8328 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8329 order to avoid putting out names that are never really used. */
8331 struct extern_func_list
8333 struct extern_func_list
*next
; /* next external */
8334 char *name
; /* name of the external */
8335 } *extern_func_head
= 0;
8338 ia64_hpux_add_extern_decl (const char *name
)
8340 struct extern_func_list
*p
;
8342 p
= (struct extern_func_list
*) xmalloc (sizeof (struct extern_func_list
));
8343 p
->name
= xmalloc (strlen (name
) + 1);
8344 strcpy(p
->name
, name
);
8345 p
->next
= extern_func_head
;
8346 extern_func_head
= p
;
8349 /* Print out the list of used global functions. */
8352 ia64_hpux_file_end (void)
8354 while (extern_func_head
)
8356 const char *real_name
;
8359 real_name
= (* targetm
.strip_name_encoding
) (extern_func_head
->name
);
8360 decl
= maybe_get_identifier (real_name
);
8363 || (! TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (decl
)))
8366 TREE_ASM_WRITTEN (decl
) = 1;
8367 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
8368 extern_func_head
->name
);
8369 fputs (TYPE_ASM_OP
, asm_out_file
);
8370 assemble_name (asm_out_file
, extern_func_head
->name
);
8371 putc (',', asm_out_file
);
8372 fprintf (asm_out_file
, TYPE_OPERAND_FMT
, "function");
8373 putc ('\n', asm_out_file
);
8375 extern_func_head
= extern_func_head
->next
;
8379 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8382 ia64_hpux_init_libfuncs (void)
8384 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
8385 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
8386 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
8387 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
8388 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
8389 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
8390 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
8391 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
8393 /* ia64_expand_compare uses this. */
8394 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
8396 /* These should never be used. */
8397 set_optab_libfunc (eq_optab
, TFmode
, 0);
8398 set_optab_libfunc (ne_optab
, TFmode
, 0);
8399 set_optab_libfunc (gt_optab
, TFmode
, 0);
8400 set_optab_libfunc (ge_optab
, TFmode
, 0);
8401 set_optab_libfunc (lt_optab
, TFmode
, 0);
8402 set_optab_libfunc (le_optab
, TFmode
, 0);
8404 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
8405 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
8406 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
8407 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
8408 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
8409 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
8411 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
8412 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
8413 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
8414 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
8416 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
8417 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
8420 /* Rename the division and modulus functions in VMS. */
8423 ia64_vms_init_libfuncs (void)
8425 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
8426 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
8427 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
8428 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
8429 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
8430 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
8431 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
8432 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
8435 /* Switch to the section to which we should output X. The only thing
8436 special we do here is to honor small data. */
8439 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
8440 unsigned HOST_WIDE_INT align
)
8442 if (GET_MODE_SIZE (mode
) > 0
8443 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8446 default_elf_select_rtx_section (mode
, x
, align
);
8449 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8450 Pretend flag_pic is always set. */
8453 ia64_rwreloc_select_section (tree exp
, int reloc
, unsigned HOST_WIDE_INT align
)
8455 default_elf_select_section_1 (exp
, reloc
, align
, true);
8459 ia64_rwreloc_unique_section (tree decl
, int reloc
)
8461 default_unique_section_1 (decl
, reloc
, true);
8465 ia64_rwreloc_select_rtx_section (enum machine_mode mode
, rtx x
,
8466 unsigned HOST_WIDE_INT align
)
8468 int save_pic
= flag_pic
;
8470 ia64_select_rtx_section (mode
, x
, align
);
8471 flag_pic
= save_pic
;
8475 ia64_rwreloc_section_type_flags (tree decl
, const char *name
, int reloc
)
8477 return default_section_type_flags_1 (decl
, name
, reloc
, true);
8481 /* Output the assembler code for a thunk function. THUNK_DECL is the
8482 declaration for the thunk function itself, FUNCTION is the decl for
8483 the target function. DELTA is an immediate constant offset to be
8484 added to THIS. If VCALL_OFFSET is nonzero, the word at
8485 *(*this + vcall_offset) should be added to THIS. */
8488 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8489 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8492 rtx
this, insn
, funexp
;
8494 reload_completed
= 1;
8495 epilogue_completed
= 1;
8498 /* Set things up as ia64_expand_prologue might. */
8499 last_scratch_gr_reg
= 15;
8501 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8502 current_frame_info
.spill_cfa_off
= -16;
8503 current_frame_info
.n_input_regs
= 1;
8504 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8506 if (!TARGET_REG_NAMES
)
8507 reg_names
[IN_REG (0)] = ia64_reg_numbers
[0];
8509 /* Mark the end of the (empty) prologue. */
8510 emit_note (NOTE_INSN_PROLOGUE_END
);
8512 this = gen_rtx_REG (Pmode
, IN_REG (0));
8515 rtx tmp
= gen_rtx_REG (ptr_mode
, IN_REG (0));
8516 REG_POINTER (tmp
) = 1;
8517 if (delta
&& CONST_OK_FOR_I (delta
))
8519 emit_insn (gen_ptr_extend_plus_imm (this, tmp
, GEN_INT (delta
)));
8523 emit_insn (gen_ptr_extend (this, tmp
));
8526 /* Apply the constant offset, if required. */
8529 rtx delta_rtx
= GEN_INT (delta
);
8531 if (!CONST_OK_FOR_I (delta
))
8533 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8534 emit_move_insn (tmp
, delta_rtx
);
8537 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8540 /* Apply the offset from the vtable, if required. */
8543 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8544 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8548 rtx t
= gen_rtx_REG (ptr_mode
, 2);
8549 REG_POINTER (t
) = 1;
8550 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this));
8551 if (CONST_OK_FOR_I (vcall_offset
))
8553 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
,
8558 emit_insn (gen_ptr_extend (tmp
, t
));
8561 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
8565 if (!CONST_OK_FOR_J (vcall_offset
))
8567 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
8568 emit_move_insn (tmp2
, vcall_offset_rtx
);
8569 vcall_offset_rtx
= tmp2
;
8571 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
8575 emit_move_insn (gen_rtx_REG (ptr_mode
, 2),
8576 gen_rtx_MEM (ptr_mode
, tmp
));
8578 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
8580 emit_insn (gen_adddi3 (this, this, tmp
));
8583 /* Generate a tail call to the target function. */
8584 if (! TREE_USED (function
))
8586 assemble_external (function
);
8587 TREE_USED (function
) = 1;
8589 funexp
= XEXP (DECL_RTL (function
), 0);
8590 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8591 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
8592 insn
= get_last_insn ();
8593 SIBLING_CALL_P (insn
) = 1;
8595 /* Code generation for calls relies on splitting. */
8596 reload_completed
= 1;
8597 epilogue_completed
= 1;
8598 try_split (PATTERN (insn
), insn
, 0);
8602 /* Run just enough of rest_of_compilation to get the insns emitted.
8603 There's not really enough bulk here to make other passes such as
8604 instruction scheduling worth while. Note that use_thunk calls
8605 assemble_start_function and assemble_end_function. */
8607 insn_locators_initialize ();
8608 emit_all_insn_group_barriers (NULL
);
8609 insn
= get_insns ();
8610 shorten_branches (insn
);
8611 final_start_function (insn
, file
, 1);
8612 final (insn
, file
, 1, 0);
8613 final_end_function ();
8615 reload_completed
= 0;
8616 epilogue_completed
= 0;
8620 #include "gt-ia64.h"