1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
3 ;; 2009 Free Software Foundation, Inc.
4 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
5 ;; David Mosberger <davidm@hpl.hp.com>.
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 3, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
26 ;; reload. This will be fixed once scheduling support is turned on.
28 ;; ??? Optimize for post-increment addressing modes.
30 ;; ??? fselect is not supported, because there is no integer register
33 ;; ??? fp abs/min/max instructions may also work for integer values.
35 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
36 ;; it assumes the operand is a register and takes REGNO of it without checking.
38 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
39 ;; it assumes the operand is a register and takes REGNO of it without checking.
41 ;; ??? Go through list of documented named patterns and look for more to
44 ;; ??? Go through instruction manual and look for more instructions that
47 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
49 ;; ??? Need a better way to describe alternate fp status registers.
53 (UNSPEC_LTOFF_DTPMOD 0)
54 (UNSPEC_LTOFF_DTPREL 1)
56 (UNSPEC_LTOFF_TPREL 3)
62 (UNSPEC_GR_RESTORE 11)
64 (UNSPEC_FR_RESTORE 13)
65 (UNSPEC_FR_RECIP_APPROX 14)
66 (UNSPEC_PRED_REL_MUTEX 15)
70 (UNSPEC_CMPXCHG_ACQ 19)
71 (UNSPEC_FETCHADD_ACQ 20)
74 (UNSPEC_BUNDLE_SELECTOR 23)
76 (UNSPEC_PROLOGUE_USE 25)
79 (UNSPEC_FR_SQRT_RECIP_APPROX 28)
92 (UNSPEC_FR_RECIP_APPROX_RES 49)
93 (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50)
99 (UNSPECV_INSN_GROUP_BARRIER 2)
102 (UNSPECV_PSAC_ALL 5) ; pred.safe_across_calls
103 (UNSPECV_PSAC_NORMAL 6)
104 (UNSPECV_SETJMP_RECEIVER 7)
105 (UNSPECV_GOTO_RECEIVER 8)
108 (include "predicates.md")
109 (include "constraints.md")
111 ;; ::::::::::::::::::::
115 ;; ::::::::::::::::::::
117 ;; Processor type. This attribute must exactly match the processor_type
118 ;; enumeration in ia64.h.
119 (define_attr "cpu" "itanium,itanium2"
120 (const (symbol_ref "((enum attr_cpu) ia64_tune)")))
122 ;; Instruction type. This primarily determines how instructions can be
123 ;; packed in bundles, and secondarily affects scheduling to function units.
125 ;; A alu, can go in I or M syllable of a bundle
130 ;; L long immediate, takes two syllables
133 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
134 ;; check this in md_reorg? Currently use unknown for patterns which emit
135 ;; multiple instructions, patterns which emit 0 instructions, and patterns
136 ;; which emit instruction that can go in any slot (e.g. nop).
138 (define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
139 fldp,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,
140 ld,chk_s_i,chk_s_f,chk_a,long_i,mmalua,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,
141 st,syst_m0, syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop,
142 nop_b,nop_f,nop_i,nop_m,nop_x,lfetch,pre_cycle"
143 (const_string "unknown"))
145 ;; chk_s_i has an I and an M form; use type A for convenience.
146 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
147 (cond [(eq_attr "itanium_class" "ld,st,fld,fldp,stf,sem,nop_m") (const_string "M")
148 (eq_attr "itanium_class" "rse_m,syst_m,syst_m0") (const_string "M")
149 (eq_attr "itanium_class" "frar_m,toar_m,frfr,tofr") (const_string "M")
150 (eq_attr "itanium_class" "lfetch") (const_string "M")
151 (eq_attr "itanium_class" "chk_s_f,chk_a") (const_string "M")
152 (eq_attr "itanium_class" "chk_s_i,ialu,icmp,ilog,mmalua")
154 (eq_attr "itanium_class" "fmisc,fmac,fcmp,xmpy") (const_string "F")
155 (eq_attr "itanium_class" "fcvtfx,nop_f") (const_string "F")
156 (eq_attr "itanium_class" "frar_i,toar_i,frbr,tobr") (const_string "I")
157 (eq_attr "itanium_class" "frpr,topr,ishf,xtd,tbit") (const_string "I")
158 (eq_attr "itanium_class" "mmmul,mmshf,mmshfi,nop_i") (const_string "I")
159 (eq_attr "itanium_class" "br,scall,nop_b") (const_string "B")
160 (eq_attr "itanium_class" "stop_bit") (const_string "S")
161 (eq_attr "itanium_class" "nop_x") (const_string "X")
162 (eq_attr "itanium_class" "long_i") (const_string "L")]
163 (const_string "unknown")))
165 (define_attr "itanium_requires_unit0" "no,yes"
166 (cond [(eq_attr "itanium_class" "syst_m0,sem,frfr,rse_m") (const_string "yes")
167 (eq_attr "itanium_class" "toar_m,frar_m") (const_string "yes")
168 (eq_attr "itanium_class" "frbr,tobr,mmmul") (const_string "yes")
169 (eq_attr "itanium_class" "tbit,ishf,topr,frpr") (const_string "yes")
170 (eq_attr "itanium_class" "toar_i,frar_i") (const_string "yes")
171 (eq_attr "itanium_class" "fmisc,fcmp") (const_string "yes")]
172 (const_string "no")))
174 ;; Predication. True iff this instruction can be predicated.
176 (define_attr "predicable" "no,yes" (const_string "yes"))
178 ;; Empty. True iff this insn does not generate any code.
180 (define_attr "empty" "no,yes" (const_string "no"))
182 ;; True iff this insn must be the first insn of an instruction group.
183 ;; This is true for the alloc instruction, and will also be true of others
184 ;; when we have full intrinsics support.
186 (define_attr "first_insn" "no,yes" (const_string "no"))
188 (define_attr "data_speculative" "no,yes" (const_string "no"))
190 (define_attr "control_speculative" "no,yes" (const_string "no"))
192 (define_attr "check_load" "no,yes" (const_string "no"))
194 (define_attr "speculable1" "no,yes" (const_string "no"))
196 (define_attr "speculable2" "no,yes" (const_string "no"))
198 ;; DFA descriptions of ia64 processors used for insn scheduling and
201 (automata_option "ndfa")
203 ;; Uncomment the following line to output automata for debugging.
204 ;; (automata_option "v")
206 (automata_option "w")
208 (include "itanium1.md")
209 (include "itanium2.md")
212 ;; ::::::::::::::::::::
216 ;; ::::::::::::::::::::
218 ;; Set of a single predicate register. This is only used to implement
219 ;; pr-to-pr move and complement.
221 (define_insn "*movcci"
222 [(set (match_operand:CCI 0 "register_operand" "=c,c,c")
223 (match_operand:CCI 1 "nonmemory_operand" "O,n,c"))]
226 cmp.ne %0, p0 = r0, r0
227 cmp.eq %0, p0 = r0, r0
228 (%1) cmp.eq.unc %0, p0 = r0, r0"
229 [(set_attr "itanium_class" "icmp")
230 (set_attr "predicable" "no")])
233 [(set (match_operand:BI 0 "destination_operand" "=c,c,?c,?*r, c,*r,*r,*m,*r")
234 (match_operand:BI 1 "move_operand" " O,n, c, c,*r, n,*m,*r,*r"))]
237 cmp.ne %0, %I0 = r0, r0
238 cmp.eq %0, %I0 = r0, r0
241 tbit.nz %0, %I0 = %1, 0
246 [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
247 (set_attr "speculable1" "yes")
248 (set_attr "speculable2" "no, no, no, no, no, no, yes,no,no")])
251 [(set (match_operand:BI 0 "register_operand" "")
252 (match_operand:BI 1 "register_operand" ""))]
254 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
255 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
256 [(cond_exec (ne (match_dup 1) (const_int 0))
257 (set (match_dup 0) (const_int 1)))
258 (cond_exec (eq (match_dup 1) (const_int 0))
259 (set (match_dup 0) (const_int 0)))]
263 [(set (match_operand:BI 0 "register_operand" "")
264 (match_operand:BI 1 "register_operand" ""))]
266 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
267 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
268 [(set (match_dup 2) (match_dup 4))
269 (set (match_dup 3) (match_dup 5))
270 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
271 "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
272 operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
273 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
274 operands[5] = gen_rtx_REG (CCImode, REGNO (operands[1]) + 1);")
276 (define_expand "movqi"
277 [(set (match_operand:QI 0 "general_operand" "")
278 (match_operand:QI 1 "general_operand" ""))]
281 rtx op1 = ia64_expand_move (operands[0], operands[1]);
287 (define_insn "movqi_internal"
288 [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
289 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
290 "ia64_move_ok (operands[0], operands[1])"
299 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
300 (set_attr "speculable1" "yes")
301 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
303 (define_expand "movhi"
304 [(set (match_operand:HI 0 "general_operand" "")
305 (match_operand:HI 1 "general_operand" ""))]
308 rtx op1 = ia64_expand_move (operands[0], operands[1]);
314 (define_insn "movhi_internal"
315 [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
316 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
317 "ia64_move_ok (operands[0], operands[1])"
326 [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
327 (set_attr "speculable1" "yes")
328 (set_attr "speculable2" "no, no, yes,no,no, no, no")])
330 (define_expand "movsi"
331 [(set (match_operand:SI 0 "general_operand" "")
332 (match_operand:SI 1 "general_operand" ""))]
335 rtx op1 = ia64_expand_move (operands[0], operands[1]);
341 (define_insn "movsi_internal"
342 [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
343 (match_operand:SI 1 "move_operand" "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
344 "ia64_move_ok (operands[0], operands[1])"
348 addp4 %0 = %1 - 0x100000000, r0
357 ;; frar_m, toar_m ??? why not frar_i and toar_i
358 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
359 (set_attr "speculable1" "yes")
360 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, no, no")])
362 (define_expand "movdi"
363 [(set (match_operand:DI 0 "general_operand" "")
364 (match_operand:DI 1 "general_operand" ""))]
367 rtx op1 = ia64_expand_move (operands[0], operands[1]);
373 (define_insn "movdi_internal"
374 [(set (match_operand:DI 0 "destination_operand"
375 "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
376 (match_operand:DI 1 "move_operand"
377 "rO,JT,j,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
378 "ia64_move_ok (operands[0], operands[1])"
380 static const char * const alt[] = {
382 "%,addl %0 = %1, r0",
383 "%,addp4 %0 = %1 - 0x100000000, r0",
385 "%,ld8%O1 %0 = %1%P1",
386 "%,st8%Q0 %0 = %r1%P0",
387 "%,getf.sig %0 = %1",
388 "%,setf.sig %0 = %r1",
402 gcc_assert (which_alternative != 2 || TARGET_NO_PIC
403 || !symbolic_operand (operands[1], VOIDmode));
405 return alt[which_alternative];
407 [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
408 (set_attr "speculable1" "yes")
409 (set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
411 (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
412 (define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")])
413 (define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
415 (define_mode_attr output_a [
416 (BI "ld1.a %0 = %1%P1")
417 (QI "ld1.a %0 = %1%P1")
418 (HI "ld2.a %0 = %1%P1")
419 (SI "ld4.a %0 = %1%P1")
432 (XF "ldfe.a %0 = %1%P1")
433 (TI "ldfp8.a %X0 = %1%P1")])
435 (define_mode_attr output_s [
436 (BI "ld1.s %0 = %1%P1")
437 (QI "ld1.s %0 = %1%P1")
438 (HI "ld2.s %0 = %1%P1")
439 (SI "ld4.s %0 = %1%P1")
452 (XF "ldfe.s %0 = %1%P1")
453 (TI "ldfp8.s %X0 = %1%P1")])
455 (define_mode_attr output_sa [
456 (BI "ld1.sa %0 = %1%P1")
457 (QI "ld1.sa %0 = %1%P1")
458 (HI "ld2.sa %0 = %1%P1")
459 (SI "ld4.sa %0 = %1%P1")
472 (XF "ldfe.sa %0 = %1%P1")
473 (TI "ldfp8.sa %X0 = %1%P1")])
475 (define_mode_attr output_c_clr [
476 (BI "ld1.c.clr%O1 %0 = %1%P1")
477 (QI "ld1.c.clr%O1 %0 = %1%P1")
478 (HI "ld2.c.clr%O1 %0 = %1%P1")
479 (SI "ld4.c.clr%O1 %0 = %1%P1")
482 ld8.c.clr%O1 %0 = %1%P1
483 ldf8.c.clr %0 = %1%P1")
486 ldfs.c.clr %0 = %1%P1
487 ld4.c.clr%O1 %0 = %1%P1")
490 ldfd.c.clr %0 = %1%P1
491 ld8.c.clr%O1 %0 = %1%P1")
492 (XF "ldfe.c.clr %0 = %1%P1")
493 (TI "ldfp8.c.clr %X0 = %1%P1")])
495 (define_mode_attr output_c_nc [
496 (BI "ld1.c.nc%O1 %0 = %1%P1")
497 (QI "ld1.c.nc%O1 %0 = %1%P1")
498 (HI "ld2.c.nc%O1 %0 = %1%P1")
499 (SI "ld4.c.nc%O1 %0 = %1%P1")
502 ld8.c.nc%O1 %0 = %1%P1
503 ldf8.c.nc %0 = %1%P1")
507 ld4.c.nc%O1 %0 = %1%P1")
511 ld8.c.nc%O1 %0 = %1%P1")
512 (XF "ldfe.c.nc %0 = %1%P1")
513 (TI "ldfp8.c.nc %X0 = %1%P1")])
515 (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
516 (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
517 (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
519 (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")])
521 ;; Define register predicate prefix.
522 ;; We can generate speculative loads only for general and fp registers - this
523 ;; is constrained in ia64.c: ia64_speculate_insn ().
524 (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")])
526 (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")])
527 (define_mode_attr chka_class [(BI "chk_a") (QI "chk_a") (HI "chk_a") (SI "chk_a") (DI "chk_a,chk_a") (SF "chk_a,chk_a") (DF "chk_a,chk_a") (XF "chk_a") (TI "chk_a")])
528 (define_mode_attr chks_class [(BI "chk_s_i") (QI "chk_s_i") (HI "chk_s_i") (SI "chk_s_i") (DI "chk_s_i,chk_s_f") (SF "chk_s_f,chk_s_i") (DF "chk_s_f,chk_s_i") (XF "chk_s_f") (TI "chk_s_i")])
530 (define_mode_attr attr_yes [(BI "yes") (QI "yes") (HI "yes") (SI "yes") (DI "yes,yes") (SF "yes,yes") (DF "yes,yes") (XF "yes") (TI "yes")])
532 (define_insn "mov<mode>_advanced"
533 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
534 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA))]
535 "ia64_move_ok (operands[0], operands[1])"
537 [(set_attr "itanium_class" "<ld_class>")
538 (set_attr "data_speculative" "<attr_yes>")])
540 (define_insn "zero_extend<mode>di2_advanced"
541 [(set (match_operand:DI 0 "gr_register_operand" "=r")
542 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDA)))]
545 [(set_attr "itanium_class" "<ld_class>")
546 (set_attr "data_speculative" "<attr_yes>")])
548 (define_insn "mov<mode>_speculative"
549 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
550 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS))]
551 "ia64_move_ok (operands[0], operands[1])"
553 [(set_attr "itanium_class" "<ld_class>")
554 (set_attr "control_speculative" "<attr_yes>")])
556 (define_insn "zero_extend<mode>di2_speculative"
557 [(set (match_operand:DI 0 "gr_register_operand" "=r")
558 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS)))]
561 [(set_attr "itanium_class" "<ld_class>")
562 (set_attr "control_speculative" "<attr_yes>")])
564 (define_insn "mov<mode>_speculative_advanced"
565 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
566 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA))]
567 "ia64_move_ok (operands[0], operands[1])"
569 [(set_attr "itanium_class" "<ld_class>")
570 (set_attr "data_speculative" "<attr_yes>")
571 (set_attr "control_speculative" "<attr_yes>")])
573 (define_insn "mov<mode>_speculative_a"
574 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
575 (unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
576 "ia64_move_ok (operands[0], operands[1])"
578 [(set_attr "itanium_class" "<ld_class>")
579 (set_attr "data_speculative" "<attr_yes>")
580 (set_attr "control_speculative" "<attr_yes>")])
582 (define_insn "zero_extend<mode>di2_speculative_advanced"
583 [(set (match_operand:DI 0 "gr_register_operand" "=r")
584 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
587 [(set_attr "itanium_class" "<ld_class>")
588 (set_attr "data_speculative" "<attr_yes>")
589 (set_attr "control_speculative" "<attr_yes>")])
591 (define_insn "zero_extend<mode>di2_speculative_a"
592 [(set (match_operand:DI 0 "gr_register_operand" "=r")
593 (zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
596 [(set_attr "itanium_class" "<ld_class>")
597 (set_attr "data_speculative" "<attr_yes>")
598 (set_attr "control_speculative" "<attr_yes>")])
600 (define_insn "mov<mode>_clr"
601 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
602 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
603 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
605 "ia64_move_ok (operands[0], operands[1])"
607 [(set_attr "itanium_class" "<ld_class>")
608 (set_attr "check_load" "<attr_yes>")])
610 (define_insn "mov<mode>_nc"
611 [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
612 (if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
613 (match_operand:MODE 1 "memory_operand" "<mem_constr>")
615 "ia64_move_ok (operands[0], operands[1])"
617 [(set_attr "itanium_class" "<ld_class>")
618 (set_attr "check_load" "<attr_yes>")])
620 (define_insn "zero_extend<mode>di2_clr"
621 [(set (match_operand:DI 0 "gr_register_operand" "+r")
622 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
623 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
627 [(set_attr "itanium_class" "<ld_class>")
628 (set_attr "check_load" "<attr_yes>")])
630 (define_insn "zero_extend<mode>di2_nc"
631 [(set (match_operand:DI 0 "gr_register_operand" "+r")
632 (if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
633 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
637 [(set_attr "itanium_class" "<ld_class>")
638 (set_attr "check_load" "<attr_yes>")])
640 (define_insn "advanced_load_check_clr_<mode>"
642 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
644 (label_ref (match_operand 1 "" ""))))]
647 [(set_attr "itanium_class" "<chka_class>")])
649 (define_insn "advanced_load_check_nc_<mode>"
651 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
653 (label_ref (match_operand 1 "" ""))))]
656 [(set_attr "itanium_class" "<chka_class>")])
658 (define_insn "speculation_check_<mode>"
660 (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
662 (label_ref (match_operand 1 "" ""))))]
665 [(set_attr "itanium_class" "<chks_class>")])
668 [(set (match_operand 0 "register_operand" "")
669 (match_operand 1 "symbolic_operand" ""))]
673 if (ia64_expand_load_address (operands[0], operands[1]))
679 (define_expand "load_fptr"
680 [(set (match_operand:DI 0 "register_operand" "")
681 (plus:DI (match_dup 2) (match_operand 1 "function_operand" "")))
682 (set (match_dup 0) (match_dup 3))]
685 operands[2] = pic_offset_table_rtx;
686 operands[3] = gen_const_mem (DImode, operands[0]);
689 (define_insn "*load_fptr_internal1"
690 [(set (match_operand:DI 0 "register_operand" "=r")
691 (plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
693 "addl %0 = @ltoff(@fptr(%1)), gp"
694 [(set_attr "itanium_class" "ialu")])
696 (define_insn "load_gprel"
697 [(set (match_operand:DI 0 "register_operand" "=r")
698 (plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
700 "addl %0 = @gprel(%1), gp"
701 [(set_attr "itanium_class" "ialu")])
703 (define_insn "*gprel64_offset"
704 [(set (match_operand:DI 0 "register_operand" "=r")
705 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
707 "movl %0 = @gprel(%1)"
708 [(set_attr "itanium_class" "long_i")])
710 (define_expand "load_gprel64"
711 [(set (match_operand:DI 0 "register_operand" "")
712 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (match_dup 2)))
714 (plus:DI (match_dup 2) (match_dup 0)))]
717 operands[2] = pic_offset_table_rtx;
720 ;; This is used as a placeholder for the return address during early
721 ;; compilation. We won't know where we've placed this until during
722 ;; reload, at which point it can wind up in b0, a general register,
723 ;; or memory. The only safe destination under these conditions is a
726 (define_insn_and_split "*movdi_ret_addr"
727 [(set (match_operand:DI 0 "register_operand" "=r")
728 (unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
734 ia64_split_return_addr_rtx (operands[0]);
737 [(set_attr "itanium_class" "ialu")])
739 (define_insn "*load_symptr_high"
740 [(set (match_operand:DI 0 "register_operand" "=r")
741 (plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
742 (match_operand:DI 2 "register_operand" "a")))]
745 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
746 return "%,addl %0 = @ltoffx(%1), %2";
748 return "%,addl %0 = @ltoff(%1), %2";
750 [(set_attr "itanium_class" "ialu")])
752 (define_insn "*load_symptr_low"
753 [(set (match_operand:DI 0 "register_operand" "=r")
754 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
755 (match_operand 2 "got_symbolic_operand" "s")))]
758 if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
759 return "%,ld8.mov %0 = [%1], %2";
761 return "%,ld8 %0 = [%1]";
763 [(set_attr "itanium_class" "ld")])
765 (define_insn_and_split "load_dtpmod"
766 [(set (match_operand:DI 0 "register_operand" "=r")
767 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
773 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPMOD)
775 (set (match_dup 0) (match_dup 3))]
777 operands[2] = pic_offset_table_rtx;
778 operands[3] = gen_const_mem (DImode, operands[0]);
781 (define_insn "*load_ltoff_dtpmod"
782 [(set (match_operand:DI 0 "register_operand" "=r")
783 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
785 (match_operand:DI 2 "register_operand" "a")))]
787 "addl %0 = @ltoff(@dtpmod(%1)), %2"
788 [(set_attr "itanium_class" "ialu")])
790 (define_expand "load_dtprel"
791 [(set (match_operand:DI 0 "register_operand" "")
792 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
797 (define_insn "*load_dtprel64"
798 [(set (match_operand:DI 0 "register_operand" "=r")
799 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
802 "movl %0 = @dtprel(%1)"
803 [(set_attr "itanium_class" "long_i")])
805 (define_insn "*load_dtprel22"
806 [(set (match_operand:DI 0 "register_operand" "=r")
807 (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
810 "addl %0 = @dtprel(%1), r0"
811 [(set_attr "itanium_class" "ialu")])
813 (define_insn_and_split "*load_dtprel_gd"
814 [(set (match_operand:DI 0 "register_operand" "=r")
815 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
821 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_DTPREL)
823 (set (match_dup 0) (match_dup 3))]
825 operands[2] = pic_offset_table_rtx;
826 operands[3] = gen_const_mem (DImode, operands[0]);
829 (define_insn "*load_ltoff_dtprel"
830 [(set (match_operand:DI 0 "register_operand" "=r")
831 (plus:DI (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
833 (match_operand:DI 2 "register_operand" "a")))]
835 "addl %0 = @ltoff(@dtprel(%1)), %2"
836 [(set_attr "itanium_class" "ialu")])
838 (define_expand "add_dtprel"
839 [(set (match_operand:DI 0 "register_operand" "")
840 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
842 (match_operand:DI 2 "register_operand" "")))]
846 (define_insn "*add_dtprel14"
847 [(set (match_operand:DI 0 "register_operand" "=r")
848 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
850 (match_operand:DI 2 "register_operand" "r")))]
852 "adds %0 = @dtprel(%1), %2"
853 [(set_attr "itanium_class" "ialu")])
855 (define_insn "*add_dtprel22"
856 [(set (match_operand:DI 0 "register_operand" "=r")
857 (plus:DI (unspec:DI [(match_operand 1 "ld_tls_symbolic_operand" "")]
859 (match_operand:DI 2 "register_operand" "a")))]
861 "addl %0 = @dtprel(%1), %2"
862 [(set_attr "itanium_class" "ialu")])
864 (define_expand "load_tprel"
865 [(set (match_operand:DI 0 "register_operand" "")
866 (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
871 (define_insn "*load_tprel64"
872 [(set (match_operand:DI 0 "register_operand" "=r")
873 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
876 "movl %0 = @tprel(%1)"
877 [(set_attr "itanium_class" "long_i")])
879 (define_insn "*load_tprel22"
880 [(set (match_operand:DI 0 "register_operand" "=r")
881 (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
884 "addl %0 = @tprel(%1), r0"
885 [(set_attr "itanium_class" "ialu")])
887 (define_insn_and_split "*load_tprel_ie"
888 [(set (match_operand:DI 0 "register_operand" "=r")
889 (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
895 (plus:DI (unspec:DI [(match_dup 1)] UNSPEC_LTOFF_TPREL)
897 (set (match_dup 0) (match_dup 3))]
899 operands[2] = pic_offset_table_rtx;
900 operands[3] = gen_const_mem (DImode, operands[0]);
903 (define_insn "*load_ltoff_tprel"
904 [(set (match_operand:DI 0 "register_operand" "=r")
905 (plus:DI (unspec:DI [(match_operand 1 "ie_tls_symbolic_operand" "")]
907 (match_operand:DI 2 "register_operand" "a")))]
909 "addl %0 = @ltoff(@tprel(%1)), %2"
910 [(set_attr "itanium_class" "ialu")])
912 (define_expand "add_tprel"
913 [(set (match_operand:DI 0 "register_operand" "")
914 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
916 (match_operand:DI 2 "register_operand" "")))]
920 (define_insn "*add_tprel14"
921 [(set (match_operand:DI 0 "register_operand" "=r")
922 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
924 (match_operand:DI 2 "register_operand" "r")))]
926 "adds %0 = @tprel(%1), %2"
927 [(set_attr "itanium_class" "ialu")])
929 (define_insn "*add_tprel22"
930 [(set (match_operand:DI 0 "register_operand" "=r")
931 (plus:DI (unspec:DI [(match_operand 1 "le_tls_symbolic_operand" "")]
933 (match_operand:DI 2 "register_operand" "a")))]
935 "addl %0 = @tprel(%1), %2"
936 [(set_attr "itanium_class" "ialu")])
938 ;; With no offsettable memory references, we've got to have a scratch
939 ;; around to play with the second word. However, in order to avoid a
940 ;; reload nightmare we lie, claim we don't need one, and fix it up
941 ;; in ia64_split_tmode_move.
942 (define_expand "movti"
943 [(set (match_operand:TI 0 "general_operand" "")
944 (match_operand:TI 1 "general_operand" ""))]
947 rtx op1 = ia64_expand_move (operands[0], operands[1]);
953 (define_insn_and_split "movti_internal"
954 [(set (match_operand:TI 0 "destination_operand" "=r, *fm,*x,*f, Q")
955 (match_operand:TI 1 "general_operand" "r*fim,r, Q, *fOQ,*f"))]
956 "ia64_move_ok (operands[0], operands[1])"
963 "reload_completed && !ia64_load_pair_ok(operands[0], operands[1])"
966 ia64_split_tmode_move (operands);
969 [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
970 (set_attr "speculable1" "yes")
971 (set_attr "speculable2" "no, no, yes, no, no")])
973 ;; Floating Point Moves
975 ;; Note - Patterns for SF mode moves are compulsory, but
976 ;; patterns for DF are optional, as GCC can synthesize them.
978 (define_expand "movsf"
979 [(set (match_operand:SF 0 "general_operand" "")
980 (match_operand:SF 1 "general_operand" ""))]
983 rtx op1 = ia64_expand_move (operands[0], operands[1]);
989 (define_insn "movsf_internal"
990 [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
991 (match_operand:SF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
992 "ia64_move_ok (operands[0], operands[1])"
1003 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
1004 (set_attr "speculable1" "yes")
1005 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
1007 (define_expand "movdf"
1008 [(set (match_operand:DF 0 "general_operand" "")
1009 (match_operand:DF 1 "general_operand" ""))]
1012 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1018 (define_insn "movdf_internal"
1019 [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m,*r")
1020 (match_operand:DF 1 "general_operand" "fG,Q,fG,fG,*r,*r, m,*r, F"))]
1021 "ia64_move_ok (operands[0], operands[1])"
1032 [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st,long_i")
1033 (set_attr "speculable1" "yes")
1034 (set_attr "speculable2" "no, yes,no, no, no, no, yes,no,no")])
1036 ;; With no offsettable memory references, we've got to have a scratch
1037 ;; around to play with the second word if the variable winds up in GRs.
1038 (define_expand "movxf"
1039 [(set (match_operand:XF 0 "general_operand" "")
1040 (match_operand:XF 1 "general_operand" ""))]
1043 if (ia64_expand_movxf_movrf (XFmode, operands))
1047 ;; ??? There's no easy way to mind volatile acquire/release semantics.
1049 (define_insn "movxf_internal"
1050 [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
1051 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
1052 "ia64_move_ok (operands[0], operands[1])"
1057 [(set_attr "itanium_class" "fmisc,fld,stf")
1058 (set_attr "speculable1" "yes")
1059 (set_attr "speculable2" "no, yes,no")])
1061 ;; Same as for movxf, but for RFmode.
1062 (define_expand "movrf"
1063 [(set (match_operand:RF 0 "general_operand" "")
1064 (match_operand:RF 1 "general_operand" ""))]
1067 if (ia64_expand_movxf_movrf (RFmode, operands))
1071 (define_insn "*movrf_internal"
1072 [(set (match_operand:RF 0 "destination_operand" "=f,f, m")
1073 (match_operand:RF 1 "general_operand" "fG,m,fG"))]
1074 "ia64_move_ok (operands[0], operands[1])"
1078 stf.spill %0 = %F1%P0"
1079 [(set_attr "itanium_class" "fmisc,fld,stf")])
1081 ;; Better code generation via insns that deal with TFmode register pairs
1082 ;; directly. Same concerns apply as for TImode.
1083 (define_expand "movtf"
1084 [(set (match_operand:TF 0 "general_operand" "")
1085 (match_operand:TF 1 "general_operand" ""))]
1088 rtx op1 = ia64_expand_move (operands[0], operands[1]);
1094 (define_insn_and_split "*movtf_internal"
1095 [(set (match_operand:TF 0 "destination_operand" "=r,r,m")
1096 (match_operand:TF 1 "general_operand" "ri,m,r"))]
1097 "ia64_move_ok (operands[0], operands[1])"
1102 ia64_split_tmode_move (operands);
1105 [(set_attr "itanium_class" "unknown")
1106 (set_attr "predicable" "no")])
1109 ;; ::::::::::::::::::::
1113 ;; ::::::::::::::::::::
1115 ;; Signed conversions from a smaller integer to a larger integer
1117 (define_insn "extendqidi2"
1118 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1119 (sign_extend:DI (match_operand:QI 1 "gr_register_operand" "r")))]
1122 [(set_attr "itanium_class" "xtd")])
1124 (define_insn "extendhidi2"
1125 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1126 (sign_extend:DI (match_operand:HI 1 "gr_register_operand" "r")))]
1129 [(set_attr "itanium_class" "xtd")])
1131 (define_insn "extendsidi2"
1132 [(set (match_operand:DI 0 "grfr_register_operand" "=r,?f")
1133 (sign_extend:DI (match_operand:SI 1 "grfr_register_operand" "r,f")))]
1138 [(set_attr "itanium_class" "xtd,fmisc")])
1140 ;; Unsigned conversions from a smaller integer to a larger integer
1142 (define_insn "zero_extendqidi2"
1143 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1144 (zero_extend:DI (match_operand:QI 1 "gr_nonimmediate_operand" "r,m")))]
1149 [(set_attr "itanium_class" "xtd,ld")
1150 (set_attr "speculable1" "yes")
1151 (set_attr "speculable2" "no, yes")])
1153 (define_insn "zero_extendhidi2"
1154 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
1155 (zero_extend:DI (match_operand:HI 1 "gr_nonimmediate_operand" "r,m")))]
1160 [(set_attr "itanium_class" "xtd,ld")
1161 (set_attr "speculable1" "yes")
1162 (set_attr "speculable2" "no, yes")])
1164 (define_insn "zero_extendsidi2"
1165 [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
1167 (match_operand:SI 1 "grfr_nonimmediate_operand" "r,m,f")))]
1173 [(set_attr "itanium_class" "ialu,ld,fmisc")
1174 (set_attr "speculable1" "yes")
1175 (set_attr "speculable2" "no, yes,no")])
1177 ;; Convert between floating point types of different sizes.
1179 ;; At first glance, it would appear that emitting fnorm for an extending
1180 ;; conversion is unnecessary. However, the stf and getf instructions work
1181 ;; correctly only if the input is properly rounded for its type. In
1182 ;; particular, we get the wrong result for getf.d/stfd if the input is a
1183 ;; denorm single. Since we don't know what the next instruction will be, we
1184 ;; have to emit an fnorm.
1186 ;; ??? Optimization opportunity here. Get rid of the insn altogether
1187 ;; when we can. Should probably use a scheme like has been proposed
1188 ;; for ia32 in dealing with operands that match unary operators. This
1189 ;; would let combine merge the thing into adjacent insns. See also how the
1190 ;; mips port handles SIGN_EXTEND as operands to integer arithmetic insns via
1191 ;; se_register_operand.
1193 (define_insn "extendsfdf2"
1194 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1195 (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1198 [(set_attr "itanium_class" "fmac")])
1200 (define_insn "extendsfxf2"
1201 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1202 (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1205 [(set_attr "itanium_class" "fmac")])
1207 (define_insn "extenddfxf2"
1208 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1209 (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1212 [(set_attr "itanium_class" "fmac")])
1214 (define_insn "truncdfsf2"
1215 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1216 (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1219 [(set_attr "itanium_class" "fmac")])
1221 (define_insn "truncxfsf2"
1222 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1223 (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1226 [(set_attr "itanium_class" "fmac")])
1228 (define_insn "truncxfdf2"
1229 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1230 (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1233 [(set_attr "itanium_class" "fmac")])
1235 ;; Convert between signed integer types and floating point.
1237 (define_insn "floatdirf2"
1238 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1239 (float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1242 [(set_attr "itanium_class" "fcvtfx")])
1244 (define_insn "floatdixf2"
1245 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1246 (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1249 [(set_attr "itanium_class" "fcvtfx")])
1251 (define_insn "fix_truncsfdi2"
1252 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1253 (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1255 "fcvt.fx.trunc %0 = %F1"
1256 [(set_attr "itanium_class" "fcvtfx")])
1258 (define_insn "fix_truncdfdi2"
1259 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1260 (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1262 "fcvt.fx.trunc %0 = %F1"
1263 [(set_attr "itanium_class" "fcvtfx")])
1265 (define_insn "fix_truncxfdi2"
1266 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1267 (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1269 "fcvt.fx.trunc %0 = %F1"
1270 [(set_attr "itanium_class" "fcvtfx")])
1272 (define_insn "fix_truncrfdi2"
1273 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1274 (fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
1276 "fcvt.fx.trunc %0 = %F1"
1277 [(set_attr "itanium_class" "fcvtfx")])
1279 ;; Convert between unsigned integer types and floating point.
1281 (define_insn "floatunsdisf2"
1282 [(set (match_operand:SF 0 "fr_register_operand" "=f")
1283 (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1285 "fcvt.xuf.s %0 = %F1"
1286 [(set_attr "itanium_class" "fcvtfx")])
1288 (define_insn "floatunsdidf2"
1289 [(set (match_operand:DF 0 "fr_register_operand" "=f")
1290 (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1292 "fcvt.xuf.d %0 = %F1"
1293 [(set_attr "itanium_class" "fcvtfx")])
1295 (define_insn "floatunsdixf2"
1296 [(set (match_operand:XF 0 "fr_register_operand" "=f")
1297 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1300 [(set_attr "itanium_class" "fcvtfx")])
1302 (define_insn "floatunsdirf2"
1303 [(set (match_operand:RF 0 "fr_register_operand" "=f")
1304 (unsigned_float:RF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
1307 [(set_attr "itanium_class" "fcvtfx")])
1309 (define_insn "fixuns_truncsfdi2"
1310 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1311 (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
1313 "fcvt.fxu.trunc %0 = %F1"
1314 [(set_attr "itanium_class" "fcvtfx")])
1316 (define_insn "fixuns_truncdfdi2"
1317 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1318 (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
1320 "fcvt.fxu.trunc %0 = %F1"
1321 [(set_attr "itanium_class" "fcvtfx")])
1323 (define_insn "fixuns_truncxfdi2"
1324 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1325 (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
1327 "fcvt.fxu.trunc %0 = %F1"
1328 [(set_attr "itanium_class" "fcvtfx")])
1330 (define_insn "fixuns_truncrfdi2"
1331 [(set (match_operand:DI 0 "fr_register_operand" "=f")
1332 (unsigned_fix:DI (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
1334 "fcvt.fxu.trunc %0 = %F1"
1335 [(set_attr "itanium_class" "fcvtfx")])
1337 ;; ::::::::::::::::::::
1339 ;; :: Bit field extraction
1341 ;; ::::::::::::::::::::
1344 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1345 (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1346 (match_operand:DI 2 "extr_len_operand" "n")
1347 (match_operand:DI 3 "shift_count_operand" "M")))]
1349 "extr %0 = %1, %3, %2"
1350 [(set_attr "itanium_class" "ishf")])
1352 (define_insn "extzv"
1353 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1354 (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
1355 (match_operand:DI 2 "extr_len_operand" "n")
1356 (match_operand:DI 3 "shift_count_operand" "M")))]
1358 "extr.u %0 = %1, %3, %2"
1359 [(set_attr "itanium_class" "ishf")])
1361 ;; Insert a bit field.
1362 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
1363 ;; Source1 can be 0 or -1.
1364 ;; Source2 can be 0.
1366 ;; ??? Actual dep instruction is more powerful than what these insv
1367 ;; patterns support. Unfortunately, combine is unable to create patterns
1368 ;; where source2 != dest.
1370 (define_expand "insv"
1371 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "")
1372 (match_operand:DI 1 "const_int_operand" "")
1373 (match_operand:DI 2 "const_int_operand" ""))
1374 (match_operand:DI 3 "nonmemory_operand" ""))]
1377 int width = INTVAL (operands[1]);
1378 int shift = INTVAL (operands[2]);
1380 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
1382 if (! register_operand (operands[3], DImode)
1383 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
1384 operands[3] = force_reg (DImode, operands[3]);
1386 /* If this is a single dep instruction, we have nothing to do. */
1387 if (! ((register_operand (operands[3], DImode) && width <= 16)
1388 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
1390 /* Check for cases that can be implemented with a mix instruction. */
1391 if (width == 32 && shift == 0)
1393 /* Directly generating the mix4left instruction confuses
1394 optimize_bit_field in function.c. Since this is performing
1395 a useful optimization, we defer generation of the complicated
1396 mix4left RTL to the first splitting phase. */
1397 rtx tmp = gen_reg_rtx (DImode);
1398 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
1401 else if (width == 32 && shift == 32)
1403 emit_insn (gen_mix4right (operands[0], operands[3]));
1407 /* We could handle remaining cases by emitting multiple dep
1410 If we need more than two dep instructions then we lose. A 6
1411 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
1412 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
1413 the latter is 6 cycles on an Itanium (TM) processor, because there is
1414 only one function unit that can execute dep and shr immed.
1416 If we only need two dep instruction, then we still lose.
1417 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
1418 the unnecessary mov, this is still undesirable because it will be
1419 hard to optimize, and it creates unnecessary pressure on the I0
1425 /* This code may be useful for other IA-64 processors, so we leave it in
1431 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
1435 tmp = gen_reg_rtx (DImode);
1436 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
1439 operands[1] = GEN_INT (width);
1440 operands[2] = GEN_INT (shift);
1445 (define_insn "*insv_internal"
1446 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1447 (match_operand:DI 1 "const_int_operand" "n")
1448 (match_operand:DI 2 "const_int_operand" "n"))
1449 (match_operand:DI 3 "nonmemory_operand" "rP"))]
1450 "(gr_register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
1451 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
1452 "dep %0 = %3, %0, %2, %1"
1453 [(set_attr "itanium_class" "ishf")])
1455 ;; Combine doesn't like to create bit-field insertions into zero.
1456 (define_insn "*shladdp4_internal"
1457 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1458 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1459 (match_operand:DI 2 "shladd_log2_operand" "n"))
1460 (match_operand:DI 3 "const_int_operand" "n")))]
1461 "ia64_depz_field_mask (operands[3], operands[2]) + INTVAL (operands[2]) == 32"
1462 "shladdp4 %0 = %1, %2, r0"
1463 [(set_attr "itanium_class" "ialu")])
1465 (define_insn "*depz_internal"
1466 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1467 (and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
1468 (match_operand:DI 2 "const_int_operand" "M"))
1469 (match_operand:DI 3 "const_int_operand" "n")))]
1470 "satisfies_constraint_M (operands[2])
1471 && ia64_depz_field_mask (operands[3], operands[2]) > 0"
1473 operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
1474 return "%,dep.z %0 = %1, %2, %3";
1476 [(set_attr "itanium_class" "ishf")])
1478 (define_insn "shift_mix4left"
1479 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1480 (const_int 32) (const_int 0))
1481 (match_operand:DI 1 "gr_register_operand" "r"))
1482 (clobber (match_operand:DI 2 "gr_register_operand" "=r"))]
1485 [(set_attr "itanium_class" "unknown")])
1488 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
1489 (const_int 32) (const_int 0))
1490 (match_operand:DI 1 "register_operand" ""))
1491 (clobber (match_operand:DI 2 "register_operand" ""))]
1493 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
1494 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
1495 (lshiftrt:DI (match_dup 3) (const_int 32)))]
1496 "operands[3] = operands[2];")
1498 (define_insn "*mix4left"
1499 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1500 (const_int 32) (const_int 0))
1501 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r")
1504 "mix4.l %0 = %0, %r1"
1505 [(set_attr "itanium_class" "mmshf")])
1507 (define_insn "mix4right"
1508 [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
1509 (const_int 32) (const_int 32))
1510 (match_operand:DI 1 "gr_reg_or_0_operand" "rO"))]
1512 "mix4.r %0 = %r1, %0"
1513 [(set_attr "itanium_class" "mmshf")])
1515 ;; This is used by the rotrsi3 pattern.
1517 (define_insn "*mix4right_3op"
1518 [(set (match_operand:DI 0 "gr_register_operand" "=r")
1519 (ior:DI (zero_extend:DI (match_operand:SI 1 "gr_register_operand" "r"))
1520 (ashift:DI (zero_extend:DI
1521 (match_operand:SI 2 "gr_register_operand" "r"))
1524 "mix4.r %0 = %2, %1"
1525 [(set_attr "itanium_class" "mmshf")])
1528 ;; ::::::::::::::::::::
1530 ;; :: 1-bit Integer arithmetic
1532 ;; ::::::::::::::::::::
1534 (define_insn_and_split "andbi3"
1535 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1536 (and:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1537 (match_operand:BI 2 "register_operand" "c,r,r")))]
1541 tbit.nz.and.orcm %0, %I0 = %2, 0
1544 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1545 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1546 [(cond_exec (eq (match_dup 2) (const_int 0))
1547 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1550 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1552 (define_insn_and_split "*andcmbi3"
1553 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1554 (and:BI (not:BI (match_operand:BI 1 "register_operand" "c,r,r"))
1555 (match_operand:BI 2 "register_operand" "0,0,r")))]
1559 tbit.z.and.orcm %0, %I0 = %1, 0
1562 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1563 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1564 [(cond_exec (ne (match_dup 1) (const_int 0))
1565 (set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
1568 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1570 (define_insn_and_split "iorbi3"
1571 [(set (match_operand:BI 0 "register_operand" "=c,c,r")
1572 (ior:BI (match_operand:BI 1 "register_operand" "%0,0,r")
1573 (match_operand:BI 2 "register_operand" "c,r,r")))]
1577 tbit.nz.or.andcm %0, %I0 = %2, 0
1580 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1581 && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
1582 [(cond_exec (ne (match_dup 2) (const_int 0))
1583 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1586 [(set_attr "itanium_class" "unknown,tbit,ilog")])
1588 (define_insn_and_split "*iorcmbi3"
1589 [(set (match_operand:BI 0 "register_operand" "=c,c")
1590 (ior:BI (not:BI (match_operand:BI 1 "register_operand" "c,r"))
1591 (match_operand:BI 2 "register_operand" "0,0")))]
1595 tbit.z.or.andcm %0, %I0 = %1, 0"
1597 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1598 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1599 [(cond_exec (eq (match_dup 1) (const_int 0))
1600 (set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
1603 [(set_attr "itanium_class" "unknown,tbit")])
1605 (define_insn "one_cmplbi2"
1606 [(set (match_operand:BI 0 "register_operand" "=c,r,c,&c")
1607 (not:BI (match_operand:BI 1 "register_operand" "r,r,0,c")))
1608 (clobber (match_scratch:BI 2 "=X,X,c,X"))]
1611 tbit.z %0, %I0 = %1, 0
1615 [(set_attr "itanium_class" "tbit,ilog,unknown,unknown")])
1618 [(set (match_operand:BI 0 "register_operand" "")
1619 (not:BI (match_operand:BI 1 "register_operand" "")))
1620 (clobber (match_scratch:BI 2 ""))]
1622 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1623 && rtx_equal_p (operands[0], operands[1])"
1624 [(set (match_dup 4) (match_dup 3))
1625 (set (match_dup 0) (const_int 1))
1626 (cond_exec (ne (match_dup 2) (const_int 0))
1627 (set (match_dup 0) (const_int 0)))
1628 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1629 "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
1630 operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
1633 [(set (match_operand:BI 0 "register_operand" "")
1634 (not:BI (match_operand:BI 1 "register_operand" "")))
1635 (clobber (match_scratch:BI 2 ""))]
1637 && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
1638 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
1639 && ! rtx_equal_p (operands[0], operands[1])"
1640 [(cond_exec (ne (match_dup 1) (const_int 0))
1641 (set (match_dup 0) (const_int 0)))
1642 (cond_exec (eq (match_dup 1) (const_int 0))
1643 (set (match_dup 0) (const_int 1)))
1644 (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
1647 (define_insn "*cmpsi_and_0"
1648 [(set (match_operand:BI 0 "register_operand" "=c")
1649 (and:BI (match_operator:BI 4 "predicate_operator"
1650 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1651 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1652 (match_operand:BI 1 "register_operand" "0")))]
1654 "cmp4.%C4.and.orcm %0, %I0 = %3, %r2"
1655 [(set_attr "itanium_class" "icmp")])
1657 (define_insn "*cmpsi_and_1"
1658 [(set (match_operand:BI 0 "register_operand" "=c")
1659 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1660 [(match_operand:SI 2 "gr_register_operand" "r")
1662 (match_operand:BI 1 "register_operand" "0")))]
1664 "cmp4.%C3.and.orcm %0, %I0 = r0, %2"
1665 [(set_attr "itanium_class" "icmp")])
1667 (define_insn "*cmpsi_andnot_0"
1668 [(set (match_operand:BI 0 "register_operand" "=c")
1669 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1670 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1671 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1672 (match_operand:BI 1 "register_operand" "0")))]
1674 "cmp4.%C4.or.andcm %I0, %0 = %3, %r2"
1675 [(set_attr "itanium_class" "icmp")])
1677 (define_insn "*cmpsi_andnot_1"
1678 [(set (match_operand:BI 0 "register_operand" "=c")
1679 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1680 [(match_operand:SI 2 "gr_register_operand" "r")
1682 (match_operand:BI 1 "register_operand" "0")))]
1684 "cmp4.%C3.or.andcm %I0, %0 = r0, %2"
1685 [(set_attr "itanium_class" "icmp")])
1687 (define_insn "*cmpdi_and_0"
1688 [(set (match_operand:BI 0 "register_operand" "=c")
1689 (and:BI (match_operator:BI 4 "predicate_operator"
1690 [(match_operand:DI 2 "gr_register_operand" "r")
1691 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1692 (match_operand:BI 1 "register_operand" "0")))]
1694 "cmp.%C4.and.orcm %0, %I0 = %3, %2"
1695 [(set_attr "itanium_class" "icmp")])
1697 (define_insn "*cmpdi_and_1"
1698 [(set (match_operand:BI 0 "register_operand" "=c")
1699 (and:BI (match_operator:BI 3 "signed_inequality_operator"
1700 [(match_operand:DI 2 "gr_register_operand" "r")
1702 (match_operand:BI 1 "register_operand" "0")))]
1704 "cmp.%C3.and.orcm %0, %I0 = r0, %2"
1705 [(set_attr "itanium_class" "icmp")])
1707 (define_insn "*cmpdi_andnot_0"
1708 [(set (match_operand:BI 0 "register_operand" "=c")
1709 (and:BI (not:BI (match_operator:BI 4 "predicate_operator"
1710 [(match_operand:DI 2 "gr_register_operand" "r")
1711 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1712 (match_operand:BI 1 "register_operand" "0")))]
1714 "cmp.%C4.or.andcm %I0, %0 = %3, %2"
1715 [(set_attr "itanium_class" "icmp")])
1717 (define_insn "*cmpdi_andnot_1"
1718 [(set (match_operand:BI 0 "register_operand" "=c")
1719 (and:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1720 [(match_operand:DI 2 "gr_register_operand" "r")
1722 (match_operand:BI 1 "register_operand" "0")))]
1724 "cmp.%C3.or.andcm %I0, %0 = r0, %2"
1725 [(set_attr "itanium_class" "icmp")])
1727 (define_insn "*tbit_and_0"
1728 [(set (match_operand:BI 0 "register_operand" "=c")
1729 (and:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1732 (match_operand:BI 2 "register_operand" "0")))]
1734 "tbit.nz.and.orcm %0, %I0 = %1, 0"
1735 [(set_attr "itanium_class" "tbit")])
1737 (define_insn "*tbit_and_1"
1738 [(set (match_operand:BI 0 "register_operand" "=c")
1739 (and:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1742 (match_operand:BI 2 "register_operand" "0")))]
1744 "tbit.z.and.orcm %0, %I0 = %1, 0"
1745 [(set_attr "itanium_class" "tbit")])
1747 (define_insn "*tbit_and_2"
1748 [(set (match_operand:BI 0 "register_operand" "=c")
1749 (and:BI (ne:BI (zero_extract:DI
1750 (match_operand:DI 1 "gr_register_operand" "r")
1752 (match_operand:DI 2 "shift_count_operand" "M"))
1754 (match_operand:BI 3 "register_operand" "0")))]
1756 "tbit.nz.and.orcm %0, %I0 = %1, %2"
1757 [(set_attr "itanium_class" "tbit")])
1759 (define_insn "*tbit_and_3"
1760 [(set (match_operand:BI 0 "register_operand" "=c")
1761 (and:BI (eq:BI (zero_extract:DI
1762 (match_operand:DI 1 "gr_register_operand" "r")
1764 (match_operand:DI 2 "shift_count_operand" "M"))
1766 (match_operand:BI 3 "register_operand" "0")))]
1768 "tbit.z.and.orcm %0, %I0 = %1, %2"
1769 [(set_attr "itanium_class" "tbit")])
1771 (define_insn "*cmpsi_or_0"
1772 [(set (match_operand:BI 0 "register_operand" "=c")
1773 (ior:BI (match_operator:BI 4 "predicate_operator"
1774 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1775 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")])
1776 (match_operand:BI 1 "register_operand" "0")))]
1778 "cmp4.%C4.or.andcm %0, %I0 = %3, %r2"
1779 [(set_attr "itanium_class" "icmp")])
1781 (define_insn "*cmpsi_or_1"
1782 [(set (match_operand:BI 0 "register_operand" "=c")
1783 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1784 [(match_operand:SI 2 "gr_register_operand" "r")
1786 (match_operand:BI 1 "register_operand" "0")))]
1788 "cmp4.%C3.or.andcm %0, %I0 = r0, %2"
1789 [(set_attr "itanium_class" "icmp")])
1791 (define_insn "*cmpsi_orcm_0"
1792 [(set (match_operand:BI 0 "register_operand" "=c")
1793 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1794 [(match_operand:SI 2 "gr_reg_or_0_operand" "rO")
1795 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))
1796 (match_operand:BI 1 "register_operand" "0")))]
1798 "cmp4.%C4.and.orcm %I0, %0 = %3, %r2"
1799 [(set_attr "itanium_class" "icmp")])
1801 (define_insn "*cmpsi_orcm_1"
1802 [(set (match_operand:BI 0 "register_operand" "=c")
1803 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1804 [(match_operand:SI 2 "gr_register_operand" "r")
1806 (match_operand:BI 1 "register_operand" "0")))]
1808 "cmp4.%C3.and.orcm %I0, %0 = r0, %2"
1809 [(set_attr "itanium_class" "icmp")])
1811 (define_insn "*cmpdi_or_0"
1812 [(set (match_operand:BI 0 "register_operand" "=c")
1813 (ior:BI (match_operator:BI 4 "predicate_operator"
1814 [(match_operand:DI 2 "gr_register_operand" "r")
1815 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")])
1816 (match_operand:BI 1 "register_operand" "0")))]
1818 "cmp.%C4.or.andcm %0, %I0 = %3, %2"
1819 [(set_attr "itanium_class" "icmp")])
1821 (define_insn "*cmpdi_or_1"
1822 [(set (match_operand:BI 0 "register_operand" "=c")
1823 (ior:BI (match_operator:BI 3 "signed_inequality_operator"
1824 [(match_operand:DI 2 "gr_register_operand" "r")
1826 (match_operand:BI 1 "register_operand" "0")))]
1828 "cmp.%C3.or.andcm %0, %I0 = r0, %2"
1829 [(set_attr "itanium_class" "icmp")])
1831 (define_insn "*cmpdi_orcm_0"
1832 [(set (match_operand:BI 0 "register_operand" "=c")
1833 (ior:BI (not:BI (match_operator:BI 4 "predicate_operator"
1834 [(match_operand:DI 2 "gr_register_operand" "r")
1835 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))
1836 (match_operand:BI 1 "register_operand" "0")))]
1838 "cmp.%C4.and.orcm %I0, %0 = %3, %2"
1839 [(set_attr "itanium_class" "icmp")])
1841 (define_insn "*cmpdi_orcm_1"
1842 [(set (match_operand:BI 0 "register_operand" "=c")
1843 (ior:BI (not:BI (match_operator:BI 3 "signed_inequality_operator"
1844 [(match_operand:DI 2 "gr_register_operand" "r")
1846 (match_operand:BI 1 "register_operand" "0")))]
1848 "cmp.%C3.and.orcm %I0, %0 = r0, %2"
1849 [(set_attr "itanium_class" "icmp")])
1851 (define_insn "*tbit_or_0"
1852 [(set (match_operand:BI 0 "register_operand" "=c")
1853 (ior:BI (ne:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1856 (match_operand:BI 2 "register_operand" "0")))]
1858 "tbit.nz.or.andcm %0, %I0 = %1, 0"
1859 [(set_attr "itanium_class" "tbit")])
1861 (define_insn "*tbit_or_1"
1862 [(set (match_operand:BI 0 "register_operand" "=c")
1863 (ior:BI (eq:BI (and:DI (match_operand:DI 1 "gr_register_operand" "r")
1866 (match_operand:BI 2 "register_operand" "0")))]
1868 "tbit.z.or.andcm %0, %I0 = %1, 0"
1869 [(set_attr "itanium_class" "tbit")])
1871 (define_insn "*tbit_or_2"
1872 [(set (match_operand:BI 0 "register_operand" "=c")
1873 (ior:BI (ne:BI (zero_extract:DI
1874 (match_operand:DI 1 "gr_register_operand" "r")
1876 (match_operand:DI 2 "shift_count_operand" "M"))
1878 (match_operand:BI 3 "register_operand" "0")))]
1880 "tbit.nz.or.andcm %0, %I0 = %1, %2"
1881 [(set_attr "itanium_class" "tbit")])
1883 (define_insn "*tbit_or_3"
1884 [(set (match_operand:BI 0 "register_operand" "=c")
1885 (ior:BI (eq:BI (zero_extract:DI
1886 (match_operand:DI 1 "gr_register_operand" "r")
1888 (match_operand:DI 2 "shift_count_operand" "M"))
1890 (match_operand:BI 3 "register_operand" "0")))]
1892 "tbit.z.or.andcm %0, %I0 = %1, %2"
1893 [(set_attr "itanium_class" "tbit")])
1895 ;; Transform test of and/or of setcc into parallel comparisons.
1898 [(set (match_operand:BI 0 "register_operand" "")
1899 (ne:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1901 (match_operand:DI 3 "register_operand" ""))
1905 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1910 [(set (match_operand:BI 0 "register_operand" "")
1911 (eq:BI (and:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1913 (match_operand:DI 3 "register_operand" ""))
1917 (and:BI (ne:BI (and:DI (match_dup 3) (const_int 1)) (const_int 0))
1919 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1920 (clobber (scratch))])]
1924 [(set (match_operand:BI 0 "register_operand" "")
1925 (ne:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1927 (match_operand:DI 3 "register_operand" ""))
1931 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1936 [(set (match_operand:BI 0 "register_operand" "")
1937 (eq:BI (ior:DI (ne:DI (match_operand:BI 2 "register_operand" "")
1939 (match_operand:DI 3 "register_operand" ""))
1943 (ior:BI (ne:BI (match_dup 3) (const_int 0))
1945 (parallel [(set (match_dup 0) (not:BI (match_dup 0)))
1946 (clobber (scratch))])]
1949 ;; ??? Incredibly hackish. Either need four proper patterns with all
1950 ;; the alternatives, or rely on sched1 to split the insn and hope that
1951 ;; nothing bad happens to the comparisons in the meantime.
1953 ;; Alternately, adjust combine to allow 2->2 and 3->3 splits, assuming
1954 ;; that we're doing height reduction.
1956 ;(define_insn_and_split ""
1957 ; [(set (match_operand:BI 0 "register_operand" "=c")
1958 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1959 ; [(match_operand 2 "" "")
1960 ; (match_operand 3 "" "")])
1961 ; (match_operator:BI 4 "comparison_operator"
1962 ; [(match_operand 5 "" "")
1963 ; (match_operand 6 "" "")]))
1965 ; "flag_schedule_insns"
1968 ; [(set (match_dup 0) (and:BI (match_dup 1) (match_dup 0)))
1969 ; (set (match_dup 0) (and:BI (match_dup 4) (match_dup 0)))]
1972 ;(define_insn_and_split ""
1973 ; [(set (match_operand:BI 0 "register_operand" "=c")
1974 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
1975 ; [(match_operand 2 "" "")
1976 ; (match_operand 3 "" "")])
1977 ; (match_operator:BI 4 "comparison_operator"
1978 ; [(match_operand 5 "" "")
1979 ; (match_operand 6 "" "")]))
1981 ; "flag_schedule_insns"
1984 ; [(set (match_dup 0) (ior:BI (match_dup 1) (match_dup 0)))
1985 ; (set (match_dup 0) (ior:BI (match_dup 4) (match_dup 0)))]
1989 ; [(set (match_operand:BI 0 "register_operand" "")
1990 ; (and:BI (and:BI (match_operator:BI 1 "comparison_operator"
1991 ; [(match_operand 2 "" "")
1992 ; (match_operand 3 "" "")])
1993 ; (match_operand:BI 7 "register_operand" ""))
1994 ; (and:BI (match_operator:BI 4 "comparison_operator"
1995 ; [(match_operand 5 "" "")
1996 ; (match_operand 6 "" "")])
1997 ; (match_operand:BI 8 "register_operand" ""))))]
1999 ; [(set (match_dup 0) (and:BI (match_dup 7) (match_dup 8)))
2000 ; (set (match_dup 0) (and:BI (and:BI (match_dup 1) (match_dup 4))
2005 ; [(set (match_operand:BI 0 "register_operand" "")
2006 ; (ior:BI (ior:BI (match_operator:BI 1 "comparison_operator"
2007 ; [(match_operand 2 "" "")
2008 ; (match_operand 3 "" "")])
2009 ; (match_operand:BI 7 "register_operand" ""))
2010 ; (ior:BI (match_operator:BI 4 "comparison_operator"
2011 ; [(match_operand 5 "" "")
2012 ; (match_operand 6 "" "")])
2013 ; (match_operand:BI 8 "register_operand" ""))))]
2015 ; [(set (match_dup 0) (ior:BI (match_dup 7) (match_dup 8)))
2016 ; (set (match_dup 0) (ior:BI (ior:BI (match_dup 1) (match_dup 4))
2020 ;; Try harder to avoid predicate copies by duplicating compares.
2021 ;; Note that we'll have already split the predicate copy, which
2022 ;; is kind of a pain, but oh well.
2025 [(set (match_operand:BI 0 "register_operand" "")
2026 (match_operand:BI 1 "comparison_operator" ""))
2027 (set (match_operand:CCI 2 "register_operand" "")
2028 (match_operand:CCI 3 "register_operand" ""))
2029 (set (match_operand:CCI 4 "register_operand" "")
2030 (match_operand:CCI 5 "register_operand" ""))
2031 (set (match_operand:BI 6 "register_operand" "")
2032 (unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
2033 "REGNO (operands[3]) == REGNO (operands[0])
2034 && REGNO (operands[4]) == REGNO (operands[0]) + 1
2035 && REGNO (operands[4]) == REGNO (operands[2]) + 1
2036 && REGNO (operands[6]) == REGNO (operands[2])"
2037 [(set (match_dup 0) (match_dup 1))
2038 (set (match_dup 6) (match_dup 7))]
2039 "operands[7] = copy_rtx (operands[1]);")
2041 ;; ::::::::::::::::::::
2043 ;; :: 16-bit Integer arithmetic
2045 ;; ::::::::::::::::::::
2047 (define_insn "mulhi3"
2048 [(set (match_operand:HI 0 "gr_register_operand" "=r")
2049 (mult:HI (match_operand:HI 1 "gr_register_operand" "r")
2050 (match_operand:HI 2 "gr_register_operand" "r")))]
2052 "pmpy2.r %0 = %1, %2"
2053 [(set_attr "itanium_class" "mmmul")])
2056 ;; ::::::::::::::::::::
2058 ;; :: 32-bit Integer arithmetic
2060 ;; ::::::::::::::::::::
2062 (define_insn "addsi3"
2063 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
2064 (plus:SI (match_operand:SI 1 "gr_register_operand" "%r,r,a")
2065 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2071 [(set_attr "itanium_class" "ialu")])
2073 (define_insn "*addsi3_plus1"
2074 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2075 (plus:SI (plus:SI (match_operand:SI 1 "gr_register_operand" "r")
2076 (match_operand:SI 2 "gr_register_operand" "r"))
2079 "add %0 = %1, %2, 1"
2080 [(set_attr "itanium_class" "ialu")])
2082 (define_insn "*addsi3_plus1_alt"
2083 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2084 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2088 "add %0 = %1, %1, 1"
2089 [(set_attr "itanium_class" "ialu")])
2091 (define_insn "*addsi3_shladd"
2092 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2093 (plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
2094 (match_operand:SI 2 "shladd_operand" "n"))
2095 (match_operand:SI 3 "gr_register_operand" "r")))]
2097 "shladd %0 = %1, %S2, %3"
2098 [(set_attr "itanium_class" "ialu")])
2100 (define_insn "subsi3"
2101 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2102 (minus:SI (match_operand:SI 1 "gr_reg_or_8bit_operand" "rK")
2103 (match_operand:SI 2 "gr_register_operand" "r")))]
2106 [(set_attr "itanium_class" "ialu")])
2108 (define_insn "*subsi3_minus1"
2109 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2110 (plus:SI (not:SI (match_operand:SI 1 "gr_register_operand" "r"))
2111 (match_operand:SI 2 "gr_register_operand" "r")))]
2113 "sub %0 = %2, %1, 1"
2114 [(set_attr "itanium_class" "ialu")])
2116 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
2118 (define_insn "mulsi3"
2119 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2120 (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2121 (match_operand:SI 2 "grfr_register_operand" "f")))]
2123 "xmpy.l %0 = %1, %2"
2124 [(set_attr "itanium_class" "xmpy")])
2126 (define_insn "maddsi4"
2127 [(set (match_operand:SI 0 "fr_register_operand" "=f")
2128 (plus:SI (mult:SI (match_operand:SI 1 "grfr_register_operand" "f")
2129 (match_operand:SI 2 "grfr_register_operand" "f"))
2130 (match_operand:SI 3 "grfr_register_operand" "f")))]
2132 "xma.l %0 = %1, %2, %3"
2133 [(set_attr "itanium_class" "xmpy")])
2135 (define_insn "negsi2"
2136 [(set (match_operand:SI 0 "gr_register_operand" "=r")
2137 (neg:SI (match_operand:SI 1 "gr_register_operand" "r")))]
2140 [(set_attr "itanium_class" "ialu")])
2142 (define_expand "abssi2"
2144 (ge:BI (match_operand:SI 1 "gr_register_operand" "") (const_int 0)))
2145 (set (match_operand:SI 0 "gr_register_operand" "")
2146 (if_then_else:SI (eq (match_dup 2) (const_int 0))
2147 (neg:SI (match_dup 1))
2150 { operands[2] = gen_reg_rtx (BImode); })
2152 (define_expand "sminsi3"
2154 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2155 (match_operand:SI 2 "gr_register_operand" "")))
2156 (set (match_operand:SI 0 "gr_register_operand" "")
2157 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2158 (match_dup 2) (match_dup 1)))]
2160 { operands[3] = gen_reg_rtx (BImode); })
2162 (define_expand "smaxsi3"
2164 (ge:BI (match_operand:SI 1 "gr_register_operand" "")
2165 (match_operand:SI 2 "gr_register_operand" "")))
2166 (set (match_operand:SI 0 "gr_register_operand" "")
2167 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2168 (match_dup 1) (match_dup 2)))]
2170 { operands[3] = gen_reg_rtx (BImode); })
2172 (define_expand "uminsi3"
2174 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2175 (match_operand:SI 2 "gr_register_operand" "")))
2176 (set (match_operand:SI 0 "gr_register_operand" "")
2177 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2178 (match_dup 2) (match_dup 1)))]
2180 { operands[3] = gen_reg_rtx (BImode); })
2182 (define_expand "umaxsi3"
2184 (geu:BI (match_operand:SI 1 "gr_register_operand" "")
2185 (match_operand:SI 2 "gr_register_operand" "")))
2186 (set (match_operand:SI 0 "gr_register_operand" "")
2187 (if_then_else:SI (ne (match_dup 3) (const_int 0))
2188 (match_dup 1) (match_dup 2)))]
2190 { operands[3] = gen_reg_rtx (BImode); })
2192 ;; ::::::::::::::::::::
2194 ;; :: 64-bit Integer arithmetic
2196 ;; ::::::::::::::::::::
2198 (define_insn "adddi3"
2199 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
2200 (plus:DI (match_operand:DI 1 "gr_register_operand" "%r,r,a")
2201 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
2207 [(set_attr "itanium_class" "ialu")])
2209 (define_insn "*adddi3_plus1"
2210 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2211 (plus:DI (plus:DI (match_operand:DI 1 "gr_register_operand" "r")
2212 (match_operand:DI 2 "gr_register_operand" "r"))
2215 "add %0 = %1, %2, 1"
2216 [(set_attr "itanium_class" "ialu")])
2218 ;; This has some of the same problems as shladd. We let the shladd
2219 ;; eliminator hack handle it, which results in the 1 being forced into
2220 ;; a register, but not more ugliness here.
2221 (define_insn "*adddi3_plus1_alt"
2222 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2223 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
2227 "add %0 = %1, %1, 1"
2228 [(set_attr "itanium_class" "ialu")])
2230 (define_insn "subdi3"
2231 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2232 (minus:DI (match_operand:DI 1 "gr_reg_or_8bit_operand" "rK")
2233 (match_operand:DI 2 "gr_register_operand" "r")))]
2236 [(set_attr "itanium_class" "ialu")])
2238 (define_insn "*subdi3_minus1"
2239 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2240 (plus:DI (not:DI (match_operand:DI 1 "gr_register_operand" "r"))
2241 (match_operand:DI 2 "gr_register_operand" "r")))]
2243 "sub %0 = %2, %1, 1"
2244 [(set_attr "itanium_class" "ialu")])
2246 ;; ??? Use grfr instead of fr because of virtual register elimination
2247 ;; and silly test cases multiplying by the frame pointer.
2248 (define_insn "muldi3"
2249 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2250 (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2251 (match_operand:DI 2 "grfr_register_operand" "f")))]
2253 "xmpy.l %0 = %1, %2"
2254 [(set_attr "itanium_class" "xmpy")])
2256 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
2257 ;; same problem that we have with shladd below. Unfortunately, this case is
2258 ;; much harder to fix because the multiply puts the result in an FP register,
2259 ;; but the add needs inputs from a general register. We add a spurious clobber
2260 ;; here so that it will be present just in case register elimination gives us
2261 ;; the funny result.
2263 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
2265 ;; ??? Maybe we should change how adds are canonicalized.
2267 (define_insn "madddi4"
2268 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2269 (plus:DI (mult:DI (match_operand:DI 1 "grfr_register_operand" "f")
2270 (match_operand:DI 2 "grfr_register_operand" "f"))
2271 (match_operand:DI 3 "grfr_register_operand" "f")))
2272 (clobber (match_scratch:DI 4 "=X"))]
2274 "xma.l %0 = %1, %2, %3"
2275 [(set_attr "itanium_class" "xmpy")])
2277 ;; This can be created by register elimination if operand3 of shladd is an
2278 ;; eliminable register or has reg_equiv_constant set.
2280 ;; We have to use nonmemory_operand for operand 4, to ensure that the
2281 ;; validate_changes call inside eliminate_regs will always succeed. If it
2282 ;; doesn't succeed, then this remain a madddi4 pattern, and will be reloaded
2285 (define_insn "*madddi4_elim"
2286 [(set (match_operand:DI 0 "register_operand" "=&r")
2287 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
2288 (match_operand:DI 2 "register_operand" "f"))
2289 (match_operand:DI 3 "register_operand" "f"))
2290 (match_operand:DI 4 "nonmemory_operand" "rI")))
2291 (clobber (match_scratch:DI 5 "=f"))]
2292 "reload_in_progress"
2294 [(set_attr "itanium_class" "unknown")])
2297 [(set (match_operand:DI 0 "register_operand" "")
2298 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2299 (match_operand:DI 2 "register_operand" ""))
2300 (match_operand:DI 3 "register_operand" ""))
2301 (match_operand:DI 4 "gr_reg_or_14bit_operand" "")))
2302 (clobber (match_scratch:DI 5 ""))]
2304 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
2306 (clobber (match_dup 0))])
2307 (set (match_dup 0) (match_dup 5))
2308 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
2311 (define_insn "smuldi3_highpart"
2312 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2315 (mult:TI (sign_extend:TI
2316 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2318 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
2321 "xmpy.h %0 = %F1, %F2"
2322 [(set_attr "itanium_class" "xmpy")])
2324 (define_insn "umuldi3_highpart"
2325 [(set (match_operand:DI 0 "fr_register_operand" "=f")
2328 (mult:TI (zero_extend:TI
2329 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2331 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
2334 "xmpy.hu %0 = %F1, %F2"
2335 [(set_attr "itanium_class" "xmpy")])
2337 (define_insn "negdi2"
2338 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2339 (neg:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2342 [(set_attr "itanium_class" "ialu")])
2344 (define_expand "absdi2"
2346 (ge:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2347 (set (match_operand:DI 0 "gr_register_operand" "")
2348 (if_then_else:DI (eq (match_dup 2) (const_int 0))
2349 (neg:DI (match_dup 1))
2352 { operands[2] = gen_reg_rtx (BImode); })
2354 (define_expand "smindi3"
2356 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2357 (match_operand:DI 2 "gr_register_operand" "")))
2358 (set (match_operand:DI 0 "gr_register_operand" "")
2359 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2360 (match_dup 2) (match_dup 1)))]
2362 { operands[3] = gen_reg_rtx (BImode); })
2364 (define_expand "smaxdi3"
2366 (ge:BI (match_operand:DI 1 "gr_register_operand" "")
2367 (match_operand:DI 2 "gr_register_operand" "")))
2368 (set (match_operand:DI 0 "gr_register_operand" "")
2369 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2370 (match_dup 1) (match_dup 2)))]
2372 { operands[3] = gen_reg_rtx (BImode); })
2374 (define_expand "umindi3"
2376 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2377 (match_operand:DI 2 "gr_register_operand" "")))
2378 (set (match_operand:DI 0 "gr_register_operand" "")
2379 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2380 (match_dup 2) (match_dup 1)))]
2382 { operands[3] = gen_reg_rtx (BImode); })
2384 (define_expand "umaxdi3"
2386 (geu:BI (match_operand:DI 1 "gr_register_operand" "")
2387 (match_operand:DI 2 "gr_register_operand" "")))
2388 (set (match_operand:DI 0 "gr_register_operand" "")
2389 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2390 (match_dup 1) (match_dup 2)))]
2392 { operands[3] = gen_reg_rtx (BImode); })
2394 (define_expand "ffsdi2"
2396 (eq:BI (match_operand:DI 1 "gr_register_operand" "") (const_int 0)))
2397 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
2398 (set (match_dup 5) (const_int 0))
2399 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
2400 (set (match_dup 4) (popcount:DI (match_dup 3)))
2401 (set (match_operand:DI 0 "gr_register_operand" "")
2402 (if_then_else:DI (ne (match_dup 6) (const_int 0))
2403 (match_dup 5) (match_dup 4)))]
2406 operands[2] = gen_reg_rtx (DImode);
2407 operands[3] = gen_reg_rtx (DImode);
2408 operands[4] = gen_reg_rtx (DImode);
2409 operands[5] = gen_reg_rtx (DImode);
2410 operands[6] = gen_reg_rtx (BImode);
2413 (define_expand "ctzdi2"
2414 [(set (match_dup 2) (plus:DI (match_operand:DI 1 "gr_register_operand" "")
2416 (set (match_dup 3) (not:DI (match_dup 1)))
2417 (set (match_dup 4) (and:DI (match_dup 2) (match_dup 3)))
2418 (set (match_operand:DI 0 "gr_register_operand" "")
2419 (popcount:DI (match_dup 4)))]
2422 operands[2] = gen_reg_rtx (DImode);
2423 operands[3] = gen_reg_rtx (DImode);
2424 operands[4] = gen_reg_rtx (DImode);
2427 ;; Note the computation here is op0 = 63 - (exp - 0xffff).
2428 (define_expand "clzdi2"
2430 (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "")))
2432 (unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
2433 (set (match_dup 4) (const_int 65598))
2434 (set (match_operand:DI 0 "gr_register_operand" "")
2435 (minus:DI (match_dup 4) (match_dup 3)))]
2438 operands[2] = gen_reg_rtx (XFmode);
2439 operands[3] = gen_reg_rtx (DImode);
2440 operands[4] = gen_reg_rtx (DImode);
2443 (define_insn "popcountdi2"
2444 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2445 (popcount:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2448 [(set_attr "itanium_class" "mmmul")])
2450 (define_insn "bswapdi2"
2451 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2452 (bswap:DI (match_operand:DI 1 "gr_register_operand" "r")))]
2454 "mux1 %0 = %1, @rev"
2455 [(set_attr "itanium_class" "mmshf")])
2457 (define_insn "*getf_exp_xf"
2458 [(set (match_operand:DI 0 "gr_register_operand" "=r")
2459 (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")]
2463 [(set_attr "itanium_class" "frfr")])
2465 ;; ::::::::::::::::::::
2467 ;; :: 128-bit Integer arithmetic
2469 ;; ::::::::::::::::::::
2471 (define_insn "addti3"
2472 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2473 (plus:TI (match_operand:TI 1 "gr_register_operand" "%r")
2474 (match_operand:TI 2 "gr_reg_or_14bit_operand" "rI")))
2475 (clobber (match_scratch:BI 3 "=&c"))]
2478 [(set_attr "itanium_class" "unknown")])
2481 [(set (match_operand:TI 0 "register_operand" "")
2482 (plus:TI (match_operand:TI 1 "register_operand" "")
2483 (match_operand:TI 2 "register_operand" "")))
2484 (clobber (match_scratch:BI 3 ""))]
2486 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2487 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2488 (cond_exec (eq (match_dup 3) (const_int 0))
2489 (set (match_dup 4) (plus:DI (match_dup 5) (match_dup 6))))
2490 (cond_exec (ne (match_dup 3) (const_int 0))
2492 (plus:DI (plus:DI (match_dup 5) (match_dup 6))
2495 operands[4] = gen_highpart (DImode, operands[0]);
2496 operands[0] = gen_lowpart (DImode, operands[0]);
2497 operands[5] = gen_highpart (DImode, operands[1]);
2498 operands[1] = gen_lowpart (DImode, operands[1]);
2499 operands[6] = gen_highpart (DImode, operands[2]);
2500 operands[2] = gen_lowpart (DImode, operands[2]);
2504 [(set (match_operand:TI 0 "register_operand" "")
2505 (plus:TI (match_operand:TI 1 "register_operand" "")
2506 (match_operand:TI 2 "immediate_operand" "")))
2507 (clobber (match_scratch:BI 3 ""))]
2509 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
2510 (set (match_dup 3) (ltu:BI (match_dup 0) (match_dup 1)))
2511 (cond_exec (eq (match_dup 3) (const_int 0))
2513 (plus:DI (match_dup 5) (match_dup 6))))
2514 (cond_exec (ne (match_dup 3) (const_int 0))
2516 (plus:DI (match_dup 5) (match_dup 7))))]
2518 operands[4] = gen_highpart (DImode, operands[0]);
2519 operands[0] = gen_lowpart (DImode, operands[0]);
2520 operands[5] = gen_highpart (DImode, operands[1]);
2521 operands[1] = gen_lowpart (DImode, operands[1]);
2522 operands[6] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2523 operands[7] = INTVAL (operands[2]) < 0 ? const0_rtx : const1_rtx;
2526 (define_insn "subti3"
2527 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2528 (minus:TI (match_operand:TI 1 "gr_reg_or_8bit_operand" "rK")
2529 (match_operand:TI 2 "gr_register_operand" "r")))
2530 (clobber (match_scratch:BI 3 "=&c"))]
2533 [(set_attr "itanium_class" "unknown")])
2536 [(set (match_operand:TI 0 "register_operand" "")
2537 (minus:TI (match_operand:TI 1 "register_operand" "")
2538 (match_operand:TI 2 "register_operand" "")))
2539 (clobber (match_scratch:BI 3 "=&c"))]
2541 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2542 (set (match_dup 3) (ltu:BI (match_dup 1) (match_dup 0)))
2543 (cond_exec (eq (match_dup 3) (const_int 0))
2544 (set (match_dup 4) (minus:DI (match_dup 5) (match_dup 6))))
2545 (cond_exec (ne (match_dup 3) (const_int 0))
2547 (plus:DI (not:DI (match_dup 6)) (match_dup 5))))]
2549 operands[4] = gen_highpart (DImode, operands[0]);
2550 operands[0] = gen_lowpart (DImode, operands[0]);
2551 operands[5] = gen_highpart (DImode, operands[1]);
2552 operands[1] = gen_lowpart (DImode, operands[1]);
2553 operands[6] = gen_highpart (DImode, operands[2]);
2554 operands[2] = gen_lowpart (DImode, operands[2]);
2558 [(set (match_operand:TI 0 "register_operand" "")
2559 (minus:TI (match_operand:TI 1 "immediate_operand" "")
2560 (match_operand:TI 2 "register_operand" "")))
2561 (clobber (match_scratch:BI 3 "=&c"))]
2562 "reload_completed && satisfies_constraint_K (operands[1])"
2563 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
2564 (set (match_dup 3) (gtu:BI (match_dup 0) (match_dup 1)))
2565 (cond_exec (ne (match_dup 3) (const_int 0))
2566 (set (match_dup 4) (minus:DI (match_dup 6) (match_dup 5))))
2567 (cond_exec (eq (match_dup 3) (const_int 0))
2568 (set (match_dup 4) (minus:DI (match_dup 7) (match_dup 5))))]
2570 operands[4] = gen_highpart (DImode, operands[0]);
2571 operands[0] = gen_lowpart (DImode, operands[0]);
2572 operands[5] = gen_highpart (DImode, operands[2]);
2573 operands[2] = gen_lowpart (DImode, operands[2]);
2574 operands[6] = INTVAL (operands[1]) < 0 ? GEN_INT (-2) : constm1_rtx;
2575 operands[7] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
2578 (define_expand "mulditi3"
2579 [(set (match_operand:TI 0 "fr_register_operand" "")
2580 (mult:TI (sign_extend:TI
2581 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
2583 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
2587 (define_insn_and_split "*mulditi3_internal"
2588 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2589 (mult:TI (sign_extend:TI
2590 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2592 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
2596 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2597 (set (match_dup 3) (truncate:DI
2599 (mult:TI (sign_extend:TI (match_dup 1))
2600 (sign_extend:TI (match_dup 2)))
2603 operands[3] = gen_highpart (DImode, operands[0]);
2604 operands[0] = gen_lowpart (DImode, operands[0]);
2606 [(set_attr "itanium_class" "unknown")])
2608 (define_expand "umulditi3"
2609 [(set (match_operand:TI 0 "fr_register_operand" "")
2610 (mult:TI (zero_extend:TI
2611 (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
2613 (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
2617 (define_insn_and_split "*umulditi3_internal"
2618 [(set (match_operand:TI 0 "fr_register_operand" "=&f")
2619 (mult:TI (zero_extend:TI
2620 (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
2622 (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
2626 [(set (match_dup 0) (mult:DI (match_dup 1) (match_dup 2)))
2627 (set (match_dup 3) (truncate:DI
2629 (mult:TI (zero_extend:TI (match_dup 1))
2630 (zero_extend:TI (match_dup 2)))
2633 operands[3] = gen_highpart (DImode, operands[0]);
2634 operands[0] = gen_lowpart (DImode, operands[0]);
2636 [(set_attr "itanium_class" "unknown")])
2638 (define_insn_and_split "negti2"
2639 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
2640 (neg:TI (match_operand:TI 1 "gr_register_operand" "r")))
2641 (clobber (match_scratch:BI 2 "=&c"))]
2645 [(set (match_dup 2) (eq:BI (match_dup 1) (const_int 0)))
2646 (set (match_dup 0) (minus:DI (const_int 0) (match_dup 1)))
2647 (cond_exec (eq (match_dup 2) (const_int 0))
2648 (set (match_dup 3) (minus:DI (const_int -1) (match_dup 4))))
2649 (cond_exec (ne (match_dup 2) (const_int 0))
2650 (set (match_dup 3) (minus:DI (const_int 0) (match_dup 4))))]
2652 operands[3] = gen_highpart (DImode, operands[0]);
2653 operands[0] = gen_lowpart (DImode, operands[0]);
2654 operands[4] = gen_highpart (DImode, operands[1]);
2655 operands[1] = gen_lowpart (DImode, operands[1]);
2657 [(set_attr "itanium_class" "unknown")])
2659 ;; ::::::::::::::::::::
2661 ;; :: 32-bit floating point arithmetic
2663 ;; ::::::::::::::::::::
2665 (define_insn "addsf3"
2666 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2667 (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2668 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2670 "fadd.s %0 = %F1, %F2"
2671 [(set_attr "itanium_class" "fmac")])
2673 (define_insn "subsf3"
2674 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2675 (minus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2676 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2678 "fsub.s %0 = %F1, %F2"
2679 [(set_attr "itanium_class" "fmac")])
2681 (define_insn "mulsf3"
2682 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2683 (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2684 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2686 "fmpy.s %0 = %F1, %F2"
2687 [(set_attr "itanium_class" "fmac")])
2689 (define_insn "abssf2"
2690 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2691 (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
2694 [(set_attr "itanium_class" "fmisc")])
2696 (define_insn "negsf2"
2697 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2698 (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
2701 [(set_attr "itanium_class" "fmisc")])
2703 (define_insn "*nabssf2"
2704 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2705 (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))]
2708 [(set_attr "itanium_class" "fmisc")])
2710 (define_insn "copysignsf3"
2711 [(set (match_operand:SF 0 "register_operand" "=f")
2712 (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2713 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2716 "fmerge.s %0 = %F2, %F1"
2717 [(set_attr "itanium_class" "fmisc")])
2719 (define_insn "*ncopysignsf3"
2720 [(set (match_operand:SF 0 "register_operand" "=f")
2721 (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2722 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")]
2725 "fmerge.ns %0 = %F2, %F1"
2726 [(set_attr "itanium_class" "fmisc")])
2728 (define_insn "sminsf3"
2729 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2730 (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2731 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2733 "fmin %0 = %F1, %F2"
2734 [(set_attr "itanium_class" "fmisc")])
2736 (define_insn "smaxsf3"
2737 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2738 (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2739 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
2741 "fmax %0 = %F1, %F2"
2742 [(set_attr "itanium_class" "fmisc")])
2744 (define_insn "*maddsf4"
2745 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2746 (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2747 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
2748 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2750 "fma.s %0 = %F1, %F2, %F3"
2751 [(set_attr "itanium_class" "fmac")])
2753 (define_insn "*msubsf4"
2754 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2755 (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2756 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
2757 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
2759 "fms.s %0 = %F1, %F2, %F3"
2760 [(set_attr "itanium_class" "fmac")])
2762 (define_insn "*nmulsf3"
2763 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2764 (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2765 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
2767 "fnmpy.s %0 = %F1, %F2"
2768 [(set_attr "itanium_class" "fmac")])
2770 (define_insn "*nmaddsf4"
2771 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2772 (minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
2773 (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
2774 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
2776 "fnma.s %0 = %F1, %F2, %F3"
2777 [(set_attr "itanium_class" "fmac")])
2779 ;; ::::::::::::::::::::
2781 ;; :: 64-bit floating point arithmetic
2783 ;; ::::::::::::::::::::
2785 (define_insn "adddf3"
2786 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2787 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2788 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2790 "fadd.d %0 = %F1, %F2"
2791 [(set_attr "itanium_class" "fmac")])
2793 (define_insn "*adddf3_trunc"
2794 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2796 (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2797 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2799 "fadd.s %0 = %F1, %F2"
2800 [(set_attr "itanium_class" "fmac")])
2802 (define_insn "subdf3"
2803 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2804 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2805 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2807 "fsub.d %0 = %F1, %F2"
2808 [(set_attr "itanium_class" "fmac")])
2810 (define_insn "*subdf3_trunc"
2811 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2813 (minus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2814 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2816 "fsub.s %0 = %F1, %F2"
2817 [(set_attr "itanium_class" "fmac")])
2819 (define_insn "muldf3"
2820 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2821 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2822 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2824 "fmpy.d %0 = %F1, %F2"
2825 [(set_attr "itanium_class" "fmac")])
2827 (define_insn "*muldf3_trunc"
2828 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2830 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2831 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2833 "fmpy.s %0 = %F1, %F2"
2834 [(set_attr "itanium_class" "fmac")])
2836 (define_insn "absdf2"
2837 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2838 (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
2841 [(set_attr "itanium_class" "fmisc")])
2843 (define_insn "negdf2"
2844 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2845 (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
2848 [(set_attr "itanium_class" "fmisc")])
2850 (define_insn "*nabsdf2"
2851 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2852 (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))]
2855 [(set_attr "itanium_class" "fmisc")])
2857 (define_insn "copysigndf3"
2858 [(set (match_operand:DF 0 "register_operand" "=f")
2859 (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2860 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2863 "fmerge.s %0 = %F2, %F1"
2864 [(set_attr "itanium_class" "fmisc")])
2866 (define_insn "*ncopysigndf3"
2867 [(set (match_operand:DF 0 "register_operand" "=f")
2868 (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2869 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")]
2872 "fmerge.ns %0 = %F2, %F1"
2873 [(set_attr "itanium_class" "fmisc")])
2875 (define_insn "smindf3"
2876 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2877 (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2878 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2880 "fmin %0 = %F1, %F2"
2881 [(set_attr "itanium_class" "fmisc")])
2883 (define_insn "smaxdf3"
2884 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2885 (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2886 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
2888 "fmax %0 = %F1, %F2"
2889 [(set_attr "itanium_class" "fmisc")])
2891 (define_insn "*madddf4"
2892 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2893 (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2894 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
2895 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2897 "fma.d %0 = %F1, %F2, %F3"
2898 [(set_attr "itanium_class" "fmac")])
2900 (define_insn "*madddf4_trunc"
2901 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2903 (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2904 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
2905 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2907 "fma.s %0 = %F1, %F2, %F3"
2908 [(set_attr "itanium_class" "fmac")])
2910 (define_insn "*msubdf4"
2911 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2912 (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2913 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
2914 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
2916 "fms.d %0 = %F1, %F2, %F3"
2917 [(set_attr "itanium_class" "fmac")])
2919 (define_insn "*msubdf4_trunc"
2920 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2922 (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2923 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
2924 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
2926 "fms.s %0 = %F1, %F2, %F3"
2927 [(set_attr "itanium_class" "fmac")])
2929 (define_insn "*nmuldf3"
2930 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2931 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2932 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2934 "fnmpy.d %0 = %F1, %F2"
2935 [(set_attr "itanium_class" "fmac")])
2937 (define_insn "*nmuldf3_trunc"
2938 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2940 (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2941 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
2943 "fnmpy.s %0 = %F1, %F2"
2944 [(set_attr "itanium_class" "fmac")])
2946 (define_insn "*nmadddf4"
2947 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2948 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
2949 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2950 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
2952 "fnma.d %0 = %F1, %F2, %F3"
2953 [(set_attr "itanium_class" "fmac")])
2955 (define_insn "*nmadddf4_truncsf"
2956 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2958 (minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
2959 (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
2960 (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
2962 "fnma.s %0 = %F1, %F2, %F3"
2963 [(set_attr "itanium_class" "fmac")])
2965 ;; ::::::::::::::::::::
2967 ;; :: 80-bit floating point arithmetic
2969 ;; ::::::::::::::::::::
2971 (define_insn "addxf3"
2972 [(set (match_operand:XF 0 "fr_register_operand" "=f")
2973 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
2974 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
2976 "fadd %0 = %F1, %F2"
2977 [(set_attr "itanium_class" "fmac")])
2979 (define_insn "*addxf3_truncsf"
2980 [(set (match_operand:SF 0 "fr_register_operand" "=f")
2982 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
2983 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
2985 "fadd.s %0 = %F1, %F2"
2986 [(set_attr "itanium_class" "fmac")])
2988 (define_insn "*addxf3_truncdf"
2989 [(set (match_operand:DF 0 "fr_register_operand" "=f")
2991 (plus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
2992 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
2994 "fadd.d %0 = %F1, %F2"
2995 [(set_attr "itanium_class" "fmac")])
2997 (define_insn "subxf3"
2998 [(set (match_operand:XF 0 "fr_register_operand" "=f")
2999 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3000 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3002 "fsub %0 = %F1, %F2"
3003 [(set_attr "itanium_class" "fmac")])
3005 (define_insn "*subxf3_truncsf"
3006 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3008 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3009 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3011 "fsub.s %0 = %F1, %F2"
3012 [(set_attr "itanium_class" "fmac")])
3014 (define_insn "*subxf3_truncdf"
3015 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3017 (minus:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3018 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3020 "fsub.d %0 = %F1, %F2"
3021 [(set_attr "itanium_class" "fmac")])
3023 (define_insn "mulxf3"
3024 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3025 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3026 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3028 "fmpy %0 = %F1, %F2"
3029 [(set_attr "itanium_class" "fmac")])
3031 (define_insn "*mulxf3_truncsf"
3032 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3034 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3035 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3037 "fmpy.s %0 = %F1, %F2"
3038 [(set_attr "itanium_class" "fmac")])
3040 (define_insn "*mulxf3_truncdf"
3041 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3043 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3044 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3046 "fmpy.d %0 = %F1, %F2"
3047 [(set_attr "itanium_class" "fmac")])
3049 (define_insn "absxf2"
3050 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3051 (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3054 [(set_attr "itanium_class" "fmisc")])
3056 (define_insn "negxf2"
3057 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3058 (neg:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")))]
3061 [(set_attr "itanium_class" "fmisc")])
3063 (define_insn "*nabsxf2"
3064 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3065 (neg:XF (abs:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG"))))]
3068 [(set_attr "itanium_class" "fmisc")])
3070 (define_insn "copysignxf3"
3071 [(set (match_operand:XF 0 "register_operand" "=f")
3072 (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3073 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3076 "fmerge.s %0 = %F2, %F1"
3077 [(set_attr "itanium_class" "fmisc")])
3079 (define_insn "*ncopysignxf3"
3080 [(set (match_operand:XF 0 "register_operand" "=f")
3081 (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
3082 (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
3085 "fmerge.ns %0 = %F2, %F1"
3086 [(set_attr "itanium_class" "fmisc")])
3088 (define_insn "sminxf3"
3089 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3090 (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3091 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3093 "fmin %0 = %F1, %F2"
3094 [(set_attr "itanium_class" "fmisc")])
3096 (define_insn "smaxxf3"
3097 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3098 (smax:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3099 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))]
3101 "fmax %0 = %F1, %F2"
3102 [(set_attr "itanium_class" "fmisc")])
3104 (define_insn "*maddxf4"
3105 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3106 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3107 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3108 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3110 "fma %0 = %F1, %F2, %F3"
3111 [(set_attr "itanium_class" "fmac")])
3113 (define_insn "*maddxf4_truncsf"
3114 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3116 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3117 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3118 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3120 "fma.s %0 = %F1, %F2, %F3"
3121 [(set_attr "itanium_class" "fmac")])
3123 (define_insn "*maddxf4_truncdf"
3124 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3126 (plus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3127 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3128 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3130 "fma.d %0 = %F1, %F2, %F3"
3131 [(set_attr "itanium_class" "fmac")])
3133 (define_insn "*msubxf4"
3134 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3135 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3136 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3137 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")))]
3139 "fms %0 = %F1, %F2, %F3"
3140 [(set_attr "itanium_class" "fmac")])
3142 (define_insn "*msubxf4_truncsf"
3143 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3145 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3146 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3147 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3149 "fms.s %0 = %F1, %F2, %F3"
3150 [(set_attr "itanium_class" "fmac")])
3152 (define_insn "*msubxf4_truncdf"
3153 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3155 (minus:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3156 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))
3157 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG"))))]
3159 "fms.d %0 = %F1, %F2, %F3"
3160 [(set_attr "itanium_class" "fmac")])
3162 (define_insn "*nmulxf3"
3163 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3164 (neg:XF (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3165 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG"))))]
3167 "fnmpy %0 = %F1, %F2"
3168 [(set_attr "itanium_class" "fmac")])
3170 (define_insn "*nmulxf3_truncsf"
3171 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3174 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3175 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3177 "fnmpy.s %0 = %F1, %F2"
3178 [(set_attr "itanium_class" "fmac")])
3180 (define_insn "*nmulxf3_truncdf"
3181 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3184 (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3185 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")))))]
3187 "fnmpy.d %0 = %F1, %F2"
3188 [(set_attr "itanium_class" "fmac")])
3190 (define_insn "*nmaddxf4"
3191 [(set (match_operand:XF 0 "fr_register_operand" "=f")
3192 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3193 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3194 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3197 "fnma %0 = %F1, %F2, %F3"
3198 [(set_attr "itanium_class" "fmac")])
3200 (define_insn "*nmaddxf4_truncsf"
3201 [(set (match_operand:SF 0 "fr_register_operand" "=f")
3203 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3204 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3205 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3208 "fnma.s %0 = %F1, %F2, %F3"
3209 [(set_attr "itanium_class" "fmac")])
3211 (define_insn "*nmaddxf4_truncdf"
3212 [(set (match_operand:DF 0 "fr_register_operand" "=f")
3214 (minus:XF (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")
3215 (mult:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG")
3216 (match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3219 "fnma.d %0 = %F1, %F2, %F3"
3220 [(set_attr "itanium_class" "fmac")])
3222 ;; ::::::::::::::::::::
3224 ;; :: 32-bit Integer Shifts and Rotates
3226 ;; ::::::::::::::::::::
3228 (define_expand "ashlsi3"
3229 [(set (match_operand:SI 0 "gr_register_operand" "")
3230 (ashift:SI (match_operand:SI 1 "gr_register_operand" "")
3231 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3234 if (GET_CODE (operands[2]) != CONST_INT)
3236 /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
3237 we've got to get rid of stray bits outside the SImode register. */
3238 rtx subshift = gen_reg_rtx (DImode);
3239 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3240 operands[2] = subshift;
3244 (define_insn "*ashlsi3_internal"
3245 [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
3246 (ashift:SI (match_operand:SI 1 "gr_register_operand" "r,r,r")
3247 (match_operand:DI 2 "gr_reg_or_5bit_operand" "R,n,r")))]
3250 shladd %0 = %1, %2, r0
3251 dep.z %0 = %1, %2, %E2
3253 [(set_attr "itanium_class" "ialu,ishf,mmshf")])
3255 (define_expand "ashrsi3"
3256 [(set (match_operand:SI 0 "gr_register_operand" "")
3257 (ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3258 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3261 rtx subtarget = gen_reg_rtx (DImode);
3262 if (GET_CODE (operands[2]) == CONST_INT)
3263 emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
3264 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3267 rtx subshift = gen_reg_rtx (DImode);
3268 emit_insn (gen_extendsidi2 (subtarget, operands[1]));
3269 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3270 emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
3272 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3276 (define_expand "lshrsi3"
3277 [(set (match_operand:SI 0 "gr_register_operand" "")
3278 (lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
3279 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3282 rtx subtarget = gen_reg_rtx (DImode);
3283 if (GET_CODE (operands[2]) == CONST_INT)
3284 emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
3285 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
3288 rtx subshift = gen_reg_rtx (DImode);
3289 emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
3290 emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
3291 emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
3293 emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
3297 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
3298 ;; here, instead of 64 like the patterns above. Keep the pattern together
3299 ;; until after combine; otherwise it won't get matched often.
3301 (define_expand "rotrsi3"
3302 [(set (match_operand:SI 0 "gr_register_operand" "")
3303 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
3304 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3307 if (GET_MODE (operands[2]) != VOIDmode)
3309 rtx tmp = gen_reg_rtx (DImode);
3310 emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
3315 (define_insn_and_split "*rotrsi3_internal"
3316 [(set (match_operand:SI 0 "gr_register_operand" "=&r")
3317 (rotatert:SI (match_operand:SI 1 "gr_register_operand" "r")
3318 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rM")))]
3323 (ior:DI (zero_extend:DI (match_dup 1))
3324 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3326 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3327 "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
3329 (define_expand "rotlsi3"
3330 [(set (match_operand:SI 0 "gr_register_operand" "")
3331 (rotate:SI (match_operand:SI 1 "gr_register_operand" "")
3332 (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
3335 if (! shift_32bit_count_operand (operands[2], SImode))
3337 rtx tmp = gen_reg_rtx (SImode);
3338 emit_insn (gen_subsi3 (tmp, GEN_INT (32), operands[2]));
3339 emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
3344 (define_insn_and_split "*rotlsi3_internal"
3345 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3346 (rotate:SI (match_operand:SI 1 "gr_register_operand" "r")
3347 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
3349 "mux2 %0 = %1, 0xe1"
3350 "reload_completed && INTVAL (operands[2]) != 16"
3352 (ior:DI (zero_extend:DI (match_dup 1))
3353 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
3355 (lshiftrt:DI (match_dup 3) (match_dup 2)))]
3357 operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
3358 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
3360 [(set_attr "itanium_class" "mmshf")])
3362 ;; ::::::::::::::::::::
3364 ;; :: 64-bit Integer Shifts and Rotates
3366 ;; ::::::::::::::::::::
3368 (define_insn "ashldi3"
3369 [(set (match_operand:DI 0 "gr_register_operand" "=r,r,r")
3370 (ashift:DI (match_operand:DI 1 "gr_register_operand" "r,r,r")
3371 (match_operand:DI 2 "gr_reg_or_6bit_operand" "R,r,rM")))]
3374 shladd %0 = %1, %2, r0
3377 [(set_attr "itanium_class" "ialu,mmshf,mmshfi")])
3379 ;; ??? Maybe combine this with the multiply and add instruction?
3381 (define_insn "*shladd"
3382 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3383 (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3384 (match_operand:DI 2 "shladd_operand" "n"))
3385 (match_operand:DI 3 "gr_register_operand" "r")))]
3387 "shladd %0 = %1, %S2, %3"
3388 [(set_attr "itanium_class" "ialu")])
3390 ;; This can be created by register elimination if operand3 of shladd is an
3391 ;; eliminable register or has reg_equiv_constant set.
3393 ;; We have to use nonmemory_operand for operand 4, to ensure that the
3394 ;; validate_changes call inside eliminate_regs will always succeed. If it
3395 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
3398 (define_insn_and_split "*shladd_elim"
3399 [(set (match_operand:DI 0 "gr_register_operand" "=&r")
3400 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "gr_register_operand" "r")
3401 (match_operand:DI 2 "shladd_operand" "n"))
3402 (match_operand:DI 3 "nonmemory_operand" "r"))
3403 (match_operand:DI 4 "nonmemory_operand" "rI")))]
3404 "reload_in_progress"
3405 "* gcc_unreachable ();"
3407 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
3409 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3411 [(set_attr "itanium_class" "unknown")])
3413 (define_insn "ashrdi3"
3414 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3415 (ashiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3416 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3421 [(set_attr "itanium_class" "mmshf,mmshfi")])
3423 (define_insn "lshrdi3"
3424 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
3425 (lshiftrt:DI (match_operand:DI 1 "gr_register_operand" "r,r")
3426 (match_operand:DI 2 "gr_reg_or_6bit_operand" "r,rM")))]
3431 [(set_attr "itanium_class" "mmshf,mmshfi")])
3433 ;; Using a predicate that accepts only constants doesn't work, because optabs
3434 ;; will load the operand into a register and call the pattern if the predicate
3435 ;; did not accept it on the first try. So we use nonmemory_operand and then
3436 ;; verify that we have an appropriate constant in the expander.
3438 (define_expand "rotrdi3"
3439 [(set (match_operand:DI 0 "gr_register_operand" "")
3440 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
3441 (match_operand:DI 2 "nonmemory_operand" "")))]
3444 if (! shift_count_operand (operands[2], DImode))
3448 (define_insn "*rotrdi3_internal"
3449 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3450 (rotatert:DI (match_operand:DI 1 "gr_register_operand" "r")
3451 (match_operand:DI 2 "shift_count_operand" "M")))]
3453 "shrp %0 = %1, %1, %2"
3454 [(set_attr "itanium_class" "ishf")])
3456 (define_expand "rotldi3"
3457 [(set (match_operand:DI 0 "gr_register_operand" "")
3458 (rotate:DI (match_operand:DI 1 "gr_register_operand" "")
3459 (match_operand:DI 2 "nonmemory_operand" "")))]
3462 if (! shift_count_operand (operands[2], DImode))
3466 (define_insn "*rotldi3_internal"
3467 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3468 (rotate:DI (match_operand:DI 1 "gr_register_operand" "r")
3469 (match_operand:DI 2 "shift_count_operand" "M")))]
3471 "shrp %0 = %1, %1, %e2"
3472 [(set_attr "itanium_class" "ishf")])
3474 ;; ::::::::::::::::::::
3476 ;; :: 128-bit Integer Shifts and Rotates
3478 ;; ::::::::::::::::::::
3480 (define_expand "ashlti3"
3481 [(set (match_operand:TI 0 "gr_register_operand" "")
3482 (ashift:TI (match_operand:TI 1 "gr_register_operand" "")
3483 (match_operand:DI 2 "nonmemory_operand" "")))]
3486 if (!dshift_count_operand (operands[2], DImode))
3490 (define_insn_and_split "*ashlti3_internal"
3491 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3492 (ashift:TI (match_operand:TI 1 "gr_register_operand" "r")
3493 (match_operand:DI 2 "dshift_count_operand" "n")))]
3499 HOST_WIDE_INT shift = INTVAL (operands[2]);
3500 rtx rl = gen_lowpart (DImode, operands[0]);
3501 rtx rh = gen_highpart (DImode, operands[0]);
3502 rtx lo = gen_lowpart (DImode, operands[1]);
3503 rtx shiftlo = GEN_INT (shift & 63);
3507 emit_move_insn (rl, const0_rtx);
3509 emit_insn (gen_ashldi3 (rh, lo, shiftlo));
3511 emit_move_insn (rh, lo);
3515 rtx hi = gen_highpart (DImode, operands[1]);
3517 emit_insn (gen_shrp (rh, hi, lo, GEN_INT (-shift & 63)));
3518 emit_insn (gen_ashldi3 (rl, lo, shiftlo));
3523 (define_expand "ashrti3"
3524 [(set (match_operand:TI 0 "gr_register_operand" "")
3525 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3526 (match_operand:DI 2 "nonmemory_operand" "")))]
3529 if (!dshift_count_operand (operands[2], DImode))
3533 (define_insn_and_split "*ashrti3_internal"
3534 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3535 (ashiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3536 (match_operand:DI 2 "dshift_count_operand" "n")))]
3542 HOST_WIDE_INT shift = INTVAL (operands[2]);
3543 rtx rl = gen_lowpart (DImode, operands[0]);
3544 rtx rh = gen_highpart (DImode, operands[0]);
3545 rtx hi = gen_highpart (DImode, operands[1]);
3546 rtx shiftlo = GEN_INT (shift & 63);
3551 emit_insn (gen_ashrdi3 (rl, hi, shiftlo));
3553 emit_move_insn (rl, hi);
3554 emit_insn (gen_ashrdi3 (rh, hi, GEN_INT (63)));
3558 rtx lo = gen_lowpart (DImode, operands[1]);
3560 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3561 emit_insn (gen_ashrdi3 (rh, hi, shiftlo));
3566 (define_expand "lshrti3"
3567 [(set (match_operand:TI 0 "gr_register_operand" "")
3568 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "")
3569 (match_operand:DI 2 "nonmemory_operand" "")))]
3572 if (!dshift_count_operand (operands[2], DImode))
3576 (define_insn_and_split "*lshrti3_internal"
3577 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3578 (lshiftrt:TI (match_operand:TI 1 "gr_register_operand" "r")
3579 (match_operand:DI 2 "dshift_count_operand" "n")))]
3585 HOST_WIDE_INT shift = INTVAL (operands[2]);
3586 rtx rl = gen_lowpart (DImode, operands[0]);
3587 rtx rh = gen_highpart (DImode, operands[0]);
3588 rtx hi = gen_highpart (DImode, operands[1]);
3589 rtx shiftlo = GEN_INT (shift & 63);
3594 emit_insn (gen_lshrdi3 (rl, hi, shiftlo));
3596 emit_move_insn (rl, hi);
3597 emit_move_insn (rh, const0_rtx);
3601 rtx lo = gen_lowpart (DImode, operands[1]);
3603 emit_insn (gen_shrp (rl, hi, lo, shiftlo));
3604 emit_insn (gen_lshrdi3 (rh, hi, shiftlo));
3609 (define_expand "rotlti3"
3610 [(set (match_operand:TI 0 "gr_register_operand" "")
3611 (rotate:TI (match_operand:TI 1 "gr_register_operand" "")
3612 (match_operand:DI 2 "nonmemory_operand" "")))]
3615 if (! dshift_count_operand (operands[2], DImode))
3619 (define_insn_and_split "*rotlti3_internal"
3620 [(set (match_operand:TI 0 "gr_register_operand" "=&r")
3621 (rotate:TI (match_operand:TI 1 "gr_register_operand" "r")
3622 (match_operand:DI 2 "dshift_count_operand" "n")))]
3628 HOST_WIDE_INT count = INTVAL (operands[2]);
3629 rtx rl = gen_lowpart (DImode, operands[0]);
3630 rtx rh = gen_highpart (DImode, operands[0]);
3631 rtx lo = gen_lowpart (DImode, operands[1]);
3632 rtx hi = gen_highpart (DImode, operands[1]);
3633 rtx countlo = GEN_INT (-count & 63);
3639 emit_insn (gen_shrp (rl, hi, lo, countlo));
3640 emit_insn (gen_shrp (rh, lo, hi, countlo));
3644 emit_move_insn (rl, hi);
3645 emit_move_insn (rh, lo);
3650 emit_insn (gen_shrp (rl, lo, hi, countlo));
3651 emit_insn (gen_shrp (rh, hi, lo, countlo));
3655 [(set_attr "itanium_class" "unknown")])
3658 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3659 (unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")
3660 (match_operand:DI 2 "gr_register_operand" "r")
3661 (match_operand:DI 3 "shift_count_operand" "M")]
3664 "shrp %0 = %1, %2, %3"
3665 [(set_attr "itanium_class" "ishf")])
3667 ;; ::::::::::::::::::::
3669 ;; :: 32-bit Integer Logical operations
3671 ;; ::::::::::::::::::::
3673 ;; We don't seem to need any other 32-bit logical operations, because gcc
3674 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
3675 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
3676 ;; This doesn't work for unary logical operations, because we don't call
3677 ;; apply_distributive_law for them.
3679 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
3680 ;; apply_distributive_law. We get inefficient code for
3681 ;; int sub4 (int i, int j) { return i & ~j; }
3682 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
3683 ;; (zero_extend (and (not A) B)) in combine.
3684 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
3685 ;; one_cmplsi2 pattern.
3687 (define_insn "one_cmplsi2"
3688 [(set (match_operand:SI 0 "gr_register_operand" "=r")
3689 (not:SI (match_operand:SI 1 "gr_register_operand" "r")))]
3692 [(set_attr "itanium_class" "ilog")])
3694 ;; ::::::::::::::::::::
3696 ;; :: 64-bit Integer Logical operations
3698 ;; ::::::::::::::::::::
3700 (define_insn "anddi3"
3701 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3702 (and:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3703 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3708 [(set_attr "itanium_class" "ilog,fmisc")])
3710 (define_insn "*andnot"
3711 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3712 (and:DI (not:DI (match_operand:DI 1 "grfr_register_operand" "r,*f"))
3713 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3718 [(set_attr "itanium_class" "ilog,fmisc")])
3720 (define_insn "iordi3"
3721 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3722 (ior:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3723 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3728 [(set_attr "itanium_class" "ilog,fmisc")])
3730 (define_insn "xordi3"
3731 [(set (match_operand:DI 0 "grfr_register_operand" "=r,*f")
3732 (xor:DI (match_operand:DI 1 "grfr_register_operand" "%r,*f")
3733 (match_operand:DI 2 "grfr_reg_or_8bit_operand" "rK,*f")))]
3738 [(set_attr "itanium_class" "ilog,fmisc")])
3740 (define_insn "one_cmpldi2"
3741 [(set (match_operand:DI 0 "gr_register_operand" "=r")
3742 (not:DI (match_operand:DI 1 "gr_register_operand" "r")))]
3745 [(set_attr "itanium_class" "ilog")])
3747 ;; ::::::::::::::::::::
3751 ;; ::::::::::::::::::::
3753 (define_expand "cbranchbi4"
3755 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3756 [(match_operand:BI 1 "register_operand" "")
3757 (match_operand:BI 2 "const_int_operand" "")])
3758 (label_ref (match_operand 3 "" ""))
3761 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3763 (define_expand "cbranchsi4"
3765 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3766 [(match_operand:SI 1 "gr_register_operand" "")
3767 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3768 (label_ref (match_operand 3 "" ""))
3771 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3773 (define_expand "cbranchdi4"
3775 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3776 [(match_operand:DI 1 "gr_register_operand" "")
3777 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
3778 (label_ref (match_operand 3 "" ""))
3781 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3783 (define_expand "cbranchsf4"
3785 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3786 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
3787 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
3788 (label_ref (match_operand 3 "" ""))
3791 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3793 (define_expand "cbranchdf4"
3795 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3796 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
3797 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
3798 (label_ref (match_operand 3 "" ""))
3801 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3803 (define_expand "cbranchxf4"
3805 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3806 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
3807 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
3808 (label_ref (match_operand 3 "" ""))
3811 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3813 (define_expand "cbranchtf4"
3815 (if_then_else (match_operator 0 "ia64_cbranch_operator"
3816 [(match_operand:TF 1 "gr_register_operand" "")
3817 (match_operand:TF 2 "gr_register_operand" "")])
3818 (label_ref (match_operand 3 "" ""))
3821 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3824 (define_insn "*cmpsi_normal"
3825 [(set (match_operand:BI 0 "register_operand" "=c")
3826 (match_operator:BI 1 "normal_comparison_operator"
3827 [(match_operand:SI 2 "gr_register_operand" "r")
3828 (match_operand:SI 3 "gr_reg_or_8bit_operand" "rK")]))]
3830 "cmp4.%C1 %0, %I0 = %3, %2"
3831 [(set_attr "itanium_class" "icmp")])
3833 ;; We use %r3 because it is possible for us to match a 0, and two of the
3834 ;; unsigned comparisons don't accept immediate operands of zero.
3836 (define_insn "*cmpsi_adjusted"
3837 [(set (match_operand:BI 0 "register_operand" "=c")
3838 (match_operator:BI 1 "adjusted_comparison_operator"
3839 [(match_operand:SI 2 "gr_register_operand" "r")
3840 (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
3842 "cmp4.%C1 %0, %I0 = %r3, %2"
3843 [(set_attr "itanium_class" "icmp")])
3845 (define_insn "*cmpdi_normal"
3846 [(set (match_operand:BI 0 "register_operand" "=c")
3847 (match_operator:BI 1 "normal_comparison_operator"
3848 [(match_operand:DI 2 "gr_reg_or_0_operand" "rO")
3849 (match_operand:DI 3 "gr_reg_or_8bit_operand" "rK")]))]
3851 "cmp.%C1 %0, %I0 = %3, %r2"
3852 [(set_attr "itanium_class" "icmp")])
3854 ;; We use %r3 because it is possible for us to match a 0, and two of the
3855 ;; unsigned comparisons don't accept immediate operands of zero.
3857 (define_insn "*cmpdi_adjusted"
3858 [(set (match_operand:BI 0 "register_operand" "=c")
3859 (match_operator:BI 1 "adjusted_comparison_operator"
3860 [(match_operand:DI 2 "gr_register_operand" "r")
3861 (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
3863 "cmp.%C1 %0, %I0 = %r3, %2"
3864 [(set_attr "itanium_class" "icmp")])
3866 (define_insn "*cmpsf_internal"
3867 [(set (match_operand:BI 0 "register_operand" "=c")
3868 (match_operator:BI 1 "comparison_operator"
3869 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")
3870 (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")]))]
3872 "fcmp.%D1 %0, %I0 = %F2, %F3"
3873 [(set_attr "itanium_class" "fcmp")])
3875 (define_insn "*cmpdf_internal"
3876 [(set (match_operand:BI 0 "register_operand" "=c")
3877 (match_operator:BI 1 "comparison_operator"
3878 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")
3879 (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")]))]
3881 "fcmp.%D1 %0, %I0 = %F2, %F3"
3882 [(set_attr "itanium_class" "fcmp")])
3884 (define_insn "*cmpxf_internal"
3885 [(set (match_operand:BI 0 "register_operand" "=c")
3886 (match_operator:BI 1 "comparison_operator"
3887 [(match_operand:XF 2 "xfreg_or_fp01_operand" "fG")
3888 (match_operand:XF 3 "xfreg_or_fp01_operand" "fG")]))]
3890 "fcmp.%D1 %0, %I0 = %F2, %F3"
3891 [(set_attr "itanium_class" "fcmp")])
3893 ;; ??? Can this pattern be generated?
3895 (define_insn "*bit_zero"
3896 [(set (match_operand:BI 0 "register_operand" "=c")
3897 (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
3899 (match_operand:DI 2 "shift_count_operand" "M"))
3902 "tbit.z %0, %I0 = %1, %2"
3903 [(set_attr "itanium_class" "tbit")])
3905 (define_insn "*bit_one"
3906 [(set (match_operand:BI 0 "register_operand" "=c")
3907 (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r")
3909 (match_operand:DI 2 "shift_count_operand" "M"))
3912 "tbit.nz %0, %I0 = %1, %2"
3913 [(set_attr "itanium_class" "tbit")])
3915 ;; ::::::::::::::::::::
3919 ;; ::::::::::::::::::::
3921 (define_insn "*br_true"
3923 (if_then_else (match_operator 0 "predicate_operator"
3924 [(match_operand:BI 1 "register_operand" "c")
3926 (label_ref (match_operand 2 "" ""))
3929 "(%J0) br.cond%+ %l2"
3930 [(set_attr "itanium_class" "br")
3931 (set_attr "predicable" "no")])
3933 (define_insn "*br_false"
3935 (if_then_else (match_operator 0 "predicate_operator"
3936 [(match_operand:BI 1 "register_operand" "c")
3939 (label_ref (match_operand 2 "" ""))))]
3941 "(%j0) br.cond%+ %l2"
3942 [(set_attr "itanium_class" "br")
3943 (set_attr "predicable" "no")])
3945 ;; ::::::::::::::::::::
3947 ;; :: Counted loop operations
3949 ;; ::::::::::::::::::::
3951 (define_expand "doloop_end"
3952 [(use (match_operand 0 "" "")) ; loop pseudo
3953 (use (match_operand 1 "" "")) ; iterations; zero if unknown
3954 (use (match_operand 2 "" "")) ; max iterations
3955 (use (match_operand 3 "" "")) ; loop level
3956 (use (match_operand 4 "" ""))] ; label
3959 /* Only use cloop on innermost loops. */
3960 if (INTVAL (operands[3]) > 1)
3962 emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
3967 (define_insn "doloop_end_internal"
3968 [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
3970 (label_ref (match_operand 1 "" ""))
3972 (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
3973 (plus:DI (match_dup 0) (const_int -1))
3976 "br.cloop.sptk.few %l1"
3977 [(set_attr "itanium_class" "br")
3978 (set_attr "predicable" "no")])
3980 ;; ::::::::::::::::::::
3982 ;; :: Set flag operations
3984 ;; ::::::::::::::::::::
3986 (define_expand "cstorebi4"
3987 [(set (match_operand:DI 0 "gr_register_operand" "")
3988 (match_operator:DI 1 "ia64_cbranch_operator"
3989 [(match_operand:BI 2 "register_operand" "")
3990 (match_operand:BI 3 "const_int_operand" "")]))]
3992 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
3994 (define_expand "cstoresi4"
3995 [(set (match_operand:DI 0 "gr_register_operand" "")
3996 (match_operator:DI 1 "ia64_cbranch_operator"
3997 [(match_operand:SI 2 "gr_register_operand" "")
3998 (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
4000 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4002 (define_expand "cstoredi4"
4003 [(set (match_operand:DI 0 "gr_register_operand" "")
4004 (match_operator:DI 1 "ia64_cbranch_operator"
4005 [(match_operand:DI 2 "gr_register_operand" "")
4006 (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
4008 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4010 (define_expand "cstoresf4"
4011 [(set (match_operand:DI 0 "gr_register_operand" "")
4012 (match_operator:DI 1 "ia64_cbranch_operator"
4013 [(match_operand:SF 2 "fr_reg_or_fp01_operand" "")
4014 (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))]
4016 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4018 (define_expand "cstoredf4"
4019 [(set (match_operand:DI 0 "gr_register_operand" "")
4020 (match_operator:DI 1 "ia64_cbranch_operator"
4021 [(match_operand:DF 2 "fr_reg_or_fp01_operand" "")
4022 (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))]
4024 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4026 (define_expand "cstorexf4"
4027 [(set (match_operand:DI 0 "gr_register_operand" "")
4028 (match_operator:DI 1 "ia64_cbranch_operator"
4029 [(match_operand:XF 2 "xfreg_or_fp01_operand" "")
4030 (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))]
4032 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4034 (define_expand "cstoretf4"
4035 [(set (match_operand:DI 0 "gr_register_operand" "")
4036 (match_operator:DI 1 "ia64_cbranch_operator"
4037 [(match_operand:TF 2 "gr_register_operand" "")
4038 (match_operand:TF 3 "gr_register_operand" "")]))]
4040 "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
4042 ;; Don't allow memory as destination here, because cmov/cmov/st is more
4043 ;; efficient than mov/mov/cst/cst.
4045 (define_insn_and_split "*sne_internal"
4046 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4047 (ne:DI (match_operand:BI 1 "register_operand" "c")
4052 [(cond_exec (ne (match_dup 1) (const_int 0))
4053 (set (match_dup 0) (const_int 1)))
4054 (cond_exec (eq (match_dup 1) (const_int 0))
4055 (set (match_dup 0) (const_int 0)))]
4057 [(set_attr "itanium_class" "unknown")])
4059 (define_insn_and_split "*seq_internal"
4060 [(set (match_operand:DI 0 "gr_register_operand" "=r")
4061 (eq:DI (match_operand:BI 1 "register_operand" "c")
4066 [(cond_exec (ne (match_dup 1) (const_int 0))
4067 (set (match_dup 0) (const_int 0)))
4068 (cond_exec (eq (match_dup 1) (const_int 0))
4069 (set (match_dup 0) (const_int 1)))]
4071 [(set_attr "itanium_class" "unknown")])
4073 ;; ::::::::::::::::::::
4075 ;; :: Conditional move instructions.
4077 ;; ::::::::::::::::::::
4079 ;; ??? Add movXXcc patterns?
4082 ;; DImode if_then_else patterns.
4085 (define_insn "*cmovdi_internal"
4086 [(set (match_operand:DI 0 "not_postinc_destination_operand"
4087 "= r, r, r, r, r, r, r, r, r, r, m, Q, *f,*b,*d*e")
4089 (match_operator 4 "predicate_operator"
4090 [(match_operand:BI 1 "register_operand"
4091 "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
4093 (match_operand:DI 2 "not_postinc_move_operand"
4094 "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO, rK")
4095 (match_operand:DI 3 "not_postinc_move_operand"
4096 "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO, rK")))]
4097 "ia64_move_ok (operands[0], operands[2])
4098 && ia64_move_ok (operands[0], operands[3])"
4099 { gcc_unreachable (); }
4100 [(set_attr "predicable" "no")])
4103 [(set (match_operand 0 "not_postinc_destination_operand" "")
4105 (match_operator 4 "predicate_operator"
4106 [(match_operand:BI 1 "register_operand" "")
4108 (match_operand 2 "not_postinc_move_operand" "")
4109 (match_operand 3 "not_postinc_move_operand" "")))]
4113 bool emitted_something = false;
4114 rtx dest = operands[0];
4115 rtx srct = operands[2];
4116 rtx srcf = operands[3];
4117 rtx cond = operands[4];
4119 if (! rtx_equal_p (dest, srct))
4121 ia64_emit_cond_move (dest, srct, cond);
4122 emitted_something = true;
4124 if (! rtx_equal_p (dest, srcf))
4126 cond = gen_rtx_fmt_ee (GET_CODE (cond) == NE ? EQ : NE,
4127 VOIDmode, operands[1], const0_rtx);
4128 ia64_emit_cond_move (dest, srcf, cond);
4129 emitted_something = true;
4131 if (! emitted_something)
4132 emit_note (NOTE_INSN_DELETED);
4136 ;; Absolute value pattern.
4138 (define_insn "*absdi2_internal"
4139 [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
4141 (match_operator 4 "predicate_operator"
4142 [(match_operand:BI 1 "register_operand" "c,c")
4144 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" "rI,rI"))
4145 (match_operand:DI 3 "gr_reg_or_22bit_operand" "0,rI")))]
4148 [(set_attr "itanium_class" "ialu,unknown")
4149 (set_attr "predicable" "no")])
4152 [(set (match_operand:DI 0 "register_operand" "")
4154 (match_operator 4 "predicate_operator"
4155 [(match_operand:BI 1 "register_operand" "c,c")
4157 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4158 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4159 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4163 (neg:DI (match_dup 2))))]
4167 [(set (match_operand:DI 0 "register_operand" "")
4169 (match_operator 4 "predicate_operator"
4170 [(match_operand:BI 1 "register_operand" "c,c")
4172 (neg:DI (match_operand:DI 2 "gr_reg_or_22bit_operand" ""))
4173 (match_operand:DI 3 "gr_reg_or_22bit_operand" "")))]
4177 (set (match_dup 0) (neg:DI (match_dup 2))))
4180 (set (match_dup 0) (match_dup 3)))]
4182 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4183 VOIDmode, operands[1], const0_rtx);
4187 ;; SImode if_then_else patterns.
4190 (define_insn "*cmovsi_internal"
4191 [(set (match_operand:SI 0 "not_postinc_destination_operand"
4192 "=r,m,*f,r,m,*f,r,m,*f")
4194 (match_operator 4 "predicate_operator"
4195 [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
4197 (match_operand:SI 2 "not_postinc_move_operand"
4198 "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
4199 (match_operand:SI 3 "not_postinc_move_operand"
4200 "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
4201 "ia64_move_ok (operands[0], operands[2])
4202 && ia64_move_ok (operands[0], operands[3])"
4203 { gcc_unreachable (); }
4204 [(set_attr "predicable" "no")])
4206 (define_insn "*abssi2_internal"
4207 [(set (match_operand:SI 0 "gr_register_operand" "=r,r")
4209 (match_operator 4 "predicate_operator"
4210 [(match_operand:BI 1 "register_operand" "c,c")
4212 (neg:SI (match_operand:SI 3 "gr_reg_or_22bit_operand" "rI,rI"))
4213 (match_operand:SI 2 "gr_reg_or_22bit_operand" "0,rI")))]
4216 [(set_attr "itanium_class" "ialu,unknown")
4217 (set_attr "predicable" "no")])
4220 [(set (match_operand:SI 0 "register_operand" "")
4222 (match_operator 4 "predicate_operator"
4223 [(match_operand:BI 1 "register_operand" "c,c")
4225 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4226 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4227 "reload_completed && rtx_equal_p (operands[0], operands[3])"
4231 (neg:SI (match_dup 2))))]
4235 [(set (match_operand:SI 0 "register_operand" "")
4237 (match_operator 4 "predicate_operator"
4238 [(match_operand:BI 1 "register_operand" "c,c")
4240 (neg:SI (match_operand:SI 2 "gr_reg_or_22bit_operand" ""))
4241 (match_operand:SI 3 "gr_reg_or_22bit_operand" "")))]
4245 (set (match_dup 0) (neg:SI (match_dup 2))))
4248 (set (match_dup 0) (match_dup 3)))]
4250 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
4251 VOIDmode, operands[1], const0_rtx);
4254 (define_insn_and_split "*cond_opsi2_internal"
4255 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4256 (match_operator:SI 5 "condop_operator"
4258 (match_operator 6 "predicate_operator"
4259 [(match_operand:BI 1 "register_operand" "c")
4261 (match_operand:SI 2 "gr_register_operand" "r")
4262 (match_operand:SI 3 "gr_register_operand" "r"))
4263 (match_operand:SI 4 "gr_register_operand" "r")]))]
4269 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
4272 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
4274 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4275 VOIDmode, operands[1], const0_rtx);
4277 [(set_attr "itanium_class" "ialu")
4278 (set_attr "predicable" "no")])
4281 (define_insn_and_split "*cond_opsi2_internal_b"
4282 [(set (match_operand:SI 0 "gr_register_operand" "=r")
4283 (match_operator:SI 5 "condop_operator"
4284 [(match_operand:SI 4 "gr_register_operand" "r")
4286 (match_operator 6 "predicate_operator"
4287 [(match_operand:BI 1 "register_operand" "c")
4289 (match_operand:SI 2 "gr_register_operand" "r")
4290 (match_operand:SI 3 "gr_register_operand" "r"))]))]
4296 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
4299 (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
4301 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
4302 VOIDmode, operands[1], const0_rtx);
4304 [(set_attr "itanium_class" "ialu")
4305 (set_attr "predicable" "no")])
4308 ;; ::::::::::::::::::::
4310 ;; :: Call and branch instructions
4312 ;; ::::::::::::::::::::
4314 ;; Subroutine call instruction returning no value. Operand 0 is the function
4315 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
4316 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
4317 ;; registers used as operands.
4319 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
4320 ;; is supplied for the sake of some RISC machines which need to put this
4321 ;; information into the assembler code; they can put it in the RTL instead of
4324 (define_expand "call"
4325 [(use (match_operand:DI 0 "" ""))
4326 (use (match_operand 1 "" ""))
4327 (use (match_operand 2 "" ""))
4328 (use (match_operand 3 "" ""))]
4331 ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
4335 (define_expand "sibcall"
4336 [(use (match_operand:DI 0 "" ""))
4337 (use (match_operand 1 "" ""))
4338 (use (match_operand 2 "" ""))
4339 (use (match_operand 3 "" ""))]
4342 ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
4346 ;; Subroutine call instruction returning a value. Operand 0 is the hard
4347 ;; register in which the value is returned. There are three more operands,
4348 ;; the same as the three operands of the `call' instruction (but with numbers
4349 ;; increased by one).
4351 ;; Subroutines that return `BLKmode' objects use the `call' insn.
4353 (define_expand "call_value"
4354 [(use (match_operand 0 "" ""))
4355 (use (match_operand:DI 1 "" ""))
4356 (use (match_operand 2 "" ""))
4357 (use (match_operand 3 "" ""))
4358 (use (match_operand 4 "" ""))]
4361 ia64_expand_call (operands[0], operands[1], operands[3], false);
4365 (define_expand "sibcall_value"
4366 [(use (match_operand 0 "" ""))
4367 (use (match_operand:DI 1 "" ""))
4368 (use (match_operand 2 "" ""))
4369 (use (match_operand 3 "" ""))
4370 (use (match_operand 4 "" ""))]
4373 ia64_expand_call (operands[0], operands[1], operands[3], true);
4377 ;; Call subroutine returning any type.
4379 (define_expand "untyped_call"
4380 [(parallel [(call (match_operand 0 "" "")
4382 (match_operand 1 "" "")
4383 (match_operand 2 "" "")])]
4388 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
4390 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4392 rtx set = XVECEXP (operands[2], 0, i);
4393 emit_move_insn (SET_DEST (set), SET_SRC (set));
4396 /* The optimizer does not know that the call sets the function value
4397 registers we stored in the result block. We avoid problems by
4398 claiming that all hard registers are used and clobbered at this
4400 emit_insn (gen_blockage ());
4405 (define_insn "call_nogp"
4406 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
4408 (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
4410 "br.call%+.many %1 = %0"
4411 [(set_attr "itanium_class" "br,scall")])
4413 (define_insn "call_value_nogp"
4414 [(set (match_operand 0 "" "=X,X")
4415 (call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
4417 (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
4419 "br.call%+.many %2 = %1"
4420 [(set_attr "itanium_class" "br,scall")])
4422 (define_insn "sibcall_nogp"
4423 [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
4427 [(set_attr "itanium_class" "br,scall")])
4429 (define_insn "call_gp"
4430 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
4432 (clobber (match_operand:DI 1 "register_operand" "=b,b"))
4433 (clobber (match_scratch:DI 2 "=&r,X"))
4434 (clobber (match_scratch:DI 3 "=b,X"))]
4437 [(set_attr "itanium_class" "br,scall")])
4439 ;; Irritatingly, we don't have access to INSN within the split body.
4440 ;; See commentary in ia64_split_call as to why these aren't peep2.
4442 [(call (mem (match_operand 0 "call_operand" ""))
4444 (clobber (match_operand:DI 1 "register_operand" ""))
4445 (clobber (match_scratch:DI 2 ""))
4446 (clobber (match_scratch:DI 3 ""))]
4447 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4450 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4451 operands[3], true, false);
4456 [(call (mem (match_operand 0 "call_operand" ""))
4458 (clobber (match_operand:DI 1 "register_operand" ""))
4459 (clobber (match_scratch:DI 2 ""))
4460 (clobber (match_scratch:DI 3 ""))]
4464 ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
4465 operands[3], false, false);
4469 (define_insn "call_value_gp"
4470 [(set (match_operand 0 "" "=X,X")
4471 (call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
4473 (clobber (match_operand:DI 2 "register_operand" "=b,b"))
4474 (clobber (match_scratch:DI 3 "=&r,X"))
4475 (clobber (match_scratch:DI 4 "=b,X"))]
4478 [(set_attr "itanium_class" "br,scall")])
4481 [(set (match_operand 0 "" "")
4482 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4484 (clobber (match_operand:DI 2 "register_operand" ""))
4485 (clobber (match_scratch:DI 3 ""))
4486 (clobber (match_scratch:DI 4 ""))]
4487 "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4490 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4491 operands[4], true, false);
4496 [(set (match_operand 0 "" "")
4497 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
4499 (clobber (match_operand:DI 2 "register_operand" ""))
4500 (clobber (match_scratch:DI 3 ""))
4501 (clobber (match_scratch:DI 4 ""))]
4505 ia64_split_call (operands[0], operands[1], operands[2], operands[3],
4506 operands[4], false, false);
4510 (define_insn_and_split "sibcall_gp"
4511 [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
4513 (clobber (match_scratch:DI 1 "=&r,X"))
4514 (clobber (match_scratch:DI 2 "=b,X"))]
4520 ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
4521 operands[2], true, true);
4524 [(set_attr "itanium_class" "br")])
4526 (define_insn "return_internal"
4528 (use (match_operand:DI 0 "register_operand" "b"))]
4530 "br.ret.sptk.many %0"
4531 [(set_attr "itanium_class" "br")])
4533 (define_insn "return"
4535 "ia64_direct_return ()"
4536 "br.ret.sptk.many rp"
4537 [(set_attr "itanium_class" "br")])
4539 (define_insn "*return_true"
4541 (if_then_else (match_operator 0 "predicate_operator"
4542 [(match_operand:BI 1 "register_operand" "c")
4546 "ia64_direct_return ()"
4547 "(%J0) br.ret%+.many rp"
4548 [(set_attr "itanium_class" "br")
4549 (set_attr "predicable" "no")])
4551 (define_insn "*return_false"
4553 (if_then_else (match_operator 0 "predicate_operator"
4554 [(match_operand:BI 1 "register_operand" "c")
4558 "ia64_direct_return ()"
4559 "(%j0) br.ret%+.many rp"
4560 [(set_attr "itanium_class" "br")
4561 (set_attr "predicable" "no")])
4564 [(set (pc) (label_ref (match_operand 0 "" "")))]
4567 [(set_attr "itanium_class" "br")])
4569 (define_insn "indirect_jump"
4570 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
4573 [(set_attr "itanium_class" "br")])
4575 (define_expand "tablejump"
4576 [(parallel [(set (pc) (match_operand:DI 0 "memory_operand" ""))
4577 (use (label_ref (match_operand 1 "" "")))])]
4580 rtx op0 = operands[0];
4583 /* ??? Bother -- do_tablejump is "helpful" and pulls the table
4584 element into a register without bothering to see whether that
4585 is necessary given the operand predicate. Check for MEM just
4586 in case someone fixes this. */
4587 if (GET_CODE (op0) == MEM)
4588 addr = XEXP (op0, 0);
4591 /* Otherwise, cheat and guess that the previous insn in the
4592 stream was the memory load. Grab the address from that.
4593 Note we have to momentarily pop out of the sequence started
4594 by the insn-emit wrapper in order to grab the last insn. */
4598 last = get_last_insn ();
4600 set = single_set (last);
4602 gcc_assert (rtx_equal_p (SET_DEST (set), op0)
4603 && GET_CODE (SET_SRC (set)) == MEM);
4604 addr = XEXP (SET_SRC (set), 0);
4605 gcc_assert (!rtx_equal_p (addr, op0));
4608 /* Jump table elements are stored pc-relative. That is, a displacement
4609 from the entry to the label. Thus to convert to an absolute address
4610 we add the address of the memory from which the value is loaded. */
4611 operands[0] = expand_simple_binop (DImode, PLUS, op0, addr,
4612 NULL_RTX, 1, OPTAB_DIRECT);
4615 (define_insn "*tablejump_internal"
4616 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
4617 (use (label_ref (match_operand 1 "" "")))]
4620 [(set_attr "itanium_class" "br")])
4623 ;; ::::::::::::::::::::
4625 ;; :: Prologue and Epilogue instructions
4627 ;; ::::::::::::::::::::
4629 (define_expand "prologue"
4633 ia64_expand_prologue ();
4637 (define_expand "epilogue"
4641 ia64_expand_epilogue (0);
4645 (define_expand "sibcall_epilogue"
4649 ia64_expand_epilogue (1);
4653 ;; This prevents the scheduler from moving the SP decrement past FP-relative
4654 ;; stack accesses. This is the same as adddi3 plus the extra set.
4656 (define_insn "prologue_allocate_stack"
4657 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
4658 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
4659 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))
4660 (set (match_operand:DI 3 "register_operand" "+r,r,r")
4667 [(set_attr "itanium_class" "ialu")])
4669 ;; This prevents the scheduler from moving the SP restore past FP-relative
4670 ;; stack accesses. This is similar to movdi plus the extra set.
4672 (define_insn "epilogue_deallocate_stack"
4673 [(set (match_operand:DI 0 "register_operand" "=r")
4674 (match_operand:DI 1 "register_operand" "+r"))
4675 (set (match_dup 1) (match_dup 1))]
4678 [(set_attr "itanium_class" "ialu")])
4680 ;; As USE insns aren't meaningful after reload, this is used instead
4681 ;; to prevent deleting instructions setting registers for EH handling
4682 (define_insn "prologue_use"
4683 [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
4684 UNSPEC_PROLOGUE_USE)]
4687 [(set_attr "itanium_class" "ignore")
4688 (set_attr "predicable" "no")
4689 (set_attr "empty" "yes")])
4691 ;; Allocate a new register frame.
4693 (define_insn "alloc"
4694 [(set (match_operand:DI 0 "register_operand" "=r")
4695 (unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
4696 (use (match_operand:DI 1 "const_int_operand" "i"))
4697 (use (match_operand:DI 2 "const_int_operand" "i"))
4698 (use (match_operand:DI 3 "const_int_operand" "i"))
4699 (use (match_operand:DI 4 "const_int_operand" "i"))]
4701 "alloc %0 = ar.pfs, %1, %2, %3, %4"
4702 [(set_attr "itanium_class" "syst_m0")
4703 (set_attr "predicable" "no")
4704 (set_attr "first_insn" "yes")])
4707 (define_expand "gr_spill"
4708 [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
4709 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4710 (match_operand:DI 2 "const_int_operand" "")]
4712 (clobber (match_dup 3))])]
4714 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4716 (define_insn "gr_spill_internal"
4717 [(set (match_operand:DI 0 "destination_operand" "=m")
4718 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
4719 (match_operand:DI 2 "const_int_operand" "")]
4721 (clobber (match_operand:DI 3 "register_operand" ""))]
4724 /* Note that we use a C output pattern here to avoid the predicate
4725 being automatically added before the .mem.offset directive. */
4726 return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
4728 [(set_attr "itanium_class" "st")])
4731 (define_expand "gr_restore"
4732 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
4733 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4734 (match_operand:DI 2 "const_int_operand" "")]
4736 (use (match_dup 3))])]
4738 "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
4740 (define_insn "gr_restore_internal"
4741 [(set (match_operand:DI 0 "register_operand" "=r")
4742 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
4743 (match_operand:DI 2 "const_int_operand" "")]
4745 (use (match_operand:DI 3 "register_operand" ""))]
4747 { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
4748 [(set_attr "itanium_class" "ld")])
4750 (define_insn "fr_spill"
4751 [(set (match_operand:XF 0 "destination_operand" "=m")
4752 (unspec:XF [(match_operand:XF 1 "register_operand" "f")]
4755 "stf.spill %0 = %1%P0"
4756 [(set_attr "itanium_class" "stf")])
4758 (define_insn "fr_restore"
4759 [(set (match_operand:XF 0 "register_operand" "=f")
4760 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")]
4761 UNSPEC_FR_RESTORE))]
4763 "ldf.fill %0 = %1%P1"
4764 [(set_attr "itanium_class" "fld")])
4766 ;; ??? The explicit stop is not ideal. It would be better if
4767 ;; rtx_needs_barrier took care of this, but this is something that can be
4768 ;; fixed later. This avoids an RSE DV.
4770 (define_insn "bsp_value"
4771 [(set (match_operand:DI 0 "register_operand" "=r")
4772 (unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
4776 return \";;\;%,mov %0 = ar.bsp\";
4778 [(set_attr "itanium_class" "frar_i")])
4780 (define_insn "set_bsp"
4781 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
4799 [(set_attr "itanium_class" "unknown")
4800 (set_attr "predicable" "no")])
4802 ;; ??? The explicit stops are not ideal. It would be better if
4803 ;; rtx_needs_barrier took care of this, but this is something that can be
4804 ;; fixed later. This avoids an RSE DV.
4806 (define_insn "flushrs"
4807 [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
4810 [(set_attr "itanium_class" "rse_m")
4811 (set_attr "predicable" "no")])
4813 ;; ::::::::::::::::::::
4815 ;; :: Miscellaneous instructions
4817 ;; ::::::::::::::::::::
4819 ;; ??? Emitting a NOP instruction isn't very useful. This should probably
4820 ;; be emitting ";;" to force a break in the instruction packing.
4822 ;; No operation, needed in case the user uses -g but not -O.
4827 [(set_attr "itanium_class" "nop")])
4829 (define_insn "nop_m"
4833 [(set_attr "itanium_class" "nop_m")])
4835 (define_insn "nop_i"
4839 [(set_attr "itanium_class" "nop_i")])
4841 (define_insn "nop_f"
4845 [(set_attr "itanium_class" "nop_f")])
4847 (define_insn "nop_b"
4851 [(set_attr "itanium_class" "nop_b")])
4853 (define_insn "nop_x"
4857 [(set_attr "itanium_class" "nop_x")
4858 (set_attr "empty" "yes")])
4860 ;; The following insn will be never generated. It is used only by
4861 ;; insn scheduler to change state before advancing cycle.
4862 (define_insn "pre_cycle"
4866 [(set_attr "itanium_class" "pre_cycle")])
4868 (define_insn "bundle_selector"
4869 [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
4871 { return get_bundle_name (INTVAL (operands[0])); }
4872 [(set_attr "itanium_class" "ignore")
4873 (set_attr "predicable" "no")])
4875 ;; Pseudo instruction that prevents the scheduler from moving code above this
4877 (define_insn "blockage"
4878 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4881 [(set_attr "itanium_class" "ignore")
4882 (set_attr "predicable" "no")])
4884 (define_insn "insn_group_barrier"
4885 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
4886 UNSPECV_INSN_GROUP_BARRIER)]
4889 [(set_attr "itanium_class" "stop_bit")
4890 (set_attr "predicable" "no")
4891 (set_attr "empty" "yes")])
4893 (define_expand "trap"
4894 [(trap_if (const_int 1) (const_int 0))]
4898 ;; ??? We don't have a match-any slot type. Setting the type to unknown
4899 ;; produces worse code that setting the slot type to A.
4901 (define_insn "*trap"
4902 [(trap_if (const_int 1) (match_operand 0 "const_int_operand" ""))]
4905 [(set_attr "itanium_class" "chk_s_i")])
4907 (define_expand "ctrapbi4"
4908 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4909 [(match_operand:BI 1 "register_operand" "")
4910 (match_operand:BI 2 "const_int_operand" "")])
4911 (match_operand 3 "" ""))]
4913 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4915 (define_expand "ctrapsi4"
4916 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4917 [(match_operand:SI 1 "gr_register_operand" "")
4918 (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4919 (match_operand 3 "" ""))]
4921 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4923 (define_expand "ctrapdi4"
4924 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4925 [(match_operand:DI 1 "gr_register_operand" "")
4926 (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
4927 (match_operand 3 "" ""))]
4929 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4931 (define_expand "ctrapsf4"
4932 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4933 [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
4934 (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
4935 (match_operand 3 "" ""))]
4937 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4939 (define_expand "ctrapdf4"
4940 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4941 [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
4942 (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
4943 (match_operand 3 "" ""))]
4945 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4947 (define_expand "ctrapxf4"
4948 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4949 [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
4950 (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
4951 (match_operand 3 "" ""))]
4953 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4955 (define_expand "ctraptf4"
4956 [(trap_if (match_operator 0 "ia64_cbranch_operator"
4957 [(match_operand:TF 1 "gr_register_operand" "")
4958 (match_operand:TF 2 "gr_register_operand" "")])
4959 (match_operand 3 "" ""))]
4961 "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
4964 (define_insn "*conditional_trap"
4965 [(trap_if (match_operator 0 "predicate_operator"
4966 [(match_operand:BI 1 "register_operand" "c")
4968 (match_operand 2 "const_int_operand" ""))]
4971 [(set_attr "itanium_class" "chk_s_i")
4972 (set_attr "predicable" "no")])
4974 (define_insn "break_f"
4975 [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
4978 [(set_attr "itanium_class" "nop_f")])
4980 (define_insn "prefetch"
4981 [(prefetch (match_operand:DI 0 "address_operand" "p")
4982 (match_operand:DI 1 "const_int_operand" "n")
4983 (match_operand:DI 2 "const_int_operand" "n"))]
4986 static const char * const alt[2][4] = {
4988 "%,lfetch.nta [%0]",
4989 "%,lfetch.nt1 [%0]",
4990 "%,lfetch.nt2 [%0]",
4994 "%,lfetch.excl.nta [%0]",
4995 "%,lfetch.excl.nt1 [%0]",
4996 "%,lfetch.excl.nt2 [%0]",
4997 "%,lfetch.excl [%0]"
5000 int i = (INTVAL (operands[1]));
5001 int j = (INTVAL (operands[2]));
5003 gcc_assert (i == 0 || i == 1);
5004 gcc_assert (j >= 0 && j <= 3);
5007 [(set_attr "itanium_class" "lfetch")])
5009 ;; Non-local goto support.
5011 (define_expand "save_stack_nonlocal"
5012 [(use (match_operand:OI 0 "memory_operand" ""))
5013 (use (match_operand:DI 1 "register_operand" ""))]
5016 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5017 \"__ia64_save_stack_nonlocal\"),
5018 LCT_NORMAL, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
5019 operands[1], Pmode);
5023 (define_expand "nonlocal_goto"
5024 [(use (match_operand 0 "general_operand" ""))
5025 (use (match_operand 1 "general_operand" ""))
5026 (use (match_operand 2 "general_operand" ""))
5027 (use (match_operand 3 "general_operand" ""))]
5030 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
5031 LCT_NORETURN, VOIDmode, 3,
5033 copy_to_reg (XEXP (operands[2], 0)), Pmode,
5034 operands[3], Pmode);
5039 (define_insn_and_split "nonlocal_goto_receiver"
5040 [(unspec_volatile [(const_int 0)] UNSPECV_GOTO_RECEIVER)]
5050 (define_insn_and_split "builtin_setjmp_receiver"
5051 [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
5061 (define_expand "eh_epilogue"
5062 [(use (match_operand:DI 0 "register_operand" "r"))
5063 (use (match_operand:DI 1 "register_operand" "r"))
5064 (use (match_operand:DI 2 "register_operand" "r"))]
5067 rtx bsp = gen_rtx_REG (Pmode, 10);
5068 rtx sp = gen_rtx_REG (Pmode, 9);
5070 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
5072 emit_move_insn (bsp, operands[0]);
5075 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
5077 emit_move_insn (sp, operands[2]);
5083 cfun->machine->ia64_eh_epilogue_sp = sp;
5084 cfun->machine->ia64_eh_epilogue_bsp = bsp;
5087 ;; Builtin apply support.
5089 (define_expand "restore_stack_nonlocal"
5090 [(use (match_operand:DI 0 "register_operand" ""))
5091 (use (match_operand:OI 1 "memory_operand" ""))]
5094 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
5095 "__ia64_restore_stack_nonlocal"),
5096 LCT_NORMAL, VOIDmode, 1,
5097 copy_to_reg (XEXP (operands[1], 0)), Pmode);
5105 [(match_operator 0 "predicate_operator"
5106 [(match_operand:BI 1 "register_operand" "c")
5111 (define_insn "pred_rel_mutex"
5112 [(set (match_operand:BI 0 "register_operand" "+c")
5113 (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
5115 ".pred.rel.mutex %0, %I0"
5116 [(set_attr "itanium_class" "ignore")
5117 (set_attr "predicable" "no")])
5119 (define_insn "safe_across_calls_all"
5120 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
5122 ".pred.safe_across_calls p1-p63"
5123 [(set_attr "itanium_class" "ignore")
5124 (set_attr "predicable" "no")])
5126 (define_insn "safe_across_calls_normal"
5127 [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
5130 emit_safe_across_calls ();
5133 [(set_attr "itanium_class" "ignore")
5134 (set_attr "predicable" "no")])
5136 ;; UNSPEC instruction definition to "swizzle" 32-bit pointer into 64-bit
5137 ;; pointer. This is used by the HP-UX 32 bit mode.
5139 (define_insn "ptr_extend"
5140 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5141 (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
5145 [(set_attr "itanium_class" "ialu")])
5148 ;; Optimizations for ptr_extend
5150 (define_insn "ptr_extend_plus_imm"
5151 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5153 [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
5154 (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
5156 "addp4_optimize_ok (operands[1], operands[2])"
5158 [(set_attr "itanium_class" "ialu")])
5160 (define_insn "*ptr_extend_plus_2"
5161 [(set (match_operand:DI 0 "gr_register_operand" "=r")
5163 [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
5164 (match_operand:SI 2 "basereg_operand" "r"))]
5166 "addp4_optimize_ok (operands[1], operands[2])"
5168 [(set_attr "itanium_class" "ialu")])
5171 ;; Get instruction pointer
5173 (define_insn "ip_value"
5174 [(set (match_operand:DI 0 "register_operand" "=r")
5178 [(set_attr "itanium_class" "frbr")])
5180 ;; Vector operations
5182 ;; Atomic operations
5184 ;; New division operations