gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 /* Driver configuration.  */
  23
  24 /* A generic LIB_SPEC with -leval and --*group tacked on.  */
  25 #undef  LIB_SPEC
  26 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  27
  28 #undef STARTFILE_SPEC
  29 #undef ENDFILE_SPEC
  30
  31 #undef  LINK_SPEC
  32 #define LINK_SPEC "%{h*} %{v:-V} \
  33                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  34
  35 \f
  36 /* Run-time target specifications.  */
  37
  38 #define TARGET_CPU_CPP_BUILTINS()               \
  39   do                                            \
  40     {                                           \
  41       builtin_define ("__iq2000__");            \
  42       builtin_assert ("cpu=iq2000");            \
  43       builtin_assert ("machine=iq2000");        \
  44     }                                           \
  45   while (0)
  46
  47 /* Macros used in the machine description to test the flags.  */
  48
  49 #define TARGET_STATS            0
  50
  51 #define TARGET_DEBUG_MODE       0
  52 #define TARGET_DEBUG_A_MODE     0
  53 #define TARGET_DEBUG_B_MODE     0
  54 #define TARGET_DEBUG_C_MODE     0
  55 #define TARGET_DEBUG_D_MODE     0
  56
  57 #ifndef IQ2000_ISA_DEFAULT
  58 #define IQ2000_ISA_DEFAULT 1
  59 #endif
  60 \f
  61 /* Storage Layout.  */
  62
  63 #define BITS_BIG_ENDIAN                 0
  64 #define BYTES_BIG_ENDIAN                1
  65 #define WORDS_BIG_ENDIAN                1
  66 #define BITS_PER_WORD                   32
  67 #define MAX_BITS_PER_WORD               64
  68 #define UNITS_PER_WORD                  4
  69 #define MIN_UNITS_PER_WORD              4
  70 #define POINTER_SIZE                    32
  71
  72 /* Define this macro if it is advisable to hold scalars in registers
  73    in a wider mode than that declared by the program.  In such cases,
  74    the value is constrained to be within the bounds of the declared
  75    type, but kept valid in the wider mode.  The signedness of the
  76    extension may differ from that of the type.
  77
  78    We promote any value smaller than SImode up to SImode.  */
  79
  80 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  81   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  82       && GET_MODE_SIZE (MODE) < 4)              \
  83     (MODE) = SImode;
  84
  85 #define PARM_BOUNDARY 32
  86
  87 #define STACK_BOUNDARY 64
  88
  89 #define FUNCTION_BOUNDARY 32
  90
  91 #define BIGGEST_ALIGNMENT 64
  92
  93 #undef  DATA_ALIGNMENT
  94 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
  95   ((((ALIGN) < BITS_PER_WORD)                                           \
  96     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
  97         || TREE_CODE (TYPE) == UNION_TYPE                               \
  98         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
  99
 100 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 101   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 102    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 103
 104 #define EMPTY_FIELD_BOUNDARY 32
 105
 106 #define STRUCTURE_SIZE_BOUNDARY 8
 107
 108 #define STRICT_ALIGNMENT 1
 109
 110 #define PCC_BITFIELD_TYPE_MATTERS 1
 111
 112 \f
 113 /* Layout of Source Language Data Types.  */
 114
 115 #define INT_TYPE_SIZE           32
 116 #define SHORT_TYPE_SIZE         16
 117 #define LONG_TYPE_SIZE          32
 118 #define LONG_LONG_TYPE_SIZE     64
 119 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 120 #define FLOAT_TYPE_SIZE         32
 121 #define DOUBLE_TYPE_SIZE        64
 122 #define LONG_DOUBLE_TYPE_SIZE   64
 123 #define DEFAULT_SIGNED_CHAR     1
 124
 125 #undef  SIZE_TYPE
 126 #define SIZE_TYPE "unsigned int"
 127
 128 #undef  PTRDIFF_TYPE
 129 #define PTRDIFF_TYPE "int"
 130
 131 #undef  WCHAR_TYPE
 132 #define WCHAR_TYPE "long int"
 133
 134 #undef  WCHAR_TYPE_SIZE
 135 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 136
 137 \f
 138 /* Register Basics.  */
 139
 140 /* On the IQ2000, we have 32 integer registers.  */
 141 #define FIRST_PSEUDO_REGISTER 33
 142
 143 #define FIXED_REGISTERS                                                 \
 144 {                                                                       \
 145   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 146   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 147 }
 148
 149 #define CALL_USED_REGISTERS                                             \
 150 {                                                                       \
 151   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 152   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 153 }
 154
 155 \f
 156 /* Order of allocation of registers.  */
 157
 158 #define REG_ALLOC_ORDER                                                 \
 159 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 160   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 161 }
 162
 163 \f
 164 /* How Values Fit in Registers.  */
 165
 166 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 167   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 168
 169 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 170  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 171   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 172   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 173
 174 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 175   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 176     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 177    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 178        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 179
 180 #define AVOID_CCMODE_COPIES
 181
 182 \f
 183 /* Register Classes.  */
 184
 185 enum reg_class
 186 {
 187   NO_REGS,                      /* No registers in set.  */
 188   GR_REGS,                      /* Integer registers.  */
 189   ALL_REGS,                     /* All registers.  */
 190   LIM_REG_CLASSES               /* Max value + 1.  */
 191 };
 192
 193 #define GENERAL_REGS GR_REGS
 194
 195 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 196
 197 #define REG_CLASS_NAMES                                         \
 198 {                                                               \
 199   "NO_REGS",                                                    \
 200   "GR_REGS",                                                    \
 201   "ALL_REGS"                                                    \
 202 }
 203
 204 #define REG_CLASS_CONTENTS                                      \
 205 {                                                               \
 206   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 207   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 208   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 209 }
 210
 211 #define REGNO_REG_CLASS(REGNO) \
 212 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 213
 214 #define BASE_REG_CLASS  (GR_REGS)
 215
 216 #define INDEX_REG_CLASS NO_REGS
 217
 218 #define REGNO_OK_FOR_INDEX_P(regno)     0
 219
 220 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 221   ((CLASS) != ALL_REGS                                          \
 222    ? (CLASS)                                                    \
 223    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 224        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 225       ? (GR_REGS)                                               \
 226       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 227           || GET_MODE (X) == VOIDmode)                          \
 228          ? (GR_REGS)                                            \
 229          : (CLASS))))
 230
 231 \f
 232 /* Basic Stack Layout.  */
 233
 234 #define STACK_GROWS_DOWNWARD
 235
 236 #define FRAME_GROWS_DOWNWARD 0
 237
 238 #define STARTING_FRAME_OFFSET                                           \
 239   (crtl->outgoing_args_size)
 240
 241 /* Use the default value zero.  */
 242 /* #define STACK_POINTER_OFFSET 0 */
 243
 244 #define FIRST_PARM_OFFSET(FNDECL) 0
 245
 246 /* The return address for the current frame is in r31 if this is a leaf
 247    function.  Otherwise, it is on the stack.  It is at a variable offset
 248    from sp/fp/ap, so we define a fake hard register rap which is a
 249    pointer to the return address on the stack.  This always gets eliminated
 250    during reload to be either the frame pointer or the stack pointer plus
 251    an offset.  */
 252
 253 #define RETURN_ADDR_RTX(count, frame)                                   \
 254   (((count) == 0)                                                       \
 255    ? (leaf_function_p ()                                                \
 256       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 257       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 258                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 259     : (rtx) 0)
 260
 261 /* Before the prologue, RA lives in r31.  */
 262 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 263
 264 \f
 265 /* Register That Address the Stack Frame.  */
 266
 267 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 268 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 269 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 270 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 271 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 272 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 273
 274 \f
 275 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 276
 277 #define ELIMINABLE_REGS                                                 \
 278 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 279  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 280  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 281  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 282  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 283  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 284  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 285
 286 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 287         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 288 \f
 289 /* Passing Function Arguments on the Stack.  */
 290
 291 /* #define PUSH_ROUNDING(BYTES) 0 */
 292
 293 #define ACCUMULATE_OUTGOING_ARGS 1
 294
 295 #define REG_PARM_STACK_SPACE(FNDECL) 0
 296
 297 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 298
 299 \f
 300 /* Function Arguments in Registers.  */
 301
 302 #define MAX_ARGS_IN_REGISTERS 8
 303
 304 typedef struct iq2000_args
 305 {
 306   int gp_reg_found;             /* Whether a gp register was found yet.  */
 307   unsigned int arg_number;      /* Argument number.  */
 308   unsigned int arg_words;       /* # total words the arguments take.  */
 309   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 310   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 311   int fp_code;                  /* Mode of FP arguments.  */
 312   unsigned int num_adjusts;     /* Number of adjustments made.  */
 313                                 /* Adjustments made to args pass in regs.  */
 314   rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
 315 } CUMULATIVE_ARGS;
 316
 317 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 318    for a call to a function whose data type is FNTYPE.
 319    For a library call, FNTYPE is 0.  */
 320 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 321   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 322
 323 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 324   (! BYTES_BIG_ENDIAN                                                   \
 325    ? upward                                                             \
 326    : (((MODE) == BLKmode                                                \
 327        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 328           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 329        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 330           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 331       ? downward : upward))
 332
 333 #define FUNCTION_ARG_REGNO_P(N)                                         \
 334   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 335
 336 \f
 337 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 338
 339 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 340
 341 \f
 342 /* How Large Values are Returned.  */
 343
 344 #define DEFAULT_PCC_STRUCT_RETURN 0
 345 \f
 346 /* Function Entry and Exit.  */
 347
 348 #define EXIT_IGNORE_STACK 1
 349
 350 \f
 351 /* Generating Code for Profiling.  */
 352
 353 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 354 {                                                                       \
 355   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 356   fprintf (FILE, "\t.set\tnoat\n");                                     \
 357   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 358            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 359   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 360   fprintf (FILE,                                                        \
 361            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 362            "subu",                                                      \
 363            reg_names[STACK_POINTER_REGNUM],                             \
 364            reg_names[STACK_POINTER_REGNUM],                             \
 365            Pmode == DImode ? 16 : 8);                                   \
 366   fprintf (FILE, "\t.set\treorder\n");                                  \
 367   fprintf (FILE, "\t.set\tat\n");                                       \
 368 }
 369
 370 \f
 371 /* Trampolines for Nested Functions.  */
 372
 373 #define TRAMPOLINE_CODE_SIZE  (8*4)
 374 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 375 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 376
 377 \f
 378 /* Addressing Modes.  */
 379
 380 #define CONSTANT_ADDRESS_P(X)                                           \
 381   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 382     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 383     || (GET_CODE (X) == CONST)))
 384
 385 #define MAX_REGS_PER_ADDRESS 1
 386
 387 #define REG_OK_FOR_INDEX_P(X) 0
 388
 389 \f
 390 /* Describing Relative Costs of Operations.  */
 391
 392 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 393
 394 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 395   (TO_P ? 2 : 16)
 396
 397 #define BRANCH_COST(speed_p, predictable_p) 2
 398
 399 #define SLOW_BYTE_ACCESS 1
 400
 401 #define NO_FUNCTION_CSE 1
 402
 403 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 404   if (REG_NOTE_KIND (LINK) != 0)                                        \
 405     (COST) = 0; /* Anti or output dependence.  */
 406
 407 \f
 408 /* Dividing the output into sections.  */
 409
 410 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 411
 412 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 413
 414 \f
 415 /* The Overall Framework of an Assembler File.  */
 416
 417 #define ASM_COMMENT_START " #"
 418
 419 #define ASM_APP_ON "#APP\n"
 420
 421 #define ASM_APP_OFF "#NO_APP\n"
 422
 423 \f
 424 /* Output and Generation of Labels.  */
 425
 426 #undef ASM_GENERATE_INTERNAL_LABEL
 427 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 428   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 429
 430 #define GLOBAL_ASM_OP "\t.globl\t"
 431
 432 \f
 433 /* Output of Assembler Instructions.  */
 434
 435 #define REGISTER_NAMES                                                  \
 436 {                                                                       \
 437  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 438  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 439  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 440  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 441 }
 442
 443 #define ADDITIONAL_REGISTER_NAMES                                       \
 444 {                                                                       \
 445   { "%0",        0 + GP_REG_FIRST },                                    \
 446   { "%1",        1 + GP_REG_FIRST },                                    \
 447   { "%2",        2 + GP_REG_FIRST },                                    \
 448   { "%3",        3 + GP_REG_FIRST },                                    \
 449   { "%4",        4 + GP_REG_FIRST },                                    \
 450   { "%5",        5 + GP_REG_FIRST },                                    \
 451   { "%6",        6 + GP_REG_FIRST },                                    \
 452   { "%7",        7 + GP_REG_FIRST },                                    \
 453   { "%8",        8 + GP_REG_FIRST },                                    \
 454   { "%9",        9 + GP_REG_FIRST },                                    \
 455   { "%10",      10 + GP_REG_FIRST },                                    \
 456   { "%11",      11 + GP_REG_FIRST },                                    \
 457   { "%12",      12 + GP_REG_FIRST },                                    \
 458   { "%13",      13 + GP_REG_FIRST },                                    \
 459   { "%14",      14 + GP_REG_FIRST },                                    \
 460   { "%15",      15 + GP_REG_FIRST },                                    \
 461   { "%16",      16 + GP_REG_FIRST },                                    \
 462   { "%17",      17 + GP_REG_FIRST },                                    \
 463   { "%18",      18 + GP_REG_FIRST },                                    \
 464   { "%19",      19 + GP_REG_FIRST },                                    \
 465   { "%20",      20 + GP_REG_FIRST },                                    \
 466   { "%21",      21 + GP_REG_FIRST },                                    \
 467   { "%22",      22 + GP_REG_FIRST },                                    \
 468   { "%23",      23 + GP_REG_FIRST },                                    \
 469   { "%24",      24 + GP_REG_FIRST },                                    \
 470   { "%25",      25 + GP_REG_FIRST },                                    \
 471   { "%26",      26 + GP_REG_FIRST },                                    \
 472   { "%27",      27 + GP_REG_FIRST },                                    \
 473   { "%28",      28 + GP_REG_FIRST },                                    \
 474   { "%29",      29 + GP_REG_FIRST },                                    \
 475   { "%30",      27 + GP_REG_FIRST },                                    \
 476   { "%31",      31 + GP_REG_FIRST },                                    \
 477   { "%rap",     32 + GP_REG_FIRST },                                    \
 478 }
 479
 480 /* Check if the current insn needs a nop in front of it
 481    because of load delays, and also update the delay slot statistics.  */
 482
 483 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 484   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 485
 486 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 487 do                                                                      \
 488   {                                                                     \
 489     fputs ("\n", STREAM);                                               \
 490   }                                                                     \
 491 while (0)
 492
 493 #define LOCAL_LABEL_PREFIX      "$"
 494
 495 #define USER_LABEL_PREFIX       ""
 496
 497 \f
 498 /* Output of dispatch tables.  */
 499
 500 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 501   do                                                                    \
 502     {                                                                   \
 503       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 504                Pmode == DImode ? ".dword" : ".word",                    \
 505                LOCAL_LABEL_PREFIX, VALUE);                              \
 506     }                                                                   \
 507   while (0)
 508
 509 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 510   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 511            Pmode == DImode ? ".dword" : ".word",                        \
 512            LOCAL_LABEL_PREFIX,                                          \
 513            VALUE)
 514
 515 \f
 516 /* Assembler Commands for Alignment.  */
 517
 518 #undef ASM_OUTPUT_SKIP
 519 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 520   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 521            (unsigned HOST_WIDE_INT)(SIZE))
 522
 523 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 524   if ((LOG) != 0)                                                       \
 525     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 526
 527 \f
 528 /* Macros Affecting all Debug Formats.  */
 529
 530 #define DEBUGGER_AUTO_OFFSET(X)  \
 531   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 532
 533 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 534   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 535
 536 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 537
 538 #define DWARF2_DEBUGGING_INFO 1
 539
 540 \f
 541 /* Miscellaneous Parameters.  */
 542
 543 #define CASE_VECTOR_MODE SImode
 544
 545 #define WORD_REGISTER_OPERATIONS
 546
 547 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 548
 549 #define MOVE_MAX 4
 550
 551 #define MAX_MOVE_MAX 8
 552
 553 #define SHIFT_COUNT_TRUNCATED 1
 554
 555 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 556
 557 #define STORE_FLAG_VALUE 1
 558
 559 #define Pmode SImode
 560
 561 #define FUNCTION_MODE SImode
 562
 563 /* IQ2000 external variables defined in iq2000.c.  */
 564
 565 /* Comparison type.  */
 566 enum cmp_type
 567 {
 568   CMP_SI,                               /* Compare four byte integers.  */
 569   CMP_DI,                               /* Compare eight byte integers.  */
 570   CMP_SF,                               /* Compare single precision floats.  */
 571   CMP_DF,                               /* Compare double precision floats.  */
 572   CMP_MAX                               /* Max comparison type.  */
 573 };
 574
 575 /* Types of delay slot.  */
 576 enum delay_type
 577 {
 578   DELAY_NONE,                           /* No delay slot.  */
 579   DELAY_LOAD,                           /* Load from memory delay.  */
 580   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 581 };
 582
 583 /* Recast the cpu class to be the cpu attribute.  */
 584 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 585
 586 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 587 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 588
 589 \f
 590 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 591
 592 /* Macros to decide whether certain features are available or not,
 593    depending on the instruction set architecture level.  */
 594
 595 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 596
 597 /* ISA has branch likely instructions.  */
 598 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 599
 600 \f
 601 #undef ASM_SPEC
 602
 603 \f
 604 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 605 #define DWARF_FRAME_REGNUM(REG)        (REG)
 606
 607 /* The DWARF 2 CFA column which tracks the return address.  */
 608 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 609
 610 /* Describe how we implement __builtin_eh_return.  */
 611 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 612
 613 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 614    location used to store the amount to adjust the stack.  This is
 615    usually a register that is available from end of the function's body
 616    to the end of the epilogue. Thus, this cannot be a register used as a
 617    temporary by the epilogue.
 618
 619    This must be an integer register.  */
 620 #define EH_RETURN_STACKADJ_REGNO        3
 621 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 622
 623 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 624    location used to store the address the processor should jump to
 625    catch exception.  This is usually a registers that is available from
 626    end of the function's body to the end of the epilogue. Thus, this
 627    cannot be a register used as a temporary by the epilogue.
 628
 629    This must be an address register.  */
 630 #define EH_RETURN_HANDLER_REGNO         26
 631 #define EH_RETURN_HANDLER_RTX           \
 632         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 633
 634 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 635 #define DWARF_CIE_DATA_ALIGNMENT 4
 636
 637 /* For IQ2000, width of a floating point register.  */
 638 #define UNITS_PER_FPREG 4
 639
 640 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 641
 642 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 643
 644 /* Internal macros to classify a register number as to whether it's a
 645    general purpose register, a floating point register, a
 646    multiply/divide register, or a status register.  */
 647
 648 #define GP_REG_FIRST 0
 649 #define GP_REG_LAST  31
 650 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 651
 652 #define RAP_REG_NUM   32
 653 #define AT_REGNUM       (GP_REG_FIRST + 1)
 654
 655 #define GP_REG_P(REGNO) \
 656   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 657
 658 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 659    is larger than 32K bytes.  These registers must come from the
 660    scratch register set, and not used for passing and returning
 661    arguments and any other information used in the calling sequence.  */
 662
 663 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 664 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 665
 666 /* This macro is used later on in the file.  */
 667 #define GR_REG_CLASS_P(CLASS)                                           \
 668   ((CLASS) == GR_REGS)
 669
 670 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 671 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 672
 673 /* Certain machines have the property that some registers cannot be
 674    copied to some other registers without using memory.  Define this
 675    macro on those machines to be a C expression that is nonzero if
 676    objects of mode MODE in registers of CLASS1 can only be copied to
 677    registers of class CLASS2 by storing a register of CLASS1 into
 678    memory and loading that memory location into a register of CLASS2.
 679
 680    Do not define this macro if its value would always be zero.  */
 681
 682 /* Return the maximum number of consecutive registers
 683    needed to represent mode MODE in a register of class CLASS.  */
 684
 685 #define CLASS_UNITS(mode, size)                                         \
 686   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 687
 688 /* If defined, gives a class of registers that cannot be used as the
 689    operand of a SUBREG that changes the mode of the object illegally.  */
 690
 691 #define CLASS_CANNOT_CHANGE_MODE 0
 692
 693 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 694
 695 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 696   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 697
 698 /* Make sure 4 words are always allocated on the stack.  */
 699
 700 #ifndef STACK_ARGS_ADJUST
 701 #define STACK_ARGS_ADJUST(SIZE)                                         \
 702   {                                                                     \
 703     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 704       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 705   }
 706 #endif
 707
 708 \f
 709 /* Symbolic macros for the registers used to return integer and floating
 710    point values.  */
 711
 712 #define GP_RETURN (GP_REG_FIRST + 2)
 713
 714 /* Symbolic macros for the first/last argument registers.  */
 715
 716 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 717 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 718
 719 #define MAX_ARGS_IN_REGISTERS   8
 720
 721 \f
 722 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 723
 724 #define MUST_SAVE_REGISTER(regno) \
 725   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 726   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 727    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 728
 729 /* ALIGN FRAMES on double word boundaries */
 730 #ifndef IQ2000_STACK_ALIGN
 731 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 732 #endif
 733
 734 \f
 735 /* These assume that REGNO is a hard or pseudo reg number.
 736    They give nonzero only if REGNO is a hard reg of the suitable class
 737    or a pseudo reg currently allocated to a suitable hard reg.
 738    These definitions are NOT overridden anywhere.  */
 739
 740 #define BASE_REG_P(regno, mode)                                 \
 741   (GP_REG_P (regno))
 742
 743 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 744   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 745              (mode))
 746
 747 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 748   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 749
 750 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 751   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 752
 753 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 754    and check its validity for a certain class.
 755    We have two alternate definitions for each of them.
 756    The usual definition accepts all pseudo regs; the other rejects them all.
 757    The symbol REG_OK_STRICT causes the latter definition to be used.
 758
 759    Most source files want to accept pseudo regs in the hope that
 760    they will get allocated to the class that the insn wants them to be in.
 761    Some source files that are used after register allocation
 762    need to be strict.  */
 763
 764 #ifndef REG_OK_STRICT
 765 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 766   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 767 #else
 768 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 769   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 770 #endif
 771
 772 #if 1
 773 #define GO_PRINTF(x)    fprintf (stderr, (x))
 774 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 775 #define GO_DEBUG_RTX(x) debug_rtx (x)
 776
 777 #else
 778 #define GO_PRINTF(x)
 779 #define GO_PRINTF2(x,y)
 780 #define GO_DEBUG_RTX(x)
 781 #endif
 782
 783 /* If defined, modifies the length assigned to instruction INSN as a
 784    function of the context in which it is used.  LENGTH is an lvalue
 785    that contains the initially computed length of the insn and should
 786    be updated with the correct length of the insn.  */
 787 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 788   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 789
 790 \f
 791
 792
 793 /* How to tell the debugger about changes of source files.  */
 794
 795 #ifndef SET_FILE_NUMBER
 796 #define SET_FILE_NUMBER() ++ num_source_filenames
 797 #endif
 798
 799 /* This is how to output a note the debugger telling it the line number
 800    to which the following sequence of instructions corresponds.  */
 801
 802 #ifndef LABEL_AFTER_LOC
 803 #define LABEL_AFTER_LOC(STREAM)
 804 #endif
 805
 806 \f
 807 /* Default to -G 8 */
 808 #ifndef IQ2000_DEFAULT_GVALUE
 809 #define IQ2000_DEFAULT_GVALUE 8
 810 #endif
 811
 812 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 813
 814 \f
 815 /* Which instruction set architecture to use.  */
 816 extern int iq2000_isa;
 817
 818 enum iq2000_builtins
 819 {
 820   IQ2000_BUILTIN_ADO16,
 821   IQ2000_BUILTIN_CFC0,
 822   IQ2000_BUILTIN_CFC1,
 823   IQ2000_BUILTIN_CFC2,
 824   IQ2000_BUILTIN_CFC3,
 825   IQ2000_BUILTIN_CHKHDR,
 826   IQ2000_BUILTIN_CTC0,
 827   IQ2000_BUILTIN_CTC1,
 828   IQ2000_BUILTIN_CTC2,
 829   IQ2000_BUILTIN_CTC3,
 830   IQ2000_BUILTIN_LU,
 831   IQ2000_BUILTIN_LUC32L,
 832   IQ2000_BUILTIN_LUC64,
 833   IQ2000_BUILTIN_LUC64L,
 834   IQ2000_BUILTIN_LUK,
 835   IQ2000_BUILTIN_LULCK,
 836   IQ2000_BUILTIN_LUM32,
 837   IQ2000_BUILTIN_LUM32L,
 838   IQ2000_BUILTIN_LUM64,
 839   IQ2000_BUILTIN_LUM64L,
 840   IQ2000_BUILTIN_LUR,
 841   IQ2000_BUILTIN_LURL,
 842   IQ2000_BUILTIN_MFC0,
 843   IQ2000_BUILTIN_MFC1,
 844   IQ2000_BUILTIN_MFC2,
 845   IQ2000_BUILTIN_MFC3,
 846   IQ2000_BUILTIN_MRGB,
 847   IQ2000_BUILTIN_MTC0,
 848   IQ2000_BUILTIN_MTC1,
 849   IQ2000_BUILTIN_MTC2,
 850   IQ2000_BUILTIN_MTC3,
 851   IQ2000_BUILTIN_PKRL,
 852   IQ2000_BUILTIN_RAM,
 853   IQ2000_BUILTIN_RB,
 854   IQ2000_BUILTIN_RX,
 855   IQ2000_BUILTIN_SRRD,
 856   IQ2000_BUILTIN_SRRDL,
 857   IQ2000_BUILTIN_SRULC,
 858   IQ2000_BUILTIN_SRULCK,
 859   IQ2000_BUILTIN_SRWR,
 860   IQ2000_BUILTIN_SRWRU,
 861   IQ2000_BUILTIN_TRAPQF,
 862   IQ2000_BUILTIN_TRAPQFL,
 863   IQ2000_BUILTIN_TRAPQN,
 864   IQ2000_BUILTIN_TRAPQNE,
 865   IQ2000_BUILTIN_TRAPRE,
 866   IQ2000_BUILTIN_TRAPREL,
 867   IQ2000_BUILTIN_WB,
 868   IQ2000_BUILTIN_WBR,
 869   IQ2000_BUILTIN_WBU,
 870   IQ2000_BUILTIN_WX,
 871   IQ2000_BUILTIN_SYSCALL
 872 };