gcc/config/iq2000/iq2000.h

   1 /* Definitions of target machine for GNU compiler.
   2    Vitesse IQ2000 processors
   3    Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 /* Driver configuration.  */
  23
  24 /* A generic LIB_SPEC with -leval and --*group tacked on.  */
  25 #undef  LIB_SPEC
  26 #define LIB_SPEC "%{!shared:%{!symbolic:--start-group -lc -leval -lgcc --end-group}}"
  27
  28 #undef STARTFILE_SPEC
  29 #undef ENDFILE_SPEC
  30
  31 #undef  LINK_SPEC
  32 #define LINK_SPEC "%{h*} %{v:-V} \
  33                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  34
  35 \f
  36 /* Run-time target specifications.  */
  37
  38 #define TARGET_CPU_CPP_BUILTINS()               \
  39   do                                            \
  40     {                                           \
  41       builtin_define ("__iq2000__");            \
  42       builtin_assert ("cpu=iq2000");            \
  43       builtin_assert ("machine=iq2000");        \
  44     }                                           \
  45   while (0)
  46
  47 /* Macros used in the machine description to test the flags.  */
  48
  49 #define TARGET_STATS            0
  50
  51 #define TARGET_DEBUG_MODE       0
  52 #define TARGET_DEBUG_A_MODE     0
  53 #define TARGET_DEBUG_B_MODE     0
  54 #define TARGET_DEBUG_C_MODE     0
  55 #define TARGET_DEBUG_D_MODE     0
  56
  57 #ifndef IQ2000_ISA_DEFAULT
  58 #define IQ2000_ISA_DEFAULT 1
  59 #endif
  60
  61 #define IQ2000_VERSION "[1.0]"
  62
  63 #ifndef MACHINE_TYPE
  64 #define MACHINE_TYPE "IQ2000"
  65 #endif
  66
  67 #ifndef TARGET_VERSION_INTERNAL
  68 #define TARGET_VERSION_INTERNAL(STREAM)                                 \
  69   fprintf (STREAM, " %s %s", IQ2000_VERSION, MACHINE_TYPE)
  70 #endif
  71
  72 #ifndef TARGET_VERSION
  73 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
  74 #endif
  75 \f
  76 /* Storage Layout.  */
  77
  78 #define BITS_BIG_ENDIAN                 0
  79 #define BYTES_BIG_ENDIAN                1
  80 #define WORDS_BIG_ENDIAN                1
  81 #define BITS_PER_WORD                   32
  82 #define MAX_BITS_PER_WORD               64
  83 #define UNITS_PER_WORD                  4
  84 #define MIN_UNITS_PER_WORD              4
  85 #define POINTER_SIZE                    32
  86
  87 /* Define this macro if it is advisable to hold scalars in registers
  88    in a wider mode than that declared by the program.  In such cases,
  89    the value is constrained to be within the bounds of the declared
  90    type, but kept valid in the wider mode.  The signedness of the
  91    extension may differ from that of the type.
  92
  93    We promote any value smaller than SImode up to SImode.  */
  94
  95 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
  96   if (GET_MODE_CLASS (MODE) == MODE_INT         \
  97       && GET_MODE_SIZE (MODE) < 4)              \
  98     (MODE) = SImode;
  99
 100 #define PARM_BOUNDARY 32
 101
 102 #define STACK_BOUNDARY 64
 103
 104 #define FUNCTION_BOUNDARY 32
 105
 106 #define BIGGEST_ALIGNMENT 64
 107
 108 #undef  DATA_ALIGNMENT
 109 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 110   ((((ALIGN) < BITS_PER_WORD)                                           \
 111     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 112         || TREE_CODE (TYPE) == UNION_TYPE                               \
 113         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 114
 115 #define CONSTANT_ALIGNMENT(EXP, ALIGN)                                  \
 116   ((TREE_CODE (EXP) == STRING_CST  || TREE_CODE (EXP) == CONSTRUCTOR)   \
 117    && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
 118
 119 #define EMPTY_FIELD_BOUNDARY 32
 120
 121 #define STRUCTURE_SIZE_BOUNDARY 8
 122
 123 #define STRICT_ALIGNMENT 1
 124
 125 #define PCC_BITFIELD_TYPE_MATTERS 1
 126
 127 \f
 128 /* Layout of Source Language Data Types.  */
 129
 130 #define INT_TYPE_SIZE           32
 131 #define SHORT_TYPE_SIZE         16
 132 #define LONG_TYPE_SIZE          32
 133 #define LONG_LONG_TYPE_SIZE     64
 134 #define CHAR_TYPE_SIZE          BITS_PER_UNIT
 135 #define FLOAT_TYPE_SIZE         32
 136 #define DOUBLE_TYPE_SIZE        64
 137 #define LONG_DOUBLE_TYPE_SIZE   64
 138 #define DEFAULT_SIGNED_CHAR     1
 139
 140 #undef  SIZE_TYPE
 141 #define SIZE_TYPE "unsigned int"
 142
 143 #undef  PTRDIFF_TYPE
 144 #define PTRDIFF_TYPE "int"
 145
 146 #undef  WCHAR_TYPE
 147 #define WCHAR_TYPE "long int"
 148
 149 #undef  WCHAR_TYPE_SIZE
 150 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 151
 152 \f
 153 /* Register Basics.  */
 154
 155 /* On the IQ2000, we have 32 integer registers.  */
 156 #define FIRST_PSEUDO_REGISTER 33
 157
 158 #define FIXED_REGISTERS                                                 \
 159 {                                                                       \
 160   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 161   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1                     \
 162 }
 163
 164 #define CALL_USED_REGISTERS                                             \
 165 {                                                                       \
 166   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,                       \
 167   0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, 1                     \
 168 }
 169
 170 \f
 171 /* Order of allocation of registers.  */
 172
 173 #define REG_ALLOC_ORDER                                                 \
 174 {  0,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,       \
 175   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31        \
 176 }
 177
 178 \f
 179 /* How Values Fit in Registers.  */
 180
 181 #define HARD_REGNO_NREGS(REGNO, MODE)   \
 182   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 183
 184 #define HARD_REGNO_MODE_OK(REGNO, MODE)                         \
 185  ((REGNO_REG_CLASS (REGNO) == GR_REGS)                          \
 186   ? ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 4             \
 187   : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) == 4)
 188
 189 #define MODES_TIEABLE_P(MODE1, MODE2)                           \
 190   ((GET_MODE_CLASS (MODE1) == MODE_FLOAT ||                     \
 191     GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT)               \
 192    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||                  \
 193        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 194
 195 #define AVOID_CCMODE_COPIES
 196
 197 \f
 198 /* Register Classes.  */
 199
 200 enum reg_class
 201 {
 202   NO_REGS,                      /* No registers in set.  */
 203   GR_REGS,                      /* Integer registers.  */
 204   ALL_REGS,                     /* All registers.  */
 205   LIM_REG_CLASSES               /* Max value + 1.  */
 206 };
 207
 208 #define GENERAL_REGS GR_REGS
 209
 210 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 211
 212 #define IRA_COVER_CLASSES       \
 213 {                               \
 214   GR_REGS, LIM_REG_CLASSES      \
 215 }
 216
 217 #define REG_CLASS_NAMES                                         \
 218 {                                                               \
 219   "NO_REGS",                                                    \
 220   "GR_REGS",                                                    \
 221   "ALL_REGS"                                                    \
 222 }
 223
 224 #define REG_CLASS_CONTENTS                                      \
 225 {                                                               \
 226   { 0x00000000, 0x00000000 },   /* No registers,  */            \
 227   { 0xffffffff, 0x00000000 },   /* Integer registers.  */       \
 228   { 0xffffffff, 0x00000001 }    /* All registers.  */           \
 229 }
 230
 231 #define REGNO_REG_CLASS(REGNO) \
 232 ((REGNO) <= GP_REG_LAST + 1 ? GR_REGS : NO_REGS)
 233
 234 #define BASE_REG_CLASS  (GR_REGS)
 235
 236 #define INDEX_REG_CLASS NO_REGS
 237
 238 #define REGNO_OK_FOR_INDEX_P(regno)     0
 239
 240 #define PREFERRED_RELOAD_CLASS(X,CLASS)                         \
 241   ((CLASS) != ALL_REGS                                          \
 242    ? (CLASS)                                                    \
 243    : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT              \
 244        || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT)  \
 245       ? (GR_REGS)                                               \
 246       : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT             \
 247           || GET_MODE (X) == VOIDmode)                          \
 248          ? (GR_REGS)                                            \
 249          : (CLASS))))
 250
 251 #define CLASS_MAX_NREGS(CLASS, MODE)    \
 252   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 253
 254 \f
 255 /* Basic Stack Layout.  */
 256
 257 #define STACK_GROWS_DOWNWARD
 258
 259 #define FRAME_GROWS_DOWNWARD 0
 260
 261 #define STARTING_FRAME_OFFSET                                           \
 262   (crtl->outgoing_args_size)
 263
 264 /* Use the default value zero.  */
 265 /* #define STACK_POINTER_OFFSET 0 */
 266
 267 #define FIRST_PARM_OFFSET(FNDECL) 0
 268
 269 /* The return address for the current frame is in r31 if this is a leaf
 270    function.  Otherwise, it is on the stack.  It is at a variable offset
 271    from sp/fp/ap, so we define a fake hard register rap which is a
 272    pointer to the return address on the stack.  This always gets eliminated
 273    during reload to be either the frame pointer or the stack pointer plus
 274    an offset.  */
 275
 276 #define RETURN_ADDR_RTX(count, frame)                                   \
 277   (((count) == 0)                                                       \
 278    ? (leaf_function_p ()                                                \
 279       ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31)                          \
 280       : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode,                         \
 281                                          RETURN_ADDRESS_POINTER_REGNUM))) \
 282     : (rtx) 0)
 283
 284 /* Before the prologue, RA lives in r31.  */
 285 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 286
 287 \f
 288 /* Register That Address the Stack Frame.  */
 289
 290 #define STACK_POINTER_REGNUM            (GP_REG_FIRST + 29)
 291 #define FRAME_POINTER_REGNUM            (GP_REG_FIRST + 1)
 292 #define HARD_FRAME_POINTER_REGNUM       (GP_REG_FIRST + 27)
 293 #define ARG_POINTER_REGNUM              GP_REG_FIRST
 294 #define RETURN_ADDRESS_POINTER_REGNUM   RAP_REG_NUM
 295 #define STATIC_CHAIN_REGNUM             (GP_REG_FIRST + 2)
 296
 297 \f
 298 /* Eliminating the Frame Pointer and the Arg Pointer.  */
 299
 300 #define ELIMINABLE_REGS                                                 \
 301 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 302  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 303  { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM},                \
 304  { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},           \
 305  { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31},                   \
 306  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 307  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 308
 309 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)                     \
 310         (OFFSET) = iq2000_initial_elimination_offset ((FROM), (TO))
 311 \f
 312 /* Passing Function Arguments on the Stack.  */
 313
 314 /* #define PUSH_ROUNDING(BYTES) 0 */
 315
 316 #define ACCUMULATE_OUTGOING_ARGS 1
 317
 318 #define REG_PARM_STACK_SPACE(FNDECL) 0
 319
 320 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 321
 322 \f
 323 /* Function Arguments in Registers.  */
 324
 325 #define MAX_ARGS_IN_REGISTERS 8
 326
 327 typedef struct iq2000_args
 328 {
 329   int gp_reg_found;             /* Whether a gp register was found yet.  */
 330   unsigned int arg_number;      /* Argument number.  */
 331   unsigned int arg_words;       /* # total words the arguments take.  */
 332   unsigned int fp_arg_words;    /* # words for FP args (IQ2000_EABI only).  */
 333   int last_arg_fp;              /* Nonzero if last arg was FP (EABI only).  */
 334   int fp_code;                  /* Mode of FP arguments.  */
 335   unsigned int num_adjusts;     /* Number of adjustments made.  */
 336                                 /* Adjustments made to args pass in regs.  */
 337   struct rtx_def * adjust[MAX_ARGS_IN_REGISTERS * 2];
 338 } CUMULATIVE_ARGS;
 339
 340 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 341    for a call to a function whose data type is FNTYPE.
 342    For a library call, FNTYPE is 0.  */
 343 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 344   init_cumulative_args (& CUM, FNTYPE, LIBNAME)                         \
 345
 346 #define FUNCTION_ARG_PADDING(MODE, TYPE)                                \
 347   (! BYTES_BIG_ENDIAN                                                   \
 348    ? upward                                                             \
 349    : (((MODE) == BLKmode                                                \
 350        ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST         \
 351           && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
 352        : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY                       \
 353           && (GET_MODE_CLASS (MODE) == MODE_INT)))                      \
 354       ? downward : upward))
 355
 356 #define FUNCTION_ARG_REGNO_P(N)                                         \
 357   (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
 358
 359 \f
 360 /* On the IQ2000, R2 and R3 are the only register thus used.  */
 361
 362 #define FUNCTION_VALUE_REGNO_P(N) iq2000_function_value_regno_p (N)
 363
 364 \f
 365 /* How Large Values are Returned.  */
 366
 367 #define DEFAULT_PCC_STRUCT_RETURN 0
 368 \f
 369 /* Function Entry and Exit.  */
 370
 371 #define EXIT_IGNORE_STACK 1
 372
 373 \f
 374 /* Generating Code for Profiling.  */
 375
 376 #define FUNCTION_PROFILER(FILE, LABELNO)                                \
 377 {                                                                       \
 378   fprintf (FILE, "\t.set\tnoreorder\n");                                \
 379   fprintf (FILE, "\t.set\tnoat\n");                                     \
 380   fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n",    \
 381            reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]);  \
 382   fprintf (FILE, "\tjal\t_mcount\n");                                   \
 383   fprintf (FILE,                                                        \
 384            "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from  stack\n",    \
 385            "subu",                                                      \
 386            reg_names[STACK_POINTER_REGNUM],                             \
 387            reg_names[STACK_POINTER_REGNUM],                             \
 388            Pmode == DImode ? 16 : 8);                                   \
 389   fprintf (FILE, "\t.set\treorder\n");                                  \
 390   fprintf (FILE, "\t.set\tat\n");                                       \
 391 }
 392
 393 \f
 394 /* Trampolines for Nested Functions.  */
 395
 396 #define TRAMPOLINE_CODE_SIZE  (8*4)
 397 #define TRAMPOLINE_SIZE       (TRAMPOLINE_CODE_SIZE + 2*GET_MODE_SIZE (Pmode))
 398 #define TRAMPOLINE_ALIGNMENT  GET_MODE_ALIGNMENT (Pmode)
 399
 400 \f
 401 /* Addressing Modes.  */
 402
 403 #define CONSTANT_ADDRESS_P(X)                                           \
 404   (   (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF          \
 405     || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH                \
 406     || (GET_CODE (X) == CONST)))
 407
 408 #define MAX_REGS_PER_ADDRESS 1
 409
 410 #define REG_OK_FOR_INDEX_P(X) 0
 411
 412 #define LEGITIMATE_CONSTANT_P(X) (1)
 413
 414 \f
 415 /* Describing Relative Costs of Operations.  */
 416
 417 #define REGISTER_MOVE_COST(MODE, FROM, TO)      2
 418
 419 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P)       \
 420   (TO_P ? 2 : 16)
 421
 422 #define BRANCH_COST(speed_p, predictable_p) 2
 423
 424 #define SLOW_BYTE_ACCESS 1
 425
 426 #define NO_FUNCTION_CSE 1
 427
 428 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)                            \
 429   if (REG_NOTE_KIND (LINK) != 0)                                        \
 430     (COST) = 0; /* Anti or output dependence.  */
 431
 432 \f
 433 /* Dividing the output into sections.  */
 434
 435 #define TEXT_SECTION_ASM_OP     "\t.text"       /* Instructions.  */
 436
 437 #define DATA_SECTION_ASM_OP     "\t.data"       /* Large data.  */
 438
 439 \f
 440 /* The Overall Framework of an Assembler File.  */
 441
 442 #define ASM_COMMENT_START " #"
 443
 444 #define ASM_APP_ON "#APP\n"
 445
 446 #define ASM_APP_OFF "#NO_APP\n"
 447
 448 \f
 449 /* Output and Generation of Labels.  */
 450
 451 #undef ASM_GENERATE_INTERNAL_LABEL
 452 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 453   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM))
 454
 455 #define GLOBAL_ASM_OP "\t.globl\t"
 456
 457 \f
 458 /* Output of Assembler Instructions.  */
 459
 460 #define REGISTER_NAMES                                                  \
 461 {                                                                       \
 462  "%0",   "%1",   "%2",   "%3",   "%4",   "%5",   "%6",   "%7",          \
 463  "%8",   "%9",   "%10",  "%11",  "%12",  "%13",  "%14",  "%15",         \
 464  "%16",  "%17",  "%18",  "%19",  "%20",  "%21",  "%22",  "%23",         \
 465  "%24",  "%25",  "%26",  "%27",  "%28",  "%29",  "%30",  "%31",  "%rap" \
 466 }
 467
 468 #define ADDITIONAL_REGISTER_NAMES                                       \
 469 {                                                                       \
 470   { "%0",        0 + GP_REG_FIRST },                                    \
 471   { "%1",        1 + GP_REG_FIRST },                                    \
 472   { "%2",        2 + GP_REG_FIRST },                                    \
 473   { "%3",        3 + GP_REG_FIRST },                                    \
 474   { "%4",        4 + GP_REG_FIRST },                                    \
 475   { "%5",        5 + GP_REG_FIRST },                                    \
 476   { "%6",        6 + GP_REG_FIRST },                                    \
 477   { "%7",        7 + GP_REG_FIRST },                                    \
 478   { "%8",        8 + GP_REG_FIRST },                                    \
 479   { "%9",        9 + GP_REG_FIRST },                                    \
 480   { "%10",      10 + GP_REG_FIRST },                                    \
 481   { "%11",      11 + GP_REG_FIRST },                                    \
 482   { "%12",      12 + GP_REG_FIRST },                                    \
 483   { "%13",      13 + GP_REG_FIRST },                                    \
 484   { "%14",      14 + GP_REG_FIRST },                                    \
 485   { "%15",      15 + GP_REG_FIRST },                                    \
 486   { "%16",      16 + GP_REG_FIRST },                                    \
 487   { "%17",      17 + GP_REG_FIRST },                                    \
 488   { "%18",      18 + GP_REG_FIRST },                                    \
 489   { "%19",      19 + GP_REG_FIRST },                                    \
 490   { "%20",      20 + GP_REG_FIRST },                                    \
 491   { "%21",      21 + GP_REG_FIRST },                                    \
 492   { "%22",      22 + GP_REG_FIRST },                                    \
 493   { "%23",      23 + GP_REG_FIRST },                                    \
 494   { "%24",      24 + GP_REG_FIRST },                                    \
 495   { "%25",      25 + GP_REG_FIRST },                                    \
 496   { "%26",      26 + GP_REG_FIRST },                                    \
 497   { "%27",      27 + GP_REG_FIRST },                                    \
 498   { "%28",      28 + GP_REG_FIRST },                                    \
 499   { "%29",      29 + GP_REG_FIRST },                                    \
 500   { "%30",      27 + GP_REG_FIRST },                                    \
 501   { "%31",      31 + GP_REG_FIRST },                                    \
 502   { "%rap",     32 + GP_REG_FIRST },                                    \
 503 }
 504
 505 /* Check if the current insn needs a nop in front of it
 506    because of load delays, and also update the delay slot statistics.  */
 507
 508 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)                      \
 509   final_prescan_insn (INSN, OPVEC, NOPERANDS)
 510
 511 #define DBR_OUTPUT_SEQEND(STREAM)                                       \
 512 do                                                                      \
 513   {                                                                     \
 514     fputs ("\n", STREAM);                                               \
 515   }                                                                     \
 516 while (0)
 517
 518 #define LOCAL_LABEL_PREFIX      "$"
 519
 520 #define USER_LABEL_PREFIX       ""
 521
 522 \f
 523 /* Output of dispatch tables.  */
 524
 525 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 526   do                                                                    \
 527     {                                                                   \
 528       fprintf (STREAM, "\t%s\t%sL%d\n",                                 \
 529                Pmode == DImode ? ".dword" : ".word",                    \
 530                LOCAL_LABEL_PREFIX, VALUE);                              \
 531     }                                                                   \
 532   while (0)
 533
 534 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 535   fprintf (STREAM, "\t%s\t%sL%d\n",                                     \
 536            Pmode == DImode ? ".dword" : ".word",                        \
 537            LOCAL_LABEL_PREFIX,                                          \
 538            VALUE)
 539
 540 \f
 541 /* Assembler Commands for Alignment.  */
 542
 543 #undef ASM_OUTPUT_SKIP
 544 #define ASM_OUTPUT_SKIP(STREAM,SIZE)                                    \
 545   fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",      \
 546            (unsigned HOST_WIDE_INT)(SIZE))
 547
 548 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 549   if ((LOG) != 0)                                                       \
 550     fprintf (STREAM, "\t.balign %d\n", 1<<(LOG))
 551
 552 \f
 553 /* Macros Affecting all Debug Formats.  */
 554
 555 #define DEBUGGER_AUTO_OFFSET(X)  \
 556   iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)
 557
 558 #define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
 559   iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
 560
 561 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 562
 563 #define DWARF2_DEBUGGING_INFO 1
 564
 565 \f
 566 /* Miscellaneous Parameters.  */
 567
 568 #define CASE_VECTOR_MODE SImode
 569
 570 #define WORD_REGISTER_OPERATIONS
 571
 572 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
 573
 574 #define MOVE_MAX 4
 575
 576 #define MAX_MOVE_MAX 8
 577
 578 #define SHIFT_COUNT_TRUNCATED 1
 579
 580 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
 581
 582 #define STORE_FLAG_VALUE 1
 583
 584 #define Pmode SImode
 585
 586 #define FUNCTION_MODE SImode
 587
 588 /* Standard GCC variables that we reference.  */
 589
 590 extern char     call_used_regs[];
 591
 592 /* IQ2000 external variables defined in iq2000.c.  */
 593
 594 /* Comparison type.  */
 595 enum cmp_type
 596 {
 597   CMP_SI,                               /* Compare four byte integers.  */
 598   CMP_DI,                               /* Compare eight byte integers.  */
 599   CMP_SF,                               /* Compare single precision floats.  */
 600   CMP_DF,                               /* Compare double precision floats.  */
 601   CMP_MAX                               /* Max comparison type.  */
 602 };
 603
 604 /* Types of delay slot.  */
 605 enum delay_type
 606 {
 607   DELAY_NONE,                           /* No delay slot.  */
 608   DELAY_LOAD,                           /* Load from memory delay.  */
 609   DELAY_FCMP                            /* Delay after doing c.<xx>.{d,s}.  */
 610 };
 611
 612 /* Recast the cpu class to be the cpu attribute.  */
 613 #define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)
 614
 615 #define BITMASK_UPPER16 ((unsigned long) 0xffff << 16)  /* 0xffff0000 */
 616 #define BITMASK_LOWER16 ((unsigned long) 0xffff)        /* 0x0000ffff */
 617
 618 \f
 619 #define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)
 620
 621 /* Macros to decide whether certain features are available or not,
 622    depending on the instruction set architecture level.  */
 623
 624 #define BRANCH_LIKELY_P()       GENERATE_BRANCHLIKELY
 625
 626 /* ISA has branch likely instructions.  */
 627 #define ISA_HAS_BRANCHLIKELY    (iq2000_isa == 1)
 628
 629 \f
 630 #undef ASM_SPEC
 631
 632 \f
 633 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
 634 #define DWARF_FRAME_REGNUM(REG)        (REG)
 635
 636 /* The DWARF 2 CFA column which tracks the return address.  */
 637 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
 638
 639 /* Describe how we implement __builtin_eh_return.  */
 640 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
 641
 642 /* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
 643    location used to store the amount to adjust the stack.  This is
 644    usually a register that is available from end of the function's body
 645    to the end of the epilogue. Thus, this cannot be a register used as a
 646    temporary by the epilogue.
 647
 648    This must be an integer register.  */
 649 #define EH_RETURN_STACKADJ_REGNO        3
 650 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
 651
 652 /* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
 653    location used to store the address the processor should jump to
 654    catch exception.  This is usually a registers that is available from
 655    end of the function's body to the end of the epilogue. Thus, this
 656    cannot be a register used as a temporary by the epilogue.
 657
 658    This must be an address register.  */
 659 #define EH_RETURN_HANDLER_REGNO         26
 660 #define EH_RETURN_HANDLER_RTX           \
 661         gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)
 662
 663 /* Offsets recorded in opcodes are a multiple of this alignment factor.  */
 664 #define DWARF_CIE_DATA_ALIGNMENT 4
 665
 666 /* For IQ2000, width of a floating point register.  */
 667 #define UNITS_PER_FPREG 4
 668
 669 /* Force right-alignment for small varargs in 32 bit little_endian mode */
 670
 671 #define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN
 672
 673 /* Internal macros to classify a register number as to whether it's a
 674    general purpose register, a floating point register, a
 675    multiply/divide register, or a status register.  */
 676
 677 #define GP_REG_FIRST 0
 678 #define GP_REG_LAST  31
 679 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 680
 681 #define RAP_REG_NUM   32
 682 #define AT_REGNUM       (GP_REG_FIRST + 1)
 683
 684 #define GP_REG_P(REGNO) \
 685   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 686
 687 /* IQ2000 registers used in prologue/epilogue code when the stack frame
 688    is larger than 32K bytes.  These registers must come from the
 689    scratch register set, and not used for passing and returning
 690    arguments and any other information used in the calling sequence.  */
 691
 692 #define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
 693 #define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)
 694
 695 /* This macro is used later on in the file.  */
 696 #define GR_REG_CLASS_P(CLASS)                                           \
 697   ((CLASS) == GR_REGS)
 698
 699 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
 700 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
 701
 702 /* Certain machines have the property that some registers cannot be
 703    copied to some other registers without using memory.  Define this
 704    macro on those machines to be a C expression that is nonzero if
 705    objects of mode MODE in registers of CLASS1 can only be copied to
 706    registers of class CLASS2 by storing a register of CLASS1 into
 707    memory and loading that memory location into a register of CLASS2.
 708
 709    Do not define this macro if its value would always be zero.  */
 710
 711 /* Return the maximum number of consecutive registers
 712    needed to represent mode MODE in a register of class CLASS.  */
 713
 714 #define CLASS_UNITS(mode, size)                                         \
 715   ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
 716
 717 /* If defined, gives a class of registers that cannot be used as the
 718    operand of a SUBREG that changes the mode of the object illegally.  */
 719
 720 #define CLASS_CANNOT_CHANGE_MODE 0
 721
 722 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */
 723
 724 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
 725   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
 726
 727 /* Make sure 4 words are always allocated on the stack.  */
 728
 729 #ifndef STACK_ARGS_ADJUST
 730 #define STACK_ARGS_ADJUST(SIZE)                                         \
 731   {                                                                     \
 732     if (SIZE.constant < 4 * UNITS_PER_WORD)                             \
 733       SIZE.constant = 4 * UNITS_PER_WORD;                               \
 734   }
 735 #endif
 736
 737 \f
 738 /* Symbolic macros for the registers used to return integer and floating
 739    point values.  */
 740
 741 #define GP_RETURN (GP_REG_FIRST + 2)
 742
 743 /* Symbolic macros for the first/last argument registers.  */
 744
 745 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
 746 #define GP_ARG_LAST  (GP_REG_FIRST + 11)
 747
 748 #define MAX_ARGS_IN_REGISTERS   8
 749
 750 \f
 751 /* Tell prologue and epilogue if register REGNO should be saved / restored.  */
 752
 753 #define MUST_SAVE_REGISTER(regno) \
 754   ((df_regs_ever_live_p (regno) && !call_used_regs[regno])              \
 755   || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)       \
 756    || (regno == (GP_REG_FIRST + 31) && df_regs_ever_live_p (GP_REG_FIRST + 31)))
 757
 758 /* ALIGN FRAMES on double word boundaries */
 759 #ifndef IQ2000_STACK_ALIGN
 760 #define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
 761 #endif
 762
 763 \f
 764 /* These assume that REGNO is a hard or pseudo reg number.
 765    They give nonzero only if REGNO is a hard reg of the suitable class
 766    or a pseudo reg currently allocated to a suitable hard reg.
 767    These definitions are NOT overridden anywhere.  */
 768
 769 #define BASE_REG_P(regno, mode)                                 \
 770   (GP_REG_P (regno))
 771
 772 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)                              \
 773   BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
 774              (mode))
 775
 776 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
 777   (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
 778
 779 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
 780   GP_REG_OR_PSEUDO_STRICT_P ((int) (regno), (mode))
 781
 782 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 783    and check its validity for a certain class.
 784    We have two alternate definitions for each of them.
 785    The usual definition accepts all pseudo regs; the other rejects them all.
 786    The symbol REG_OK_STRICT causes the latter definition to be used.
 787
 788    Most source files want to accept pseudo regs in the hope that
 789    they will get allocated to the class that the insn wants them to be in.
 790    Some source files that are used after register allocation
 791    need to be strict.  */
 792
 793 #ifndef REG_OK_STRICT
 794 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 795   iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
 796 #else
 797 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 798   iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
 799 #endif
 800
 801 #if 1
 802 #define GO_PRINTF(x)    fprintf (stderr, (x))
 803 #define GO_PRINTF2(x,y) fprintf (stderr, (x), (y))
 804 #define GO_DEBUG_RTX(x) debug_rtx (x)
 805
 806 #else
 807 #define GO_PRINTF(x)
 808 #define GO_PRINTF2(x,y)
 809 #define GO_DEBUG_RTX(x)
 810 #endif
 811
 812 /* If defined, modifies the length assigned to instruction INSN as a
 813    function of the context in which it is used.  LENGTH is an lvalue
 814    that contains the initially computed length of the insn and should
 815    be updated with the correct length of the insn.  */
 816 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
 817   ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))
 818
 819 \f
 820
 821
 822 /* How to tell the debugger about changes of source files.  */
 823
 824 #ifndef SET_FILE_NUMBER
 825 #define SET_FILE_NUMBER() ++ num_source_filenames
 826 #endif
 827
 828 /* This is how to output a note the debugger telling it the line number
 829    to which the following sequence of instructions corresponds.  */
 830
 831 #ifndef LABEL_AFTER_LOC
 832 #define LABEL_AFTER_LOC(STREAM)
 833 #endif
 834
 835 \f
 836 /* Default to -G 8 */
 837 #ifndef IQ2000_DEFAULT_GVALUE
 838 #define IQ2000_DEFAULT_GVALUE 8
 839 #endif
 840
 841 #define SDATA_SECTION_ASM_OP    "\t.sdata"      /* Small data.  */
 842
 843 \f
 844 /* Which instruction set architecture to use.  */
 845 extern int iq2000_isa;
 846
 847 enum iq2000_builtins
 848 {
 849   IQ2000_BUILTIN_ADO16,
 850   IQ2000_BUILTIN_CFC0,
 851   IQ2000_BUILTIN_CFC1,
 852   IQ2000_BUILTIN_CFC2,
 853   IQ2000_BUILTIN_CFC3,
 854   IQ2000_BUILTIN_CHKHDR,
 855   IQ2000_BUILTIN_CTC0,
 856   IQ2000_BUILTIN_CTC1,
 857   IQ2000_BUILTIN_CTC2,
 858   IQ2000_BUILTIN_CTC3,
 859   IQ2000_BUILTIN_LU,
 860   IQ2000_BUILTIN_LUC32L,
 861   IQ2000_BUILTIN_LUC64,
 862   IQ2000_BUILTIN_LUC64L,
 863   IQ2000_BUILTIN_LUK,
 864   IQ2000_BUILTIN_LULCK,
 865   IQ2000_BUILTIN_LUM32,
 866   IQ2000_BUILTIN_LUM32L,
 867   IQ2000_BUILTIN_LUM64,
 868   IQ2000_BUILTIN_LUM64L,
 869   IQ2000_BUILTIN_LUR,
 870   IQ2000_BUILTIN_LURL,
 871   IQ2000_BUILTIN_MFC0,
 872   IQ2000_BUILTIN_MFC1,
 873   IQ2000_BUILTIN_MFC2,
 874   IQ2000_BUILTIN_MFC3,
 875   IQ2000_BUILTIN_MRGB,
 876   IQ2000_BUILTIN_MTC0,
 877   IQ2000_BUILTIN_MTC1,
 878   IQ2000_BUILTIN_MTC2,
 879   IQ2000_BUILTIN_MTC3,
 880   IQ2000_BUILTIN_PKRL,
 881   IQ2000_BUILTIN_RAM,
 882   IQ2000_BUILTIN_RB,
 883   IQ2000_BUILTIN_RX,
 884   IQ2000_BUILTIN_SRRD,
 885   IQ2000_BUILTIN_SRRDL,
 886   IQ2000_BUILTIN_SRULC,
 887   IQ2000_BUILTIN_SRULCK,
 888   IQ2000_BUILTIN_SRWR,
 889   IQ2000_BUILTIN_SRWRU,
 890   IQ2000_BUILTIN_TRAPQF,
 891   IQ2000_BUILTIN_TRAPQFL,
 892   IQ2000_BUILTIN_TRAPQN,
 893   IQ2000_BUILTIN_TRAPQNE,
 894   IQ2000_BUILTIN_TRAPRE,
 895   IQ2000_BUILTIN_TRAPREL,
 896   IQ2000_BUILTIN_WB,
 897   IQ2000_BUILTIN_WBR,
 898   IQ2000_BUILTIN_WBU,
 899   IQ2000_BUILTIN_WX,
 900   IQ2000_BUILTIN_SYSCALL
 901 };