1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors
2 ;; Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
69 ;; UNSPEC values used in iq2000.md
72 ;; 1 movsi_us, get_fnaddr
74 ;; 20 builtin_setjmp_setup
76 ;; UNSPEC_VOLATILE values
80 ;; 4 exception_receiver
92 ;; ....................
96 ;; ....................
98 ;; Classification of each insn.
99 ;; branch conditional branch
100 ;; jump unconditional jump
101 ;; call unconditional call
102 ;; load load instruction(s)
103 ;; store store instruction(s)
104 ;; move data movement within same register set
105 ;; xfer transfer to/from coprocessor
106 ;; arith integer arithmetic instruction
107 ;; darith double precision integer arithmetic instructions
108 ;; imul integer multiply
109 ;; idiv integer divide
110 ;; icmp integer compare
111 ;; fadd floating point add/subtract
112 ;; fmul floating point multiply
113 ;; fmadd floating point multiply-add
114 ;; fdiv floating point divide
115 ;; fabs floating point absolute value
116 ;; fneg floating point negation
117 ;; fcmp floating point compare
118 ;; fcvt floating point convert
119 ;; fsqrt floating point square root
120 ;; multi multiword sequence (or user asm statements)
124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
125 (const_string "unknown"))
127 ;; Main data type used by the insn
128 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
130 ;; Length (in # of bytes). A conditional branch is allowed only to a
131 ;; location within a signed 18-bit offset of the delay slot. If that
132 ;; provides too small a range, we use the `j' instruction. This
133 ;; instruction takes a 28-bit value, but that value is not an offset.
134 ;; Instead, it's bitwise-ored with the high-order four bits of the
135 ;; instruction in the delay slot, which means it cannot be used to
136 ;; cross a 256MB boundary. We could fall back back on the jr,
137 ;; instruction which allows full access to the entire address space,
138 ;; but we do not do so at present.
140 (define_attr "length" ""
141 (cond [(eq_attr "type" "branch")
142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
150 (const (symbol_ref "iq2000_cpu_attr")))
152 ;; Does the instruction have a mandatory delay slot? has_dslot
153 ;; Can the instruction be in a delay slot? ok_in_dslot
154 ;; Can the instruction not be in a delay slot? not_in_dslot
155 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
157 (const_string "has_dslot")
158 (const_string "ok_in_dslot")))
160 ;; Attribute defining whether or not we can use the branch-likely instructions
162 (define_attr "branch_likely" "no,yes"
164 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
166 (const_string "no"))))
169 ;; Describe a user's asm statement.
170 (define_asm_attributes
171 [(set_attr "type" "multi")])
175 ;; .........................
177 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
179 ;; .........................
181 (define_delay (eq_attr "type" "jump")
182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
186 (define_delay (eq_attr "type" "branch")
187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
191 (define_delay (eq_attr "type" "call")
192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
196 (include "predicates.md")
197 (include "constraints.md")
200 ;; .........................
204 ;; .........................
206 (define_automaton "iq2000")
207 (define_cpu_unit "core,memory" "iq2000")
209 (define_insn_reservation "nonmemory" 1
210 (eq_attr "type" "!load,move,store,xfer")
213 (define_insn_reservation "iq2000_load_move" 3
214 (and (eq_attr "type" "load,move")
215 (eq_attr "cpu" "iq2000"))
218 (define_insn_reservation "other_load_move" 1
219 (and (eq_attr "type" "load,move")
220 (eq_attr "cpu" "!iq2000"))
223 (define_insn_reservation "store" 1
224 (eq_attr "type" "store")
227 (define_insn_reservation "xfer" 2
228 (eq_attr "type" "xfer")
232 ;; ....................
236 ;; ....................
240 [(trap_if (const_int 1) (const_int 0))]
248 ;; ....................
252 ;; ....................
255 (define_expand "addsi3"
256 [(set (match_operand:SI 0 "register_operand" "=d")
257 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
258 (match_operand:SI 2 "arith_operand" "dI")))]
262 (define_insn "addsi3_internal"
263 [(set (match_operand:SI 0 "register_operand" "=d,d")
264 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
265 (match_operand:SI 2 "arith_operand" "d,I")))]
270 [(set_attr "type" "arith")
271 (set_attr "mode" "SI")])
274 ;; ....................
278 ;; ....................
281 (define_expand "subsi3"
282 [(set (match_operand:SI 0 "register_operand" "=d")
283 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
284 (match_operand:SI 2 "arith_operand" "dI")))]
288 (define_insn "subsi3_internal"
289 [(set (match_operand:SI 0 "register_operand" "=d,d")
290 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
291 (match_operand:SI 2 "arith_operand" "d,I")))]
296 [(set_attr "type" "arith")
297 (set_attr "mode" "SI")])
300 ;; ....................
302 ;; NEGATION and ONE'S COMPLEMENT
304 ;; ....................
306 (define_insn "negsi2"
307 [(set (match_operand:SI 0 "register_operand" "=d")
308 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
312 operands[2] = const0_rtx;
313 return \"subu\\t%0,%z2,%1\";
315 [(set_attr "type" "arith")
316 (set_attr "mode" "SI")])
318 (define_insn "one_cmplsi2"
319 [(set (match_operand:SI 0 "register_operand" "=d")
320 (not:SI (match_operand:SI 1 "register_operand" "d")))]
324 operands[2] = const0_rtx;
325 return \"nor\\t%0,%z2,%1\";
327 [(set_attr "type" "arith")
328 (set_attr "mode" "SI")])
331 ;; ....................
335 ;; ....................
338 (define_expand "andsi3"
339 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
340 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
341 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
346 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
347 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
348 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
352 if (which_alternative == 0)
353 return \"and\\t%0,%1,%2\";
354 else if (which_alternative == 1)
355 return \"andi\\t%0,%1,%x2\";
356 else if (which_alternative == 2)
358 if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
360 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
361 return \"andoui\\t%0,%1,%x2\";
365 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
366 return \"andoi\\t%0,%1,%x2\";
372 [(set_attr "type" "arith")
373 (set_attr "mode" "SI")])
375 (define_expand "iorsi3"
376 [(set (match_operand:SI 0 "register_operand" "=d,d")
377 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
378 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
383 [(set (match_operand:SI 0 "register_operand" "=d,d")
384 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
385 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
390 [(set_attr "type" "arith")
391 (set_attr "mode" "SI")])
393 (define_expand "xorsi3"
394 [(set (match_operand:SI 0 "register_operand" "=d,d")
395 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
396 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
401 [(set (match_operand:SI 0 "register_operand" "=d,d")
402 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
403 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
408 [(set_attr "type" "arith")
409 (set_attr "mode" "SI")])
411 (define_insn "*norsi3"
412 [(set (match_operand:SI 0 "register_operand" "=d")
413 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
414 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
417 [(set_attr "type" "arith")
418 (set_attr "mode" "SI")])
421 ;; ....................
425 ;; ....................
428 ;; Those for integer source operand are ordered widest source type first.
430 (define_expand "zero_extendhisi2"
431 [(set (match_operand:SI 0 "register_operand" "")
432 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
437 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
438 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
442 if (which_alternative == 0)
443 return \"andi\\t%0,%1,0xffff\";
445 return iq2000_move_1word (operands, insn, TRUE);
447 [(set_attr "type" "arith,load,load")
448 (set_attr "mode" "SI")
449 (set_attr "length" "4,4,8")])
451 (define_expand "zero_extendqihi2"
452 [(set (match_operand:HI 0 "register_operand" "")
453 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
458 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
459 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
463 if (which_alternative == 0)
464 return \"andi\\t%0,%1,0x00ff\";
466 return iq2000_move_1word (operands, insn, TRUE);
468 [(set_attr "type" "arith,load,load")
469 (set_attr "mode" "HI")
470 (set_attr "length" "4,4,8")])
472 (define_expand "zero_extendqisi2"
473 [(set (match_operand:SI 0 "register_operand" "")
474 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
479 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
480 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
484 if (which_alternative == 0)
485 return \"andi\\t%0,%1,0x00ff\";
487 return iq2000_move_1word (operands, insn, TRUE);
489 [(set_attr "type" "arith,load,load")
490 (set_attr "mode" "SI")
491 (set_attr "length" "4,4,8")])
494 ;; ....................
498 ;; ....................
501 ;; Those for integer source operand are ordered widest source type first.
503 ;; These patterns originally accepted general_operands, however, slightly
504 ;; better code is generated by only accepting register_operands, and then
505 ;; letting combine generate the lh and lb insns.
507 (define_expand "extendhisi2"
508 [(set (match_operand:SI 0 "register_operand" "")
509 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
513 if (optimize && GET_CODE (operands[1]) == MEM)
514 operands[1] = force_not_mem (operands[1]);
516 if (GET_CODE (operands[1]) != MEM)
518 rtx op1 = gen_lowpart (SImode, operands[1]);
519 rtx temp = gen_reg_rtx (SImode);
520 rtx shift = GEN_INT (16);
522 emit_insn (gen_ashlsi3 (temp, op1, shift));
523 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
528 (define_insn "extendhisi2_internal"
529 [(set (match_operand:SI 0 "register_operand" "=d,d")
530 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
532 "* return iq2000_move_1word (operands, insn, FALSE);"
533 [(set_attr "type" "load")
534 (set_attr "mode" "SI")
535 (set_attr "length" "4,8")])
537 (define_expand "extendqihi2"
538 [(set (match_operand:HI 0 "register_operand" "")
539 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
543 if (optimize && GET_CODE (operands[1]) == MEM)
544 operands[1] = force_not_mem (operands[1]);
546 if (GET_CODE (operands[1]) != MEM)
548 rtx op0 = gen_lowpart (SImode, operands[0]);
549 rtx op1 = gen_lowpart (SImode, operands[1]);
550 rtx temp = gen_reg_rtx (SImode);
551 rtx shift = GEN_INT (24);
553 emit_insn (gen_ashlsi3 (temp, op1, shift));
554 emit_insn (gen_ashrsi3 (op0, temp, shift));
559 (define_insn "extendqihi2_internal"
560 [(set (match_operand:HI 0 "register_operand" "=d,d")
561 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
563 "* return iq2000_move_1word (operands, insn, FALSE);"
564 [(set_attr "type" "load")
565 (set_attr "mode" "SI")
566 (set_attr "length" "4,8")])
569 (define_expand "extendqisi2"
570 [(set (match_operand:SI 0 "register_operand" "")
571 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
575 if (optimize && GET_CODE (operands[1]) == MEM)
576 operands[1] = force_not_mem (operands[1]);
578 if (GET_CODE (operands[1]) != MEM)
580 rtx op1 = gen_lowpart (SImode, operands[1]);
581 rtx temp = gen_reg_rtx (SImode);
582 rtx shift = GEN_INT (24);
584 emit_insn (gen_ashlsi3 (temp, op1, shift));
585 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
590 (define_insn "extendqisi2_insn"
591 [(set (match_operand:SI 0 "register_operand" "=d,d")
592 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
594 "* return iq2000_move_1word (operands, insn, FALSE);"
595 [(set_attr "type" "load")
596 (set_attr "mode" "SI")
597 (set_attr "length" "4,8")])
600 ;; ........................
602 ;; BIT FIELD EXTRACTION
604 ;; ........................
607 [(set (match_operand:SI 0 "register_operand" "=r")
608 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
609 (match_operand:SI 2 "const_int_operand" "O")
610 (match_operand:SI 3 "const_int_operand" "O")))]
615 value[2] = INTVAL (operands[2]);
616 value[3] = INTVAL (operands[3]);
617 operands[2] = GEN_INT ((value[3]));
618 operands[3] = GEN_INT ((32 - value[2]));
619 return \"ram\\t%0,%1,%2,%3,0x0\";
621 [(set_attr "type" "arith")])
624 ;; ....................
628 ;; ....................
630 /* Take care of constants that don't fit in single instruction */
632 [(set (match_operand:SI 0 "register_operand" "")
633 (match_operand:SI 1 "general_operand" ""))]
634 "(reload_in_progress || reload_completed)
635 && large_int (operands[1], SImode)"
638 (high:SI (match_dup 1)))
640 (lo_sum:SI (match_dup 0)
644 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
648 [(set (match_operand:SI 0 "register_operand" "=r")
649 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
651 "lui\\t%0,%%hi(%1) # high"
652 [(set_attr "type" "move")])
655 [(set (match_operand:SI 0 "register_operand" "=r")
656 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
657 (match_operand:SI 2 "immediate_operand" "")))]
659 "addiu\\t%0,%1,%%lo(%2) # low"
660 [(set_attr "type" "arith")
661 (set_attr "mode" "SI")])
663 ;; 32-bit Integer moves
666 [(set (match_operand:SI 0 "register_operand" "")
667 (match_operand:SI 1 "large_int" ""))]
668 "reload_in_progress | reload_completed"
672 (ior:SI (match_dup 0)
676 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
679 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
682 ;; Unlike most other insns, the move insns can't be split with
683 ;; different predicates, because register spilling and other parts of
684 ;; the compiler, have memoized the insn number already.
686 (define_expand "movsi"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "")
688 (match_operand:SI 1 "general_operand" ""))]
692 if (iq2000_check_split (operands[1], SImode))
694 machine_mode mode = GET_MODE (operands[0]);
695 rtx tem = ((reload_in_progress | reload_completed)
696 ? operands[0] : gen_reg_rtx (mode));
698 emit_insn (gen_rtx_SET (VOIDmode, tem,
699 gen_rtx_HIGH (mode, operands[1])));
701 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
704 if ((reload_in_progress | reload_completed) == 0
705 && !register_operand (operands[0], SImode)
706 && !register_operand (operands[1], SImode)
707 && (GET_CODE (operands[1]) != CONST_INT
708 || INTVAL (operands[1]) != 0))
710 rtx temp = force_reg (SImode, operands[1]);
711 emit_move_insn (operands[0], temp);
715 /* Take care of constants that don't fit in single instruction */
716 if ((reload_in_progress || reload_completed)
717 && CONSTANT_P (operands[1])
718 && GET_CODE (operands[1]) != HIGH
719 && GET_CODE (operands[1]) != LO_SUM
720 && ! SMALL_INT_UNSIGNED (operands[1]))
722 rtx tem = ((reload_in_progress | reload_completed)
723 ? operands[0] : gen_reg_rtx (SImode));
725 emit_insn (gen_rtx_SET (VOIDmode, tem,
726 gen_rtx_HIGH (SImode, operands[1])));
727 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
731 ;; The difference between these two is whether or not ints are allowed
732 ;; in FP registers (off by default, use -mdebugh to enable).
734 (define_insn "movsi_internal2"
735 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m")
736 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
737 "(register_operand (operands[0], SImode)
738 || register_operand (operands[1], SImode)
739 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
740 "* return iq2000_move_1word (operands, insn, FALSE);"
741 [(set_attr "type" "move,arith,arith,load,load,store,store")
742 (set_attr "mode" "SI")
743 (set_attr "length" "4,4,8,8,8,4,8")])
745 ;; 16-bit Integer moves
747 ;; Unlike most other insns, the move insns can't be split with
748 ;; different predicates, because register spilling and other parts of
749 ;; the compiler, have memoized the insn number already.
750 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
752 (define_expand "movhi"
753 [(set (match_operand:HI 0 "nonimmediate_operand" "")
754 (match_operand:HI 1 "general_operand" ""))]
758 if ((reload_in_progress | reload_completed) == 0
759 && !register_operand (operands[0], HImode)
760 && !register_operand (operands[1], HImode)
761 && ((GET_CODE (operands[1]) != CONST_INT
762 || INTVAL (operands[1]) != 0)))
764 rtx temp = force_reg (HImode, operands[1]);
765 emit_move_insn (operands[0], temp);
770 ;; The difference between these two is whether or not ints are allowed
771 ;; in FP registers (off by default, use -mdebugh to enable).
773 (define_insn "movhi_internal2"
774 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
775 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
776 "(register_operand (operands[0], HImode)
777 || register_operand (operands[1], HImode)
778 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
779 "* return iq2000_move_1word (operands, insn, TRUE);"
780 [(set_attr "type" "move,arith,load,load,store,store")
781 (set_attr "mode" "HI")
782 (set_attr "length" "4,4,4,8,4,8")])
784 ;; 8-bit Integer moves
786 ;; Unlike most other insns, the move insns can't be split with
787 ;; different predicates, because register spilling and other parts of
788 ;; the compiler, have memoized the insn number already.
789 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
791 (define_expand "movqi"
792 [(set (match_operand:QI 0 "nonimmediate_operand" "")
793 (match_operand:QI 1 "general_operand" ""))]
797 if ((reload_in_progress | reload_completed) == 0
798 && !register_operand (operands[0], QImode)
799 && !register_operand (operands[1], QImode)
800 && (GET_CODE (operands[1]) != CONST_INT
801 || INTVAL (operands[1]) != 0))
803 rtx temp = force_reg (QImode, operands[1]);
804 emit_move_insn (operands[0], temp);
809 ;; The difference between these two is whether or not ints are allowed
810 ;; in FP registers (off by default, use -mdebugh to enable).
812 (define_insn "movqi_internal2"
813 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
814 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
815 "(register_operand (operands[0], QImode)
816 || register_operand (operands[1], QImode)
817 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
818 "* return iq2000_move_1word (operands, insn, TRUE);"
819 [(set_attr "type" "move,arith,load,load,store,store")
820 (set_attr "mode" "QI")
821 (set_attr "length" "4,4,4,8,4,8")])
823 ;; 32-bit floating point moves
825 (define_expand "movsf"
826 [(set (match_operand:SF 0 "general_operand" "")
827 (match_operand:SF 1 "general_operand" ""))]
831 if (!reload_in_progress
833 && GET_CODE (operands[0]) == MEM
834 && (GET_CODE (operands[1]) == MEM
835 || GET_CODE (operands[1]) == CONST_DOUBLE))
836 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
838 /* Take care of reg <- SF constant */
839 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
841 emit_insn (gen_movsf_high (operands[0], operands[1]));
842 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
847 (define_insn "movsf_lo_sum"
848 [(set (match_operand:SF 0 "register_operand" "=r")
849 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
850 (match_operand:SF 2 "const_double_operand" "")))]
857 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
858 REAL_VALUE_TO_TARGET_SINGLE (r, i);
859 operands[2] = GEN_INT (i);
860 return \"addiu\\t%0,%1,%%lo(%2) # low\";
862 [(set_attr "length" "4")
863 (set_attr "type" "arith")])
865 (define_insn "movsf_high"
866 [(set (match_operand:SF 0 "register_operand" "=r")
867 (high:SF (match_operand:SF 1 "const_double_operand" "")))]
874 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
875 REAL_VALUE_TO_TARGET_SINGLE (r, i);
876 operands[1] = GEN_INT (i);
877 return \"lui\\t%0,%%hi(%1) # high\";
879 [(set_attr "length" "4")
880 (set_attr "type" "arith")])
882 (define_insn "*movsf_internal"
883 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
884 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
885 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
888 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
889 if (which_alternative == 0)
890 return \"or\\t%0,%1,%1\";
891 else if (which_alternative == 1)
892 return \"lw\\t%0,%1\";
893 else if (which_alternative == 2)
894 return \"sw\\t%1,%0\";
898 [(set_attr "length" "4,4,4")
899 (set_attr "type" "arith,load,store")]
903 ;; ....................
907 ;; ....................
909 (define_expand "ashlsi3"
910 [(set (match_operand:SI 0 "register_operand" "=d")
911 (ashift:SI (match_operand:SI 1 "register_operand" "d")
912 (match_operand:SI 2 "arith_operand" "dI")))]
916 (define_insn "ashlsi3_internal1"
917 [(set (match_operand:SI 0 "register_operand" "=d")
918 (ashift:SI (match_operand:SI 1 "register_operand" "d")
919 (match_operand:SI 2 "arith_operand" "dI")))]
923 if (GET_CODE (operands[2]) == CONST_INT)
925 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
926 return \"sll\\t%0,%1,%2\";
929 return \"sllv\\t%0,%1,%2\";
931 [(set_attr "type" "arith")
932 (set_attr "mode" "SI")])
934 (define_expand "ashrsi3"
935 [(set (match_operand:SI 0 "register_operand" "=d")
936 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
937 (match_operand:SI 2 "arith_operand" "dI")))]
941 (define_insn "ashrsi3_internal1"
942 [(set (match_operand:SI 0 "register_operand" "=d")
943 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
944 (match_operand:SI 2 "arith_operand" "dI")))]
948 if (GET_CODE (operands[2]) == CONST_INT)
950 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
951 return \"sra\\t%0,%1,%2\";
954 return \"srav\\t%0,%1,%2\";
956 [(set_attr "type" "arith")
957 (set_attr "mode" "SI")])
959 (define_expand "lshrsi3"
960 [(set (match_operand:SI 0 "register_operand" "=d")
961 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
962 (match_operand:SI 2 "arith_operand" "dI")))]
966 (define_insn "lshrsi3_internal1"
967 [(set (match_operand:SI 0 "register_operand" "=d")
968 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
969 (match_operand:SI 2 "arith_operand" "dI")))]
973 if (GET_CODE (operands[2]) == CONST_INT)
975 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
976 return \"srl\\t%0,%1,%2\";
979 return \"srlv\\t%0,%1,%2\";
981 [(set_attr "type" "arith")
982 (set_attr "mode" "SI")])
985 (define_insn "rotrsi3"
986 [(set (match_operand:SI 0 "register_operand" "=r")
987 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
988 (match_operand:SI 2 "uns_arith_operand" "O")))]
990 "ram %0,%1,%2,0x0,0x0"
991 [(set_attr "type" "arith")])
995 ;; ....................
997 ;; CONDITIONAL BRANCHES
999 ;; ....................
1001 (define_expand "cbranchsi4"
1004 (match_operator 0 "ordered_comparison_operator"
1005 [(match_operand:SI 1 "register_operand")
1006 (match_operand:SI 2 "reg_or_const_operand")])
1007 (label_ref (match_operand 3 ""))
1012 gen_conditional_branch (operands, SImode);
1017 ;; Conditional branches on comparisons with zero.
1019 (define_insn "branch_zero"
1022 (match_operator 0 "cmp_op"
1023 [(match_operand:SI 2 "register_operand" "d")
1025 (label_ref (match_operand 1 "" ""))
1030 return iq2000_output_conditional_branch (insn,
1032 /*two_operands_p=*/0,
1035 get_attr_length (insn));
1037 [(set_attr "type" "branch")
1038 (set_attr "mode" "none")])
1040 (define_insn "branch_zero_inverted"
1043 (match_operator 0 "cmp_op"
1044 [(match_operand:SI 2 "register_operand" "d")
1047 (label_ref (match_operand 1 "" ""))))]
1051 return iq2000_output_conditional_branch (insn,
1053 /*two_operands_p=*/0,
1056 get_attr_length (insn));
1058 [(set_attr "type" "branch")
1059 (set_attr "mode" "none")])
1061 ;; Conditional branch on equality comparison.
1063 (define_insn "branch_equality"
1066 (match_operator 0 "equality_op"
1067 [(match_operand:SI 2 "register_operand" "d")
1068 (match_operand:SI 3 "register_operand" "d")])
1069 (label_ref (match_operand 1 "" ""))
1074 return iq2000_output_conditional_branch (insn,
1076 /*two_operands_p=*/1,
1079 get_attr_length (insn));
1081 [(set_attr "type" "branch")
1082 (set_attr "mode" "none")])
1084 (define_insn "branch_equality_inverted"
1087 (match_operator 0 "equality_op"
1088 [(match_operand:SI 2 "register_operand" "d")
1089 (match_operand:SI 3 "register_operand" "d")])
1091 (label_ref (match_operand 1 "" ""))))]
1095 return iq2000_output_conditional_branch (insn,
1097 /*two_operands_p=*/1,
1100 get_attr_length (insn));
1102 [(set_attr "type" "branch")
1103 (set_attr "mode" "none")])
1106 ;; Recognize bbi and bbin instructions. These use two unusual template
1107 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF
1108 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC
1109 ;; and outputs the operand if `x' is a LABEL_REF.
1114 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1116 (match_operand:SI 1 "arith_operand" "I"))
1118 (match_operand 2 "pc_or_label_operand" "")
1119 (match_operand 3 "pc_or_label_operand" "")))]
1121 "bb%A2\\t%0(31-%1),%P2%P3"
1122 [(set_attr "length" "4")
1123 (set_attr "type" "branch")])
1128 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1130 (match_operand:SI 1 "arith_operand" "I"))
1132 (match_operand 2 "pc_or_label_operand" "")
1133 (match_operand 3 "pc_or_label_operand" "")))]
1135 "bb%A3\\t%0(31-%1),%P2%P3"
1136 [(set_attr "length" "4")
1137 (set_attr "type" "branch")])
1142 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1144 (match_operand:SI 1 "arith_operand" "I"))
1146 (match_operand 2 "pc_or_label_operand" "")
1147 (match_operand 3 "pc_or_label_operand" "")))]
1149 "bb%A2\\t%0(31-%1),%P2%P3"
1150 [(set_attr "length" "4")
1151 (set_attr "type" "branch")])
1156 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1158 (match_operand:SI 1 "arith_operand" "I"))
1160 (match_operand 2 "pc_or_label_operand" "")
1161 (match_operand 3 "pc_or_label_operand" "")))]
1163 "bb%A3\\t%0(31-%1),%P2%P3"
1164 [(set_attr "length" "4")
1165 (set_attr "type" "branch")])
1170 (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1171 (match_operand:SI 1 "power_of_2_operand" "I"))
1173 (match_operand 2 "pc_or_label_operand" "")
1174 (match_operand 3 "pc_or_label_operand" "")))]
1176 "bb%A3\\t%0(%p1),%P2%P3"
1177 [(set_attr "length" "4")
1178 (set_attr "type" "branch")])
1183 (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1184 (match_operand:SI 1 "power_of_2_operand" "I"))
1186 (match_operand 2 "pc_or_label_operand" "")
1187 (match_operand 3 "pc_or_label_operand" "")))]
1189 "bb%A2\\t%0(%p1),%P2%P3"
1190 [(set_attr "length" "4")
1191 (set_attr "type" "branch")])
1194 ;; ....................
1196 ;; SETTING A REGISTER FROM A COMPARISON
1198 ;; ....................
1200 (define_expand "cstoresi4"
1201 [(set (match_operand:SI 0 "register_operand" "=d")
1202 (match_operator:SI 1 "ordered_comparison_operator"
1203 [(match_operand:SI 2 "register_operand")
1204 (match_operand:SI 3 "reg_or_const_operand")]))]
1208 gen_int_relational (GET_CODE (operands[1]), operands[0],
1209 operands[2], operands[3], (int *)0);
1213 (define_insn "seq_si_zero"
1214 [(set (match_operand:SI 0 "register_operand" "=d")
1215 (eq:SI (match_operand:SI 1 "register_operand" "d")
1219 [(set_attr "type" "arith")
1220 (set_attr "mode" "SI")])
1222 (define_insn "sne_si_zero"
1223 [(set (match_operand:SI 0 "register_operand" "=d")
1224 (ne:SI (match_operand:SI 1 "register_operand" "d")
1228 [(set_attr "type" "arith")
1229 (set_attr "mode" "SI")])
1231 (define_insn "sgt_si"
1232 [(set (match_operand:SI 0 "register_operand" "=d,d")
1233 (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1234 (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1239 [(set_attr "type" "arith,arith")
1240 (set_attr "mode" "SI,SI")])
1242 (define_insn "slt_si"
1243 [(set (match_operand:SI 0 "register_operand" "=d,d")
1244 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1245 (match_operand:SI 2 "arith_operand" "d,I")))]
1250 [(set_attr "type" "arith,arith")
1251 (set_attr "mode" "SI,SI")])
1253 (define_insn "sle_si_const"
1254 [(set (match_operand:SI 0 "register_operand" "=d")
1255 (le:SI (match_operand:SI 1 "register_operand" "d")
1256 (match_operand:SI 2 "small_int" "I")))]
1257 "INTVAL (operands[2]) < 32767"
1260 operands[2] = GEN_INT (INTVAL (operands[2])+1);
1261 return \"slti\\t%0,%1,%2\";
1263 [(set_attr "type" "arith")
1264 (set_attr "mode" "SI")])
1266 (define_insn "sgtu_si"
1267 [(set (match_operand:SI 0 "register_operand" "=d")
1268 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1269 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1272 [(set_attr "type" "arith")
1273 (set_attr "mode" "SI")])
1275 (define_insn "sltu_si"
1276 [(set (match_operand:SI 0 "register_operand" "=d,d")
1277 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1278 (match_operand:SI 2 "arith_operand" "d,I")))]
1283 [(set_attr "type" "arith,arith")
1284 (set_attr "mode" "SI,SI")])
1286 (define_insn "sleu_si_const"
1287 [(set (match_operand:SI 0 "register_operand" "=d")
1288 (leu:SI (match_operand:SI 1 "register_operand" "d")
1289 (match_operand:SI 2 "small_int" "I")))]
1290 "INTVAL (operands[2]) < 32767"
1293 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1294 return \"sltiu\\t%0,%1,%2\";
1296 [(set_attr "type" "arith")
1297 (set_attr "mode" "SI")])
1301 ;; ....................
1303 ;; UNCONDITIONAL BRANCHES
1305 ;; ....................
1307 ;; Unconditional branches.
1311 (label_ref (match_operand 0 "" "")))]
1315 if (GET_CODE (operands[0]) == REG)
1318 /* return \"b\\t%l0\";*/
1320 [(set_attr "type" "jump")
1321 (set_attr "mode" "none")])
1323 (define_expand "indirect_jump"
1324 [(set (pc) (match_operand 0 "register_operand" "d"))]
1330 if (operands[0]) /* eliminate unused code warnings */
1333 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1334 operands[0] = copy_to_mode_reg (Pmode, dest);
1336 if (!(Pmode == DImode))
1337 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1339 internal_error (\"unimplemented functionality\");
1345 (define_insn "indirect_jump_internal1"
1346 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1347 "!(Pmode == DImode)"
1349 [(set_attr "type" "jump")
1350 (set_attr "mode" "none")])
1352 (define_expand "tablejump"
1354 (match_operand 0 "register_operand" "d"))
1355 (use (label_ref (match_operand 1 "" "")))]
1359 if (operands[0]) /* eliminate unused code warnings */
1361 gcc_assert (GET_MODE (operands[0]) == Pmode);
1363 if (!(Pmode == DImode))
1364 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1366 internal_error (\"unimplemented functionality\");
1372 (define_insn "tablejump_internal1"
1374 (match_operand:SI 0 "register_operand" "d"))
1375 (use (label_ref (match_operand 1 "" "")))]
1376 "!(Pmode == DImode)"
1378 [(set_attr "type" "jump")
1379 (set_attr "mode" "none")])
1381 (define_expand "tablejump_internal3"
1382 [(parallel [(set (pc)
1383 (plus:SI (match_operand:SI 0 "register_operand" "d")
1384 (label_ref:SI (match_operand 1 "" ""))))
1385 (use (label_ref:SI (match_dup 1)))])]
1389 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
1390 ;;; it is not valid. ??? With the USE, the condition tests may not be required
1393 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
1394 ;;; We just use the conservative number here.
1398 (plus:SI (match_operand:SI 0 "register_operand" "d")
1399 (label_ref:SI (match_operand 1 "" ""))))
1400 (use (label_ref:SI (match_dup 1)))]
1401 "!(Pmode == DImode) && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
1402 && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC"
1407 [(set_attr "type" "jump")
1408 (set_attr "mode" "none")
1409 (set_attr "length" "8")])
1412 ;; ....................
1414 ;; Function prologue/epilogue
1416 ;; ....................
1419 (define_expand "prologue"
1424 if (iq2000_isa >= 0) /* avoid unused code warnings */
1426 iq2000_expand_prologue ();
1431 ;; Block any insns from being moved before this point, since the
1432 ;; profiling call to mcount can use various registers that aren't
1433 ;; saved or used to pass arguments.
1435 (define_insn "blockage"
1436 [(unspec_volatile [(const_int 0)] 0)]
1439 [(set_attr "type" "unknown")
1440 (set_attr "mode" "none")
1441 (set_attr "length" "0")])
1443 (define_expand "epilogue"
1448 if (iq2000_isa >= 0) /* avoid unused code warnings */
1450 iq2000_expand_epilogue ();
1455 ;; Trivial return. Make it look like a normal return insn as that
1456 ;; allows jump optimizations to work better .
1457 (define_insn "return"
1459 "iq2000_can_use_return_insn ()"
1461 [(set_attr "type" "jump")
1462 (set_attr "mode" "none")])
1466 (define_insn "return_internal"
1467 [(use (match_operand 0 "pmode_register_operand" ""))
1474 [(set_attr "type" "jump")
1475 (set_attr "mode" "none")])
1477 (define_insn "eh_return_internal"
1484 [(set_attr "type" "jump")
1485 (set_attr "mode" "none")])
1487 (define_expand "eh_return"
1488 [(use (match_operand:SI 0 "register_operand" "r"))]
1492 iq2000_expand_eh_return (operands[0]);
1498 ;; ....................
1502 ;; ....................
1504 ;; calls.c now passes a third argument, make saber happy
1506 (define_expand "call"
1507 [(parallel [(call (match_operand 0 "memory_operand" "m")
1508 (match_operand 1 "" "i"))
1509 (clobber (reg:SI 31))
1510 (use (match_operand 2 "" "")) ;; next_arg_reg
1511 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
1517 if (operands[0]) /* eliminate unused code warnings */
1519 addr = XEXP (operands[0], 0);
1520 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1521 || ! call_insn_operand (addr, VOIDmode))
1522 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1524 /* In order to pass small structures by value in registers
1525 compatibly with the IQ2000 compiler, we need to shift the value
1526 into the high part of the register. Function_arg has encoded
1527 a PARALLEL rtx, holding a vector of adjustments to be made
1528 as the next_arg_reg variable, so we split up the insns,
1529 and emit them separately. */
1531 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1533 rtvec adjust = XVEC (operands[2], 0);
1534 int num = GET_NUM_ELEM (adjust);
1537 for (i = 0; i < num; i++)
1538 emit_insn (RTVEC_ELT (adjust, i));
1541 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1542 gen_rtx_REG (SImode,
1543 GP_REG_FIRST + 31)));
1548 (define_expand "call_internal0"
1549 [(parallel [(call (match_operand 0 "" "")
1550 (match_operand 1 "" ""))
1551 (clobber (match_operand:SI 2 "" ""))])]
1555 (define_insn "call_internal1"
1556 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1557 (match_operand 1 "" "i"))
1558 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1562 register rtx target = operands[0];
1564 if (GET_CODE (target) == CONST_INT)
1565 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1566 else if (CONSTANT_ADDRESS_P (target))
1567 return \"jal\\t%0\";
1569 return \"jalr\\t%2,%0\";
1571 [(set_attr "type" "call")
1572 (set_attr "mode" "none")])
1574 ;; calls.c now passes a fourth argument, make saber happy
1576 (define_expand "call_value"
1577 [(parallel [(set (match_operand 0 "register_operand" "=d")
1578 (call (match_operand 1 "memory_operand" "m")
1579 (match_operand 2 "" "i")))
1580 (clobber (reg:SI 31))
1581 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1587 if (operands[0]) /* eliminate unused code warning */
1589 addr = XEXP (operands[1], 0);
1590 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1591 || ! call_insn_operand (addr, VOIDmode))
1592 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1594 /* In order to pass small structures by value in registers
1595 compatibly with the IQ2000 compiler, we need to shift the value
1596 into the high part of the register. Function_arg has encoded
1597 a PARALLEL rtx, holding a vector of adjustments to be made
1598 as the next_arg_reg variable, so we split up the insns,
1599 and emit them separately. */
1601 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1603 rtvec adjust = XVEC (operands[3], 0);
1604 int num = GET_NUM_ELEM (adjust);
1607 for (i = 0; i < num; i++)
1608 emit_insn (RTVEC_ELT (adjust, i));
1611 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1613 emit_call_insn (gen_call_value_multiple_internal0
1614 (XEXP (XVECEXP (operands[0], 0, 0), 0),
1615 operands[1], operands[2],
1616 XEXP (XVECEXP (operands[0], 0, 1), 0),
1617 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1621 /* We have a call returning a DImode structure in an FP reg.
1622 Strip off the now unnecessary PARALLEL. */
1623 if (GET_CODE (operands[0]) == PARALLEL)
1624 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1626 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1627 gen_rtx_REG (SImode,
1628 GP_REG_FIRST + 31)));
1634 (define_expand "call_value_internal0"
1635 [(parallel [(set (match_operand 0 "" "")
1636 (call (match_operand 1 "" "")
1637 (match_operand 2 "" "")))
1638 (clobber (match_operand:SI 3 "" ""))])]
1642 (define_insn "call_value_internal1"
1643 [(set (match_operand 0 "register_operand" "=d")
1644 (call (mem (match_operand 1 "call_insn_operand" "r"))
1645 (match_operand 2 "" "i")))
1646 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1650 register rtx target = operands[1];
1652 if (GET_CODE (target) == CONST_INT)
1653 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
1654 else if (CONSTANT_ADDRESS_P (target))
1655 return \"jal\\t%1\";
1657 return \"jalr\\t%3,%1\";
1659 [(set_attr "type" "call")
1660 (set_attr "mode" "none")])
1662 (define_expand "call_value_multiple_internal0"
1663 [(parallel [(set (match_operand 0 "" "")
1664 (call (match_operand 1 "" "")
1665 (match_operand 2 "" "")))
1666 (set (match_operand 3 "" "")
1669 (clobber (match_operand:SI 4 "" ""))])]
1673 ;; ??? May eventually need all 6 versions of the call patterns with multiple
1676 (define_insn "call_value_multiple_internal1"
1677 [(set (match_operand 0 "register_operand" "=d")
1678 (call (mem (match_operand 1 "call_insn_operand" "r"))
1679 (match_operand 2 "" "i")))
1680 (set (match_operand 3 "register_operand" "=d")
1681 (call (mem (match_dup 1))
1683 (clobber (match_operand:SI 4 "register_operand" "=d"))]
1687 register rtx target = operands[1];
1689 if (GET_CODE (target) == CONST_INT)
1690 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
1691 else if (CONSTANT_ADDRESS_P (target))
1692 return \"jal\\t%1\";
1694 return \"jalr\\t%4,%1\";
1696 [(set_attr "type" "call")
1697 (set_attr "mode" "none")])
1699 ;; Call subroutine returning any type.
1701 (define_expand "untyped_call"
1702 [(parallel [(call (match_operand 0 "" "")
1704 (match_operand 1 "" "")
1705 (match_operand 2 "" "")])]
1709 if (operands[0]) /* silence statement not reached warnings */
1713 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
1715 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1717 rtx set = XVECEXP (operands[2], 0, i);
1718 emit_move_insn (SET_DEST (set), SET_SRC (set));
1721 emit_insn (gen_blockage ());
1727 ;; ....................
1731 ;; ....................
1738 [(set_attr "type" "nop")
1739 (set_attr "mode" "none")])
1742 ;; For the rare case where we need to load an address into a register
1743 ;; that cannot be recognized by the normal movsi/addsi instructions.
1744 ;; I have no idea how many insns this can actually generate. It should
1745 ;; be rare, so over-estimating as 10 instructions should not have any
1746 ;; real performance impact.
1747 (define_insn "leasi"
1748 [(set (match_operand:SI 0 "register_operand" "=d")
1749 (match_operand:SI 1 "address_operand" "p"))]
1755 xoperands[0] = operands[0];
1756 xoperands[1] = XEXP (operands[1], 0);
1757 xoperands[2] = XEXP (operands[1], 1);
1758 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
1761 [(set_attr "type" "arith")
1762 (set_attr "mode" "SI")
1763 (set_attr "length" "40")])
1765 (define_insn "ado16"
1766 [(set (match_operand:SI 0 "register_operand" "=r")
1767 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1768 (match_operand:SI 2 "register_operand" "r")]
1771 "ado16\\t%0, %1, %2"
1775 [(set (match_operand:SI 0 "register_operand" "=r")
1776 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1777 (match_operand:SI 2 "const_int_operand" "I")
1778 (match_operand:SI 3 "const_int_operand" "I")
1779 (match_operand:SI 4 "const_int_operand" "I")]
1782 "ram\\t%0, %1, %2, %3, %4"
1785 (define_insn "chkhdr"
1786 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
1787 (match_operand:SI 1 "register_operand" "r")]
1790 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
1791 [(set_attr "dslot" "not_in_dslot")]
1795 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1796 (match_operand:SI 1 "register_operand" "r")]
1799 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
1800 [(set_attr "dslot" "not_in_dslot")]
1804 [(set (match_operand:SI 0 "register_operand" "=r")
1805 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1808 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1809 [(set_attr "dslot" "ok_in_dslot")]
1813 [(set (match_operand:SI 0 "register_operand" "=r")
1814 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1817 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1818 [(set_attr "dslot" "ok_in_dslot")]
1822 [(set (match_operand:SI 0 "register_operand" "=r")
1823 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1826 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1827 [(set_attr "dslot" "not_in_dslot")]
1831 [(set (match_operand:SI 0 "register_operand" "=r")
1832 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1835 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1836 [(set_attr "dslot" "not_in_dslot")]
1840 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1841 (match_operand:SI 1 "const_int_operand" "I")]
1844 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1845 [(set_attr "dslot" "ok_in_dslot")]
1849 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1850 (match_operand:SI 1 "const_int_operand" "I")]
1853 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1854 [(set_attr "dslot" "ok_in_dslot")]
1858 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1859 (match_operand:SI 1 "const_int_operand" "I")]
1862 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1863 [(set_attr "dslot" "ok_in_dslot")]
1867 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1868 (match_operand:SI 1 "const_int_operand" "I")]
1871 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1872 [(set_attr "dslot" "ok_in_dslot")]
1876 [(set (match_operand:SI 0 "register_operand" "=r")
1877 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1880 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1881 [(set_attr "dslot" "ok_in_dslot")]
1885 [(set (match_operand:SI 0 "register_operand" "=r")
1886 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1889 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1890 [(set_attr "dslot" "ok_in_dslot")]
1894 [(set (match_operand:SI 0 "register_operand" "=r")
1895 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1898 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1899 [(set_attr "dslot" "not_in_dslot")]
1903 [(set (match_operand:SI 0 "register_operand" "=r")
1904 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1907 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1908 [(set_attr "dslot" "not_in_dslot")]
1912 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1913 (match_operand:SI 1 "const_int_operand" "I")]
1916 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1917 [(set_attr "dslot" "ok_in_dslot")]
1921 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1922 (match_operand:SI 1 "const_int_operand" "I")]
1925 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1926 [(set_attr "dslot" "ok_in_dslot")]
1930 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1931 (match_operand:SI 1 "const_int_operand" "I")]
1934 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1935 [(set_attr "dslot" "ok_in_dslot")]
1939 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1940 (match_operand:SI 1 "const_int_operand" "I")]
1943 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1944 [(set_attr "dslot" "ok_in_dslot")]
1948 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1949 (match_operand:SI 1 "register_operand" "r")]
1952 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
1953 [(set_attr "dslot" "not_in_dslot")]
1957 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1958 (match_operand:SI 1 "register_operand" "r")]
1961 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
1962 [(set_attr "dslot" "not_in_dslot")]
1966 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1967 (match_operand:SI 1 "register_operand" "r")]
1970 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
1971 [(set_attr "dslot" "not_in_dslot")]
1975 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1978 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
1979 [(set_attr "dslot" "not_in_dslot")]
1983 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1984 (match_operand:SI 1 "register_operand" "r")]
1987 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
1988 [(set_attr "dslot" "not_in_dslot")]
1992 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1993 (match_operand:SI 1 "register_operand" "r")]
1996 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
1997 [(set_attr "dslot" "not_in_dslot")]
2001 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2002 (match_operand:SI 1 "register_operand" "r")]
2005 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2006 [(set_attr "dslot" "not_in_dslot")]
2009 (define_insn "luc32"
2010 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2011 (match_operand:SI 1 "register_operand" "r")]
2014 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2015 [(set_attr "dslot" "not_in_dslot")]
2018 (define_insn "luc32l"
2019 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2020 (match_operand:SI 1 "register_operand" "r")]
2023 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2024 [(set_attr "dslot" "not_in_dslot")]
2027 (define_insn "luc64"
2028 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2029 (match_operand:SI 1 "register_operand" "r")]
2032 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2033 [(set_attr "dslot" "not_in_dslot")]
2036 (define_insn "luc64l"
2037 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2038 (match_operand:SI 1 "register_operand" "r")]
2041 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2042 [(set_attr "dslot" "not_in_dslot")]
2046 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2047 (match_operand:SI 1 "register_operand" "r")]
2050 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2051 [(set_attr "dslot" "ok_in_dslot")]
2054 (define_insn "lulck"
2055 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2058 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2059 [(set_attr "dslot" "not_in_dslot")]
2062 (define_insn "lum32"
2063 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2064 (match_operand:SI 1 "register_operand" "r")]
2067 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2068 [(set_attr "dslot" "not_in_dslot")]
2071 (define_insn "lum32l"
2072 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2073 (match_operand:SI 1 "register_operand" "r")]
2076 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2077 [(set_attr "dslot" "not_in_dslot")]
2080 (define_insn "lum64"
2081 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2082 (match_operand:SI 1 "register_operand" "r")]
2085 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2086 [(set_attr "dslot" "not_in_dslot")]
2089 (define_insn "lum64l"
2090 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2091 (match_operand:SI 1 "register_operand" "r")]
2094 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2095 [(set_attr "dslot" "not_in_dslot")]
2099 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2100 (match_operand:SI 1 "register_operand" "r")]
2103 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2104 [(set_attr "dslot" "not_in_dslot")]
2108 [(set (match_operand:SI 0 "register_operand" "=r")
2109 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2110 (match_operand:SI 2 "register_operand" "r")
2111 (match_operand:SI 3 "const_int_operand" "I")]
2114 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2115 [(set_attr "dslot" "ok_in_dslot")]
2118 (define_insn "srrdl"
2119 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2122 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2123 [(set_attr "dslot" "not_in_dslot")]
2126 (define_insn "srulck"
2127 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2130 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2131 [(set_attr "dslot" "not_in_dslot")]
2134 (define_insn "srwru"
2135 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2136 (match_operand:SI 1 "register_operand" "r")]
2139 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2140 [(set_attr "dslot" "not_in_dslot")]
2143 (define_insn "trapqfl"
2144 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2146 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2147 [(set_attr "dslot" "not_in_dslot")]
2150 (define_insn "trapqne"
2151 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2153 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2154 [(set_attr "dslot" "not_in_dslot")]
2157 (define_insn "traprel"
2158 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2161 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2162 [(set_attr "dslot" "not_in_dslot")]
2166 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2167 (match_operand:SI 1 "register_operand" "r")]
2170 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2171 [(set_attr "dslot" "not_in_dslot")]
2174 (define_insn "syscall"
2175 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2178 [(set_attr "dslot" "not_in_dslot")]