gcc/config/iq2000/iq2000.md

   1 ;;  iq2000.md        Machine Description for Vitesse IQ2000 processors
   2 ;;  Copyright (C) 2003, 2004, 2005, 2007, 2010, 2011, 2012
   3 ;;  Free Software Foundation, Inc.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_constants
  22   [(UNSPEC_ADO16 0)
  23    (UNSPEC_RAM  1)
  24    (UNSPEC_CHKHDR 2)
  25    (UNSPEC_PKRL 3)
  26    (UNSPEC_CFC0 4)
  27    (UNSPEC_CFC1 5)
  28    (UNSPEC_CFC2 6)
  29    (UNSPEC_CFC3 7)
  30    (UNSPEC_CTC0 8)
  31    (UNSPEC_CTC1 9)
  32    (UNSPEC_CTC2 10)
  33    (UNSPEC_CTC3 11)
  34    (UNSPEC_MFC0 12)
  35    (UNSPEC_MFC1 13)
  36    (UNSPEC_MFC2 14)
  37    (UNSPEC_MFC3 15)
  38    (UNSPEC_MTC0 16)
  39    (UNSPEC_MTC1 17)
  40    (UNSPEC_MTC2 18)
  41    (UNSPEC_MTC3 19)
  42    (UNSPEC_LUR  20)
  43    (UNSPEC_RB   21)
  44    (UNSPEC_RX   22)
  45    (UNSPEC_SRRD 23)
  46    (UNSPEC_SRWR 24)
  47    (UNSPEC_WB   25)
  48    (UNSPEC_WX   26)
  49    (UNSPEC_LUC32 49)
  50    (UNSPEC_LUC32L 27)
  51    (UNSPEC_LUC64 28)
  52    (UNSPEC_LUC64L 29)
  53    (UNSPEC_LUK 30)
  54    (UNSPEC_LULCK 31)
  55    (UNSPEC_LUM32 32)
  56    (UNSPEC_LUM32L 33)
  57    (UNSPEC_LUM64 34)
  58    (UNSPEC_LUM64L 35)
  59    (UNSPEC_LURL 36)
  60    (UNSPEC_MRGB 37)
  61    (UNSPEC_SRRDL 38)
  62    (UNSPEC_SRULCK 39)
  63    (UNSPEC_SRWRU 40)
  64    (UNSPEC_TRAPQFL 41)
  65    (UNSPEC_TRAPQNE 42)
  66    (UNSPEC_TRAPREL 43)
  67    (UNSPEC_WBU 44)
  68    (UNSPEC_SYSCALL 45)]
  69 )
  70 ;; UNSPEC values used in iq2000.md
  71 ;; Number       USE
  72 ;; 0            movsi_ul
  73 ;; 1            movsi_us, get_fnaddr
  74 ;; 3            eh_set_return
  75 ;; 20           builtin_setjmp_setup
  76 ;;
  77 ;; UNSPEC_VOLATILE values
  78 ;; 0            blockage
  79 ;; 2            loadgp
  80 ;; 3            builtin_longjmp
  81 ;; 4            exception_receiver
  82 ;; 10           consttable_qi
  83 ;; 11           consttable_hi
  84 ;; 12           consttable_si
  85 ;; 13           consttable_di
  86 ;; 14           consttable_sf
  87 ;; 15           consttable_df
  88 ;; 16           align_2
  89 ;; 17           align_4
  90 ;; 18           align_8
  91 \f
  92
  93 ;; ....................
  94 ;;
  95 ;;      Attributes
  96 ;;
  97 ;; ....................
  98
  99 ;; Classification of each insn.
 100 ;; branch       conditional branch
 101 ;; jump         unconditional jump
 102 ;; call         unconditional call
 103 ;; load         load instruction(s)
 104 ;; store        store instruction(s)
 105 ;; move         data movement within same register set
 106 ;; xfer         transfer to/from coprocessor
 107 ;; arith        integer arithmetic instruction
 108 ;; darith       double precision integer arithmetic instructions
 109 ;; imul         integer multiply
 110 ;; idiv         integer divide
 111 ;; icmp         integer compare
 112 ;; fadd         floating point add/subtract
 113 ;; fmul         floating point multiply
 114 ;; fmadd        floating point multiply-add
 115 ;; fdiv         floating point divide
 116 ;; fabs         floating point absolute value
 117 ;; fneg         floating point negation
 118 ;; fcmp         floating point compare
 119 ;; fcvt         floating point convert
 120 ;; fsqrt        floating point square root
 121 ;; multi        multiword sequence (or user asm statements)
 122 ;; nop          no operation
 123
 124 (define_attr "type"
 125   "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
 126   (const_string "unknown"))
 127
 128 ;; Main data type used by the insn
 129 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
 130
 131 ;; Length (in # of bytes).  A conditional branch is allowed only to a
 132 ;; location within a signed 18-bit offset of the delay slot.  If that
 133 ;; provides too small a range, we use the `j' instruction.  This
 134 ;; instruction takes a 28-bit value, but that value is not an offset.
 135 ;; Instead, it's bitwise-ored with the high-order four bits of the
 136 ;; instruction in the delay slot, which means it cannot be used to
 137 ;; cross a 256MB boundary.  We could fall back back on the jr,
 138 ;; instruction which allows full access to the entire address space,
 139 ;; but we do not do so at present.
 140
 141 (define_attr "length" ""
 142    (cond [(eq_attr "type" "branch")
 143           (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
 144                      (const_int 131072))
 145                  (const_int 4)]
 146                  (const_int 12))]
 147           (const_int 4)))
 148
 149 (define_attr "cpu"
 150   "default,iq2000"
 151   (const (symbol_ref "iq2000_cpu_attr")))
 152
 153 ;; Does the instruction have a mandatory delay slot? has_dslot
 154 ;; Can the instruction be in a delay slot? ok_in_dslot
 155 ;; Can the instruction not be in a delay slot? not_in_dslot
 156 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
 157   (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
 158                 (const_string "has_dslot")
 159                 (const_string "ok_in_dslot")))
 160
 161 ;; Attribute defining whether or not we can use the branch-likely instructions
 162
 163 (define_attr "branch_likely" "no,yes"
 164   (const
 165    (if_then_else (match_test "GENERATE_BRANCHLIKELY")
 166                  (const_string "yes")
 167                  (const_string "no"))))
 168
 169
 170 ;; Describe a user's asm statement.
 171 (define_asm_attributes
 172   [(set_attr "type" "multi")])
 173
 174 \f
 175
 176 ;; .........................
 177 ;;
 178 ;;      Delay slots, can't describe load/fcmp/xfer delay slots here
 179 ;;
 180 ;; .........................
 181
 182 (define_delay (eq_attr "type" "jump")
 183   [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
 184    (nil)
 185    (nil)])
 186
 187 (define_delay (eq_attr "type" "branch")
 188   [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
 189    (nil)
 190    (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
 191
 192 (define_delay (eq_attr "type" "call")
 193   [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
 194    (nil)
 195    (nil)])
 196
 197 (include "predicates.md")
 198 (include "constraints.md")
 199 \f
 200
 201 ;; .........................
 202 ;;
 203 ;;      Pipeline model
 204 ;;
 205 ;; .........................
 206
 207 (define_automaton "iq2000")
 208 (define_cpu_unit "core,memory" "iq2000")
 209
 210 (define_insn_reservation "nonmemory" 1
 211   (eq_attr "type" "!load,move,store,xfer")
 212   "core")
 213
 214 (define_insn_reservation "iq2000_load_move" 3
 215   (and (eq_attr "type" "load,move")
 216        (eq_attr "cpu" "iq2000"))
 217   "memory")
 218
 219 (define_insn_reservation "other_load_move" 1
 220   (and (eq_attr "type" "load,move")
 221        (eq_attr "cpu" "!iq2000"))
 222   "memory")
 223
 224 (define_insn_reservation "store" 1
 225   (eq_attr "type" "store")
 226   "memory")
 227
 228 (define_insn_reservation "xfer" 2
 229   (eq_attr "type" "xfer")
 230   "memory")
 231 \f
 232 ;;
 233 ;;  ....................
 234 ;;
 235 ;;      CONDITIONAL TRAPS
 236 ;;
 237 ;;  ....................
 238 ;;
 239
 240 (define_insn "trap"
 241   [(trap_if (const_int 1) (const_int 0))]
 242   ""
 243   "*
 244 {
 245   return \"break\";
 246 }")
 247 \f
 248 ;;
 249 ;;  ....................
 250 ;;
 251 ;;      ADDITION
 252 ;;
 253 ;;  ....................
 254 ;;
 255
 256 (define_expand "addsi3"
 257   [(set (match_operand:SI 0 "register_operand" "=d")
 258         (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
 259                  (match_operand:SI 2 "arith_operand" "dI")))]
 260   ""
 261   "")
 262
 263 (define_insn "addsi3_internal"
 264   [(set (match_operand:SI 0 "register_operand" "=d,=d")
 265         (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 266                  (match_operand:SI 2 "arith_operand" "d,I")))]
 267   ""
 268   "@
 269    addu\\t%0,%z1,%2
 270    addiu\\t%0,%z1,%2"
 271   [(set_attr "type"     "arith")
 272    (set_attr "mode"     "SI")])
 273 \f
 274 ;;
 275 ;;  ....................
 276 ;;
 277 ;;      SUBTRACTION
 278 ;;
 279 ;;  ....................
 280 ;;
 281
 282 (define_expand "subsi3"
 283   [(set (match_operand:SI 0 "register_operand" "=d")
 284         (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
 285                   (match_operand:SI 2 "arith_operand" "dI")))]
 286   ""
 287   "")
 288
 289 (define_insn "subsi3_internal"
 290   [(set (match_operand:SI 0 "register_operand" "=d,=d")
 291         (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
 292                   (match_operand:SI 2 "arith_operand" "d,I")))]
 293   ""
 294   "@
 295    subu\\t%0,%z1,%2
 296    addiu\\t%0,%z1,%n2"
 297   [(set_attr "type"     "arith")
 298    (set_attr "mode"     "SI")])
 299 \f
 300 ;;
 301 ;;  ....................
 302 ;;
 303 ;;      NEGATION and ONE'S COMPLEMENT
 304 ;;
 305 ;;  ....................
 306
 307 (define_insn "negsi2"
 308   [(set (match_operand:SI 0 "register_operand" "=d")
 309         (neg:SI (match_operand:SI 1 "register_operand" "d")))]
 310   ""
 311   "*
 312 {
 313   operands[2] = const0_rtx;
 314   return \"subu\\t%0,%z2,%1\";
 315 }"
 316   [(set_attr "type"     "arith")
 317    (set_attr "mode"     "SI")])
 318
 319 (define_insn "one_cmplsi2"
 320   [(set (match_operand:SI 0 "register_operand" "=d")
 321         (not:SI (match_operand:SI 1 "register_operand" "d")))]
 322   ""
 323   "*
 324 {
 325   operands[2] = const0_rtx;
 326   return \"nor\\t%0,%z2,%1\";
 327 }"
 328   [(set_attr "type"     "arith")
 329    (set_attr "mode"     "SI")])
 330 \f
 331 ;;
 332 ;;  ....................
 333 ;;
 334 ;;      LOGICAL
 335 ;;
 336 ;;  ....................
 337 ;;
 338
 339 (define_expand "andsi3"
 340   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
 341         (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
 342                 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
 343   ""
 344   "")
 345
 346 (define_insn ""
 347   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
 348         (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
 349                 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
 350   ""
 351   "*
 352 {
 353   if (which_alternative == 0)
 354     return \"and\\t%0,%1,%2\";
 355   else if (which_alternative == 1)
 356     return \"andi\\t%0,%1,%x2\";
 357   else if (which_alternative == 2)
 358     {
 359       if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
 360         {
 361           operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
 362           return \"andoui\\t%0,%1,%x2\";
 363         }
 364       else
 365         {
 366           operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
 367           return \"andoi\\t%0,%1,%x2\";
 368         }
 369     }
 370   else
 371     gcc_unreachable ();
 372 }"
 373   [(set_attr "type"     "arith")
 374    (set_attr "mode"     "SI")])
 375
 376 (define_expand "iorsi3"
 377   [(set (match_operand:SI 0 "register_operand" "=d,d")
 378         (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 379                 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
 380   ""
 381   "")
 382
 383 (define_insn ""
 384   [(set (match_operand:SI 0 "register_operand" "=d,d")
 385         (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 386                 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
 387   ""
 388   "@
 389    or\\t%0,%1,%2
 390    ori\\t%0,%1,%x2"
 391   [(set_attr "type"     "arith")
 392    (set_attr "mode"     "SI")])
 393
 394 (define_expand "xorsi3"
 395   [(set (match_operand:SI 0 "register_operand" "=d,d")
 396         (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 397                 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
 398   ""
 399   "")
 400
 401 (define_insn ""
 402   [(set (match_operand:SI 0 "register_operand" "=d,d")
 403         (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 404                 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
 405   ""
 406   "@
 407    xor\\t%0,%1,%2
 408    xori\\t%0,%1,%x2"
 409   [(set_attr "type"     "arith")
 410    (set_attr "mode"     "SI")])
 411
 412 (define_insn "*norsi3"
 413   [(set (match_operand:SI 0 "register_operand" "=d")
 414         (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
 415                 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
 416   ""
 417   "nor\\t%0,%z1,%z2"
 418   [(set_attr "type"     "arith")
 419    (set_attr "mode"     "SI")])
 420 \f
 421 ;;
 422 ;;  ....................
 423 ;;
 424 ;;      ZERO EXTENSION
 425 ;;
 426 ;;  ....................
 427
 428 ;; Extension insns.
 429 ;; Those for integer source operand are ordered widest source type first.
 430
 431 (define_expand "zero_extendhisi2"
 432   [(set (match_operand:SI 0 "register_operand" "")
 433         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
 434   ""
 435   "")
 436
 437 (define_insn ""
 438   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
 439         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
 440   ""
 441   "*
 442 {
 443   if (which_alternative == 0)
 444     return \"andi\\t%0,%1,0xffff\";
 445   else
 446     return iq2000_move_1word (operands, insn, TRUE);
 447 }"
 448   [(set_attr "type"     "arith,load,load")
 449    (set_attr "mode"     "SI")
 450    (set_attr "length"   "4,4,8")])
 451
 452 (define_expand "zero_extendqihi2"
 453   [(set (match_operand:HI 0 "register_operand" "")
 454         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
 455   ""
 456   "")
 457
 458 (define_insn ""
 459   [(set (match_operand:HI 0 "register_operand" "=d,d,d")
 460         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
 461   ""
 462   "*
 463 {
 464   if (which_alternative == 0)
 465     return \"andi\\t%0,%1,0x00ff\";
 466   else
 467     return iq2000_move_1word (operands, insn, TRUE);
 468 }"
 469   [(set_attr "type"     "arith,load,load")
 470    (set_attr "mode"     "HI")
 471    (set_attr "length"   "4,4,8")])
 472
 473 (define_expand "zero_extendqisi2"
 474   [(set (match_operand:SI 0 "register_operand" "")
 475         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
 476   ""
 477   "")
 478
 479 (define_insn ""
 480   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
 481         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
 482   ""
 483   "*
 484 {
 485   if (which_alternative == 0)
 486     return \"andi\\t%0,%1,0x00ff\";
 487   else
 488     return iq2000_move_1word (operands, insn, TRUE);
 489 }"
 490   [(set_attr "type"     "arith,load,load")
 491    (set_attr "mode"     "SI")
 492    (set_attr "length"   "4,4,8")])
 493
 494 ;;
 495 ;;  ....................
 496 ;;
 497 ;;      SIGN EXTENSION
 498 ;;
 499 ;;  ....................
 500
 501 ;; Extension insns.
 502 ;; Those for integer source operand are ordered widest source type first.
 503
 504 ;; These patterns originally accepted general_operands, however, slightly
 505 ;; better code is generated by only accepting register_operands, and then
 506 ;; letting combine generate the lh and lb insns.
 507
 508 (define_expand "extendhisi2"
 509   [(set (match_operand:SI 0 "register_operand" "")
 510         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
 511   ""
 512   "
 513 {
 514   if (optimize && GET_CODE (operands[1]) == MEM)
 515     operands[1] = force_not_mem (operands[1]);
 516
 517   if (GET_CODE (operands[1]) != MEM)
 518     {
 519       rtx op1   = gen_lowpart (SImode, operands[1]);
 520       rtx temp  = gen_reg_rtx (SImode);
 521       rtx shift = GEN_INT (16);
 522
 523       emit_insn (gen_ashlsi3 (temp, op1, shift));
 524       emit_insn (gen_ashrsi3 (operands[0], temp, shift));
 525       DONE;
 526     }
 527 }")
 528
 529 (define_insn "extendhisi2_internal"
 530   [(set (match_operand:SI 0 "register_operand" "=d,d")
 531         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
 532   ""
 533   "* return iq2000_move_1word (operands, insn, FALSE);"
 534   [(set_attr "type"     "load")
 535    (set_attr "mode"     "SI")
 536    (set_attr "length"   "4,8")])
 537
 538 (define_expand "extendqihi2"
 539   [(set (match_operand:HI 0 "register_operand" "")
 540         (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
 541   ""
 542   "
 543 {
 544   if (optimize && GET_CODE (operands[1]) == MEM)
 545     operands[1] = force_not_mem (operands[1]);
 546
 547   if (GET_CODE (operands[1]) != MEM)
 548     {
 549       rtx op0   = gen_lowpart (SImode, operands[0]);
 550       rtx op1   = gen_lowpart (SImode, operands[1]);
 551       rtx temp  = gen_reg_rtx (SImode);
 552       rtx shift = GEN_INT (24);
 553
 554       emit_insn (gen_ashlsi3 (temp, op1, shift));
 555       emit_insn (gen_ashrsi3 (op0, temp, shift));
 556       DONE;
 557     }
 558 }")
 559
 560 (define_insn "extendqihi2_internal"
 561   [(set (match_operand:HI 0 "register_operand" "=d,d")
 562         (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
 563   ""
 564   "* return iq2000_move_1word (operands, insn, FALSE);"
 565   [(set_attr "type"     "load")
 566    (set_attr "mode"     "SI")
 567    (set_attr "length"   "4,8")])
 568
 569
 570 (define_expand "extendqisi2"
 571   [(set (match_operand:SI 0 "register_operand" "")
 572         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
 573   ""
 574   "
 575 {
 576   if (optimize && GET_CODE (operands[1]) == MEM)
 577     operands[1] = force_not_mem (operands[1]);
 578
 579   if (GET_CODE (operands[1]) != MEM)
 580     {
 581       rtx op1   = gen_lowpart (SImode, operands[1]);
 582       rtx temp  = gen_reg_rtx (SImode);
 583       rtx shift = GEN_INT (24);
 584
 585       emit_insn (gen_ashlsi3 (temp, op1, shift));
 586       emit_insn (gen_ashrsi3 (operands[0], temp, shift));
 587       DONE;
 588     }
 589 }")
 590
 591 (define_insn "extendqisi2_insn"
 592   [(set (match_operand:SI 0 "register_operand" "=d,d")
 593         (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
 594   ""
 595   "* return iq2000_move_1word (operands, insn, FALSE);"
 596   [(set_attr "type"     "load")
 597    (set_attr "mode"     "SI")
 598    (set_attr "length"   "4,8")])
 599 \f
 600 ;;
 601 ;;  ........................
 602 ;;
 603 ;;      BIT FIELD EXTRACTION
 604 ;;
 605 ;;  ........................
 606
 607 (define_insn "extzv"
 608   [(set (match_operand:SI 0 "register_operand" "=r")
 609         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 610                          (match_operand:SI 2 "const_int_operand" "O")
 611                          (match_operand:SI 3 "const_int_operand" "O")))]
 612   ""
 613   "*
 614 {
 615   int value[4];
 616   value[2] = INTVAL (operands[2]);
 617   value[3] = INTVAL (operands[3]);
 618   operands[2] = GEN_INT ((value[3]));
 619   operands[3] = GEN_INT ((32 - value[2]));
 620   return \"ram\\t%0,%1,%2,%3,0x0\";
 621 }"
 622   [(set_attr "type" "arith")])
 623 \f
 624 ;;
 625 ;;  ....................
 626 ;;
 627 ;;      DATA MOVEMENT
 628 ;;
 629 ;;  ....................
 630
 631 /* Take care of constants that don't fit in single instruction */
 632 (define_split
 633   [(set (match_operand:SI 0 "register_operand" "")
 634         (match_operand:SI 1 "general_operand" ""))]
 635   "(reload_in_progress || reload_completed)
 636    && large_int (operands[1], SImode)"
 637
 638   [(set (match_dup 0 )
 639         (high:SI (match_dup 1)))
 640    (set (match_dup 0 )
 641         (lo_sum:SI (match_dup 0)
 642                    (match_dup 1)))]
 643 )
 644
 645 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
 646 ;; unnecessary.
 647
 648 (define_insn "high"
 649   [(set (match_operand:SI 0 "register_operand" "=r")
 650         (high:SI (match_operand:SI 1 "immediate_operand" "")))]
 651   ""
 652   "lui\\t%0,%%hi(%1) # high"
 653   [(set_attr "type"     "move")])
 654
 655 (define_insn "low"
 656   [(set (match_operand:SI 0 "register_operand" "=r")
 657         (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 658                    (match_operand:SI 2 "immediate_operand" "")))]
 659   ""
 660   "addiu\\t%0,%1,%%lo(%2) # low"
 661   [(set_attr "type"     "arith")
 662    (set_attr "mode"     "SI")])
 663
 664 ;; 32-bit Integer moves
 665
 666 (define_split
 667   [(set (match_operand:SI 0 "register_operand" "")
 668         (match_operand:SI 1 "large_int" ""))]
 669   "reload_in_progress | reload_completed"
 670   [(set (match_dup 0)
 671         (match_dup 2))
 672    (set (match_dup 0)
 673         (ior:SI (match_dup 0)
 674                 (match_dup 3)))]
 675   "
 676 {
 677   operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
 678                                              & BITMASK_UPPER16,
 679                                              SImode));
 680   operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
 681 }")
 682
 683 ;; Unlike most other insns, the move insns can't be split with
 684 ;; different predicates, because register spilling and other parts of
 685 ;; the compiler, have memoized the insn number already.
 686
 687 (define_expand "movsi"
 688   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 689         (match_operand:SI 1 "general_operand" ""))]
 690   ""
 691   "
 692 {
 693   if (iq2000_check_split (operands[1], SImode))
 694     {
 695       enum machine_mode mode = GET_MODE (operands[0]);
 696       rtx tem = ((reload_in_progress | reload_completed)
 697                  ? operands[0] : gen_reg_rtx (mode));
 698
 699       emit_insn (gen_rtx_SET (VOIDmode, tem,
 700                               gen_rtx_HIGH (mode, operands[1])));
 701
 702       operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
 703     }
 704
 705   if ((reload_in_progress | reload_completed) == 0
 706       && !register_operand (operands[0], SImode)
 707       && !register_operand (operands[1], SImode)
 708       && (GET_CODE (operands[1]) != CONST_INT
 709           || INTVAL (operands[1]) != 0))
 710     {
 711       rtx temp = force_reg (SImode, operands[1]);
 712       emit_move_insn (operands[0], temp);
 713       DONE;
 714     }
 715
 716   /* Take care of constants that don't fit in single instruction */
 717   if ((reload_in_progress || reload_completed)
 718       && CONSTANT_P (operands[1])
 719       && GET_CODE (operands[1]) != HIGH
 720       && GET_CODE (operands[1]) != LO_SUM
 721       && ! SMALL_INT_UNSIGNED (operands[1]))
 722     {
 723       rtx tem = ((reload_in_progress | reload_completed)
 724                  ? operands[0] : gen_reg_rtx (SImode));
 725
 726       emit_insn (gen_rtx_SET (VOIDmode, tem,
 727                               gen_rtx_HIGH (SImode, operands[1])));
 728       operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
 729     }
 730 }")
 731
 732 ;; The difference between these two is whether or not ints are allowed
 733 ;; in FP registers (off by default, use -mdebugh to enable).
 734
 735 (define_insn "movsi_internal2"
 736   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m")
 737         (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
 738   "(register_operand (operands[0], SImode)
 739        || register_operand (operands[1], SImode)
 740        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
 741   "* return iq2000_move_1word (operands, insn, FALSE);"
 742   [(set_attr "type"     "move,arith,arith,load,load,store,store")
 743    (set_attr "mode"     "SI")
 744    (set_attr "length"   "4,4,8,8,8,4,8")])
 745
 746 ;; 16-bit Integer moves
 747
 748 ;; Unlike most other insns, the move insns can't be split with
 749 ;; different predicates, because register spilling and other parts of
 750 ;; the compiler, have memoized the insn number already.
 751 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
 752
 753 (define_expand "movhi"
 754   [(set (match_operand:HI 0 "nonimmediate_operand" "")
 755         (match_operand:HI 1 "general_operand" ""))]
 756   ""
 757   "
 758 {
 759   if ((reload_in_progress | reload_completed) == 0
 760       && !register_operand (operands[0], HImode)
 761       && !register_operand (operands[1], HImode)
 762       && ((GET_CODE (operands[1]) != CONST_INT
 763           || INTVAL (operands[1]) != 0)))
 764     {
 765       rtx temp = force_reg (HImode, operands[1]);
 766       emit_move_insn (operands[0], temp);
 767       DONE;
 768     }
 769 }")
 770
 771 ;; The difference between these two is whether or not ints are allowed
 772 ;; in FP registers (off by default, use -mdebugh to enable).
 773
 774 (define_insn "movhi_internal2"
 775   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
 776         (match_operand:HI 1 "general_operand"       "d,IK,R,m,dJ,dJ"))]
 777   "(register_operand (operands[0], HImode)
 778        || register_operand (operands[1], HImode)
 779        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
 780   "* return iq2000_move_1word (operands, insn, TRUE);"
 781   [(set_attr "type"     "move,arith,load,load,store,store")
 782    (set_attr "mode"     "HI")
 783    (set_attr "length"   "4,4,4,8,4,8")])
 784
 785 ;; 8-bit Integer moves
 786
 787 ;; Unlike most other insns, the move insns can't be split with
 788 ;; different predicates, because register spilling and other parts of
 789 ;; the compiler, have memoized the insn number already.
 790 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
 791
 792 (define_expand "movqi"
 793   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 794         (match_operand:QI 1 "general_operand" ""))]
 795   ""
 796   "
 797 {
 798   if ((reload_in_progress | reload_completed) == 0
 799       && !register_operand (operands[0], QImode)
 800       && !register_operand (operands[1], QImode)
 801       && (GET_CODE (operands[1]) != CONST_INT
 802           || INTVAL (operands[1]) != 0))
 803     {
 804       rtx temp = force_reg (QImode, operands[1]);
 805       emit_move_insn (operands[0], temp);
 806       DONE;
 807     }
 808 }")
 809
 810 ;; The difference between these two is whether or not ints are allowed
 811 ;; in FP registers (off by default, use -mdebugh to enable).
 812
 813 (define_insn "movqi_internal2"
 814   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m")
 815         (match_operand:QI 1 "general_operand"       "d,IK,R,m,dJ,dJ"))]
 816   "(register_operand (operands[0], QImode)
 817        || register_operand (operands[1], QImode)
 818        || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
 819   "* return iq2000_move_1word (operands, insn, TRUE);"
 820   [(set_attr "type"     "move,arith,load,load,store,store")
 821    (set_attr "mode"     "QI")
 822    (set_attr "length"   "4,4,4,8,4,8")])
 823
 824 ;; 32-bit floating point moves
 825
 826 (define_expand "movsf"
 827   [(set (match_operand:SF 0 "general_operand" "")
 828         (match_operand:SF 1 "general_operand" ""))]
 829   ""
 830   "
 831 {
 832   if (!reload_in_progress
 833       && !reload_completed
 834       && GET_CODE (operands[0]) == MEM
 835       && (GET_CODE (operands[1]) == MEM
 836          || GET_CODE (operands[1]) == CONST_DOUBLE))
 837     operands[1] = copy_to_mode_reg (SFmode, operands[1]);
 838
 839   /* Take care of reg <- SF constant */
 840   if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
 841     {
 842       emit_insn (gen_movsf_high (operands[0], operands[1]));
 843       emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
 844       DONE;
 845     }
 846 }")
 847
 848 (define_insn "movsf_lo_sum"
 849   [(set (match_operand:SF 0 "register_operand" "=r")
 850         (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
 851                    (match_operand:SF 2 "const_double_operand" "")))]
 852   ""
 853   "*
 854 {
 855   REAL_VALUE_TYPE r;
 856   long i;
 857
 858   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
 859   REAL_VALUE_TO_TARGET_SINGLE (r, i);
 860   operands[2] = GEN_INT (i);
 861   return \"addiu\\t%0,%1,%%lo(%2) # low\";
 862 }"
 863   [(set_attr "length" "4")
 864    (set_attr "type" "arith")])
 865
 866 (define_insn "movsf_high"
 867   [(set (match_operand:SF 0 "register_operand" "=r")
 868         (high:SF (match_operand:SF 1 "const_double_operand" "")))]
 869   ""
 870   "*
 871 {
 872   REAL_VALUE_TYPE r;
 873   long i;
 874
 875   REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
 876   REAL_VALUE_TO_TARGET_SINGLE (r, i);
 877   operands[1] = GEN_INT (i);
 878   return \"lui\\t%0,%%hi(%1) # high\";
 879 }"
 880   [(set_attr "length" "4")
 881    (set_attr "type" "arith")])
 882
 883 (define_insn "*movsf_internal"
 884   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
 885         (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
 886   "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
 887   "*
 888 {
 889   iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
 890   if (which_alternative == 0)
 891     return \"or\\t%0,%1,%1\";
 892   else if (which_alternative == 1)
 893     return \"lw\\t%0,%1\";
 894   else if (which_alternative == 2)
 895     return \"sw\\t%1,%0\";
 896   else
 897     gcc_unreachable ();
 898 }"
 899   [(set_attr "length" "4,4,4")
 900    (set_attr "type" "arith,load,store")]
 901 )
 902 \f
 903 ;;
 904 ;;  ....................
 905 ;;
 906 ;;      SHIFTS
 907 ;;
 908 ;;  ....................
 909
 910 (define_expand "ashlsi3"
 911   [(set (match_operand:SI 0 "register_operand" "=d")
 912         (ashift:SI (match_operand:SI 1 "register_operand" "d")
 913                    (match_operand:SI 2 "arith_operand" "dI")))]
 914   ""
 915   "")
 916
 917 (define_insn "ashlsi3_internal1"
 918   [(set (match_operand:SI 0 "register_operand" "=d")
 919         (ashift:SI (match_operand:SI 1 "register_operand" "d")
 920                    (match_operand:SI 2 "arith_operand" "dI")))]
 921   ""
 922   "*
 923 {
 924   if (GET_CODE (operands[2]) == CONST_INT)
 925     {
 926       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 927       return \"sll\\t%0,%1,%2\";
 928     }
 929   else
 930     return \"sllv\\t%0,%1,%2\";
 931 }"
 932   [(set_attr "type"     "arith")
 933    (set_attr "mode"     "SI")])
 934
 935 (define_expand "ashrsi3"
 936   [(set (match_operand:SI 0 "register_operand" "=d")
 937         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
 938                      (match_operand:SI 2 "arith_operand" "dI")))]
 939   ""
 940   "")
 941
 942 (define_insn "ashrsi3_internal1"
 943   [(set (match_operand:SI 0 "register_operand" "=d")
 944         (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
 945                      (match_operand:SI 2 "arith_operand" "dI")))]
 946   ""
 947   "*
 948 {
 949   if (GET_CODE (operands[2]) == CONST_INT)
 950     {
 951       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 952       return \"sra\\t%0,%1,%2\";
 953     }
 954   else
 955     return \"srav\\t%0,%1,%2\";
 956 }"
 957   [(set_attr "type"     "arith")
 958    (set_attr "mode"     "SI")])
 959
 960 (define_expand "lshrsi3"
 961   [(set (match_operand:SI 0 "register_operand" "=d")
 962         (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
 963                      (match_operand:SI 2 "arith_operand" "dI")))]
 964   ""
 965   "")
 966
 967 (define_insn "lshrsi3_internal1"
 968   [(set (match_operand:SI 0 "register_operand" "=d")
 969         (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
 970                      (match_operand:SI 2 "arith_operand" "dI")))]
 971   ""
 972   "*
 973 {
 974   if (GET_CODE (operands[2]) == CONST_INT)
 975     {
 976       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 977       return \"srl\\t%0,%1,%2\";
 978     }
 979   else
 980     return \"srlv\\t%0,%1,%2\";
 981 }"
 982   [(set_attr "type"     "arith")
 983    (set_attr "mode"     "SI")])
 984
 985 ;; Rotate Right
 986 (define_insn "rotrsi3"
 987   [(set (match_operand:SI 0 "register_operand" "=r")
 988         (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 989                      (match_operand:SI 2 "uns_arith_operand" "O")))]
 990   ""
 991   "ram %0,%1,%2,0x0,0x0"
 992   [(set_attr "type" "arith")])
 993
 994 \f
 995 ;;
 996 ;;  ....................
 997 ;;
 998 ;;      CONDITIONAL BRANCHES
 999 ;;
1000 ;;  ....................
1001
1002 (define_expand "cbranchsi4"
1003   [(set (pc)
1004         (if_then_else
1005          (match_operator 0 "ordered_comparison_operator"
1006                          [(match_operand:SI 1 "register_operand")
1007                           (match_operand:SI 2 "reg_or_const_operand")])
1008          (label_ref (match_operand 3 ""))
1009          (pc)))]
1010   ""
1011   "
1012 {
1013   gen_conditional_branch (operands, SImode);
1014   DONE;
1015 }")
1016
1017
1018 ;; Conditional branches on comparisons with zero.
1019
1020 (define_insn "branch_zero"
1021   [(set (pc)
1022         (if_then_else
1023          (match_operator 0 "cmp_op"
1024                          [(match_operand:SI 2 "register_operand" "d")
1025                           (const_int 0)])
1026         (label_ref (match_operand 1 "" ""))
1027         (pc)))]
1028   ""
1029   "*
1030 {
1031   return iq2000_output_conditional_branch (insn,
1032                                          operands,
1033                                          /*two_operands_p=*/0,
1034                                          /*float_p=*/0,
1035                                          /*inverted_p=*/0,
1036                                          get_attr_length (insn));
1037 }"
1038   [(set_attr "type"     "branch")
1039    (set_attr "mode"     "none")])
1040
1041 (define_insn "branch_zero_inverted"
1042   [(set (pc)
1043         (if_then_else
1044          (match_operator 0 "cmp_op"
1045                          [(match_operand:SI 2 "register_operand" "d")
1046                           (const_int 0)])
1047         (pc)
1048         (label_ref (match_operand 1 "" ""))))]
1049   ""
1050   "*
1051 {
1052   return iq2000_output_conditional_branch (insn,
1053                                          operands,
1054                                          /*two_operands_p=*/0,
1055                                          /*float_p=*/0,
1056                                          /*inverted_p=*/1,
1057                                          get_attr_length (insn));
1058 }"
1059   [(set_attr "type"     "branch")
1060    (set_attr "mode"     "none")])
1061
1062 ;; Conditional branch on equality comparison.
1063
1064 (define_insn "branch_equality"
1065   [(set (pc)
1066         (if_then_else
1067          (match_operator 0 "equality_op"
1068                          [(match_operand:SI 2 "register_operand" "d")
1069                           (match_operand:SI 3 "register_operand" "d")])
1070          (label_ref (match_operand 1 "" ""))
1071          (pc)))]
1072   ""
1073   "*
1074 {
1075   return iq2000_output_conditional_branch (insn,
1076                                          operands,
1077                                          /*two_operands_p=*/1,
1078                                          /*float_p=*/0,
1079                                          /*inverted_p=*/0,
1080                                          get_attr_length (insn));
1081 }"
1082   [(set_attr "type"     "branch")
1083    (set_attr "mode"     "none")])
1084
1085 (define_insn "branch_equality_inverted"
1086   [(set (pc)
1087         (if_then_else
1088          (match_operator 0 "equality_op"
1089                          [(match_operand:SI 2 "register_operand" "d")
1090                           (match_operand:SI 3 "register_operand" "d")])
1091          (pc)
1092          (label_ref (match_operand 1 "" ""))))]
1093   ""
1094   "*
1095 {
1096   return iq2000_output_conditional_branch (insn,
1097                                          operands,
1098                                          /*two_operands_p=*/1,
1099                                          /*float_p=*/0,
1100                                          /*inverted_p=*/1,
1101                                          get_attr_length (insn));
1102 }"
1103   [(set_attr "type"     "branch")
1104    (set_attr "mode"     "none")])
1105
1106
1107 ;; Recognize bbi and bbin instructions.  These use two unusual template
1108 ;; patterns, %Ax and %Px.  %Ax outputs an 'i' if operand `x' is a LABEL_REF
1109 ;; otherwise it outputs an 'in'.  %Px does nothing if `x' is PC
1110 ;; and outputs the operand if `x' is a LABEL_REF.
1111
1112 (define_insn ""
1113   [(set (pc)
1114         (if_then_else
1115          (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1116                               (const_int 1)
1117                               (match_operand:SI 1 "arith_operand" "I"))
1118              (const_int 0))
1119          (match_operand 2 "pc_or_label_operand" "")
1120          (match_operand 3 "pc_or_label_operand" "")))]
1121   ""
1122   "bb%A2\\t%0(31-%1),%P2%P3"
1123   [(set_attr "length" "4")
1124    (set_attr "type" "branch")])
1125
1126 (define_insn ""
1127   [(set (pc)
1128         (if_then_else
1129          (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1130                               (const_int 1)
1131                               (match_operand:SI 1 "arith_operand" "I"))
1132              (const_int 0))
1133          (match_operand 2 "pc_or_label_operand" "")
1134          (match_operand 3 "pc_or_label_operand" "")))]
1135   ""
1136   "bb%A3\\t%0(31-%1),%P2%P3"
1137   [(set_attr "length" "4")
1138    (set_attr "type" "branch")])
1139
1140 (define_insn ""
1141   [(set (pc)
1142         (if_then_else
1143          (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1144                               (const_int 1)
1145                               (match_operand:SI 1 "arith_operand" "I"))
1146              (const_int 0))
1147          (match_operand 2 "pc_or_label_operand" "")
1148          (match_operand 3 "pc_or_label_operand" "")))]
1149   "0"
1150   "bb%A2\\t%0(31-%1),%P2%P3"
1151   [(set_attr "length" "4")
1152    (set_attr "type" "branch")])
1153
1154 (define_insn ""
1155   [(set (pc)
1156         (if_then_else
1157          (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1158                               (const_int 1)
1159                               (match_operand:SI 1 "arith_operand" "I"))
1160              (const_int 0))
1161          (match_operand 2 "pc_or_label_operand" "")
1162          (match_operand 3 "pc_or_label_operand" "")))]
1163   "0"
1164   "bb%A3\\t%0(31-%1),%P2%P3"
1165   [(set_attr "length" "4")
1166    (set_attr "type" "branch")])
1167
1168 (define_insn ""
1169   [(set (pc)
1170         (if_then_else
1171          (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1172                      (match_operand:SI 1 "power_of_2_operand" "I"))
1173               (const_int 0))
1174          (match_operand 2 "pc_or_label_operand" "")
1175          (match_operand 3 "pc_or_label_operand" "")))]
1176   ""
1177   "bb%A3\\t%0(%p1),%P2%P3"
1178   [(set_attr "length" "4")
1179    (set_attr "type" "branch")])
1180
1181 (define_insn ""
1182   [(set (pc)
1183         (if_then_else
1184          (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1185                      (match_operand:SI 1 "power_of_2_operand" "I"))
1186              (const_int 0))
1187          (match_operand 2 "pc_or_label_operand" "")
1188          (match_operand 3 "pc_or_label_operand" "")))]
1189   ""
1190   "bb%A2\\t%0(%p1),%P2%P3"
1191   [(set_attr "length" "4")
1192    (set_attr "type" "branch")])
1193 \f
1194 ;;
1195 ;;  ....................
1196 ;;
1197 ;;      SETTING A REGISTER FROM A COMPARISON
1198 ;;
1199 ;;  ....................
1200
1201 (define_expand "cstoresi4"
1202   [(set (match_operand:SI 0 "register_operand" "=d")
1203         (match_operator:SI 1 "ordered_comparison_operator"
1204          [(match_operand:SI 2 "register_operand")
1205           (match_operand:SI 3 "reg_or_const_operand")]))]
1206   ""
1207   "
1208 {
1209   gen_int_relational (GET_CODE (operands[1]), operands[0],
1210                       operands[2], operands[3], (int *)0);
1211   DONE;
1212 }")
1213
1214 (define_insn "seq_si_zero"
1215   [(set (match_operand:SI 0 "register_operand" "=d")
1216         (eq:SI (match_operand:SI 1 "register_operand" "d")
1217                (const_int 0)))]
1218   ""
1219   "sltiu\\t%0,%1,1"
1220   [(set_attr "type"     "arith")
1221    (set_attr "mode"     "SI")])
1222
1223 (define_insn "sne_si_zero"
1224   [(set (match_operand:SI 0 "register_operand" "=d")
1225         (ne:SI (match_operand:SI 1 "register_operand" "d")
1226                (const_int 0)))]
1227   ""
1228   "sltu\\t%0,%.,%1"
1229   [(set_attr "type"     "arith")
1230    (set_attr "mode"     "SI")])
1231
1232 (define_insn "sgt_si"
1233   [(set (match_operand:SI 0 "register_operand" "=d,=d")
1234         (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1235                (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1236   ""
1237   "@
1238    slt\\t%0,%z2,%1
1239    slt\\t%0,%z2,%1"
1240   [(set_attr "type"     "arith,arith")
1241    (set_attr "mode"     "SI,SI")])
1242
1243 (define_insn "slt_si"
1244   [(set (match_operand:SI 0 "register_operand" "=d,=d")
1245         (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1246                (match_operand:SI 2 "arith_operand" "d,I")))]
1247   ""
1248   "@
1249    slt\\t%0,%1,%2
1250    slti\\t%0,%1,%2"
1251   [(set_attr "type"     "arith,arith")
1252    (set_attr "mode"     "SI,SI")])
1253
1254 (define_insn "sle_si_const"
1255   [(set (match_operand:SI 0 "register_operand" "=d")
1256         (le:SI (match_operand:SI 1 "register_operand" "d")
1257                (match_operand:SI 2 "small_int" "I")))]
1258   "INTVAL (operands[2]) < 32767"
1259   "*
1260 {
1261   operands[2] = GEN_INT (INTVAL (operands[2])+1);
1262   return \"slti\\t%0,%1,%2\";
1263 }"
1264   [(set_attr "type"     "arith")
1265    (set_attr "mode"     "SI")])
1266
1267 (define_insn "sgtu_si"
1268   [(set (match_operand:SI 0 "register_operand" "=d")
1269         (gtu:SI (match_operand:SI 1 "register_operand" "d")
1270                 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1271   ""
1272   "sltu\\t%0,%z2,%1"
1273   [(set_attr "type"     "arith")
1274    (set_attr "mode"     "SI")])
1275
1276 (define_insn "sltu_si"
1277   [(set (match_operand:SI 0 "register_operand" "=d,=d")
1278         (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1279                 (match_operand:SI 2 "arith_operand" "d,I")))]
1280   ""
1281   "@
1282    sltu\\t%0,%1,%2
1283    sltiu\\t%0,%1,%2"
1284   [(set_attr "type"     "arith,arith")
1285    (set_attr "mode"     "SI,SI")])
1286
1287 (define_insn "sleu_si_const"
1288   [(set (match_operand:SI 0 "register_operand" "=d")
1289         (leu:SI (match_operand:SI 1 "register_operand" "d")
1290                 (match_operand:SI 2 "small_int" "I")))]
1291   "INTVAL (operands[2]) < 32767"
1292   "*
1293 {
1294   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1295   return \"sltiu\\t%0,%1,%2\";
1296 }"
1297   [(set_attr "type"     "arith")
1298    (set_attr "mode"     "SI")])
1299
1300 \f
1301 ;;
1302 ;;  ....................
1303 ;;
1304 ;;      UNCONDITIONAL BRANCHES
1305 ;;
1306 ;;  ....................
1307
1308 ;; Unconditional branches.
1309
1310 (define_insn "jump"
1311   [(set (pc)
1312         (label_ref (match_operand 0 "" "")))]
1313   ""
1314   "*
1315 {
1316   if (GET_CODE (operands[0]) == REG)
1317     return \"j\\t%0\";
1318   return \"j\\t%l0\";
1319   /* return \"b\\t%l0\";*/
1320 }"
1321   [(set_attr "type"     "jump")
1322    (set_attr "mode"     "none")])
1323
1324 (define_expand "indirect_jump"
1325   [(set (pc) (match_operand 0 "register_operand" "d"))]
1326   ""
1327   "
1328 {
1329   rtx dest;
1330
1331   if (operands[0])              /* eliminate unused code warnings */
1332     {
1333       dest = operands[0];
1334       if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1335         operands[0] = copy_to_mode_reg (Pmode, dest);
1336
1337       if (!(Pmode == DImode))
1338         emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1339       else
1340         internal_error (\"unimplemented functionality\");
1341
1342       DONE;
1343     }
1344 }")
1345
1346 (define_insn "indirect_jump_internal1"
1347   [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1348   "!(Pmode == DImode)"
1349   "j\\t%0"
1350   [(set_attr "type"     "jump")
1351    (set_attr "mode"     "none")])
1352
1353 (define_expand "tablejump"
1354   [(set (pc)
1355         (match_operand 0 "register_operand" "d"))
1356    (use (label_ref (match_operand 1 "" "")))]
1357   ""
1358   "
1359 {
1360   if (operands[0])              /* eliminate unused code warnings */
1361     {
1362       gcc_assert (GET_MODE (operands[0]) == Pmode);
1363
1364       if (!(Pmode == DImode))
1365         emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1366       else
1367         internal_error (\"unimplemented functionality\");
1368
1369       DONE;
1370     }
1371 }")
1372
1373 (define_insn "tablejump_internal1"
1374   [(set (pc)
1375         (match_operand:SI 0 "register_operand" "d"))
1376    (use (label_ref (match_operand 1 "" "")))]
1377   "!(Pmode == DImode)"
1378   "j\\t%0"
1379   [(set_attr "type"     "jump")
1380    (set_attr "mode"     "none")])
1381
1382 (define_expand "tablejump_internal3"
1383   [(parallel [(set (pc)
1384                    (plus:SI (match_operand:SI 0 "register_operand" "d")
1385                             (label_ref:SI (match_operand 1 "" ""))))
1386               (use (label_ref:SI (match_dup 1)))])]
1387   ""
1388   "")
1389
1390 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC.  Otherwise
1391 ;;; it is not valid.  ??? With the USE, the condition tests may not be required
1392 ;;; any longer.
1393
1394 ;;; ??? The length depends on the ABI.  It is two for o32, and one for n32.
1395 ;;; We just use the conservative number here.
1396
1397 (define_insn ""
1398   [(set (pc)
1399         (plus:SI (match_operand:SI 0 "register_operand" "d")
1400                  (label_ref:SI (match_operand 1 "" ""))))
1401    (use (label_ref:SI (match_dup 1)))]
1402   "!(Pmode == DImode) && next_active_insn (insn) != 0
1403    && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
1404    && PREV_INSN (next_active_insn (insn)) == operands[1]"
1405   "*
1406 {
1407   return \"j\\t%0\";
1408 }"
1409   [(set_attr "type"     "jump")
1410    (set_attr "mode"     "none")
1411    (set_attr "length"   "8")])
1412 \f
1413 ;;
1414 ;;  ....................
1415 ;;
1416 ;;      Function prologue/epilogue
1417 ;;
1418 ;;  ....................
1419 ;;
1420
1421 (define_expand "prologue"
1422   [(const_int 1)]
1423   ""
1424   "
1425 {
1426   if (iq2000_isa >= 0)          /* avoid unused code warnings */
1427     {
1428       iq2000_expand_prologue ();
1429       DONE;
1430     }
1431 }")
1432
1433 ;; Block any insns from being moved before this point, since the
1434 ;; profiling call to mcount can use various registers that aren't
1435 ;; saved or used to pass arguments.
1436
1437 (define_insn "blockage"
1438   [(unspec_volatile [(const_int 0)] 0)]
1439   ""
1440   ""
1441   [(set_attr "type"     "unknown")
1442    (set_attr "mode"     "none")
1443    (set_attr "length"   "0")])
1444
1445 (define_expand "epilogue"
1446   [(const_int 2)]
1447   ""
1448   "
1449 {
1450   if (iq2000_isa >= 0)            /* avoid unused code warnings */
1451     {
1452       iq2000_expand_epilogue ();
1453       DONE;
1454     }
1455 }")
1456
1457 ;; Trivial return.  Make it look like a normal return insn as that
1458 ;; allows jump optimizations to work better .
1459 (define_insn "return"
1460   [(return)]
1461   "iq2000_can_use_return_insn ()"
1462   "j\\t%%31"
1463   [(set_attr "type"     "jump")
1464    (set_attr "mode"     "none")])
1465
1466 ;; Normal return.
1467
1468 (define_insn "return_internal"
1469   [(use (match_operand 0 "pmode_register_operand" ""))
1470    (return)]
1471   ""
1472   "*
1473 {
1474   return \"j\\t%0\";
1475 }"
1476   [(set_attr "type"     "jump")
1477    (set_attr "mode"     "none")])
1478
1479 (define_insn "eh_return_internal"
1480   [(const_int 4)
1481    (return)
1482    (use (reg:SI 26))
1483    (use (reg:SI 31))]
1484   ""
1485   "j\\t%%26"
1486   [(set_attr "type"     "jump")
1487    (set_attr "mode"     "none")])
1488
1489 (define_expand "eh_return"
1490   [(use (match_operand:SI 0 "register_operand" "r"))]
1491   ""
1492   "
1493 {
1494   iq2000_expand_eh_return (operands[0]);
1495   DONE;
1496 }")
1497
1498 \f
1499 ;;
1500 ;;  ....................
1501 ;;
1502 ;;      FUNCTION CALLS
1503 ;;
1504 ;;  ....................
1505
1506 ;; calls.c now passes a third argument, make saber happy
1507
1508 (define_expand "call"
1509   [(parallel [(call (match_operand 0 "memory_operand" "m")
1510                     (match_operand 1 "" "i"))
1511               (clobber (reg:SI 31))
1512               (use (match_operand 2 "" ""))             ;; next_arg_reg
1513               (use (match_operand 3 "" ""))])]          ;; struct_value_size_rtx
1514   ""
1515   "
1516 {
1517   rtx addr;
1518
1519   if (operands[0])              /* eliminate unused code warnings */
1520     {
1521       addr = XEXP (operands[0], 0);
1522       if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1523           || ! call_insn_operand (addr, VOIDmode))
1524         XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1525
1526       /* In order to pass small structures by value in registers
1527          compatibly with the IQ2000 compiler, we need to shift the value
1528          into the high part of the register.  Function_arg has encoded
1529          a PARALLEL rtx, holding a vector of adjustments to be made
1530          as the next_arg_reg variable, so we split up the insns,
1531          and emit them separately.  */
1532
1533       if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1534         {
1535           rtvec adjust = XVEC (operands[2], 0);
1536           int num = GET_NUM_ELEM (adjust);
1537           int i;
1538
1539           for (i = 0; i < num; i++)
1540             emit_insn (RTVEC_ELT (adjust, i));
1541         }
1542
1543       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1544                                           gen_rtx_REG (SImode,
1545                                                        GP_REG_FIRST + 31)));
1546       DONE;
1547     }
1548 }")
1549
1550 (define_expand "call_internal0"
1551   [(parallel [(call (match_operand 0 "" "")
1552                     (match_operand 1 "" ""))
1553               (clobber (match_operand:SI 2 "" ""))])]
1554   ""
1555   "")
1556
1557 (define_insn "call_internal1"
1558   [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1559          (match_operand 1 "" "i"))
1560    (clobber (match_operand:SI 2 "register_operand" "=d"))]
1561   ""
1562   "*
1563 {
1564   register rtx target = operands[0];
1565
1566   if (GET_CODE (target) == CONST_INT)
1567     return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1568   else if (CONSTANT_ADDRESS_P (target))
1569     return \"jal\\t%0\";
1570   else
1571     return \"jalr\\t%2,%0\";
1572 }"
1573   [(set_attr "type"     "call")
1574    (set_attr "mode"     "none")])
1575
1576 ;; calls.c now passes a fourth argument, make saber happy
1577
1578 (define_expand "call_value"
1579   [(parallel [(set (match_operand 0 "register_operand" "=d")
1580                    (call (match_operand 1 "memory_operand" "m")
1581                          (match_operand 2 "" "i")))
1582               (clobber (reg:SI 31))
1583               (use (match_operand 3 "" ""))])]          ;; next_arg_reg
1584   ""
1585   "
1586 {
1587   rtx addr;
1588
1589   if (operands[0])              /* eliminate unused code warning */
1590     {
1591       addr = XEXP (operands[1], 0);
1592       if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1593           || ! call_insn_operand (addr, VOIDmode))
1594         XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1595
1596       /* In order to pass small structures by value in registers
1597          compatibly with the IQ2000 compiler, we need to shift the value
1598          into the high part of the register.  Function_arg has encoded
1599          a PARALLEL rtx, holding a vector of adjustments to be made
1600          as the next_arg_reg variable, so we split up the insns,
1601          and emit them separately.  */
1602
1603       if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1604         {
1605           rtvec adjust = XVEC (operands[3], 0);
1606           int num = GET_NUM_ELEM (adjust);
1607           int i;
1608
1609           for (i = 0; i < num; i++)
1610             emit_insn (RTVEC_ELT (adjust, i));
1611         }
1612
1613       if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1614         {
1615           emit_call_insn (gen_call_value_multiple_internal0
1616                           (XEXP (XVECEXP (operands[0], 0, 0), 0),
1617                            operands[1], operands[2],
1618                            XEXP (XVECEXP (operands[0], 0, 1), 0),
1619                            gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1620           DONE;
1621         }
1622
1623       /* We have a call returning a DImode structure in an FP reg.
1624          Strip off the now unnecessary PARALLEL.  */
1625       if (GET_CODE (operands[0]) == PARALLEL)
1626         operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1627
1628       emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1629                                                 gen_rtx_REG (SImode,
1630                                                              GP_REG_FIRST + 31)));
1631
1632       DONE;
1633     }
1634 }")
1635
1636 (define_expand "call_value_internal0"
1637   [(parallel [(set (match_operand 0 "" "")
1638                    (call (match_operand 1 "" "")
1639                          (match_operand 2 "" "")))
1640               (clobber (match_operand:SI 3 "" ""))])]
1641   ""
1642   "")
1643
1644 (define_insn "call_value_internal1"
1645   [(set (match_operand 0 "register_operand" "=d")
1646         (call (mem (match_operand 1 "call_insn_operand" "r"))
1647               (match_operand 2 "" "i")))
1648    (clobber (match_operand:SI 3 "register_operand" "=d"))]
1649   ""
1650   "*
1651 {
1652   register rtx target = operands[1];
1653
1654   if (GET_CODE (target) == CONST_INT)
1655     return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
1656   else if (CONSTANT_ADDRESS_P (target))
1657     return \"jal\\t%1\";
1658   else
1659     return \"jalr\\t%3,%1\";
1660 }"
1661   [(set_attr "type"     "call")
1662    (set_attr "mode"     "none")])
1663
1664 (define_expand "call_value_multiple_internal0"
1665   [(parallel [(set (match_operand 0 "" "")
1666                    (call (match_operand 1 "" "")
1667                          (match_operand 2 "" "")))
1668               (set (match_operand 3 "" "")
1669                    (call (match_dup 1)
1670                          (match_dup 2)))
1671               (clobber (match_operand:SI 4 "" ""))])]
1672   ""
1673   "")
1674
1675 ;; ??? May eventually need all 6 versions of the call patterns with multiple
1676 ;; return values.
1677
1678 (define_insn "call_value_multiple_internal1"
1679   [(set (match_operand 0 "register_operand" "=d")
1680         (call (mem (match_operand 1 "call_insn_operand" "r"))
1681               (match_operand 2 "" "i")))
1682    (set (match_operand 3 "register_operand" "=d")
1683         (call (mem (match_dup 1))
1684               (match_dup 2)))
1685   (clobber (match_operand:SI 4 "register_operand" "=d"))]
1686   ""
1687   "*
1688 {
1689   register rtx target = operands[1];
1690
1691   if (GET_CODE (target) == CONST_INT)
1692     return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
1693   else if (CONSTANT_ADDRESS_P (target))
1694     return \"jal\\t%1\";
1695   else
1696     return \"jalr\\t%4,%1\";
1697 }"
1698   [(set_attr "type"     "call")
1699    (set_attr "mode"     "none")])
1700
1701 ;; Call subroutine returning any type.
1702
1703 (define_expand "untyped_call"
1704   [(parallel [(call (match_operand 0 "" "")
1705                     (const_int 0))
1706               (match_operand 1 "" "")
1707               (match_operand 2 "" "")])]
1708   ""
1709   "
1710 {
1711   if (operands[0])              /* silence statement not reached warnings */
1712     {
1713       int i;
1714
1715       emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
1716
1717       for (i = 0; i < XVECLEN (operands[2], 0); i++)
1718         {
1719           rtx set = XVECEXP (operands[2], 0, i);
1720           emit_move_insn (SET_DEST (set), SET_SRC (set));
1721         }
1722
1723       emit_insn (gen_blockage ());
1724       DONE;
1725     }
1726 }")
1727 \f
1728 ;;
1729 ;;  ....................
1730 ;;
1731 ;;      MISC.
1732 ;;
1733 ;;  ....................
1734 ;;
1735
1736 (define_insn "nop"
1737   [(const_int 0)]
1738   ""
1739   "nop"
1740   [(set_attr "type"     "nop")
1741    (set_attr "mode"     "none")])
1742
1743 \f
1744 ;; For the rare case where we need to load an address into a register
1745 ;; that cannot be recognized by the normal movsi/addsi instructions.
1746 ;; I have no idea how many insns this can actually generate.  It should
1747 ;; be rare, so over-estimating as 10 instructions should not have any
1748 ;; real performance impact.
1749 (define_insn "leasi"
1750   [(set (match_operand:SI 0 "register_operand" "=d")
1751         (match_operand:SI 1 "address_operand" "p"))]
1752   "Pmode == SImode"
1753   "*
1754 {
1755   rtx xoperands [3];
1756
1757   xoperands[0] = operands[0];
1758   xoperands[1] = XEXP (operands[1], 0);
1759   xoperands[2] = XEXP (operands[1], 1);
1760   output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
1761   return \"\";
1762 }"
1763   [(set_attr "type"     "arith")
1764    (set_attr "mode"     "SI")
1765    (set_attr "length"   "40")])
1766
1767 (define_insn "ado16"
1768   [(set (match_operand:SI             0 "register_operand" "=r")
1769         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1770                     (match_operand:SI 2 "register_operand" "r")]
1771                 UNSPEC_ADO16))]
1772   ""
1773   "ado16\\t%0, %1, %2"
1774 )
1775
1776 (define_insn "ram"
1777   [(set (match_operand:SI             0 "register_operand" "=r")
1778               (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1779                                 (match_operand:SI 2 "const_int_operand" "I")
1780                                 (match_operand:SI 3 "const_int_operand" "I")
1781                                 (match_operand:SI 4 "const_int_operand" "I")]
1782                      UNSPEC_RAM))]
1783   ""
1784   "ram\\t%0, %1, %2, %3, %4"
1785 )
1786
1787 (define_insn "chkhdr"
1788   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
1789                 (match_operand:SI 1 "register_operand" "r")]
1790                 UNSPEC_CHKHDR)]
1791   ""
1792   "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
1793   [(set_attr "dslot"    "not_in_dslot")]
1794 )
1795
1796 (define_insn "pkrl"
1797   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1798                 (match_operand:SI 1 "register_operand" "r")]
1799                 UNSPEC_PKRL)]
1800   ""
1801   "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
1802   [(set_attr "dslot"    "not_in_dslot")]
1803 )
1804
1805 (define_insn "cfc0"
1806    [(set (match_operand:SI                0 "register_operand" "=r")
1807     (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1808                 UNSPEC_CFC0))]
1809   ""
1810   "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1811   [(set_attr "dslot"    "ok_in_dslot")]
1812 )
1813
1814 (define_insn "cfc1"
1815    [(set (match_operand:SI                0 "register_operand" "=r")
1816    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1817                 UNSPEC_CFC1))]
1818   ""
1819   "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1820   [(set_attr "dslot"    "ok_in_dslot")]
1821 )
1822
1823 (define_insn "cfc2"
1824    [(set (match_operand:SI                0 "register_operand" "=r")
1825    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1826                 UNSPEC_CFC2))]
1827   ""
1828   "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1829   [(set_attr "dslot"    "not_in_dslot")]
1830 )
1831
1832 (define_insn "cfc3"
1833    [(set (match_operand:SI                0 "register_operand" "=r")
1834    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1835                 UNSPEC_CFC3))]
1836   ""
1837   "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1838   [(set_attr "dslot"    "not_in_dslot")]
1839 )
1840
1841 (define_insn "ctc0"
1842   [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1843                 (match_operand:SI 1 "const_int_operand" "I")]
1844                 UNSPEC_CTC0)]
1845   ""
1846   "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1847   [(set_attr "dslot"    "ok_in_dslot")]
1848 )
1849
1850 (define_insn "ctc1"
1851   [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1852                 (match_operand:SI 1 "const_int_operand" "I")]
1853                 UNSPEC_CTC1)]
1854   ""
1855   "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1856   [(set_attr "dslot"    "ok_in_dslot")]
1857 )
1858
1859 (define_insn "ctc2"
1860   [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1861                 (match_operand:SI 1 "const_int_operand" "I")]
1862                 UNSPEC_CTC2)]
1863   ""
1864   "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1865   [(set_attr "dslot"    "ok_in_dslot")]
1866 )
1867
1868 (define_insn "ctc3"
1869   [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
1870                 (match_operand:SI 1 "const_int_operand" "I")]
1871                 UNSPEC_CTC3)]
1872   ""
1873   "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
1874   [(set_attr "dslot"    "ok_in_dslot")]
1875 )
1876
1877 (define_insn "mfc0"
1878    [(set (match_operand:SI                0 "register_operand" "=r")
1879    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1880                 UNSPEC_MFC0))]
1881   ""
1882   "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1883   [(set_attr "dslot"    "ok_in_dslot")]
1884 )
1885
1886 (define_insn "mfc1"
1887    [(set (match_operand:SI                0 "register_operand" "=r")
1888    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1889                 UNSPEC_MFC1))]
1890   ""
1891   "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1892   [(set_attr "dslot"    "ok_in_dslot")]
1893 )
1894
1895 (define_insn "mfc2"
1896    [(set (match_operand:SI                0 "register_operand" "=r")
1897    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1898                 UNSPEC_MFC2))]
1899   ""
1900   "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1901   [(set_attr "dslot"    "not_in_dslot")]
1902 )
1903
1904 (define_insn "mfc3"
1905    [(set (match_operand:SI                0 "register_operand" "=r")
1906    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
1907                 UNSPEC_MFC3))]
1908   ""
1909   "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
1910   [(set_attr "dslot"    "not_in_dslot")]
1911 )
1912
1913 (define_insn "mtc0"
1914   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1915                 (match_operand:SI 1 "const_int_operand" "I")]
1916                 UNSPEC_MTC0)]
1917   ""
1918   "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1919   [(set_attr "dslot"    "ok_in_dslot")]
1920 )
1921
1922 (define_insn "mtc1"
1923   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1924                 (match_operand:SI 1 "const_int_operand" "I")]
1925                 UNSPEC_MTC1)]
1926   ""
1927   "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1928   [(set_attr "dslot"    "ok_in_dslot")]
1929 )
1930
1931 (define_insn "mtc2"
1932   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1933                 (match_operand:SI 1 "const_int_operand" "I")]
1934                 UNSPEC_MTC2)]
1935   ""
1936   "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1937   [(set_attr "dslot"    "ok_in_dslot")]
1938 )
1939
1940 (define_insn "mtc3"
1941   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1942                 (match_operand:SI 1 "const_int_operand" "I")]
1943                 UNSPEC_MTC3)]
1944   ""
1945   "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
1946   [(set_attr "dslot"    "ok_in_dslot")]
1947 )
1948
1949 (define_insn "lur"
1950   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1951                 (match_operand:SI 1 "register_operand" "r")]
1952                 UNSPEC_LUR)]
1953   ""
1954   "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
1955   [(set_attr "dslot"    "not_in_dslot")]
1956 )
1957
1958 (define_insn "rb"
1959   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1960                 (match_operand:SI 1 "register_operand" "r")]
1961                 UNSPEC_RB)]
1962   ""
1963   "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
1964   [(set_attr "dslot"    "not_in_dslot")]
1965 )
1966
1967 (define_insn "rx"
1968   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1969                 (match_operand:SI 1 "register_operand" "r")]
1970                 UNSPEC_RX)]
1971   ""
1972   "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
1973   [(set_attr "dslot"    "not_in_dslot")]
1974 )
1975
1976 (define_insn "srrd"
1977   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1978                 UNSPEC_SRRD)]
1979   ""
1980   "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
1981   [(set_attr "dslot"    "not_in_dslot")]
1982 )
1983
1984 (define_insn "srwr"
1985   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1986                 (match_operand:SI 1 "register_operand" "r")]
1987                 UNSPEC_SRWR)]
1988   ""
1989   "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
1990   [(set_attr "dslot"    "not_in_dslot")]
1991 )
1992
1993 (define_insn "wb"
1994   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
1995                 (match_operand:SI 1 "register_operand" "r")]
1996                 UNSPEC_WB)]
1997   ""
1998   "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
1999   [(set_attr "dslot"    "not_in_dslot")]
2000 )
2001
2002 (define_insn "wx"
2003   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2004                 (match_operand:SI 1 "register_operand" "r")]
2005                 UNSPEC_WX)]
2006   ""
2007   "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2008   [(set_attr "dslot"    "not_in_dslot")]
2009 )
2010
2011 (define_insn "luc32"
2012   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2013                 (match_operand:SI 1 "register_operand" "r")]
2014                 UNSPEC_LUC32)]
2015   ""
2016   "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2017   [(set_attr "dslot"    "not_in_dslot")]
2018 )
2019
2020 (define_insn "luc32l"
2021   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2022                 (match_operand:SI 1 "register_operand" "r")]
2023                 UNSPEC_LUC32L)]
2024   ""
2025   "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2026   [(set_attr "dslot"    "not_in_dslot")]
2027 )
2028
2029 (define_insn "luc64"
2030   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2031                 (match_operand:SI 1 "register_operand" "r")]
2032                 UNSPEC_LUC64)]
2033   ""
2034   "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2035   [(set_attr "dslot"    "not_in_dslot")]
2036 )
2037
2038 (define_insn "luc64l"
2039   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2040                 (match_operand:SI 1 "register_operand" "r")]
2041                 UNSPEC_LUC64L)]
2042   ""
2043   "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2044   [(set_attr "dslot"    "not_in_dslot")]
2045 )
2046
2047 (define_insn "luk"
2048   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2049                 (match_operand:SI 1 "register_operand" "r")]
2050                 UNSPEC_LUK)]
2051   ""
2052   "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2053   [(set_attr "dslot"    "ok_in_dslot")]
2054 )
2055
2056 (define_insn "lulck"
2057   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2058                 UNSPEC_LULCK)]
2059   ""
2060   "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2061   [(set_attr "dslot"    "not_in_dslot")]
2062 )
2063
2064 (define_insn "lum32"
2065   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2066                 (match_operand:SI 1 "register_operand" "r")]
2067                 UNSPEC_LUM32)]
2068   ""
2069   "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2070   [(set_attr "dslot"    "not_in_dslot")]
2071 )
2072
2073 (define_insn "lum32l"
2074   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2075                 (match_operand:SI 1 "register_operand" "r")]
2076                 UNSPEC_LUM32L)]
2077   ""
2078   "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2079   [(set_attr "dslot"    "not_in_dslot")]
2080 )
2081
2082 (define_insn "lum64"
2083   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2084                 (match_operand:SI 1 "register_operand" "r")]
2085                 UNSPEC_LUM64)]
2086   ""
2087   "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2088   [(set_attr "dslot"    "not_in_dslot")]
2089 )
2090
2091 (define_insn "lum64l"
2092   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2093                 (match_operand:SI 1 "register_operand" "r")]
2094                 UNSPEC_LUM64L)]
2095   ""
2096   "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2097   [(set_attr "dslot"    "not_in_dslot")]
2098 )
2099
2100 (define_insn "lurl"
2101   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2102                 (match_operand:SI 1 "register_operand" "r")]
2103                 UNSPEC_LURL)]
2104   ""
2105   "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2106   [(set_attr "dslot"    "not_in_dslot")]
2107 )
2108
2109 (define_insn "mrgb"
2110   [(set (match_operand:SI                 0 "register_operand" "=r")
2111         (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2112                 (match_operand:SI 2 "register_operand" "r")
2113                 (match_operand:SI 3 "const_int_operand" "I")]
2114                 UNSPEC_MRGB))]
2115   ""
2116   "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2117   [(set_attr "dslot"    "ok_in_dslot")]
2118 )
2119
2120 (define_insn "srrdl"
2121   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2122                 UNSPEC_SRRDL)]
2123   ""
2124   "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2125   [(set_attr "dslot"    "not_in_dslot")]
2126 )
2127
2128 (define_insn "srulck"
2129   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2130                 UNSPEC_SRULCK)]
2131   ""
2132   "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2133   [(set_attr "dslot"    "not_in_dslot")]
2134 )
2135
2136 (define_insn "srwru"
2137   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2138                 (match_operand:SI 1 "register_operand" "r")]
2139                 UNSPEC_SRWRU)]
2140   ""
2141   "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2142   [(set_attr "dslot"    "not_in_dslot")]
2143 )
2144
2145 (define_insn "trapqfl"
2146   [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2147   ""
2148   "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2149   [(set_attr "dslot"    "not_in_dslot")]
2150 )
2151
2152 (define_insn "trapqne"
2153   [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2154   ""
2155   "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2156   [(set_attr "dslot"    "not_in_dslot")]
2157 )
2158
2159 (define_insn "traprel"
2160   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2161                 UNSPEC_TRAPREL)]
2162   ""
2163   "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2164   [(set_attr "dslot"    "not_in_dslot")]
2165 )
2166
2167 (define_insn "wbu"
2168   [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2169                 (match_operand:SI 1 "register_operand" "r")]
2170                 UNSPEC_WBU)]
2171   ""
2172   "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2173   [(set_attr "dslot"    "not_in_dslot")]
2174 )
2175
2176 (define_insn "syscall"
2177   [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2178   ""
2179   "syscall"
2180   [(set_attr "dslot"    "not_in_dslot")]
2181 )