gcc/config/loongarch/lsx.md

   1 ;; Machine Description for LARCH Loongson SX ASE
   2 ;;
   3 ;; Copyright (C) 2018-2024 Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20 ;;
  21
  22 (define_c_enum "unspec" [
  23   UNSPEC_LSX_ABSD_S
  24   UNSPEC_LSX_VABSD_U
  25   UNSPEC_LSX_VAVG_S
  26   UNSPEC_LSX_VAVG_U
  27   UNSPEC_LSX_VAVGR_S
  28   UNSPEC_LSX_VAVGR_U
  29   UNSPEC_LSX_VBITCLR
  30   UNSPEC_LSX_VBITCLRI
  31   UNSPEC_LSX_VBITREV
  32   UNSPEC_LSX_VBITREVI
  33   UNSPEC_LSX_VBITSET
  34   UNSPEC_LSX_VBITSETI
  35   UNSPEC_LSX_BRANCH_V
  36   UNSPEC_LSX_BRANCH
  37   UNSPEC_LSX_VFCLASS
  38   UNSPEC_LSX_VFCVT
  39   UNSPEC_LSX_VFCVTH
  40   UNSPEC_LSX_VFCVTL
  41   UNSPEC_LSX_VFLOGB
  42   UNSPEC_LSX_VFRECIP
  43   UNSPEC_LSX_VFRECIPE
  44   UNSPEC_LSX_VFRINT
  45   UNSPEC_LSX_VFRSQRT
  46   UNSPEC_LSX_VFRSQRTE
  47   UNSPEC_LSX_VFTINT_U
  48   UNSPEC_LSX_VSAT_S
  49   UNSPEC_LSX_VSAT_U
  50   UNSPEC_LSX_VREPLVEI
  51   UNSPEC_LSX_VSRAR
  52   UNSPEC_LSX_VSRARI
  53   UNSPEC_LSX_VSRLR
  54   UNSPEC_LSX_VSRLRI
  55   UNSPEC_LSX_VSHUF
  56   UNSPEC_LSX_VEXTW_S
  57   UNSPEC_LSX_VEXTW_U
  58   UNSPEC_LSX_VSLLWIL_S
  59   UNSPEC_LSX_VSLLWIL_U
  60   UNSPEC_LSX_VSRAN
  61   UNSPEC_LSX_VSSRAN_S
  62   UNSPEC_LSX_VSSRAN_U
  63   UNSPEC_LSX_VSRAIN
  64   UNSPEC_LSX_VSRAINS_S
  65   UNSPEC_LSX_VSRAINS_U
  66   UNSPEC_LSX_VSRARN
  67   UNSPEC_LSX_VSRLN
  68   UNSPEC_LSX_VSRLRN
  69   UNSPEC_LSX_VSSRLRN_U
  70   UNSPEC_LSX_VFRSTPI
  71   UNSPEC_LSX_VFRSTP
  72   UNSPEC_LSX_VSHUF4I
  73   UNSPEC_LSX_VBSRL_V
  74   UNSPEC_LSX_VBSLL_V
  75   UNSPEC_LSX_VEXTRINS
  76   UNSPEC_LSX_VMSKLTZ
  77   UNSPEC_LSX_VSIGNCOV
  78   UNSPEC_LSX_VFTINT_W_D
  79   UNSPEC_LSX_VFFINT_S_L
  80   UNSPEC_LSX_VFTINTRZ_W_D
  81   UNSPEC_LSX_VFTINTRP_W_D
  82   UNSPEC_LSX_VFTINTRM_W_D
  83   UNSPEC_LSX_VFTINTRNE_W_D
  84   UNSPEC_LSX_VFTINTL_L_S
  85   UNSPEC_LSX_VFFINTH_D_W
  86   UNSPEC_LSX_VFFINTL_D_W
  87   UNSPEC_LSX_VFTINTRZL_L_S
  88   UNSPEC_LSX_VFTINTRZH_L_S
  89   UNSPEC_LSX_VFTINTRPL_L_S
  90   UNSPEC_LSX_VFTINTRPH_L_S
  91   UNSPEC_LSX_VFTINTRMH_L_S
  92   UNSPEC_LSX_VFTINTRML_L_S
  93   UNSPEC_LSX_VFTINTRNEL_L_S
  94   UNSPEC_LSX_VFTINTRNEH_L_S
  95   UNSPEC_LSX_VFTINTH_L_H
  96   UNSPEC_LSX_VSSRARN_S
  97   UNSPEC_LSX_VSSRARN_U
  98   UNSPEC_LSX_VSSRLN_U
  99   UNSPEC_LSX_VSSRLN
 100   UNSPEC_LSX_VSSRLRN
 101   UNSPEC_LSX_VLDI
 102   UNSPEC_LSX_VSHUF_B
 103   UNSPEC_LSX_VLDX
 104   UNSPEC_LSX_VSTX
 105   UNSPEC_LSX_VEXTL_QU_DU
 106   UNSPEC_LSX_VSETEQZ_V
 107   UNSPEC_LSX_VADDWEV
 108   UNSPEC_LSX_VADDWEV2
 109   UNSPEC_LSX_VADDWEV3
 110   UNSPEC_LSX_VADDWOD
 111   UNSPEC_LSX_VADDWOD2
 112   UNSPEC_LSX_VADDWOD3
 113   UNSPEC_LSX_VSUBWEV
 114   UNSPEC_LSX_VSUBWEV2
 115   UNSPEC_LSX_VSUBWOD
 116   UNSPEC_LSX_VSUBWOD2
 117   UNSPEC_LSX_VMULWEV
 118   UNSPEC_LSX_VMULWEV2
 119   UNSPEC_LSX_VMULWEV3
 120   UNSPEC_LSX_VMULWOD
 121   UNSPEC_LSX_VMULWOD2
 122   UNSPEC_LSX_VMULWOD3
 123   UNSPEC_LSX_VHADDW_Q_D
 124   UNSPEC_LSX_VHADDW_QU_DU
 125   UNSPEC_LSX_VHSUBW_Q_D
 126   UNSPEC_LSX_VHSUBW_QU_DU
 127   UNSPEC_LSX_VMADDWEV
 128   UNSPEC_LSX_VMADDWEV2
 129   UNSPEC_LSX_VMADDWEV3
 130   UNSPEC_LSX_VMADDWOD
 131   UNSPEC_LSX_VMADDWOD2
 132   UNSPEC_LSX_VMADDWOD3
 133   UNSPEC_LSX_VADD_Q
 134   UNSPEC_LSX_VSUB_Q
 135   UNSPEC_LSX_VEXTH_Q_D
 136   UNSPEC_LSX_VEXTH_QU_DU
 137   UNSPEC_LSX_VMSKGEZ
 138   UNSPEC_LSX_VMSKNZ
 139   UNSPEC_LSX_VEXTL_Q_D
 140   UNSPEC_LSX_VSRLNI
 141   UNSPEC_LSX_VSRLRNI
 142   UNSPEC_LSX_VSSRLNI
 143   UNSPEC_LSX_VSSRLNI2
 144   UNSPEC_LSX_VSSRLRNI
 145   UNSPEC_LSX_VSSRLRNI2
 146   UNSPEC_LSX_VSRANI
 147   UNSPEC_LSX_VSRARNI
 148   UNSPEC_LSX_VSSRANI
 149   UNSPEC_LSX_VSSRANI2
 150   UNSPEC_LSX_VSSRARNI
 151   UNSPEC_LSX_VSSRARNI2
 152   UNSPEC_LSX_VPERMI
 153   UNSPEC_LSX_VILVL_INTERNAL
 154   UNSPEC_LSX_VREPLVEI_MIRROR
 155 ])
 156
 157 ;; This attribute gives suffix for integers in VHMODE.
 158 (define_mode_attr dlsxfmt
 159   [(V2DI "q")
 160    (V4SI "d")
 161    (V8HI "w")
 162    (V16QI "h")])
 163
 164 (define_mode_attr dlsxfmt_u
 165   [(V2DI "qu")
 166    (V4SI "du")
 167    (V8HI "wu")
 168    (V16QI "hu")])
 169
 170 (define_mode_attr d2lsxfmt
 171   [(V4SI "q")
 172    (V8HI "d")
 173    (V16QI "w")])
 174
 175 (define_mode_attr d2lsxfmt_u
 176   [(V4SI "qu")
 177    (V8HI "du")
 178    (V16QI "wu")])
 179
 180 ;; The attribute gives two double modes for vector modes.
 181 (define_mode_attr VD2MODE
 182   [(V4SI "V2DI")
 183    (V8HI "V2DI")
 184    (V16QI "V4SI")])
 185
 186 ;; All vector modes with 128 bits.
 187 (define_mode_iterator LSX      [V2DF V4SF V2DI V4SI V8HI V16QI])
 188
 189 ;; Same as LSX.  Used by vcond to iterate two modes.
 190 (define_mode_iterator LSX_2    [V2DF V4SF V2DI V4SI V8HI V16QI])
 191
 192 ;; Only used for vilvh and splitting insert_d and copy_{u,s}.d.
 193 (define_mode_iterator LSX_D    [V2DI V2DF])
 194
 195 ;; Only used for copy_{u,s}.w and vilvh.
 196 (define_mode_iterator LSX_W    [V4SI V4SF])
 197
 198 ;; As ILSX but excludes V16QI.
 199 (define_mode_iterator ILSX_DWH [V2DI V4SI V8HI])
 200
 201 ;; As LSX but excludes V16QI.
 202 (define_mode_iterator LSX_DWH  [V2DF V4SF V2DI V4SI V8HI])
 203
 204 ;; As ILSX but excludes V2DI.
 205 (define_mode_iterator ILSX_WHB [V4SI V8HI V16QI])
 206
 207 ;; Only integer modes equal or larger than a word.
 208 (define_mode_iterator ILSX_DW  [V2DI V4SI])
 209
 210 ;; Only integer modes smaller than a word.
 211 (define_mode_iterator ILSX_HB  [V8HI V16QI])
 212
 213 ;;;; Only integer modes for fixed-point madd_q/maddr_q.
 214 ;;(define_mode_iterator ILSX_WH  [V4SI V8HI])
 215
 216 ;; Only used for immediate set shuffle elements instruction.
 217 (define_mode_iterator LSX_WHB_W [V4SI V8HI V16QI V4SF])
 218
 219 ;; The attribute gives half modes for vector modes.
 220 (define_mode_attr VHMODE
 221   [(V8HI "V16QI")
 222    (V4SI "V8HI")
 223    (V2DI "V4SI")])
 224
 225 ;; The attribute gives double modes for vector modes.
 226 (define_mode_attr VDMODE
 227   [(V2DI "V2DI")
 228    (V4SI "V2DI")
 229    (V8HI "V4SI")
 230    (V16QI "V8HI")])
 231
 232 ;; The attribute gives half modes with same number of elements for vector modes.
 233 (define_mode_attr VTRUNCMODE
 234   [(V8HI "V8QI")
 235    (V4SI "V4HI")
 236    (V2DI "V2SI")])
 237
 238 ;; Double-sized Vector MODE with same elemet type. "Vector, Enlarged-MODE"
 239 (define_mode_attr VEMODE
 240   [(V4SF "V8SF")
 241    (V4SI "V8SI")
 242    (V2DI "V4DI")
 243    (V2DF "V4DF")])
 244
 245 ;; This attribute gives the mode of the result for "vpickve2gr_b, copy_u_b" etc.
 246 (define_mode_attr VRES
 247   [(V2DF "DF")
 248    (V4SF "SF")
 249    (V2DI "DI")
 250    (V4SI "SI")
 251    (V8HI "SI")
 252    (V16QI "SI")])
 253
 254 ;; Only used with LSX_D iterator.
 255 (define_mode_attr lsx_d
 256   [(V2DI "reg_or_0")
 257    (V2DF "register")])
 258
 259 ;; This attribute gives the integer vector mode with same size.
 260 (define_mode_attr mode_i
 261   [(V2DF "v2di")
 262    (V4SF "v4si")
 263    (V2DI "v2di")
 264    (V4SI "v4si")
 265    (V8HI "v8hi")
 266    (V16QI "v16qi")])
 267
 268 ;; This attribute gives suffix for LSX instructions.
 269 (define_mode_attr lsxfmt
 270   [(V2DF "d")
 271    (V4SF "w")
 272    (V2DI "d")
 273    (V4SI "w")
 274    (V8HI "h")
 275    (V16QI "b")])
 276
 277 ;; This attribute gives suffix for LSX instructions.
 278 (define_mode_attr lsxfmt_u
 279   [(V2DF "du")
 280    (V4SF "wu")
 281    (V2DI "du")
 282    (V4SI "wu")
 283    (V8HI "hu")
 284    (V16QI "bu")])
 285
 286 ;; This attribute gives suffix for integers in VHMODE.
 287 (define_mode_attr hlsxfmt
 288   [(V2DI "w")
 289    (V4SI "h")
 290    (V8HI "b")])
 291
 292 ;; This attribute gives suffix for integers in VHMODE.
 293 (define_mode_attr hlsxfmt_u
 294   [(V2DI "wu")
 295    (V4SI "hu")
 296    (V8HI "bu")])
 297
 298 ;; This attribute gives define_insn suffix for LSX instructions that need
 299 ;; distinction between integer and floating point.
 300 (define_mode_attr lsxfmt_f
 301   [(V2DF "d_f")
 302    (V4SF "w_f")
 303    (V2DI "d")
 304    (V4SI "w")
 305    (V8HI "h")
 306    (V16QI "b")])
 307
 308 (define_mode_attr flsxfmt_f
 309   [(V2DF "d_f")
 310    (V4SF "s_f")
 311    (V2DI "d")
 312    (V4SI "w")
 313    (V8HI "h")
 314    (V16QI "b")])
 315
 316 (define_mode_attr flsxfmt
 317   [(V2DF "d")
 318    (V4SF "s")
 319    (V2DI "d")
 320    (V4SI "s")])
 321
 322 (define_mode_attr flsxfrint
 323   [(V2DF "d")
 324    (V4SF "s")])
 325
 326 (define_mode_attr ilsxfmt
 327   [(V2DF "l")
 328    (V4SF "w")])
 329
 330 (define_mode_attr ilsxfmt_u
 331   [(V2DF "lu")
 332    (V4SF "wu")])
 333
 334 ;; This is used to form an immediate operand constraint using
 335 ;; "const_<indeximm>_operand".
 336 (define_mode_attr indeximm
 337   [(V2DF "0_or_1")
 338    (V4SF "0_to_3")
 339    (V2DI "0_or_1")
 340    (V4SI "0_to_3")
 341    (V8HI "uimm3")
 342    (V16QI "uimm4")])
 343
 344 ;; This attribute represents bitmask needed for vec_merge using
 345 ;; "const_<bitmask>_operand".
 346 (define_mode_attr bitmask
 347   [(V2DF "exp_2")
 348    (V4SF "exp_4")
 349    (V2DI "exp_2")
 350    (V4SI "exp_4")
 351    (V8HI "exp_8")
 352    (V16QI "exp_16")])
 353
 354 (define_expand "vec_init<mode><unitmode>"
 355   [(match_operand:LSX 0 "register_operand")
 356    (match_operand:LSX 1 "")]
 357   "ISA_HAS_LSX"
 358 {
 359   loongarch_expand_vector_init (operands[0], operands[1]);
 360   DONE;
 361 })
 362
 363 ;; vpickev pattern with implicit type conversion.
 364 (define_insn "vec_pack_trunc_<mode>"
 365   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
 366         (vec_concat:<VHMODE>
 367           (truncate:<VTRUNCMODE>
 368             (match_operand:ILSX_DWH 1 "register_operand" "f"))
 369           (truncate:<VTRUNCMODE>
 370             (match_operand:ILSX_DWH 2 "register_operand" "f"))))]
 371   "ISA_HAS_LSX"
 372   "vpickev.<hlsxfmt>\t%w0,%w2,%w1"
 373   [(set_attr "type" "simd_permute")
 374    (set_attr "mode" "<MODE>")])
 375
 376 (define_expand "vec_unpacks_hi_v4sf"
 377   [(set (match_operand:V2DF 0 "register_operand" "=f")
 378         (float_extend:V2DF
 379           (vec_select:V2SF
 380             (match_operand:V4SF 1 "register_operand" "f")
 381             (match_dup 2))))]
 382   "ISA_HAS_LSX"
 383 {
 384   operands[2] = loongarch_lsx_vec_parallel_const_half (V4SFmode,
 385       true/*high_p*/);
 386 })
 387
 388 (define_expand "vec_unpacks_lo_v4sf"
 389   [(set (match_operand:V2DF 0 "register_operand" "=f")
 390         (float_extend:V2DF
 391           (vec_select:V2SF
 392             (match_operand:V4SF 1 "register_operand" "f")
 393             (match_dup 2))))]
 394   "ISA_HAS_LSX"
 395 {
 396   operands[2] = loongarch_lsx_vec_parallel_const_half (V4SFmode,
 397       false/*high_p*/);
 398 })
 399
 400 (define_expand "vec_unpacks_hi_<mode>"
 401   [(match_operand:<VDMODE> 0 "register_operand")
 402    (match_operand:ILSX_WHB 1 "register_operand")]
 403   "ISA_HAS_LSX"
 404 {
 405   loongarch_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/);
 406   DONE;
 407 })
 408
 409 (define_expand "vec_unpacks_lo_<mode>"
 410   [(match_operand:<VDMODE> 0 "register_operand")
 411    (match_operand:ILSX_WHB 1 "register_operand")]
 412   "ISA_HAS_LSX"
 413 {
 414   loongarch_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/);
 415   DONE;
 416 })
 417
 418 (define_expand "vec_unpacku_hi_<mode>"
 419   [(match_operand:<VDMODE> 0 "register_operand")
 420    (match_operand:ILSX_WHB 1 "register_operand")]
 421   "ISA_HAS_LSX"
 422 {
 423   loongarch_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/);
 424   DONE;
 425 })
 426
 427 (define_expand "vec_unpacku_lo_<mode>"
 428   [(match_operand:<VDMODE> 0 "register_operand")
 429    (match_operand:ILSX_WHB 1 "register_operand")]
 430   "ISA_HAS_LSX"
 431 {
 432   loongarch_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/);
 433   DONE;
 434 })
 435
 436 (define_expand "vec_extract<mode><unitmode>"
 437   [(match_operand:<UNITMODE> 0 "register_operand")
 438    (match_operand:ILSX 1 "register_operand")
 439    (match_operand 2 "const_<indeximm>_operand")]
 440   "ISA_HAS_LSX"
 441 {
 442   if (<UNITMODE>mode == QImode || <UNITMODE>mode == HImode)
 443     {
 444       rtx dest1 = gen_reg_rtx (SImode);
 445       emit_insn (gen_lsx_vpickve2gr_<lsxfmt> (dest1, operands[1], operands[2]));
 446       emit_move_insn (operands[0],
 447                       gen_lowpart (<UNITMODE>mode, dest1));
 448     }
 449   else
 450     emit_insn (gen_lsx_vpickve2gr_<lsxfmt> (operands[0], operands[1], operands[2]));
 451   DONE;
 452 })
 453
 454 (define_expand "vec_extract<mode><unitmode>"
 455   [(match_operand:<UNITMODE> 0 "register_operand")
 456    (match_operand:FLSX 1 "register_operand")
 457    (match_operand 2 "const_<indeximm>_operand")]
 458   "ISA_HAS_LSX"
 459 {
 460   rtx temp;
 461   HOST_WIDE_INT val = INTVAL (operands[2]);
 462
 463   if (val == 0)
 464     temp = operands[1];
 465   else
 466     {
 467       rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode));
 468       temp = gen_reg_rtx (<MODE>mode);
 469       emit_insn (gen_lsx_vbsrl_<lsxfmt_f> (temp, operands[1], n));
 470     }
 471   emit_insn (gen_lsx_vec_extract_<lsxfmt_f> (operands[0], temp));
 472   DONE;
 473 })
 474
 475 (define_insn_and_split "lsx_vec_extract_<lsxfmt_f>"
 476   [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
 477         (vec_select:<UNITMODE>
 478           (match_operand:FLSX 1 "register_operand" "f")
 479           (parallel [(const_int 0)])))]
 480   "ISA_HAS_LSX"
 481   "#"
 482   "&& reload_completed"
 483   [(set (match_dup 0) (match_dup 1))]
 484 {
 485   operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
 486 }
 487   [(set_attr "move_type" "fmove")
 488    (set_attr "mode" "<UNITMODE>")])
 489
 490 (define_expand "vec_set<mode>"
 491   [(match_operand:ILSX 0 "register_operand")
 492    (match_operand:<UNITMODE> 1 "reg_or_0_operand")
 493    (match_operand 2 "const_<indeximm>_operand")]
 494   "ISA_HAS_LSX"
 495 {
 496   rtx index = GEN_INT (1 << INTVAL (operands[2]));
 497   emit_insn (gen_lsx_vinsgr2vr_<lsxfmt> (operands[0], operands[1],
 498                                          operands[0], index));
 499   DONE;
 500 })
 501
 502 (define_expand "vec_set<mode>"
 503   [(match_operand:FLSX 0 "register_operand")
 504    (match_operand:<UNITMODE> 1 "register_operand")
 505    (match_operand 2 "const_<indeximm>_operand")]
 506   "ISA_HAS_LSX"
 507 {
 508   rtx index = GEN_INT (1 << INTVAL (operands[2]));
 509   emit_insn (gen_lsx_vextrins_<lsxfmt_f>_scalar (operands[0], operands[1],
 510                                                  operands[0], index));
 511   DONE;
 512 })
 513
 514 (define_expand "vec_cmp<mode><mode_i>"
 515   [(set (match_operand:<VIMODE> 0 "register_operand")
 516         (match_operator 1 ""
 517           [(match_operand:LSX 2 "register_operand")
 518            (match_operand:LSX 3 "register_operand")]))]
 519   "ISA_HAS_LSX"
 520 {
 521   bool ok = loongarch_expand_vec_cmp (operands);
 522   gcc_assert (ok);
 523   DONE;
 524 })
 525
 526 (define_expand "vec_cmpu<ILSX:mode><mode_i>"
 527   [(set (match_operand:<VIMODE> 0 "register_operand")
 528         (match_operator 1 ""
 529           [(match_operand:ILSX 2 "register_operand")
 530            (match_operand:ILSX 3 "register_operand")]))]
 531   "ISA_HAS_LSX"
 532 {
 533   bool ok = loongarch_expand_vec_cmp (operands);
 534   gcc_assert (ok);
 535   DONE;
 536 })
 537
 538 (define_expand "vcondu<LSX:mode><ILSX:mode>"
 539   [(match_operand:LSX 0 "register_operand")
 540    (match_operand:LSX 1 "reg_or_m1_operand")
 541    (match_operand:LSX 2 "reg_or_0_operand")
 542    (match_operator 3 ""
 543      [(match_operand:ILSX 4 "register_operand")
 544       (match_operand:ILSX 5 "register_operand")])]
 545   "ISA_HAS_LSX
 546    && (GET_MODE_NUNITS (<LSX:MODE>mode) == GET_MODE_NUNITS (<ILSX:MODE>mode))"
 547 {
 548   loongarch_expand_vec_cond_expr (<LSX:MODE>mode, <LSX:VIMODE>mode, operands);
 549   DONE;
 550 })
 551
 552 (define_expand "vcond<LSX:mode><LSX_2:mode>"
 553   [(match_operand:LSX 0 "register_operand")
 554    (match_operand:LSX 1 "reg_or_m1_operand")
 555    (match_operand:LSX 2 "reg_or_0_operand")
 556    (match_operator 3 ""
 557      [(match_operand:LSX_2 4 "register_operand")
 558       (match_operand:LSX_2 5 "register_operand")])]
 559   "ISA_HAS_LSX
 560    && (GET_MODE_NUNITS (<LSX:MODE>mode) == GET_MODE_NUNITS (<LSX_2:MODE>mode))"
 561 {
 562   loongarch_expand_vec_cond_expr (<LSX:MODE>mode, <LSX:VIMODE>mode, operands);
 563   DONE;
 564 })
 565
 566 (define_expand "vcond_mask_<mode><mode_i>"
 567   [(match_operand:LSX 0 "register_operand")
 568    (match_operand:LSX 1 "reg_or_m1_operand")
 569    (match_operand:LSX 2 "reg_or_0_operand")
 570    (match_operand:<VIMODE> 3 "register_operand")]
 571   "ISA_HAS_LSX"
 572 {
 573   loongarch_expand_vec_cond_mask_expr (<MODE>mode,
 574                                        <VIMODE>mode, operands);
 575   DONE;
 576 })
 577
 578 (define_insn "lsx_vinsgr2vr_<lsxfmt>"
 579   [(set (match_operand:ILSX 0 "register_operand" "=f")
 580         (vec_merge:ILSX
 581           (vec_duplicate:ILSX
 582             (match_operand:<UNITMODE> 1 "reg_or_0_operand" "rJ"))
 583           (match_operand:ILSX 2 "register_operand" "0")
 584           (match_operand 3 "const_<bitmask>_operand" "")))]
 585   "ISA_HAS_LSX"
 586 {
 587   if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
 588     return "#";
 589   else
 590     return "vinsgr2vr.<lsxfmt>\t%w0,%z1,%y3";
 591 }
 592   [(set_attr "type" "simd_insert")
 593    (set_attr "mode" "<MODE>")])
 594
 595 (define_split
 596   [(set (match_operand:LSX_D 0 "register_operand")
 597         (vec_merge:LSX_D
 598           (vec_duplicate:LSX_D
 599             (match_operand:<UNITMODE> 1 "<LSX_D:lsx_d>_operand"))
 600           (match_operand:LSX_D 2 "register_operand")
 601           (match_operand 3 "const_<bitmask>_operand")))]
 602   "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
 603   [(const_int 0)]
 604 {
 605   loongarch_split_lsx_insert_d (operands[0], operands[2], operands[3], operands[1]);
 606   DONE;
 607 })
 608
 609 (define_insn "lsx_vextrins_<lsxfmt_f>_internal"
 610   [(set (match_operand:LSX 0 "register_operand" "=f")
 611         (vec_merge:LSX
 612           (vec_duplicate:LSX
 613             (vec_select:<UNITMODE>
 614               (match_operand:LSX 1 "register_operand" "f")
 615               (parallel [(const_int 0)])))
 616           (match_operand:LSX 2 "register_operand" "0")
 617           (match_operand 3 "const_<bitmask>_operand" "")))]
 618   "ISA_HAS_LSX"
 619   "vextrins.<lsxfmt>\t%w0,%w1,%y3<<4"
 620   [(set_attr "type" "simd_insert")
 621    (set_attr "mode" "<MODE>")])
 622
 623 ;; Operand 3 is a scalar.
 624 (define_insn "lsx_vextrins_<lsxfmt_f>_scalar"
 625   [(set (match_operand:FLSX 0 "register_operand" "=f")
 626         (vec_merge:FLSX
 627           (vec_duplicate:FLSX
 628             (match_operand:<UNITMODE> 1 "register_operand" "f"))
 629           (match_operand:FLSX 2 "register_operand" "0")
 630           (match_operand 3 "const_<bitmask>_operand" "")))]
 631   "ISA_HAS_LSX"
 632   "vextrins.<lsxfmt>\t%w0,%w1,%y3<<4"
 633   [(set_attr "type" "simd_insert")
 634    (set_attr "mode" "<MODE>")])
 635
 636 (define_insn "lsx_vpickve2gr_<lsxfmt><u>"
 637   [(set (match_operand:<VRES> 0 "register_operand" "=r")
 638         (any_extend:<VRES>
 639           (vec_select:<UNITMODE>
 640             (match_operand:ILSX_HB 1 "register_operand" "f")
 641             (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
 642   "ISA_HAS_LSX"
 643   "vpickve2gr.<lsxfmt><u>\t%0,%w1,%2"
 644   [(set_attr "type" "simd_copy")
 645    (set_attr "mode" "<MODE>")])
 646
 647 (define_insn "lsx_vpickve2gr_<lsxfmt_f><u>"
 648   [(set (match_operand:<UNITMODE> 0 "register_operand" "=r")
 649         (any_extend:<UNITMODE>
 650           (vec_select:<UNITMODE>
 651             (match_operand:LSX_W 1 "register_operand" "f")
 652             (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
 653   "ISA_HAS_LSX"
 654   "vpickve2gr.<lsxfmt><u>\t%0,%w1,%2"
 655   [(set_attr "type" "simd_copy")
 656    (set_attr "mode" "<MODE>")])
 657
 658 (define_insn_and_split "lsx_vpickve2gr_du"
 659   [(set (match_operand:DI 0 "register_operand" "=r")
 660         (vec_select:DI
 661           (match_operand:V2DI 1 "register_operand" "f")
 662           (parallel [(match_operand 2 "const_0_or_1_operand" "")])))]
 663   "ISA_HAS_LSX"
 664 {
 665   if (TARGET_64BIT)
 666     return "vpickve2gr.du\t%0,%w1,%2";
 667   else
 668     return "#";
 669 }
 670   "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
 671   [(const_int 0)]
 672 {
 673   loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2],
 674                               gen_lsx_vpickve2gr_wu);
 675   DONE;
 676 }
 677   [(set_attr "type" "simd_copy")
 678    (set_attr "mode" "V2DI")])
 679
 680 (define_insn_and_split "lsx_vpickve2gr_<lsxfmt_f>"
 681   [(set (match_operand:<UNITMODE> 0 "register_operand" "=r")
 682         (vec_select:<UNITMODE>
 683           (match_operand:LSX_D 1 "register_operand" "f")
 684           (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
 685   "ISA_HAS_LSX"
 686 {
 687   if (TARGET_64BIT)
 688     return "vpickve2gr.<lsxfmt>\t%0,%w1,%2";
 689   else
 690     return "#";
 691 }
 692   "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
 693   [(const_int 0)]
 694 {
 695   loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2],
 696                               gen_lsx_vpickve2gr_w);
 697   DONE;
 698 }
 699   [(set_attr "type" "simd_copy")
 700    (set_attr "mode" "<MODE>")])
 701
 702
 703 (define_expand "abs<mode>2"
 704   [(match_operand:ILSX 0 "register_operand" "=f")
 705    (abs:ILSX (match_operand:ILSX 1 "register_operand" "f"))]
 706   "ISA_HAS_LSX"
 707 {
 708   if (ISA_HAS_LSX)
 709   {
 710     emit_insn (gen_vabs<mode>2 (operands[0], operands[1]));
 711     DONE;
 712   }
 713   else
 714   {
 715     rtx reg = gen_reg_rtx (<MODE>mode);
 716     emit_move_insn (reg, CONST0_RTX (<MODE>mode));
 717     emit_insn (gen_lsx_vadda_<lsxfmt> (operands[0], operands[1], reg));
 718     DONE;
 719   }
 720 })
 721
 722 (define_expand "neg<mode>2"
 723   [(set (match_operand:ILSX 0 "register_operand")
 724         (neg:ILSX (match_operand:ILSX 1 "register_operand")))]
 725   "ISA_HAS_LSX"
 726 {
 727   emit_insn (gen_vneg<mode>2 (operands[0], operands[1]));
 728   DONE;
 729 })
 730
 731 (define_expand "neg<mode>2"
 732   [(set (match_operand:FLSX 0 "register_operand")
 733         (neg:FLSX (match_operand:FLSX 1 "register_operand")))]
 734   "ISA_HAS_LSX"
 735 {
 736   rtx reg = gen_reg_rtx (<MODE>mode);
 737   emit_move_insn (reg, CONST0_RTX (<MODE>mode));
 738   emit_insn (gen_sub<mode>3 (operands[0], reg, operands[1]));
 739   DONE;
 740 })
 741
 742 (define_expand "lsx_vrepli<mode>"
 743   [(match_operand:ILSX 0 "register_operand")
 744    (match_operand 1 "const_imm10_operand")]
 745   "ISA_HAS_LSX"
 746 {
 747   if (<MODE>mode == V16QImode)
 748     operands[1] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]),
 749                                                <UNITMODE>mode));
 750   emit_move_insn (operands[0],
 751                   loongarch_gen_const_int_vector (<MODE>mode, INTVAL (operands[1])));
 752   DONE;
 753 })
 754
 755 (define_expand "vec_perm<mode>"
 756  [(match_operand:LSX 0 "register_operand")
 757   (match_operand:LSX 1 "register_operand")
 758   (match_operand:LSX 2 "register_operand")
 759   (match_operand:<VIMODE> 3 "register_operand")]
 760   "ISA_HAS_LSX"
 761 {
 762   loongarch_expand_vec_perm (operands[0], operands[1],
 763                              operands[2], operands[3]);
 764   DONE;
 765 })
 766
 767 (define_insn "lsx_vshuf_<lsxfmt_f>"
 768   [(set (match_operand:LSX_DWH 0 "register_operand" "=f")
 769         (unspec:LSX_DWH [(match_operand:LSX_DWH 1 "register_operand" "0")
 770                          (match_operand:LSX_DWH 2 "register_operand" "f")
 771                          (match_operand:LSX_DWH 3 "register_operand" "f")]
 772                         UNSPEC_LSX_VSHUF))]
 773   "ISA_HAS_LSX"
 774   "vshuf.<lsxfmt>\t%w0,%w2,%w3"
 775   [(set_attr "type" "simd_sld")
 776    (set_attr "mode" "<MODE>")])
 777
 778 (define_expand "mov<mode>"
 779   [(set (match_operand:LSX 0)
 780         (match_operand:LSX 1))]
 781   "ISA_HAS_LSX"
 782 {
 783   if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
 784     DONE;
 785 })
 786
 787 (define_expand "movmisalign<mode>"
 788   [(set (match_operand:LSX 0)
 789         (match_operand:LSX 1))]
 790   "ISA_HAS_LSX"
 791 {
 792   if (loongarch_legitimize_move (<MODE>mode, operands[0], operands[1]))
 793     DONE;
 794 })
 795
 796 (define_insn "mov<mode>_lsx"
 797   [(set (match_operand:LSX 0 "nonimmediate_operand" "=f,f,R,*r,*f,*r")
 798         (match_operand:LSX 1 "move_operand" "fYGYI,R,f,*f,*r,*r"))]
 799   "ISA_HAS_LSX"
 800 { return loongarch_output_move (operands[0], operands[1]); }
 801   [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert,simd_copy")
 802    (set_attr "mode" "<MODE>")])
 803
 804 (define_split
 805   [(set (match_operand:LSX 0 "nonimmediate_operand")
 806         (match_operand:LSX 1 "move_operand"))]
 807   "reload_completed && ISA_HAS_LSX
 808    && loongarch_split_move_p (operands[0], operands[1])"
 809   [(const_int 0)]
 810 {
 811   loongarch_split_move (operands[0], operands[1]);
 812   DONE;
 813 })
 814
 815 ;; Offset load
 816 (define_expand "lsx_ld_<lsxfmt_f>"
 817   [(match_operand:LSX 0 "register_operand")
 818    (match_operand 1 "pmode_register_operand")
 819    (match_operand 2 "aq10<lsxfmt>_operand")]
 820   "ISA_HAS_LSX"
 821 {
 822   rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
 823                             INTVAL (operands[2]));
 824   loongarch_emit_move (operands[0], gen_rtx_MEM (<MODE>mode, addr));
 825   DONE;
 826 })
 827
 828 ;; Offset store
 829 (define_expand "lsx_st_<lsxfmt_f>"
 830   [(match_operand:LSX 0 "register_operand")
 831    (match_operand 1 "pmode_register_operand")
 832    (match_operand 2 "aq10<lsxfmt>_operand")]
 833   "ISA_HAS_LSX"
 834 {
 835   rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
 836                             INTVAL (operands[2]));
 837   loongarch_emit_move (gen_rtx_MEM (<MODE>mode, addr), operands[0]);
 838   DONE;
 839 })
 840
 841 ;; Integer operations
 842 (define_insn "add<mode>3"
 843   [(set (match_operand:ILSX 0 "register_operand" "=f,f,f")
 844         (plus:ILSX
 845           (match_operand:ILSX 1 "register_operand" "f,f,f")
 846           (match_operand:ILSX 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))]
 847   "ISA_HAS_LSX"
 848 {
 849   switch (which_alternative)
 850     {
 851     case 0:
 852       return "vadd.<lsxfmt>\t%w0,%w1,%w2";
 853     case 1:
 854       {
 855         HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (operands[2], 0));
 856
 857         operands[2] = GEN_INT (-val);
 858         return "vsubi.<lsxfmt_u>\t%w0,%w1,%d2";
 859       }
 860     case 2:
 861       return "vaddi.<lsxfmt_u>\t%w0,%w1,%E2";
 862     default:
 863       gcc_unreachable ();
 864     }
 865 }
 866   [(set_attr "alu_type" "simd_add")
 867    (set_attr "type" "simd_int_arith")
 868    (set_attr "mode" "<MODE>")])
 869
 870 (define_insn "sub<mode>3"
 871   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
 872         (minus:ILSX
 873           (match_operand:ILSX 1 "register_operand" "f,f")
 874           (match_operand:ILSX 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
 875   "ISA_HAS_LSX"
 876   "@
 877    vsub.<lsxfmt>\t%w0,%w1,%w2
 878    vsubi.<lsxfmt_u>\t%w0,%w1,%E2"
 879   [(set_attr "alu_type" "simd_add")
 880    (set_attr "type" "simd_int_arith")
 881    (set_attr "mode" "<MODE>")])
 882
 883 (define_insn "mul<mode>3"
 884   [(set (match_operand:ILSX 0 "register_operand" "=f")
 885         (mult:ILSX (match_operand:ILSX 1 "register_operand" "f")
 886                    (match_operand:ILSX 2 "register_operand" "f")))]
 887   "ISA_HAS_LSX"
 888   "vmul.<lsxfmt>\t%w0,%w1,%w2"
 889   [(set_attr "type" "simd_mul")
 890    (set_attr "mode" "<MODE>")])
 891
 892 (define_insn "lsx_vmadd_<lsxfmt>"
 893   [(set (match_operand:ILSX 0 "register_operand" "=f")
 894         (plus:ILSX (mult:ILSX (match_operand:ILSX 2 "register_operand" "f")
 895                               (match_operand:ILSX 3 "register_operand" "f"))
 896                    (match_operand:ILSX 1 "register_operand" "0")))]
 897   "ISA_HAS_LSX"
 898   "vmadd.<lsxfmt>\t%w0,%w2,%w3"
 899   [(set_attr "type" "simd_mul")
 900    (set_attr "mode" "<MODE>")])
 901
 902 (define_insn "lsx_vmsub_<lsxfmt>"
 903   [(set (match_operand:ILSX 0 "register_operand" "=f")
 904         (minus:ILSX (match_operand:ILSX 1 "register_operand" "0")
 905                     (mult:ILSX (match_operand:ILSX 2 "register_operand" "f")
 906                                (match_operand:ILSX 3 "register_operand" "f"))))]
 907   "ISA_HAS_LSX"
 908   "vmsub.<lsxfmt>\t%w0,%w2,%w3"
 909   [(set_attr "type" "simd_mul")
 910    (set_attr "mode" "<MODE>")])
 911
 912 (define_insn "div<mode>3"
 913   [(set (match_operand:ILSX 0 "register_operand" "=f")
 914         (div:ILSX (match_operand:ILSX 1 "register_operand" "f")
 915                   (match_operand:ILSX 2 "register_operand" "f")))]
 916   "ISA_HAS_LSX"
 917 { return loongarch_lsx_output_division ("vdiv.<lsxfmt>\t%w0,%w1,%w2", operands); }
 918   [(set_attr "type" "simd_div")
 919    (set_attr "mode" "<MODE>")])
 920
 921 (define_insn "udiv<mode>3"
 922   [(set (match_operand:ILSX 0 "register_operand" "=f")
 923         (udiv:ILSX (match_operand:ILSX 1 "register_operand" "f")
 924                    (match_operand:ILSX 2 "register_operand" "f")))]
 925   "ISA_HAS_LSX"
 926 { return loongarch_lsx_output_division ("vdiv.<lsxfmt_u>\t%w0,%w1,%w2", operands); }
 927   [(set_attr "type" "simd_div")
 928    (set_attr "mode" "<MODE>")])
 929
 930 (define_insn "mod<mode>3"
 931   [(set (match_operand:ILSX 0 "register_operand" "=f")
 932         (mod:ILSX (match_operand:ILSX 1 "register_operand" "f")
 933                   (match_operand:ILSX 2 "register_operand" "f")))]
 934   "ISA_HAS_LSX"
 935 { return loongarch_lsx_output_division ("vmod.<lsxfmt>\t%w0,%w1,%w2", operands); }
 936   [(set_attr "type" "simd_div")
 937    (set_attr "mode" "<MODE>")])
 938
 939 (define_insn "umod<mode>3"
 940   [(set (match_operand:ILSX 0 "register_operand" "=f")
 941         (umod:ILSX (match_operand:ILSX 1 "register_operand" "f")
 942                    (match_operand:ILSX 2 "register_operand" "f")))]
 943   "ISA_HAS_LSX"
 944 { return loongarch_lsx_output_division ("vmod.<lsxfmt_u>\t%w0,%w1,%w2", operands); }
 945   [(set_attr "type" "simd_div")
 946    (set_attr "mode" "<MODE>")])
 947
 948 (define_insn "xor<mode>3"
 949   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
 950         (xor:LSX
 951           (match_operand:LSX 1 "register_operand" "f,f,f")
 952           (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
 953   "ISA_HAS_LSX"
 954   "@
 955    vxor.v\t%w0,%w1,%w2
 956    vbitrevi.%v0\t%w0,%w1,%V2
 957    vxori.b\t%w0,%w1,%B2"
 958   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
 959    (set_attr "mode" "<MODE>")])
 960
 961 (define_insn "ior<mode>3"
 962   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
 963         (ior:LSX
 964           (match_operand:LSX 1 "register_operand" "f,f,f")
 965           (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
 966   "ISA_HAS_LSX"
 967   "@
 968    vor.v\t%w0,%w1,%w2
 969    vbitseti.%v0\t%w0,%w1,%V2
 970    vori.b\t%w0,%w1,%B2"
 971   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
 972    (set_attr "mode" "<MODE>")])
 973
 974 (define_insn "and<mode>3"
 975   [(set (match_operand:LSX 0 "register_operand" "=f,f,f")
 976         (and:LSX
 977           (match_operand:LSX 1 "register_operand" "f,f,f")
 978           (match_operand:LSX 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
 979   "ISA_HAS_LSX"
 980 {
 981   switch (which_alternative)
 982     {
 983     case 0:
 984       return "vand.v\t%w0,%w1,%w2";
 985     case 1:
 986       {
 987         rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
 988         unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
 989         operands[2] = loongarch_gen_const_int_vector (<MODE>mode, val & (-val));
 990         return "vbitclri.%v0\t%w0,%w1,%V2";
 991       }
 992     case 2:
 993       return "vandi.b\t%w0,%w1,%B2";
 994     default:
 995       gcc_unreachable ();
 996     }
 997 }
 998   [(set_attr "type" "simd_logic,simd_bit,simd_logic")
 999    (set_attr "mode" "<MODE>")])
1000
1001 (define_insn "one_cmpl<mode>2"
1002   [(set (match_operand:ILSX 0 "register_operand" "=f")
1003         (not:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
1004   "ISA_HAS_LSX"
1005   "vnor.v\t%w0,%w1,%w1"
1006   [(set_attr "type" "simd_logic")
1007    (set_attr "mode" "TI")])
1008
1009 (define_insn "vlshr<mode>3"
1010   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1011         (lshiftrt:ILSX
1012           (match_operand:ILSX 1 "register_operand" "f,f")
1013           (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
1014   "ISA_HAS_LSX"
1015   "@
1016    vsrl.<lsxfmt>\t%w0,%w1,%w2
1017    vsrli.<lsxfmt>\t%w0,%w1,%E2"
1018   [(set_attr "type" "simd_shift")
1019    (set_attr "mode" "<MODE>")])
1020
1021 (define_insn "vashr<mode>3"
1022   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1023         (ashiftrt:ILSX
1024           (match_operand:ILSX 1 "register_operand" "f,f")
1025           (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
1026   "ISA_HAS_LSX"
1027   "@
1028    vsra.<lsxfmt>\t%w0,%w1,%w2
1029    vsrai.<lsxfmt>\t%w0,%w1,%E2"
1030   [(set_attr "type" "simd_shift")
1031    (set_attr "mode" "<MODE>")])
1032
1033 (define_insn "vashl<mode>3"
1034   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1035         (ashift:ILSX
1036           (match_operand:ILSX 1 "register_operand" "f,f")
1037           (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
1038   "ISA_HAS_LSX"
1039   "@
1040    vsll.<lsxfmt>\t%w0,%w1,%w2
1041    vslli.<lsxfmt>\t%w0,%w1,%E2"
1042   [(set_attr "type" "simd_shift")
1043    (set_attr "mode" "<MODE>")])
1044
1045 ;; Floating-point operations
1046 (define_insn "add<mode>3"
1047   [(set (match_operand:FLSX 0 "register_operand" "=f")
1048         (plus:FLSX (match_operand:FLSX 1 "register_operand" "f")
1049                    (match_operand:FLSX 2 "register_operand" "f")))]
1050   "ISA_HAS_LSX"
1051   "vfadd.<flsxfmt>\t%w0,%w1,%w2"
1052   [(set_attr "type" "simd_fadd")
1053    (set_attr "mode" "<MODE>")])
1054
1055 (define_insn "sub<mode>3"
1056   [(set (match_operand:FLSX 0 "register_operand" "=f")
1057         (minus:FLSX (match_operand:FLSX 1 "register_operand" "f")
1058                     (match_operand:FLSX 2 "register_operand" "f")))]
1059   "ISA_HAS_LSX"
1060   "vfsub.<flsxfmt>\t%w0,%w1,%w2"
1061   [(set_attr "type" "simd_fadd")
1062    (set_attr "mode" "<MODE>")])
1063
1064 (define_insn "mul<mode>3"
1065   [(set (match_operand:FLSX 0 "register_operand" "=f")
1066         (mult:FLSX (match_operand:FLSX 1 "register_operand" "f")
1067                    (match_operand:FLSX 2 "register_operand" "f")))]
1068   "ISA_HAS_LSX"
1069   "vfmul.<flsxfmt>\t%w0,%w1,%w2"
1070   [(set_attr "type" "simd_fmul")
1071    (set_attr "mode" "<MODE>")])
1072
1073 (define_expand "div<mode>3"
1074   [(set (match_operand:FLSX 0 "register_operand")
1075     (div:FLSX (match_operand:FLSX 1 "reg_or_vecotr_1_operand")
1076               (match_operand:FLSX 2 "register_operand")))]
1077   "ISA_HAS_LSX"
1078 {
1079   if (<MODE>mode == V4SFmode
1080     && TARGET_RECIP_VEC_DIV
1081     && optimize_insn_for_speed_p ()
1082     && flag_finite_math_only && !flag_trapping_math
1083     && flag_unsafe_math_optimizations)
1084   {
1085     loongarch_emit_swdivsf (operands[0], operands[1],
1086         operands[2], V4SFmode);
1087     DONE;
1088   }
1089 })
1090
1091 (define_insn "*div<mode>3"
1092   [(set (match_operand:FLSX 0 "register_operand" "=f")
1093         (div:FLSX (match_operand:FLSX 1 "register_operand" "f")
1094                   (match_operand:FLSX 2 "register_operand" "f")))]
1095   "ISA_HAS_LSX"
1096   "vfdiv.<flsxfmt>\t%w0,%w1,%w2"
1097   [(set_attr "type" "simd_fdiv")
1098    (set_attr "mode" "<MODE>")])
1099
1100 (define_insn "fma<mode>4"
1101   [(set (match_operand:FLSX 0 "register_operand" "=f")
1102         (fma:FLSX (match_operand:FLSX 1 "register_operand" "f")
1103                   (match_operand:FLSX 2 "register_operand" "f")
1104                   (match_operand:FLSX 3 "register_operand" "f")))]
1105   "ISA_HAS_LSX"
1106   "vfmadd.<flsxfmt>\t%w0,%w1,%w2,%w3"
1107   [(set_attr "type" "simd_fmadd")
1108    (set_attr "mode" "<MODE>")])
1109
1110 (define_insn "fnma<mode>4"
1111   [(set (match_operand:FLSX 0 "register_operand" "=f")
1112         (fma:FLSX (neg:FLSX (match_operand:FLSX 1 "register_operand" "f"))
1113                   (match_operand:FLSX 2 "register_operand" "f")
1114                   (match_operand:FLSX 3 "register_operand" "0")))]
1115   "ISA_HAS_LSX"
1116   "vfnmsub.<flsxfmt>\t%w0,%w1,%w2,%w0"
1117   [(set_attr "type" "simd_fmadd")
1118    (set_attr "mode" "<MODE>")])
1119
1120 (define_expand "sqrt<mode>2"
1121   [(set (match_operand:FLSX 0 "register_operand")
1122     (sqrt:FLSX (match_operand:FLSX 1 "register_operand")))]
1123   "ISA_HAS_LSX"
1124 {
1125   if (<MODE>mode == V4SFmode
1126       && TARGET_RECIP_VEC_SQRT
1127       && flag_unsafe_math_optimizations
1128       && optimize_insn_for_speed_p ()
1129       && flag_finite_math_only && !flag_trapping_math)
1130     {
1131       loongarch_emit_swrsqrtsf (operands[0], operands[1], V4SFmode, 0);
1132       DONE;
1133     }
1134 })
1135
1136 (define_insn "*sqrt<mode>2"
1137   [(set (match_operand:FLSX 0 "register_operand" "=f")
1138         (sqrt:FLSX (match_operand:FLSX 1 "register_operand" "f")))]
1139   "ISA_HAS_LSX"
1140   "vfsqrt.<flsxfmt>\t%w0,%w1"
1141   [(set_attr "type" "simd_fdiv")
1142    (set_attr "mode" "<MODE>")])
1143
1144 ;; Built-in functions
1145 (define_insn "lsx_vadda_<lsxfmt>"
1146   [(set (match_operand:ILSX 0 "register_operand" "=f")
1147         (plus:ILSX (abs:ILSX (match_operand:ILSX 1 "register_operand" "f"))
1148                    (abs:ILSX (match_operand:ILSX 2 "register_operand" "f"))))]
1149   "ISA_HAS_LSX"
1150   "vadda.<lsxfmt>\t%w0,%w1,%w2"
1151   [(set_attr "type" "simd_int_arith")
1152    (set_attr "mode" "<MODE>")])
1153
1154 (define_insn "ssadd<mode>3"
1155   [(set (match_operand:ILSX 0 "register_operand" "=f")
1156         (ss_plus:ILSX (match_operand:ILSX 1 "register_operand" "f")
1157                       (match_operand:ILSX 2 "register_operand" "f")))]
1158   "ISA_HAS_LSX"
1159   "vsadd.<lsxfmt>\t%w0,%w1,%w2"
1160   [(set_attr "type" "simd_int_arith")
1161    (set_attr "mode" "<MODE>")])
1162
1163 (define_insn "usadd<mode>3"
1164   [(set (match_operand:ILSX 0 "register_operand" "=f")
1165         (us_plus:ILSX (match_operand:ILSX 1 "register_operand" "f")
1166                       (match_operand:ILSX 2 "register_operand" "f")))]
1167   "ISA_HAS_LSX"
1168   "vsadd.<lsxfmt_u>\t%w0,%w1,%w2"
1169   [(set_attr "type" "simd_int_arith")
1170    (set_attr "mode" "<MODE>")])
1171
1172 (define_insn "lsx_vabsd_s_<lsxfmt>"
1173   [(set (match_operand:ILSX 0 "register_operand" "=f")
1174         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1175                       (match_operand:ILSX 2 "register_operand" "f")]
1176                      UNSPEC_LSX_ABSD_S))]
1177   "ISA_HAS_LSX"
1178   "vabsd.<lsxfmt>\t%w0,%w1,%w2"
1179   [(set_attr "type" "simd_int_arith")
1180    (set_attr "mode" "<MODE>")])
1181
1182 (define_insn "lsx_vabsd_u_<lsxfmt_u>"
1183   [(set (match_operand:ILSX 0 "register_operand" "=f")
1184         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1185                       (match_operand:ILSX 2 "register_operand" "f")]
1186                      UNSPEC_LSX_VABSD_U))]
1187   "ISA_HAS_LSX"
1188   "vabsd.<lsxfmt_u>\t%w0,%w1,%w2"
1189   [(set_attr "type" "simd_int_arith")
1190    (set_attr "mode" "<MODE>")])
1191
1192 (define_insn "lsx_vavg_s_<lsxfmt>"
1193   [(set (match_operand:ILSX 0 "register_operand" "=f")
1194         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1195                       (match_operand:ILSX 2 "register_operand" "f")]
1196                      UNSPEC_LSX_VAVG_S))]
1197   "ISA_HAS_LSX"
1198   "vavg.<lsxfmt>\t%w0,%w1,%w2"
1199   [(set_attr "type" "simd_int_arith")
1200    (set_attr "mode" "<MODE>")])
1201
1202 (define_insn "lsx_vavg_u_<lsxfmt_u>"
1203   [(set (match_operand:ILSX 0 "register_operand" "=f")
1204         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1205                       (match_operand:ILSX 2 "register_operand" "f")]
1206                      UNSPEC_LSX_VAVG_U))]
1207   "ISA_HAS_LSX"
1208   "vavg.<lsxfmt_u>\t%w0,%w1,%w2"
1209   [(set_attr "type" "simd_int_arith")
1210    (set_attr "mode" "<MODE>")])
1211
1212 (define_insn "lsx_vavgr_s_<lsxfmt>"
1213   [(set (match_operand:ILSX 0 "register_operand" "=f")
1214         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1215                       (match_operand:ILSX 2 "register_operand" "f")]
1216                      UNSPEC_LSX_VAVGR_S))]
1217   "ISA_HAS_LSX"
1218   "vavgr.<lsxfmt>\t%w0,%w1,%w2"
1219   [(set_attr "type" "simd_int_arith")
1220    (set_attr "mode" "<MODE>")])
1221
1222 (define_insn "lsx_vavgr_u_<lsxfmt_u>"
1223   [(set (match_operand:ILSX 0 "register_operand" "=f")
1224         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1225                       (match_operand:ILSX 2 "register_operand" "f")]
1226                      UNSPEC_LSX_VAVGR_U))]
1227   "ISA_HAS_LSX"
1228   "vavgr.<lsxfmt_u>\t%w0,%w1,%w2"
1229   [(set_attr "type" "simd_int_arith")
1230    (set_attr "mode" "<MODE>")])
1231
1232 (define_insn "lsx_vbitclr_<lsxfmt>"
1233   [(set (match_operand:ILSX 0 "register_operand" "=f")
1234         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1235                       (match_operand:ILSX 2 "register_operand" "f")]
1236                      UNSPEC_LSX_VBITCLR))]
1237   "ISA_HAS_LSX"
1238   "vbitclr.<lsxfmt>\t%w0,%w1,%w2"
1239   [(set_attr "type" "simd_bit")
1240    (set_attr "mode" "<MODE>")])
1241
1242 (define_insn "lsx_vbitclri_<lsxfmt>"
1243   [(set (match_operand:ILSX 0 "register_operand" "=f")
1244         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1245                       (match_operand 2 "const_<bitimm>_operand" "")]
1246                      UNSPEC_LSX_VBITCLRI))]
1247   "ISA_HAS_LSX"
1248   "vbitclri.<lsxfmt>\t%w0,%w1,%2"
1249   [(set_attr "type" "simd_bit")
1250    (set_attr "mode" "<MODE>")])
1251
1252 (define_insn "lsx_vbitrev_<lsxfmt>"
1253   [(set (match_operand:ILSX 0 "register_operand" "=f")
1254         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1255                       (match_operand:ILSX 2 "register_operand" "f")]
1256                      UNSPEC_LSX_VBITREV))]
1257   "ISA_HAS_LSX"
1258   "vbitrev.<lsxfmt>\t%w0,%w1,%w2"
1259   [(set_attr "type" "simd_bit")
1260    (set_attr "mode" "<MODE>")])
1261
1262 (define_insn "lsx_vbitrevi_<lsxfmt>"
1263   [(set (match_operand:ILSX 0 "register_operand" "=f")
1264         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1265                        (match_operand 2 "const_lsx_branch_operand" "")]
1266                      UNSPEC_LSX_VBITREVI))]
1267   "ISA_HAS_LSX"
1268   "vbitrevi.<lsxfmt>\t%w0,%w1,%2"
1269   [(set_attr "type" "simd_bit")
1270    (set_attr "mode" "<MODE>")])
1271
1272 (define_insn "lsx_vbitsel_<lsxfmt>"
1273   [(set (match_operand:ILSX 0 "register_operand" "=f")
1274         (ior:ILSX (and:ILSX (not:ILSX
1275                               (match_operand:ILSX 3 "register_operand" "f"))
1276                             (match_operand:ILSX 1 "register_operand" "f"))
1277                   (and:ILSX (match_dup 3)
1278                             (match_operand:ILSX 2 "register_operand" "f"))))]
1279   "ISA_HAS_LSX"
1280   "vbitsel.v\t%w0,%w1,%w2,%w3"
1281   [(set_attr "type" "simd_bitmov")
1282    (set_attr "mode" "<MODE>")])
1283
1284 (define_insn "lsx_vbitseli_b"
1285   [(set (match_operand:V16QI 0 "register_operand" "=f")
1286         (ior:V16QI (and:V16QI (not:V16QI
1287                                 (match_operand:V16QI 1 "register_operand" "0"))
1288                               (match_operand:V16QI 2 "register_operand" "f"))
1289                    (and:V16QI (match_dup 1)
1290                               (match_operand:V16QI 3 "const_vector_same_val_operand" "Urv8"))))]
1291   "ISA_HAS_LSX"
1292   "vbitseli.b\t%w0,%w2,%B3"
1293   [(set_attr "type" "simd_bitmov")
1294    (set_attr "mode" "V16QI")])
1295
1296 (define_insn "lsx_vbitset_<lsxfmt>"
1297   [(set (match_operand:ILSX 0 "register_operand" "=f")
1298         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1299                       (match_operand:ILSX 2 "register_operand" "f")]
1300                      UNSPEC_LSX_VBITSET))]
1301   "ISA_HAS_LSX"
1302   "vbitset.<lsxfmt>\t%w0,%w1,%w2"
1303   [(set_attr "type" "simd_bit")
1304    (set_attr "mode" "<MODE>")])
1305
1306 (define_insn "lsx_vbitseti_<lsxfmt>"
1307   [(set (match_operand:ILSX 0 "register_operand" "=f")
1308         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
1309                       (match_operand 2 "const_<bitimm>_operand" "")]
1310                      UNSPEC_LSX_VBITSETI))]
1311   "ISA_HAS_LSX"
1312   "vbitseti.<lsxfmt>\t%w0,%w1,%2"
1313   [(set_attr "type" "simd_bit")
1314    (set_attr "mode" "<MODE>")])
1315
1316 (define_code_iterator ICC [eq le leu lt ltu])
1317
1318 (define_code_attr icc
1319   [(eq  "eq")
1320    (le  "le")
1321    (leu "le")
1322    (lt  "lt")
1323    (ltu "lt")])
1324
1325 (define_code_attr icci
1326   [(eq  "eqi")
1327    (le  "lei")
1328    (leu "lei")
1329    (lt  "lti")
1330    (ltu "lti")])
1331
1332 (define_code_attr cmpi
1333   [(eq   "s")
1334    (le   "s")
1335    (leu  "u")
1336    (lt   "s")
1337    (ltu  "u")])
1338
1339 (define_code_attr cmpi_1
1340   [(eq   "")
1341    (le   "")
1342    (leu  "u")
1343    (lt   "")
1344    (ltu  "u")])
1345
1346 (define_insn "lsx_vs<ICC:icc>_<ILSX:lsxfmt><ICC:cmpi_1>"
1347   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1348         (ICC:ILSX
1349           (match_operand:ILSX 1 "register_operand" "f,f")
1350           (match_operand:ILSX 2 "reg_or_vector_same_<ICC:cmpi>imm5_operand" "f,U<ICC:cmpi>v5")))]
1351   "ISA_HAS_LSX"
1352   "@
1353    vs<ICC:icc>.<ILSX:lsxfmt><ICC:cmpi_1>\t%w0,%w1,%w2
1354    vs<ICC:icci>.<ILSX:lsxfmt><ICC:cmpi_1>\t%w0,%w1,%E2"
1355   [(set_attr "type" "simd_int_arith")
1356    (set_attr "mode" "<MODE>")])
1357
1358 (define_insn "lsx_vfclass_<flsxfmt>"
1359   [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1360         (unspec:<VIMODE> [(match_operand:FLSX 1 "register_operand" "f")]
1361                          UNSPEC_LSX_VFCLASS))]
1362   "ISA_HAS_LSX"
1363   "vfclass.<flsxfmt>\t%w0,%w1"
1364   [(set_attr "type" "simd_fclass")
1365    (set_attr "mode" "<MODE>")])
1366
1367 (define_mode_attr fint
1368   [(V4SF "v4si")
1369    (V2DF "v2di")])
1370
1371 (define_mode_attr FINTCNV
1372   [(V4SF "I2S")
1373    (V2DF "I2D")])
1374
1375 (define_mode_attr FINTCNV_2
1376   [(V4SF "S2I")
1377    (V2DF "D2I")])
1378
1379 (define_insn "float<fint><FLSX:mode>2"
1380   [(set (match_operand:FLSX 0 "register_operand" "=f")
1381         (float:FLSX (match_operand:<VIMODE> 1 "register_operand" "f")))]
1382   "ISA_HAS_LSX"
1383   "vffint.<flsxfmt>.<ilsxfmt>\t%w0,%w1"
1384   [(set_attr "type" "simd_fcvt")
1385    (set_attr "cnv_mode" "<FINTCNV>")
1386    (set_attr "mode" "<MODE>")])
1387
1388 (define_insn "floatuns<fint><FLSX:mode>2"
1389   [(set (match_operand:FLSX 0 "register_operand" "=f")
1390         (unsigned_float:FLSX
1391           (match_operand:<VIMODE> 1 "register_operand" "f")))]
1392   "ISA_HAS_LSX"
1393   "vffint.<flsxfmt>.<ilsxfmt_u>\t%w0,%w1"
1394   [(set_attr "type" "simd_fcvt")
1395    (set_attr "cnv_mode" "<FINTCNV>")
1396    (set_attr "mode" "<MODE>")])
1397
1398 (define_mode_attr FFQ
1399   [(V4SF "V8HI")
1400    (V2DF "V4SI")])
1401
1402 (define_insn "lsx_vreplgr2vr_<lsxfmt_f>"
1403   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1404         (vec_duplicate:ILSX
1405           (match_operand:<UNITMODE> 1 "reg_or_0_operand" "r,J")))]
1406   "ISA_HAS_LSX"
1407 {
1408   if (which_alternative == 1)
1409     return "vldi.<lsxfmt>\t%w0,0";
1410
1411   if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
1412     return "#";
1413   else
1414     return "vreplgr2vr.<lsxfmt>\t%w0,%z1";
1415 }
1416   [(set_attr "type" "simd_fill")
1417    (set_attr "mode" "<MODE>")])
1418
1419 (define_split
1420   [(set (match_operand:LSX_D 0 "register_operand")
1421         (vec_duplicate:LSX_D
1422           (match_operand:<UNITMODE> 1 "register_operand")))]
1423   "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
1424   [(const_int 0)]
1425 {
1426   loongarch_split_lsx_fill_d (operands[0], operands[1]);
1427   DONE;
1428 })
1429
1430 (define_insn "logb<mode>2"
1431   [(set (match_operand:FLSX 0 "register_operand" "=f")
1432         (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
1433                      UNSPEC_LSX_VFLOGB))]
1434   "ISA_HAS_LSX"
1435   "vflogb.<flsxfmt>\t%w0,%w1"
1436   [(set_attr "type" "simd_flog2")
1437    (set_attr "mode" "<MODE>")])
1438
1439 ;; Only for loongarch_expand_vector_init in loongarch.cc.
1440 ;; Merge two scalar floating-point op1 and op2 into a LSX op0.
1441 (define_insn "lsx_vilvl_<lsxfmt_f>_internal"
1442   [(set (match_operand:FLSX 0 "register_operand" "=f")
1443         (unspec:FLSX [(match_operand:<UNITMODE> 1 "register_operand" "f")
1444                       (match_operand:<UNITMODE> 2 "register_operand" "f")]
1445                      UNSPEC_LSX_VILVL_INTERNAL))]
1446   "ISA_HAS_LSX"
1447   "vilvl.<lsxfmt>\t%w0,%w2,%w1"
1448   [(set_attr "type" "simd_permute")
1449    (set_attr "mode" "<MODE>")])
1450
1451 (define_insn "smax<mode>3"
1452   [(set (match_operand:FLSX 0 "register_operand" "=f")
1453         (smax:FLSX (match_operand:FLSX 1 "register_operand" "f")
1454                    (match_operand:FLSX 2 "register_operand" "f")))]
1455   "ISA_HAS_LSX"
1456   "vfmax.<flsxfmt>\t%w0,%w1,%w2"
1457   [(set_attr "type" "simd_fminmax")
1458    (set_attr "mode" "<MODE>")])
1459
1460 (define_insn "lsx_vfmaxa_<flsxfmt>"
1461   [(set (match_operand:FLSX 0 "register_operand" "=f")
1462         (if_then_else:FLSX
1463            (gt (abs:FLSX (match_operand:FLSX 1 "register_operand" "f"))
1464                (abs:FLSX (match_operand:FLSX 2 "register_operand" "f")))
1465            (match_dup 1)
1466            (match_dup 2)))]
1467   "ISA_HAS_LSX"
1468   "vfmaxa.<flsxfmt>\t%w0,%w1,%w2"
1469   [(set_attr "type" "simd_fminmax")
1470    (set_attr "mode" "<MODE>")])
1471
1472 (define_insn "smin<mode>3"
1473   [(set (match_operand:FLSX 0 "register_operand" "=f")
1474         (smin:FLSX (match_operand:FLSX 1 "register_operand" "f")
1475                    (match_operand:FLSX 2 "register_operand" "f")))]
1476   "ISA_HAS_LSX"
1477   "vfmin.<flsxfmt>\t%w0,%w1,%w2"
1478   [(set_attr "type" "simd_fminmax")
1479    (set_attr "mode" "<MODE>")])
1480
1481 (define_insn "lsx_vfmina_<flsxfmt>"
1482   [(set (match_operand:FLSX 0 "register_operand" "=f")
1483         (if_then_else:FLSX
1484            (lt (abs:FLSX (match_operand:FLSX 1 "register_operand" "f"))
1485                (abs:FLSX (match_operand:FLSX 2 "register_operand" "f")))
1486            (match_dup 1)
1487            (match_dup 2)))]
1488   "ISA_HAS_LSX"
1489   "vfmina.<flsxfmt>\t%w0,%w1,%w2"
1490   [(set_attr "type" "simd_fminmax")
1491    (set_attr "mode" "<MODE>")])
1492
1493 (define_insn "recip<mode>3"
1494   [(set (match_operand:FLSX 0 "register_operand" "=f")
1495        (div:FLSX (match_operand:FLSX 1 "const_vector_1_operand" "")
1496                  (match_operand:FLSX 2 "register_operand" "f")))]
1497   "ISA_HAS_LSX"
1498   "vfrecip.<flsxfmt>\t%w0,%w2"
1499   [(set_attr "type" "simd_fdiv")
1500    (set_attr "mode" "<MODE>")])
1501
1502 ;; Approximate Reciprocal Instructions.
1503
1504 (define_insn "lsx_vfrecipe_<flsxfmt>"
1505   [(set (match_operand:FLSX 0 "register_operand" "=f")
1506     (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
1507                  UNSPEC_LSX_VFRECIPE))]
1508   "ISA_HAS_LSX && TARGET_FRECIPE"
1509   "vfrecipe.<flsxfmt>\t%w0,%w1"
1510   [(set_attr "type" "simd_fdiv")
1511    (set_attr "mode" "<MODE>")])
1512
1513 (define_expand "rsqrt<mode>2"
1514   [(set (match_operand:FLSX 0 "register_operand" "=f")
1515     (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
1516              UNSPEC_LSX_VFRSQRT))]
1517  "ISA_HAS_LSX"
1518 {
1519  if (<MODE>mode == V4SFmode && TARGET_RECIP_VEC_RSQRT)
1520    {
1521      loongarch_emit_swrsqrtsf (operands[0], operands[1], V4SFmode, 1);
1522      DONE;
1523    }
1524 })
1525
1526 (define_insn "*rsqrt<mode>2"
1527   [(set (match_operand:FLSX 0 "register_operand" "=f")
1528     (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
1529                  UNSPEC_LSX_VFRSQRT))]
1530   "ISA_HAS_LSX"
1531   "vfrsqrt.<flsxfmt>\t%w0,%w1"
1532   [(set_attr "type" "simd_fdiv")
1533    (set_attr "mode" "<MODE>")])
1534
1535 ;; Approximate Reciprocal Square Root Instructions.
1536
1537 (define_insn "lsx_vfrsqrte_<flsxfmt>"
1538   [(set (match_operand:FLSX 0 "register_operand" "=f")
1539     (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
1540                  UNSPEC_LSX_VFRSQRTE))]
1541   "ISA_HAS_LSX && TARGET_FRECIPE"
1542   "vfrsqrte.<flsxfmt>\t%w0,%w1"
1543   [(set_attr "type" "simd_fdiv")
1544    (set_attr "mode" "<MODE>")])
1545
1546 (define_insn "lsx_vftint_u_<ilsxfmt_u>_<flsxfmt>"
1547   [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1548         (unspec:<VIMODE> [(match_operand:FLSX 1 "register_operand" "f")]
1549                          UNSPEC_LSX_VFTINT_U))]
1550   "ISA_HAS_LSX"
1551   "vftint.<ilsxfmt_u>.<flsxfmt>\t%w0,%w1"
1552   [(set_attr "type" "simd_fcvt")
1553    (set_attr "cnv_mode" "<FINTCNV_2>")
1554    (set_attr "mode" "<MODE>")])
1555
1556 (define_insn "fixuns_trunc<FLSX:mode><mode_i>2"
1557   [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1558         (unsigned_fix:<VIMODE> (match_operand:FLSX 1 "register_operand" "f")))]
1559   "ISA_HAS_LSX"
1560   "vftintrz.<ilsxfmt_u>.<flsxfmt>\t%w0,%w1"
1561   [(set_attr "type" "simd_fcvt")
1562    (set_attr "cnv_mode" "<FINTCNV_2>")
1563    (set_attr "mode" "<MODE>")])
1564
1565 (define_insn "lsx_vh<optab>w_h<u>_b<u>"
1566   [(set (match_operand:V8HI 0 "register_operand" "=f")
1567         (addsub:V8HI
1568           (any_extend:V8HI
1569             (vec_select:V8QI
1570               (match_operand:V16QI 1 "register_operand" "f")
1571               (parallel [(const_int 1) (const_int 3)
1572                          (const_int 5) (const_int 7)
1573                          (const_int 9) (const_int 11)
1574                          (const_int 13) (const_int 15)])))
1575           (any_extend:V8HI
1576             (vec_select:V8QI
1577               (match_operand:V16QI 2 "register_operand" "f")
1578               (parallel [(const_int 0) (const_int 2)
1579                          (const_int 4) (const_int 6)
1580                          (const_int 8) (const_int 10)
1581                          (const_int 12) (const_int 14)])))))]
1582   "ISA_HAS_LSX"
1583   "vh<optab>w.h<u>.b<u>\t%w0,%w1,%w2"
1584   [(set_attr "type" "simd_int_arith")
1585    (set_attr "mode" "V8HI")])
1586
1587 (define_insn "lsx_vh<optab>w_w<u>_h<u>"
1588   [(set (match_operand:V4SI 0 "register_operand" "=f")
1589         (addsub:V4SI
1590           (any_extend:V4SI
1591             (vec_select:V4HI
1592               (match_operand:V8HI 1 "register_operand" "f")
1593               (parallel [(const_int 1) (const_int 3)
1594                          (const_int 5) (const_int 7)])))
1595           (any_extend:V4SI
1596             (vec_select:V4HI
1597               (match_operand:V8HI 2 "register_operand" "f")
1598               (parallel [(const_int 0) (const_int 2)
1599                          (const_int 4) (const_int 6)])))))]
1600   "ISA_HAS_LSX"
1601   "vh<optab>w.w<u>.h<u>\t%w0,%w1,%w2"
1602   [(set_attr "type" "simd_int_arith")
1603    (set_attr "mode" "V4SI")])
1604
1605 (define_insn "lsx_vh<optab>w_d<u>_w<u>"
1606   [(set (match_operand:V2DI 0 "register_operand" "=f")
1607         (addsub:V2DI
1608           (any_extend:V2DI
1609             (vec_select:V2SI
1610               (match_operand:V4SI 1 "register_operand" "f")
1611               (parallel [(const_int 1) (const_int 3)])))
1612           (any_extend:V2DI
1613             (vec_select:V2SI
1614               (match_operand:V4SI 2 "register_operand" "f")
1615               (parallel [(const_int 0) (const_int 2)])))))]
1616   "ISA_HAS_LSX"
1617   "vh<optab>w.d<u>.w<u>\t%w0,%w1,%w2"
1618   [(set_attr "type" "simd_int_arith")
1619    (set_attr "mode" "V2DI")])
1620
1621 (define_insn "lsx_vpackev_b"
1622   [(set (match_operand:V16QI 0 "register_operand" "=f")
1623         (vec_select:V16QI
1624           (vec_concat:V32QI
1625             (match_operand:V16QI 1 "register_operand" "f")
1626             (match_operand:V16QI 2 "register_operand" "f"))
1627           (parallel [(const_int 0)  (const_int 16)
1628                      (const_int 2)  (const_int 18)
1629                      (const_int 4)  (const_int 20)
1630                      (const_int 6)  (const_int 22)
1631                      (const_int 8)  (const_int 24)
1632                      (const_int 10) (const_int 26)
1633                      (const_int 12) (const_int 28)
1634                      (const_int 14) (const_int 30)])))]
1635   "ISA_HAS_LSX"
1636   "vpackev.b\t%w0,%w2,%w1"
1637   [(set_attr "type" "simd_permute")
1638    (set_attr "mode" "V16QI")])
1639
1640 (define_insn "lsx_vpackev_h"
1641   [(set (match_operand:V8HI 0 "register_operand" "=f")
1642         (vec_select:V8HI
1643           (vec_concat:V16HI
1644             (match_operand:V8HI 1 "register_operand" "f")
1645             (match_operand:V8HI 2 "register_operand" "f"))
1646           (parallel [(const_int 0) (const_int 8)
1647                      (const_int 2) (const_int 10)
1648                      (const_int 4) (const_int 12)
1649                      (const_int 6) (const_int 14)])))]
1650   "ISA_HAS_LSX"
1651   "vpackev.h\t%w0,%w2,%w1"
1652   [(set_attr "type" "simd_permute")
1653    (set_attr "mode" "V8HI")])
1654
1655 (define_insn "lsx_vpackev_w"
1656   [(set (match_operand:V4SI 0 "register_operand" "=f")
1657         (vec_select:V4SI
1658           (vec_concat:V8SI
1659             (match_operand:V4SI 1 "register_operand" "f")
1660             (match_operand:V4SI 2 "register_operand" "f"))
1661           (parallel [(const_int 0) (const_int 4)
1662                      (const_int 2) (const_int 6)])))]
1663   "ISA_HAS_LSX"
1664   "vpackev.w\t%w0,%w2,%w1"
1665   [(set_attr "type" "simd_permute")
1666    (set_attr "mode" "V4SI")])
1667
1668 (define_insn "lsx_vpackev_w_f"
1669   [(set (match_operand:V4SF 0 "register_operand" "=f")
1670         (vec_select:V4SF
1671           (vec_concat:V8SF
1672             (match_operand:V4SF 1 "register_operand" "f")
1673             (match_operand:V4SF 2 "register_operand" "f"))
1674           (parallel [(const_int 0) (const_int 4)
1675                      (const_int 2) (const_int 6)])))]
1676   "ISA_HAS_LSX"
1677   "vpackev.w\t%w0,%w2,%w1"
1678   [(set_attr "type" "simd_permute")
1679    (set_attr "mode" "V4SF")])
1680
1681 (define_insn "lsx_vilvh_b"
1682   [(set (match_operand:V16QI 0 "register_operand" "=f")
1683         (vec_select:V16QI
1684           (vec_concat:V32QI
1685             (match_operand:V16QI 1 "register_operand" "f")
1686             (match_operand:V16QI 2 "register_operand" "f"))
1687           (parallel [(const_int 8)  (const_int 24)
1688                      (const_int 9)  (const_int 25)
1689                      (const_int 10) (const_int 26)
1690                      (const_int 11) (const_int 27)
1691                      (const_int 12) (const_int 28)
1692                      (const_int 13) (const_int 29)
1693                      (const_int 14) (const_int 30)
1694                      (const_int 15) (const_int 31)])))]
1695   "ISA_HAS_LSX"
1696   "vilvh.b\t%w0,%w2,%w1"
1697   [(set_attr "type" "simd_permute")
1698    (set_attr "mode" "V16QI")])
1699
1700 (define_insn "lsx_vilvh_h"
1701   [(set (match_operand:V8HI 0 "register_operand" "=f")
1702         (vec_select:V8HI
1703           (vec_concat:V16HI
1704             (match_operand:V8HI 1 "register_operand" "f")
1705             (match_operand:V8HI 2 "register_operand" "f"))
1706           (parallel [(const_int 4) (const_int 12)
1707                      (const_int 5) (const_int 13)
1708                      (const_int 6) (const_int 14)
1709                      (const_int 7) (const_int 15)])))]
1710   "ISA_HAS_LSX"
1711   "vilvh.h\t%w0,%w2,%w1"
1712   [(set_attr "type" "simd_permute")
1713    (set_attr "mode" "V8HI")])
1714
1715 (define_mode_attr vilvh_suffix
1716   [(V4SI "") (V4SF "_f")
1717    (V2DI "") (V2DF "_f")])
1718
1719 (define_insn "lsx_vilvh_w<vilvh_suffix>"
1720   [(set (match_operand:LSX_W 0 "register_operand" "=f")
1721         (vec_select:LSX_W
1722           (vec_concat:<VEMODE>
1723             (match_operand:LSX_W 1 "register_operand" "f")
1724             (match_operand:LSX_W 2 "register_operand" "f"))
1725           (parallel [(const_int 2) (const_int 6)
1726                      (const_int 3) (const_int 7)])))]
1727   "ISA_HAS_LSX"
1728   "vilvh.w\t%w0,%w2,%w1"
1729   [(set_attr "type" "simd_permute")
1730    (set_attr "mode" "<MODE>")])
1731
1732 (define_insn "lsx_vilvh_d<vilvh_suffix>"
1733   [(set (match_operand:LSX_D 0 "register_operand" "=f")
1734         (vec_select:LSX_D
1735           (vec_concat:<VEMODE>
1736             (match_operand:LSX_D 1 "register_operand" "f")
1737             (match_operand:LSX_D 2 "register_operand" "f"))
1738           (parallel [(const_int 1) (const_int 3)])))]
1739   "ISA_HAS_LSX"
1740   "vilvh.d\t%w0,%w2,%w1"
1741   [(set_attr "type" "simd_permute")
1742    (set_attr "mode" "<MODE>")])
1743
1744 (define_insn "lsx_vpackod_b"
1745   [(set (match_operand:V16QI 0 "register_operand" "=f")
1746         (vec_select:V16QI
1747           (vec_concat:V32QI
1748             (match_operand:V16QI 1 "register_operand" "f")
1749             (match_operand:V16QI 2 "register_operand" "f"))
1750           (parallel [(const_int 1)  (const_int 17)
1751                      (const_int 3)  (const_int 19)
1752                      (const_int 5)  (const_int 21)
1753                      (const_int 7)  (const_int 23)
1754                      (const_int 9)  (const_int 25)
1755                      (const_int 11) (const_int 27)
1756                      (const_int 13) (const_int 29)
1757                      (const_int 15) (const_int 31)])))]
1758   "ISA_HAS_LSX"
1759   "vpackod.b\t%w0,%w2,%w1"
1760   [(set_attr "type" "simd_permute")
1761    (set_attr "mode" "V16QI")])
1762
1763 (define_insn "lsx_vpackod_h"
1764   [(set (match_operand:V8HI 0 "register_operand" "=f")
1765         (vec_select:V8HI
1766           (vec_concat:V16HI
1767             (match_operand:V8HI 1 "register_operand" "f")
1768             (match_operand:V8HI 2 "register_operand" "f"))
1769           (parallel [(const_int 1) (const_int 9)
1770                      (const_int 3) (const_int 11)
1771                      (const_int 5) (const_int 13)
1772                      (const_int 7) (const_int 15)])))]
1773   "ISA_HAS_LSX"
1774   "vpackod.h\t%w0,%w2,%w1"
1775   [(set_attr "type" "simd_permute")
1776    (set_attr "mode" "V8HI")])
1777
1778 (define_insn "lsx_vpackod_w"
1779   [(set (match_operand:V4SI 0 "register_operand" "=f")
1780         (vec_select:V4SI
1781           (vec_concat:V8SI
1782             (match_operand:V4SI 1 "register_operand" "f")
1783             (match_operand:V4SI 2 "register_operand" "f"))
1784           (parallel [(const_int 1) (const_int 5)
1785                      (const_int 3) (const_int 7)])))]
1786   "ISA_HAS_LSX"
1787   "vpackod.w\t%w0,%w2,%w1"
1788   [(set_attr "type" "simd_permute")
1789    (set_attr "mode" "V4SI")])
1790
1791 (define_insn "lsx_vpackod_w_f"
1792   [(set (match_operand:V4SF 0 "register_operand" "=f")
1793         (vec_select:V4SF
1794           (vec_concat:V8SF
1795             (match_operand:V4SF 1 "register_operand" "f")
1796             (match_operand:V4SF 2 "register_operand" "f"))
1797           (parallel [(const_int 1) (const_int 5)
1798                      (const_int 3) (const_int 7)])))]
1799   "ISA_HAS_LSX"
1800   "vpackod.w\t%w0,%w2,%w1"
1801   [(set_attr "type" "simd_permute")
1802    (set_attr "mode" "V4SF")])
1803
1804 (define_insn "lsx_vilvl_b"
1805   [(set (match_operand:V16QI 0 "register_operand" "=f")
1806         (vec_select:V16QI
1807           (vec_concat:V32QI
1808             (match_operand:V16QI 1 "register_operand" "f")
1809             (match_operand:V16QI 2 "register_operand" "f"))
1810           (parallel [(const_int 0) (const_int 16)
1811                      (const_int 1) (const_int 17)
1812                      (const_int 2) (const_int 18)
1813                      (const_int 3) (const_int 19)
1814                      (const_int 4) (const_int 20)
1815                      (const_int 5) (const_int 21)
1816                      (const_int 6) (const_int 22)
1817                      (const_int 7) (const_int 23)])))]
1818   "ISA_HAS_LSX"
1819   "vilvl.b\t%w0,%w2,%w1"
1820   [(set_attr "type" "simd_permute")
1821    (set_attr "mode" "V16QI")])
1822
1823 (define_insn "lsx_vilvl_h"
1824   [(set (match_operand:V8HI 0 "register_operand" "=f")
1825         (vec_select:V8HI
1826           (vec_concat:V16HI
1827             (match_operand:V8HI 1 "register_operand" "f")
1828             (match_operand:V8HI 2 "register_operand" "f"))
1829           (parallel [(const_int 0) (const_int 8)
1830                      (const_int 1) (const_int 9)
1831                      (const_int 2) (const_int 10)
1832                      (const_int 3) (const_int 11)])))]
1833   "ISA_HAS_LSX"
1834   "vilvl.h\t%w0,%w2,%w1"
1835   [(set_attr "type" "simd_permute")
1836    (set_attr "mode" "V8HI")])
1837
1838 (define_insn "lsx_vilvl_w"
1839   [(set (match_operand:V4SI 0 "register_operand" "=f")
1840         (vec_select:V4SI
1841           (vec_concat:V8SI
1842             (match_operand:V4SI 1 "register_operand" "f")
1843             (match_operand:V4SI 2 "register_operand" "f"))
1844           (parallel [(const_int 0) (const_int 4)
1845                      (const_int 1) (const_int 5)])))]
1846   "ISA_HAS_LSX"
1847   "vilvl.w\t%w0,%w2,%w1"
1848   [(set_attr "type" "simd_permute")
1849    (set_attr "mode" "V4SI")])
1850
1851 (define_insn "lsx_vilvl_w_f"
1852   [(set (match_operand:V4SF 0 "register_operand" "=f")
1853         (vec_select:V4SF
1854           (vec_concat:V8SF
1855             (match_operand:V4SF 1 "register_operand" "f")
1856             (match_operand:V4SF 2 "register_operand" "f"))
1857           (parallel [(const_int 0) (const_int 4)
1858                      (const_int 1) (const_int 5)])))]
1859   "ISA_HAS_LSX"
1860   "vilvl.w\t%w0,%w2,%w1"
1861   [(set_attr "type" "simd_permute")
1862    (set_attr "mode" "V4SF")])
1863
1864 (define_insn "lsx_vilvl_d"
1865   [(set (match_operand:V2DI 0 "register_operand" "=f")
1866         (vec_select:V2DI
1867           (vec_concat:V4DI
1868             (match_operand:V2DI 1 "register_operand" "f")
1869             (match_operand:V2DI 2 "register_operand" "f"))
1870           (parallel [(const_int 0) (const_int 2)])))]
1871   "ISA_HAS_LSX"
1872   "vilvl.d\t%w0,%w2,%w1"
1873   [(set_attr "type" "simd_permute")
1874    (set_attr "mode" "V2DI")])
1875
1876 (define_insn "lsx_vilvl_d_f"
1877   [(set (match_operand:V2DF 0 "register_operand" "=f")
1878         (vec_select:V2DF
1879           (vec_concat:V4DF
1880             (match_operand:V2DF 1 "register_operand" "f")
1881             (match_operand:V2DF 2 "register_operand" "f"))
1882           (parallel [(const_int 0) (const_int 2)])))]
1883   "ISA_HAS_LSX"
1884   "vilvl.d\t%w0,%w2,%w1"
1885   [(set_attr "type" "simd_permute")
1886    (set_attr "mode" "V2DF")])
1887
1888 (define_insn "smax<mode>3"
1889   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1890         (smax:ILSX (match_operand:ILSX 1 "register_operand" "f,f")
1891                    (match_operand:ILSX 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
1892   "ISA_HAS_LSX"
1893   "@
1894    vmax.<lsxfmt>\t%w0,%w1,%w2
1895    vmaxi.<lsxfmt>\t%w0,%w1,%E2"
1896   [(set_attr "type" "simd_int_arith")
1897    (set_attr "mode" "<MODE>")])
1898
1899 (define_insn "umax<mode>3"
1900   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1901         (umax:ILSX (match_operand:ILSX 1 "register_operand" "f,f")
1902                    (match_operand:ILSX 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
1903   "ISA_HAS_LSX"
1904   "@
1905    vmax.<lsxfmt_u>\t%w0,%w1,%w2
1906    vmaxi.<lsxfmt_u>\t%w0,%w1,%B2"
1907   [(set_attr "type" "simd_int_arith")
1908    (set_attr "mode" "<MODE>")])
1909
1910 (define_insn "smin<mode>3"
1911   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1912         (smin:ILSX (match_operand:ILSX 1 "register_operand" "f,f")
1913                    (match_operand:ILSX 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
1914   "ISA_HAS_LSX"
1915   "@
1916    vmin.<lsxfmt>\t%w0,%w1,%w2
1917    vmini.<lsxfmt>\t%w0,%w1,%E2"
1918   [(set_attr "type" "simd_int_arith")
1919    (set_attr "mode" "<MODE>")])
1920
1921 (define_insn "umin<mode>3"
1922   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1923         (umin:ILSX (match_operand:ILSX 1 "register_operand" "f,f")
1924                    (match_operand:ILSX 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
1925   "ISA_HAS_LSX"
1926   "@
1927    vmin.<lsxfmt_u>\t%w0,%w1,%w2
1928    vmini.<lsxfmt_u>\t%w0,%w1,%B2"
1929   [(set_attr "type" "simd_int_arith")
1930    (set_attr "mode" "<MODE>")])
1931
1932 (define_insn "lsx_vclo_<lsxfmt>"
1933   [(set (match_operand:ILSX 0 "register_operand" "=f")
1934         (clz:ILSX (not:ILSX (match_operand:ILSX 1 "register_operand" "f"))))]
1935   "ISA_HAS_LSX"
1936   "vclo.<lsxfmt>\t%w0,%w1"
1937   [(set_attr "type" "simd_bit")
1938    (set_attr "mode" "<MODE>")])
1939
1940 (define_insn "clz<mode>2"
1941   [(set (match_operand:ILSX 0 "register_operand" "=f")
1942         (clz:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
1943   "ISA_HAS_LSX"
1944   "vclz.<lsxfmt>\t%w0,%w1"
1945   [(set_attr "type" "simd_bit")
1946    (set_attr "mode" "<MODE>")])
1947
1948 (define_insn "lsx_nor_<lsxfmt>"
1949   [(set (match_operand:ILSX 0 "register_operand" "=f,f")
1950         (and:ILSX (not:ILSX (match_operand:ILSX 1 "register_operand" "f,f"))
1951                   (not:ILSX (match_operand:ILSX 2 "reg_or_vector_same_val_operand" "f,Urv8"))))]
1952   "ISA_HAS_LSX"
1953   "@
1954    vnor.v\t%w0,%w1,%w2
1955    vnori.b\t%w0,%w1,%B2"
1956   [(set_attr "type" "simd_logic")
1957    (set_attr "mode" "<MODE>")])
1958
1959 (define_insn "lsx_vpickev_b"
1960 [(set (match_operand:V16QI 0 "register_operand" "=f")
1961       (vec_select:V16QI
1962         (vec_concat:V32QI
1963           (match_operand:V16QI 1 "register_operand" "f")
1964           (match_operand:V16QI 2 "register_operand" "f"))
1965         (parallel [(const_int 0) (const_int 2)
1966                    (const_int 4) (const_int 6)
1967                    (const_int 8) (const_int 10)
1968                    (const_int 12) (const_int 14)
1969                    (const_int 16) (const_int 18)
1970                    (const_int 20) (const_int 22)
1971                    (const_int 24) (const_int 26)
1972                    (const_int 28) (const_int 30)])))]
1973   "ISA_HAS_LSX"
1974   "vpickev.b\t%w0,%w2,%w1"
1975   [(set_attr "type" "simd_permute")
1976    (set_attr "mode" "V16QI")])
1977
1978 (define_insn "lsx_vpickev_h"
1979 [(set (match_operand:V8HI 0 "register_operand" "=f")
1980       (vec_select:V8HI
1981         (vec_concat:V16HI
1982           (match_operand:V8HI 1 "register_operand" "f")
1983           (match_operand:V8HI 2 "register_operand" "f"))
1984         (parallel [(const_int 0) (const_int 2)
1985                    (const_int 4) (const_int 6)
1986                    (const_int 8) (const_int 10)
1987                    (const_int 12) (const_int 14)])))]
1988   "ISA_HAS_LSX"
1989   "vpickev.h\t%w0,%w2,%w1"
1990   [(set_attr "type" "simd_permute")
1991    (set_attr "mode" "V8HI")])
1992
1993 (define_insn "lsx_vpickev_w"
1994 [(set (match_operand:V4SI 0 "register_operand" "=f")
1995       (vec_select:V4SI
1996         (vec_concat:V8SI
1997           (match_operand:V4SI 1 "register_operand" "f")
1998           (match_operand:V4SI 2 "register_operand" "f"))
1999         (parallel [(const_int 0) (const_int 2)
2000                    (const_int 4) (const_int 6)])))]
2001   "ISA_HAS_LSX"
2002   "vpickev.w\t%w0,%w2,%w1"
2003   [(set_attr "type" "simd_permute")
2004    (set_attr "mode" "V4SI")])
2005
2006 (define_insn "lsx_vpickev_w_f"
2007 [(set (match_operand:V4SF 0 "register_operand" "=f")
2008       (vec_select:V4SF
2009         (vec_concat:V8SF
2010           (match_operand:V4SF 1 "register_operand" "f")
2011           (match_operand:V4SF 2 "register_operand" "f"))
2012         (parallel [(const_int 0) (const_int 2)
2013                    (const_int 4) (const_int 6)])))]
2014   "ISA_HAS_LSX"
2015   "vpickev.w\t%w0,%w2,%w1"
2016   [(set_attr "type" "simd_permute")
2017    (set_attr "mode" "V4SF")])
2018
2019 (define_insn "lsx_vpickod_b"
2020 [(set (match_operand:V16QI 0 "register_operand" "=f")
2021       (vec_select:V16QI
2022         (vec_concat:V32QI
2023           (match_operand:V16QI 1 "register_operand" "f")
2024           (match_operand:V16QI 2 "register_operand" "f"))
2025         (parallel [(const_int 1) (const_int 3)
2026                    (const_int 5) (const_int 7)
2027                    (const_int 9) (const_int 11)
2028                    (const_int 13) (const_int 15)
2029                    (const_int 17) (const_int 19)
2030                    (const_int 21) (const_int 23)
2031                    (const_int 25) (const_int 27)
2032                    (const_int 29) (const_int 31)])))]
2033   "ISA_HAS_LSX"
2034   "vpickod.b\t%w0,%w2,%w1"
2035   [(set_attr "type" "simd_permute")
2036    (set_attr "mode" "V16QI")])
2037
2038 (define_insn "lsx_vpickod_h"
2039 [(set (match_operand:V8HI 0 "register_operand" "=f")
2040       (vec_select:V8HI
2041         (vec_concat:V16HI
2042           (match_operand:V8HI 1 "register_operand" "f")
2043           (match_operand:V8HI 2 "register_operand" "f"))
2044         (parallel [(const_int 1) (const_int 3)
2045                    (const_int 5) (const_int 7)
2046                    (const_int 9) (const_int 11)
2047                    (const_int 13) (const_int 15)])))]
2048   "ISA_HAS_LSX"
2049   "vpickod.h\t%w0,%w2,%w1"
2050   [(set_attr "type" "simd_permute")
2051    (set_attr "mode" "V8HI")])
2052
2053 (define_insn "lsx_vpickod_w"
2054 [(set (match_operand:V4SI 0 "register_operand" "=f")
2055       (vec_select:V4SI
2056         (vec_concat:V8SI
2057           (match_operand:V4SI 1 "register_operand" "f")
2058           (match_operand:V4SI 2 "register_operand" "f"))
2059         (parallel [(const_int 1) (const_int 3)
2060                    (const_int 5) (const_int 7)])))]
2061   "ISA_HAS_LSX"
2062   "vpickod.w\t%w0,%w2,%w1"
2063   [(set_attr "type" "simd_permute")
2064    (set_attr "mode" "V4SI")])
2065
2066 (define_insn "lsx_vpickod_w_f"
2067 [(set (match_operand:V4SF 0 "register_operand" "=f")
2068       (vec_select:V4SF
2069         (vec_concat:V8SF
2070           (match_operand:V4SF 1 "register_operand" "f")
2071           (match_operand:V4SF 2 "register_operand" "f"))
2072         (parallel [(const_int 1) (const_int 3)
2073                    (const_int 5) (const_int 7)])))]
2074   "ISA_HAS_LSX"
2075   "vpickod.w\t%w0,%w2,%w1"
2076   [(set_attr "type" "simd_permute")
2077    (set_attr "mode" "V4SF")])
2078
2079 (define_insn "popcount<mode>2"
2080   [(set (match_operand:ILSX 0 "register_operand" "=f")
2081         (popcount:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
2082   "ISA_HAS_LSX"
2083   "vpcnt.<lsxfmt>\t%w0,%w1"
2084   [(set_attr "type" "simd_pcnt")
2085    (set_attr "mode" "<MODE>")])
2086
2087 (define_insn "lsx_vsat_s_<lsxfmt>"
2088   [(set (match_operand:ILSX 0 "register_operand" "=f")
2089         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2090                       (match_operand 2 "const_<bitimm>_operand" "")]
2091                      UNSPEC_LSX_VSAT_S))]
2092   "ISA_HAS_LSX"
2093   "vsat.<lsxfmt>\t%w0,%w1,%2"
2094   [(set_attr "type" "simd_sat")
2095    (set_attr "mode" "<MODE>")])
2096
2097 (define_insn "lsx_vsat_u_<lsxfmt_u>"
2098   [(set (match_operand:ILSX 0 "register_operand" "=f")
2099         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2100                       (match_operand 2 "const_<bitimm>_operand" "")]
2101                      UNSPEC_LSX_VSAT_U))]
2102   "ISA_HAS_LSX"
2103   "vsat.<lsxfmt_u>\t%w0,%w1,%2"
2104   [(set_attr "type" "simd_sat")
2105    (set_attr "mode" "<MODE>")])
2106
2107 (define_insn "lsx_vshuf4i_<lsxfmt_f>"
2108   [(set (match_operand:LSX_WHB_W 0 "register_operand" "=f")
2109         (vec_select:LSX_WHB_W
2110           (match_operand:LSX_WHB_W 1 "register_operand" "f")
2111           (match_operand 2 "par_const_vector_shf_set_operand" "")))]
2112   "ISA_HAS_LSX"
2113 {
2114   HOST_WIDE_INT val = 0;
2115   unsigned int i;
2116
2117   /* We convert the selection to an immediate.  */
2118   for (i = 0; i < 4; i++)
2119     val |= INTVAL (XVECEXP (operands[2], 0, i)) << (2 * i);
2120
2121   operands[2] = GEN_INT (val);
2122   return "vshuf4i.<lsxfmt>\t%w0,%w1,%X2";
2123 }
2124   [(set_attr "type" "simd_shf")
2125    (set_attr "mode" "<MODE>")])
2126
2127 (define_insn "lsx_vsrar_<lsxfmt>"
2128   [(set (match_operand:ILSX 0 "register_operand" "=f")
2129         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2130                       (match_operand:ILSX 2 "register_operand" "f")]
2131                      UNSPEC_LSX_VSRAR))]
2132   "ISA_HAS_LSX"
2133   "vsrar.<lsxfmt>\t%w0,%w1,%w2"
2134   [(set_attr "type" "simd_shift")
2135    (set_attr "mode" "<MODE>")])
2136
2137 (define_insn "lsx_vsrari_<lsxfmt>"
2138   [(set (match_operand:ILSX 0 "register_operand" "=f")
2139         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2140                       (match_operand 2 "const_<bitimm>_operand" "")]
2141                      UNSPEC_LSX_VSRARI))]
2142   "ISA_HAS_LSX"
2143   "vsrari.<lsxfmt>\t%w0,%w1,%2"
2144   [(set_attr "type" "simd_shift")
2145    (set_attr "mode" "<MODE>")])
2146
2147 (define_insn "lsx_vsrlr_<lsxfmt>"
2148   [(set (match_operand:ILSX 0 "register_operand" "=f")
2149         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2150                       (match_operand:ILSX 2 "register_operand" "f")]
2151                      UNSPEC_LSX_VSRLR))]
2152   "ISA_HAS_LSX"
2153   "vsrlr.<lsxfmt>\t%w0,%w1,%w2"
2154   [(set_attr "type" "simd_shift")
2155    (set_attr "mode" "<MODE>")])
2156
2157 (define_insn "lsx_vsrlri_<lsxfmt>"
2158   [(set (match_operand:ILSX 0 "register_operand" "=f")
2159         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2160                       (match_operand 2 "const_<bitimm>_operand" "")]
2161                      UNSPEC_LSX_VSRLRI))]
2162   "ISA_HAS_LSX"
2163   "vsrlri.<lsxfmt>\t%w0,%w1,%2"
2164   [(set_attr "type" "simd_shift")
2165    (set_attr "mode" "<MODE>")])
2166
2167 (define_insn "lsx_vssub_s_<lsxfmt>"
2168   [(set (match_operand:ILSX 0 "register_operand" "=f")
2169         (ss_minus:ILSX (match_operand:ILSX 1 "register_operand" "f")
2170                       (match_operand:ILSX 2 "register_operand" "f")))]
2171   "ISA_HAS_LSX"
2172   "vssub.<lsxfmt>\t%w0,%w1,%w2"
2173   [(set_attr "type" "simd_int_arith")
2174    (set_attr "mode" "<MODE>")])
2175
2176 (define_insn "lsx_vssub_u_<lsxfmt_u>"
2177   [(set (match_operand:ILSX 0 "register_operand" "=f")
2178         (us_minus:ILSX (match_operand:ILSX 1 "register_operand" "f")
2179                       (match_operand:ILSX 2 "register_operand" "f")))]
2180   "ISA_HAS_LSX"
2181   "vssub.<lsxfmt_u>\t%w0,%w1,%w2"
2182   [(set_attr "type" "simd_int_arith")
2183    (set_attr "mode" "<MODE>")])
2184
2185 (define_insn "lsx_vreplve_<lsxfmt_f>"
2186   [(set (match_operand:LSX 0 "register_operand" "=f")
2187         (vec_duplicate:LSX
2188           (vec_select:<UNITMODE>
2189             (match_operand:LSX 1 "register_operand" "f")
2190             (parallel [(match_operand:SI 2 "register_operand" "r")]))))]
2191   "ISA_HAS_LSX"
2192   "vreplve.<lsxfmt>\t%w0,%w1,%z2"
2193   [(set_attr "type" "simd_splat")
2194    (set_attr "mode" "<MODE>")])
2195
2196 (define_insn "lsx_vreplvei_mirror_<lsxfmt_f>"
2197   [(set (match_operand:LSX 0 "register_operand" "=f")
2198         (unspec: LSX [(match_operand:LSX 1 "register_operand" "f")
2199                                 (match_operand 2 "const_<indeximm>_operand" "")]
2200                                 UNSPEC_LSX_VREPLVEI_MIRROR))]
2201   "ISA_HAS_LSX"
2202   "vreplvei.d\t%w0,%w1,%2"
2203   [(set_attr "type" "simd_splat")
2204    (set_attr "mode" "<MODE>")])
2205
2206 (define_insn "lsx_vreplvei_<lsxfmt_f>"
2207   [(set (match_operand:LSX 0 "register_operand" "=f")
2208         (vec_duplicate:LSX
2209           (vec_select:<UNITMODE>
2210             (match_operand:LSX 1 "register_operand" "f")
2211             (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
2212   "ISA_HAS_LSX"
2213   "vreplvei.<lsxfmt>\t%w0,%w1,%2"
2214   [(set_attr "type" "simd_splat")
2215    (set_attr "mode" "<MODE>")])
2216
2217 (define_insn "lsx_vreplvei_<lsxfmt_f>_scalar"
2218   [(set (match_operand:LSX 0 "register_operand" "=f")
2219       (vec_duplicate:LSX
2220         (match_operand:<UNITMODE> 1 "register_operand" "f")))]
2221   "ISA_HAS_LSX"
2222   "vreplvei.<lsxfmt>\t%w0,%w1,0"
2223   [(set_attr "type" "simd_splat")
2224    (set_attr "mode" "<MODE>")])
2225
2226 (define_insn "lsx_vfcvt_h_s"
2227   [(set (match_operand:V8HI 0 "register_operand" "=f")
2228         (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
2229                       (match_operand:V4SF 2 "register_operand" "f")]
2230                      UNSPEC_LSX_VFCVT))]
2231   "ISA_HAS_LSX"
2232   "vfcvt.h.s\t%w0,%w1,%w2"
2233   [(set_attr "type" "simd_fcvt")
2234    (set_attr "mode" "V8HI")])
2235
2236 (define_insn "lsx_vfcvt_s_d"
2237   [(set (match_operand:V4SF 0 "register_operand" "=f")
2238         (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "f")
2239                       (match_operand:V2DF 2 "register_operand" "f")]
2240                      UNSPEC_LSX_VFCVT))]
2241   "ISA_HAS_LSX"
2242   "vfcvt.s.d\t%w0,%w1,%w2"
2243   [(set_attr "type" "simd_fcvt")
2244    (set_attr "mode" "V4SF")])
2245
2246 (define_insn "vec_pack_trunc_v2df"
2247   [(set (match_operand:V4SF 0 "register_operand" "=f")
2248         (vec_concat:V4SF
2249           (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f"))
2250           (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))]
2251   "ISA_HAS_LSX"
2252   "vfcvt.s.d\t%w0,%w2,%w1"
2253   [(set_attr "type" "simd_fcvt")
2254    (set_attr "mode" "V4SF")])
2255
2256 (define_insn "lsx_vfcvth_s_h"
2257   [(set (match_operand:V4SF 0 "register_operand" "=f")
2258         (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2259                      UNSPEC_LSX_VFCVTH))]
2260   "ISA_HAS_LSX"
2261   "vfcvth.s.h\t%w0,%w1"
2262   [(set_attr "type" "simd_fcvt")
2263    (set_attr "mode" "V4SF")])
2264
2265 (define_insn "lsx_vfcvth_d_s"
2266   [(set (match_operand:V2DF 0 "register_operand" "=f")
2267         (float_extend:V2DF
2268         (vec_select:V2SF
2269           (match_operand:V4SF 1 "register_operand" "f")
2270           (parallel [(const_int 2) (const_int 3)]))))]
2271   "ISA_HAS_LSX"
2272   "vfcvth.d.s\t%w0,%w1"
2273   [(set_attr "type" "simd_fcvt")
2274    (set_attr "mode" "V2DF")])
2275
2276 (define_insn "lsx_vfcvtl_s_h"
2277   [(set (match_operand:V4SF 0 "register_operand" "=f")
2278         (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2279                      UNSPEC_LSX_VFCVTL))]
2280   "ISA_HAS_LSX"
2281   "vfcvtl.s.h\t%w0,%w1"
2282   [(set_attr "type" "simd_fcvt")
2283    (set_attr "mode" "V4SF")])
2284
2285 (define_insn "lsx_vfcvtl_d_s"
2286   [(set (match_operand:V2DF 0 "register_operand" "=f")
2287         (float_extend:V2DF
2288         (vec_select:V2SF
2289           (match_operand:V4SF 1 "register_operand" "f")
2290           (parallel [(const_int 0) (const_int 1)]))))]
2291   "ISA_HAS_LSX"
2292   "vfcvtl.d.s\t%w0,%w1"
2293   [(set_attr "type" "simd_fcvt")
2294    (set_attr "mode" "V2DF")])
2295
2296 (define_code_attr lsxbr
2297   [(eq "bz")
2298    (ne "bnz")])
2299
2300 (define_code_attr lsxeq_v
2301   [(eq "eqz")
2302    (ne "nez")])
2303
2304 (define_code_attr lsxne_v
2305   [(eq "nez")
2306    (ne "eqz")])
2307
2308 (define_code_attr lsxeq
2309   [(eq "anyeqz")
2310    (ne "allnez")])
2311
2312 (define_code_attr lsxne
2313   [(eq "allnez")
2314    (ne "anyeqz")])
2315
2316 (define_insn "lsx_<lsxbr>_<lsxfmt_f>"
2317  [(set (pc) (if_then_else
2318               (equality_op
2319                 (unspec:SI [(match_operand:LSX 1 "register_operand" "f")]
2320                             UNSPEC_LSX_BRANCH)
2321                   (match_operand:SI 2 "const_0_operand"))
2322                   (label_ref (match_operand 0))
2323                   (pc)))
2324       (clobber (match_scratch:FCC 3 "=z"))]
2325  "ISA_HAS_LSX"
2326 {
2327   return loongarch_output_conditional_branch (insn, operands,
2328                                          "vset<lsxeq>.<lsxfmt>\t%Z3%w1\n\tbcnez\t%Z3%0",
2329                                          "vset<lsxne>.<lsxfmt>\t%Z3%w1\n\tbcnez\t%Z3%0");
2330 }
2331  [(set_attr "type" "simd_branch")
2332   (set_attr "mode" "<MODE>")])
2333
2334 (define_insn "lsx_<lsxbr>_v_<lsxfmt_f>"
2335  [(set (pc) (if_then_else
2336               (equality_op
2337                 (unspec:SI [(match_operand:LSX 1 "register_operand" "f")]
2338                             UNSPEC_LSX_BRANCH_V)
2339                   (match_operand:SI 2 "const_0_operand"))
2340                   (label_ref (match_operand 0))
2341                   (pc)))
2342       (clobber (match_scratch:FCC 3 "=z"))]
2343  "ISA_HAS_LSX"
2344 {
2345   return loongarch_output_conditional_branch (insn, operands,
2346                                          "vset<lsxeq_v>.v\t%Z3%w1\n\tbcnez\t%Z3%0",
2347                                          "vset<lsxne_v>.v\t%Z3%w1\n\tbcnez\t%Z3%0");
2348 }
2349  [(set_attr "type" "simd_branch")
2350   (set_attr "mode" "TI")])
2351
2352 ;; vec_concate
2353 (define_expand "vec_concatv2di"
2354   [(set (match_operand:V2DI 0 "register_operand")
2355         (vec_concat:V2DI
2356           (match_operand:DI 1 "register_operand")
2357           (match_operand:DI 2 "register_operand")))]
2358   "ISA_HAS_LSX"
2359 {
2360   emit_insn (gen_lsx_vinsgr2vr_d (operands[0], operands[1],
2361                                   operands[0], GEN_INT (0)));
2362   emit_insn (gen_lsx_vinsgr2vr_d (operands[0], operands[2],
2363                                   operands[0], GEN_INT (1)));
2364   DONE;
2365 })
2366
2367 ;; Implement vec_concatv2df by vilvl.d.
2368 (define_insn_and_split "vec_concatv2df"
2369   [(set (match_operand:V2DF 0 "register_operand" "=f")
2370         (vec_concat:V2DF
2371           (match_operand:DF 1 "register_operand" "f")
2372           (match_operand:DF 2 "register_operand" "f")))]
2373   "ISA_HAS_LSX"
2374   ""
2375   "&& reload_completed"
2376   [(const_int 0)]
2377 {
2378   emit_insn (gen_lsx_vilvl_d_f (operands[0],
2379                                 gen_rtx_REG (V2DFmode, REGNO (operands[1])),
2380                                 gen_rtx_REG (V2DFmode, REGNO (operands[2]))));
2381   DONE;
2382 }
2383   [(set_attr "mode" "V2DF")])
2384
2385 ;; Implement vec_concatv4sf.
2386 ;; Optimize based on hardware register allocation of operands.
2387 (define_insn_and_split "vec_concatv4sf"
2388   [(set (match_operand:V4SF 0 "register_operand" "=f")
2389         (vec_concat:V4SF
2390           (vec_concat:V2SF
2391             (match_operand:SF 1 "register_operand" "f")
2392             (match_operand:SF 2 "register_operand" "f"))
2393           (vec_concat:V2SF
2394             (match_operand:SF 3 "register_operand" "f")
2395             (match_operand:SF 4 "register_operand" "f"))))]
2396   "ISA_HAS_LSX"
2397   ""
2398   "&& reload_completed"
2399   [(const_int 0)]
2400 {
2401   operands[5] = GEN_INT (1);
2402   operands[6] = GEN_INT (2);
2403   operands[7] = GEN_INT (4);
2404   operands[8] = GEN_INT (8);
2405
2406   /* If all input are same, use vreplvei.w to broadcast.  */
2407   if (REGNO (operands[1]) == REGNO (operands[2])
2408       && REGNO (operands[1]) == REGNO (operands[3])
2409       && REGNO (operands[1]) == REGNO (operands[4]))
2410     {
2411       emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[1]));
2412     }
2413   /* If op0 is equal to op3, use vreplvei.w to set each element of op0 as op3.
2414      If other input is different from op3, use vextrins.w to insert.  */
2415   else if (REGNO (operands[0]) == REGNO (operands[3]))
2416     {
2417       emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[3]));
2418       if (REGNO (operands[1]) != REGNO (operands[3]))
2419         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[1],
2420                                                 operands[0], operands[5]));
2421       if (REGNO (operands[2]) != REGNO (operands[3]))
2422         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[2],
2423                                                 operands[0], operands[6]));
2424       if (REGNO (operands[4]) != REGNO (operands[3]))
2425         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[4],
2426                                                 operands[0], operands[8]));
2427     }
2428   /* If op0 is equal to op4, use vreplvei.w to set each element of op0 as op4.
2429      If other input is different from op4, use vextrins.w to insert.  */
2430   else if (REGNO (operands[0]) == REGNO (operands[4]))
2431     {
2432       emit_insn (gen_lsx_vreplvei_w_f_scalar (operands[0], operands[4]));
2433       if (REGNO (operands[1]) != REGNO (operands[4]))
2434         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[1],
2435                                                 operands[0], operands[5]));
2436       if (REGNO (operands[2]) != REGNO (operands[4]))
2437         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[2],
2438                                                 operands[0], operands[6]));
2439       if (REGNO (operands[3]) != REGNO (operands[4]))
2440         emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[3],
2441                                                 operands[0], operands[7]));
2442     }
2443   /* Otherwise, use vilvl.w to merge op1 and op2 first.
2444      If op3 is different from op1, use vextrins.w to insert.
2445      If op4 is different from op2, use vextrins.w to insert.  */
2446   else
2447     {
2448       emit_insn (
2449         gen_lsx_vilvl_w_f (operands[0],
2450                            gen_rtx_REG (V4SFmode, REGNO (operands[1])),
2451                            gen_rtx_REG (V4SFmode, REGNO (operands[2]))));
2452       emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[3],
2453                                               operands[0], operands[7]));
2454       emit_insn (gen_lsx_vextrins_w_f_scalar (operands[0], operands[4],
2455                                               operands[0], operands[8]));
2456     }
2457   DONE;
2458 }
2459   [(set_attr "mode" "V4SF")])
2460
2461 (define_insn "vandn<mode>3"
2462   [(set (match_operand:LSX 0 "register_operand" "=f")
2463         (and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f"))
2464                  (match_operand:LSX 2 "register_operand" "f")))]
2465   "ISA_HAS_LSX"
2466   "vandn.v\t%w0,%w1,%w2"
2467   [(set_attr "type" "simd_logic")
2468    (set_attr "mode" "<MODE>")])
2469
2470 (define_insn "vabs<mode>2"
2471   [(set (match_operand:ILSX 0 "register_operand" "=f")
2472         (abs:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
2473   "ISA_HAS_LSX"
2474   "vsigncov.<lsxfmt>\t%w0,%w1,%w1"
2475   [(set_attr "type" "simd_logic")
2476    (set_attr "mode" "<MODE>")])
2477
2478 (define_insn "vneg<mode>2"
2479   [(set (match_operand:ILSX 0 "register_operand" "=f")
2480         (neg:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
2481   "ISA_HAS_LSX"
2482   "vneg.<lsxfmt>\t%w0,%w1"
2483   [(set_attr "type" "simd_logic")
2484    (set_attr "mode" "<MODE>")])
2485
2486 (define_insn "lsx_vextw_s_d"
2487   [(set (match_operand:V2DI 0 "register_operand" "=f")
2488         (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "f")]
2489                      UNSPEC_LSX_VEXTW_S))]
2490   "ISA_HAS_LSX"
2491   "vextw_s.d\t%w0,%w1"
2492   [(set_attr "type" "simd_fcvt")
2493    (set_attr "mode" "V4SI")])
2494
2495 (define_insn "lsx_vextw_u_d"
2496   [(set (match_operand:V2DI 0 "register_operand" "=f")
2497         (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "f")]
2498                      UNSPEC_LSX_VEXTW_U))]
2499   "ISA_HAS_LSX"
2500   "vextw_u.d\t%w0,%w1"
2501   [(set_attr "type" "simd_fcvt")
2502    (set_attr "mode" "V4SI")])
2503
2504 (define_insn "lsx_vsllwil_s_<dlsxfmt>_<lsxfmt>"
2505   [(set (match_operand:<VDMODE> 0 "register_operand" "=f")
2506         (unspec:<VDMODE> [(match_operand:ILSX_WHB 1 "register_operand" "f")
2507                           (match_operand 2 "const_<bitimm>_operand" "")]
2508                          UNSPEC_LSX_VSLLWIL_S))]
2509   "ISA_HAS_LSX"
2510   "vsllwil.<dlsxfmt>.<lsxfmt>\t%w0,%w1,%2"
2511   [(set_attr "type" "simd_shift")
2512    (set_attr "mode" "<MODE>")])
2513
2514 (define_insn "lsx_vsllwil_u_<dlsxfmt_u>_<lsxfmt_u>"
2515   [(set (match_operand:<VDMODE> 0 "register_operand" "=f")
2516         (unspec:<VDMODE> [(match_operand:ILSX_WHB 1 "register_operand" "f")
2517                           (match_operand 2 "const_<bitimm>_operand" "")]
2518                          UNSPEC_LSX_VSLLWIL_U))]
2519   "ISA_HAS_LSX"
2520   "vsllwil.<dlsxfmt_u>.<lsxfmt_u>\t%w0,%w1,%2"
2521   [(set_attr "type" "simd_shift")
2522    (set_attr "mode" "<MODE>")])
2523
2524 (define_insn "lsx_vsran_<hlsxfmt>_<lsxfmt>"
2525   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2526         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2527                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2528                          UNSPEC_LSX_VSRAN))]
2529   "ISA_HAS_LSX"
2530   "vsran.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2531   [(set_attr "type" "simd_int_arith")
2532    (set_attr "mode" "<MODE>")])
2533
2534 (define_insn "lsx_vssran_s_<hlsxfmt>_<lsxfmt>"
2535   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2536         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2537                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2538                          UNSPEC_LSX_VSSRAN_S))]
2539   "ISA_HAS_LSX"
2540   "vssran.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2541   [(set_attr "type" "simd_int_arith")
2542    (set_attr "mode" "<MODE>")])
2543
2544 (define_insn "lsx_vssran_u_<hlsxfmt_u>_<lsxfmt>"
2545   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2546         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2547                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2548                          UNSPEC_LSX_VSSRAN_U))]
2549   "ISA_HAS_LSX"
2550   "vssran.<hlsxfmt_u>.<lsxfmt>\t%w0,%w1,%w2"
2551   [(set_attr "type" "simd_int_arith")
2552    (set_attr "mode" "<MODE>")])
2553
2554 (define_insn "lsx_vsrain_<hlsxfmt>"
2555   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2556         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2557                           (match_operand 2 "const_<bitimm>_operand" "")]
2558                          UNSPEC_LSX_VSRAIN))]
2559   "ISA_HAS_LSX"
2560   "vsrain.<hlsxfmt>\t%w0,%w1,%2"
2561   [(set_attr "type" "simd_shift")
2562    (set_attr "mode" "<MODE>")])
2563
2564 ;; FIXME: bitimm
2565 (define_insn "lsx_vsrains_s_<hlsxfmt>"
2566   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2567         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2568                           (match_operand 2 "const_<bitimm>_operand" "")]
2569                          UNSPEC_LSX_VSRAINS_S))]
2570   "ISA_HAS_LSX"
2571   "vsrains_s.<hlsxfmt>\t%w0,%w1,%2"
2572   [(set_attr "type" "simd_shift")
2573    (set_attr "mode" "<MODE>")])
2574
2575 ;; FIXME: bitimm
2576 (define_insn "lsx_vsrains_u_<hlsxfmt>"
2577   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2578         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2579                           (match_operand 2 "const_<bitimm>_operand" "")]
2580                          UNSPEC_LSX_VSRAINS_U))]
2581   "ISA_HAS_LSX"
2582   "vsrains_u.<hlsxfmt>\t%w0,%w1,%2"
2583   [(set_attr "type" "simd_shift")
2584    (set_attr "mode" "<MODE>")])
2585
2586 (define_insn "lsx_vsrarn_<hlsxfmt>_<lsxfmt>"
2587   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2588         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2589                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2590                          UNSPEC_LSX_VSRARN))]
2591   "ISA_HAS_LSX"
2592   "vsrarn.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2593   [(set_attr "type" "simd_int_arith")
2594    (set_attr "mode" "<MODE>")])
2595
2596 (define_insn "lsx_vssrarn_s_<hlsxfmt>_<lsxfmt>"
2597   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2598         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2599                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2600                          UNSPEC_LSX_VSSRARN_S))]
2601   "ISA_HAS_LSX"
2602   "vssrarn.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2603   [(set_attr "type" "simd_int_arith")
2604    (set_attr "mode" "<MODE>")])
2605
2606 (define_insn "lsx_vssrarn_u_<hlsxfmt_u>_<lsxfmt>"
2607   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2608         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2609                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2610                          UNSPEC_LSX_VSSRARN_U))]
2611   "ISA_HAS_LSX"
2612   "vssrarn.<hlsxfmt_u>.<lsxfmt>\t%w0,%w1,%w2"
2613   [(set_attr "type" "simd_int_arith")
2614    (set_attr "mode" "<MODE>")])
2615
2616 (define_insn "lsx_vsrln_<hlsxfmt>_<lsxfmt>"
2617   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2618         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2619                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2620                          UNSPEC_LSX_VSRLN))]
2621   "ISA_HAS_LSX"
2622   "vsrln.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2623   [(set_attr "type" "simd_int_arith")
2624    (set_attr "mode" "<MODE>")])
2625
2626 (define_insn "lsx_vssrln_u_<hlsxfmt_u>_<lsxfmt>"
2627   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2628         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2629                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2630                          UNSPEC_LSX_VSSRLN_U))]
2631   "ISA_HAS_LSX"
2632   "vssrln.<hlsxfmt_u>.<lsxfmt>\t%w0,%w1,%w2"
2633   [(set_attr "type" "simd_int_arith")
2634    (set_attr "mode" "<MODE>")])
2635
2636 (define_insn "lsx_vsrlrn_<hlsxfmt>_<lsxfmt>"
2637   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2638         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2639                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2640                          UNSPEC_LSX_VSRLRN))]
2641   "ISA_HAS_LSX"
2642   "vsrlrn.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
2643   [(set_attr "type" "simd_int_arith")
2644    (set_attr "mode" "<MODE>")])
2645
2646 (define_insn "lsx_vssrlrn_u_<hlsxfmt_u>_<lsxfmt>"
2647   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
2648         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
2649                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
2650                          UNSPEC_LSX_VSSRLRN_U))]
2651   "ISA_HAS_LSX"
2652   "vssrlrn.<hlsxfmt_u>.<lsxfmt>\t%w0,%w1,%w2"
2653   [(set_attr "type" "simd_int_arith")
2654    (set_attr "mode" "<MODE>")])
2655
2656 (define_insn "lsx_vfrstpi_<lsxfmt>"
2657   [(set (match_operand:ILSX_HB 0 "register_operand" "=f")
2658         (unspec:ILSX_HB [(match_operand:ILSX_HB 1 "register_operand" "0")
2659                          (match_operand:ILSX_HB 2 "register_operand" "f")
2660                          (match_operand 3 "const_uimm5_operand" "")]
2661                         UNSPEC_LSX_VFRSTPI))]
2662   "ISA_HAS_LSX"
2663   "vfrstpi.<lsxfmt>\t%w0,%w2,%3"
2664   [(set_attr "type" "simd_shift")
2665    (set_attr "mode" "<MODE>")])
2666
2667 (define_insn "lsx_vfrstp_<lsxfmt>"
2668   [(set (match_operand:ILSX_HB 0 "register_operand" "=f")
2669         (unspec:ILSX_HB [(match_operand:ILSX_HB 1 "register_operand" "0")
2670                          (match_operand:ILSX_HB 2 "register_operand" "f")
2671                          (match_operand:ILSX_HB 3 "register_operand" "f")]
2672                         UNSPEC_LSX_VFRSTP))]
2673   "ISA_HAS_LSX"
2674   "vfrstp.<lsxfmt>\t%w0,%w2,%w3"
2675   [(set_attr "type" "simd_int_arith")
2676    (set_attr "mode" "<MODE>")])
2677
2678 (define_insn "lsx_vshuf4i_d"
2679   [(set (match_operand:V2DI 0 "register_operand" "=f")
2680         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
2681                       (match_operand:V2DI 2 "register_operand" "f")
2682                       (match_operand 3 "const_uimm8_operand")]
2683                      UNSPEC_LSX_VSHUF4I))]
2684   "ISA_HAS_LSX"
2685   "vshuf4i.d\t%w0,%w2,%3"
2686   [(set_attr "type" "simd_sld")
2687    (set_attr "mode" "V2DI")])
2688
2689 (define_insn "lsx_vbsrl_<lsxfmt_f>"
2690   [(set (match_operand:LSX 0 "register_operand" "=f")
2691         (unspec:LSX [(match_operand:LSX 1 "register_operand" "f")
2692                      (match_operand 2 "const_uimm5_operand" "")]
2693                     UNSPEC_LSX_VBSRL_V))]
2694   "ISA_HAS_LSX"
2695   "vbsrl.v\t%w0,%w1,%2"
2696   [(set_attr "type" "simd_shift")
2697    (set_attr "mode" "<MODE>")])
2698
2699 (define_insn "lsx_vbsll_<lsxfmt>"
2700   [(set (match_operand:ILSX 0 "register_operand" "=f")
2701         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2702                       (match_operand 2 "const_uimm5_operand" "")]
2703                      UNSPEC_LSX_VBSLL_V))]
2704   "ISA_HAS_LSX"
2705   "vbsll.v\t%w0,%w1,%2"
2706   [(set_attr "type" "simd_shift")
2707    (set_attr "mode" "<MODE>")])
2708
2709 (define_insn "lsx_vextrins_<lsxfmt>"
2710   [(set (match_operand:ILSX 0 "register_operand" "=f")
2711         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
2712                       (match_operand:ILSX 2 "register_operand" "f")
2713                       (match_operand 3 "const_uimm8_operand" "")]
2714                      UNSPEC_LSX_VEXTRINS))]
2715   "ISA_HAS_LSX"
2716   "vextrins.<lsxfmt>\t%w0,%w2,%3"
2717   [(set_attr "type" "simd_shift")
2718    (set_attr "mode" "<MODE>")])
2719
2720 (define_insn "lsx_vmskltz_<lsxfmt>"
2721   [(set (match_operand:ILSX 0 "register_operand" "=f")
2722         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")]
2723                      UNSPEC_LSX_VMSKLTZ))]
2724   "ISA_HAS_LSX"
2725   "vmskltz.<lsxfmt>\t%w0,%w1"
2726   [(set_attr "type" "simd_shift")
2727    (set_attr "mode" "<MODE>")])
2728
2729 (define_insn "lsx_vsigncov_<lsxfmt>"
2730   [(set (match_operand:ILSX 0 "register_operand" "=f")
2731         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f")
2732                       (match_operand:ILSX 2 "register_operand" "f")]
2733                      UNSPEC_LSX_VSIGNCOV))]
2734   "ISA_HAS_LSX"
2735   "vsigncov.<lsxfmt>\t%w0,%w1,%w2"
2736   [(set_attr "type" "simd_int_arith")
2737    (set_attr "mode" "<MODE>")])
2738
2739 (define_expand "copysign<mode>3"
2740   [(set (match_dup 4)
2741         (and:FLSX
2742           (not:FLSX (match_dup 3))
2743           (match_operand:FLSX 1 "register_operand")))
2744    (set (match_dup 5)
2745         (and:FLSX (match_dup 3)
2746                   (match_operand:FLSX 2 "reg_or_vector_same_val_operand")))
2747    (set (match_operand:FLSX 0 "register_operand")
2748         (ior:FLSX (match_dup 4) (match_dup 5)))]
2749   "ISA_HAS_LSX"
2750 {
2751   /* copysign (x, -1) should instead be expanded as setting the sign
2752      bit.  */
2753   if (!REG_P (operands[2]))
2754     {
2755       rtx op2_elt = unwrap_const_vec_duplicate (operands[2]);
2756       if (GET_CODE (op2_elt) == CONST_DOUBLE
2757           && real_isneg (CONST_DOUBLE_REAL_VALUE (op2_elt)))
2758         {
2759           rtx n = GEN_INT (8 * GET_MODE_SIZE (<UNITMODE>mode) - 1);
2760           operands[0] = lowpart_subreg (<VIMODE>mode, operands[0],
2761                                         <MODE>mode);
2762           operands[1] = lowpart_subreg (<VIMODE>mode, operands[1],
2763                                         <MODE>mode);
2764           emit_insn (gen_lsx_vbitseti_<lsxfmt> (operands[0], operands[1],
2765                                                 n));
2766           DONE;
2767         }
2768     }
2769
2770   operands[2] = force_reg (<MODE>mode, operands[2]);
2771   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
2772
2773   operands[4] = gen_reg_rtx (<MODE>mode);
2774   operands[5] = gen_reg_rtx (<MODE>mode);
2775 })
2776
2777 (define_expand "@xorsign<mode>3"
2778   [(set (match_dup 4)
2779     (and:FLSX (match_dup 3)
2780         (match_operand:FLSX 2 "register_operand")))
2781    (set (match_operand:FLSX 0 "register_operand")
2782     (xor:FLSX (match_dup 4)
2783          (match_operand:FLSX 1 "register_operand")))]
2784   "ISA_HAS_LSX"
2785 {
2786   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
2787
2788   operands[4] = gen_reg_rtx (<MODE>mode);
2789 })
2790
2791
2792 (define_insn "absv2df2"
2793   [(set (match_operand:V2DF 0 "register_operand" "=f")
2794         (abs:V2DF (match_operand:V2DF 1 "register_operand" "f")))]
2795   "ISA_HAS_LSX"
2796   "vbitclri.d\t%w0,%w1,63"
2797   [(set_attr "type" "simd_logic")
2798    (set_attr "mode" "V2DF")])
2799
2800 (define_insn "absv4sf2"
2801   [(set (match_operand:V4SF 0 "register_operand" "=f")
2802         (abs:V4SF (match_operand:V4SF 1 "register_operand" "f")))]
2803   "ISA_HAS_LSX"
2804   "vbitclri.w\t%w0,%w1,31"
2805   [(set_attr "type" "simd_logic")
2806    (set_attr "mode" "V4SF")])
2807
2808 (define_insn "vfmadd<mode>4"
2809   [(set (match_operand:FLSX 0 "register_operand" "=f")
2810         (fma:FLSX (match_operand:FLSX 1 "register_operand" "f")
2811                   (match_operand:FLSX 2 "register_operand" "f")
2812                   (match_operand:FLSX 3 "register_operand" "f")))]
2813   "ISA_HAS_LSX"
2814   "vfmadd.<flsxfmt>\t%w0,%w1,$w2,%w3"
2815   [(set_attr "type" "simd_fmadd")
2816    (set_attr "mode" "<MODE>")])
2817
2818 (define_insn "fms<mode>4"
2819   [(set (match_operand:FLSX 0 "register_operand" "=f")
2820         (fma:FLSX (match_operand:FLSX 1 "register_operand" "f")
2821                   (match_operand:FLSX 2 "register_operand" "f")
2822                   (neg:FLSX (match_operand:FLSX 3 "register_operand" "f"))))]
2823   "ISA_HAS_LSX"
2824   "vfmsub.<flsxfmt>\t%w0,%w1,%w2,%w3"
2825   [(set_attr "type" "simd_fmadd")
2826    (set_attr "mode" "<MODE>")])
2827
2828 (define_insn "vfnmsub<mode>4_nmsub4"
2829   [(set (match_operand:FLSX 0 "register_operand" "=f")
2830         (neg:FLSX
2831           (fma:FLSX
2832             (match_operand:FLSX 1 "register_operand" "f")
2833             (match_operand:FLSX 2 "register_operand" "f")
2834             (neg:FLSX (match_operand:FLSX 3 "register_operand" "f")))))]
2835   "ISA_HAS_LSX"
2836   "vfnmsub.<flsxfmt>\t%w0,%w1,%w2,%w3"
2837   [(set_attr "type" "simd_fmadd")
2838    (set_attr "mode" "<MODE>")])
2839
2840
2841 (define_insn "vfnmadd<mode>4_nmadd4"
2842   [(set (match_operand:FLSX 0 "register_operand" "=f")
2843         (neg:FLSX
2844           (fma:FLSX
2845             (match_operand:FLSX 1 "register_operand" "f")
2846             (match_operand:FLSX 2 "register_operand" "f")
2847             (match_operand:FLSX 3 "register_operand" "f"))))]
2848   "ISA_HAS_LSX"
2849   "vfnmadd.<flsxfmt>\t%w0,%w1,%w2,%w3"
2850   [(set_attr "type" "simd_fmadd")
2851    (set_attr "mode" "<MODE>")])
2852
2853 (define_insn "lsx_vftint_w_d"
2854   [(set (match_operand:V4SI 0 "register_operand" "=f")
2855         (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
2856                       (match_operand:V2DF 2 "register_operand" "f")]
2857                      UNSPEC_LSX_VFTINT_W_D))]
2858   "ISA_HAS_LSX"
2859   "vftint.w.d\t%w0,%w1,%w2"
2860   [(set_attr "type" "simd_int_arith")
2861    (set_attr "mode" "V2DF")])
2862
2863 (define_insn "lsx_vffint_s_l"
2864   [(set (match_operand:V4SF 0 "register_operand" "=f")
2865         (unspec:V4SF [(match_operand:V2DI 1 "register_operand" "f")
2866                       (match_operand:V2DI 2 "register_operand" "f")]
2867                      UNSPEC_LSX_VFFINT_S_L))]
2868   "ISA_HAS_LSX"
2869   "vffint.s.l\t%w0,%w1,%w2"
2870   [(set_attr "type" "simd_int_arith")
2871    (set_attr "mode" "V2DI")])
2872
2873 (define_insn "lsx_vftintrz_w_d"
2874   [(set (match_operand:V4SI 0 "register_operand" "=f")
2875         (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
2876                       (match_operand:V2DF 2 "register_operand" "f")]
2877                      UNSPEC_LSX_VFTINTRZ_W_D))]
2878   "ISA_HAS_LSX"
2879   "vftintrz.w.d\t%w0,%w1,%w2"
2880   [(set_attr "type" "simd_int_arith")
2881    (set_attr "mode" "V2DF")])
2882
2883 (define_insn "lsx_vftintrp_w_d"
2884   [(set (match_operand:V4SI 0 "register_operand" "=f")
2885         (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
2886                       (match_operand:V2DF 2 "register_operand" "f")]
2887                      UNSPEC_LSX_VFTINTRP_W_D))]
2888   "ISA_HAS_LSX"
2889   "vftintrp.w.d\t%w0,%w1,%w2"
2890   [(set_attr "type" "simd_int_arith")
2891    (set_attr "mode" "V2DF")])
2892
2893 (define_insn "lsx_vftintrm_w_d"
2894   [(set (match_operand:V4SI 0 "register_operand" "=f")
2895         (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
2896                       (match_operand:V2DF 2 "register_operand" "f")]
2897                      UNSPEC_LSX_VFTINTRM_W_D))]
2898   "ISA_HAS_LSX"
2899   "vftintrm.w.d\t%w0,%w1,%w2"
2900   [(set_attr "type" "simd_int_arith")
2901    (set_attr "mode" "V2DF")])
2902
2903 (define_insn "lsx_vftintrne_w_d"
2904   [(set (match_operand:V4SI 0 "register_operand" "=f")
2905         (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
2906                       (match_operand:V2DF 2 "register_operand" "f")]
2907                      UNSPEC_LSX_VFTINTRNE_W_D))]
2908   "ISA_HAS_LSX"
2909   "vftintrne.w.d\t%w0,%w1,%w2"
2910   [(set_attr "type" "simd_int_arith")
2911    (set_attr "mode" "V2DF")])
2912
2913 (define_insn "lsx_vftinth_l_s"
2914   [(set (match_operand:V2DI 0 "register_operand" "=f")
2915         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2916                      UNSPEC_LSX_VFTINTH_L_H))]
2917   "ISA_HAS_LSX"
2918   "vftinth.l.s\t%w0,%w1"
2919   [(set_attr "type" "simd_shift")
2920    (set_attr "mode" "V4SF")])
2921
2922 (define_insn "lsx_vftintl_l_s"
2923   [(set (match_operand:V2DI 0 "register_operand" "=f")
2924         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2925                      UNSPEC_LSX_VFTINTL_L_S))]
2926   "ISA_HAS_LSX"
2927   "vftintl.l.s\t%w0,%w1"
2928   [(set_attr "type" "simd_shift")
2929    (set_attr "mode" "V4SF")])
2930
2931 (define_insn "lsx_vffinth_d_w"
2932   [(set (match_operand:V2DF 0 "register_operand" "=f")
2933         (unspec:V2DF [(match_operand:V4SI 1 "register_operand" "f")]
2934                      UNSPEC_LSX_VFFINTH_D_W))]
2935   "ISA_HAS_LSX"
2936   "vffinth.d.w\t%w0,%w1"
2937   [(set_attr "type" "simd_shift")
2938    (set_attr "mode" "V4SI")])
2939
2940 (define_insn "lsx_vffintl_d_w"
2941   [(set (match_operand:V2DF 0 "register_operand" "=f")
2942         (unspec:V2DF [(match_operand:V4SI 1 "register_operand" "f")]
2943                      UNSPEC_LSX_VFFINTL_D_W))]
2944   "ISA_HAS_LSX"
2945   "vffintl.d.w\t%w0,%w1"
2946   [(set_attr "type" "simd_shift")
2947    (set_attr "mode" "V4SI")])
2948
2949 (define_insn "lsx_vftintrzh_l_s"
2950   [(set (match_operand:V2DI 0 "register_operand" "=f")
2951         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2952                      UNSPEC_LSX_VFTINTRZH_L_S))]
2953   "ISA_HAS_LSX"
2954   "vftintrzh.l.s\t%w0,%w1"
2955   [(set_attr "type" "simd_shift")
2956    (set_attr "mode" "V4SF")])
2957
2958 (define_insn "lsx_vftintrzl_l_s"
2959   [(set (match_operand:V2DI 0 "register_operand" "=f")
2960         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2961                      UNSPEC_LSX_VFTINTRZL_L_S))]
2962   "ISA_HAS_LSX"
2963   "vftintrzl.l.s\t%w0,%w1"
2964   [(set_attr "type" "simd_shift")
2965    (set_attr "mode" "V4SF")])
2966
2967 (define_insn "lsx_vftintrph_l_s"
2968   [(set (match_operand:V2DI 0 "register_operand" "=f")
2969         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2970                      UNSPEC_LSX_VFTINTRPH_L_S))]
2971   "ISA_HAS_LSX"
2972   "vftintrph.l.s\t%w0,%w1"
2973   [(set_attr "type" "simd_shift")
2974    (set_attr "mode" "V4SF")])
2975
2976 (define_insn "lsx_vftintrpl_l_s"
2977   [(set (match_operand:V2DI 0 "register_operand" "=f")
2978         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2979                      UNSPEC_LSX_VFTINTRPL_L_S))]
2980   "ISA_HAS_LSX"
2981   "vftintrpl.l.s\t%w0,%w1"
2982   [(set_attr "type" "simd_shift")
2983    (set_attr "mode" "V4SF")])
2984
2985 (define_insn "lsx_vftintrmh_l_s"
2986   [(set (match_operand:V2DI 0 "register_operand" "=f")
2987         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2988                      UNSPEC_LSX_VFTINTRMH_L_S))]
2989   "ISA_HAS_LSX"
2990   "vftintrmh.l.s\t%w0,%w1"
2991   [(set_attr "type" "simd_shift")
2992    (set_attr "mode" "V4SF")])
2993
2994 (define_insn "lsx_vftintrml_l_s"
2995   [(set (match_operand:V2DI 0 "register_operand" "=f")
2996         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
2997                      UNSPEC_LSX_VFTINTRML_L_S))]
2998   "ISA_HAS_LSX"
2999   "vftintrml.l.s\t%w0,%w1"
3000   [(set_attr "type" "simd_shift")
3001    (set_attr "mode" "V4SF")])
3002
3003 (define_insn "lsx_vftintrneh_l_s"
3004   [(set (match_operand:V2DI 0 "register_operand" "=f")
3005         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
3006                      UNSPEC_LSX_VFTINTRNEH_L_S))]
3007   "ISA_HAS_LSX"
3008   "vftintrneh.l.s\t%w0,%w1"
3009   [(set_attr "type" "simd_shift")
3010    (set_attr "mode" "V4SF")])
3011
3012 (define_insn "lsx_vftintrnel_l_s"
3013   [(set (match_operand:V2DI 0 "register_operand" "=f")
3014         (unspec:V2DI [(match_operand:V4SF 1 "register_operand" "f")]
3015                      UNSPEC_LSX_VFTINTRNEL_L_S))]
3016   "ISA_HAS_LSX"
3017   "vftintrnel.l.s\t%w0,%w1"
3018   [(set_attr "type" "simd_shift")
3019    (set_attr "mode" "V4SF")])
3020
3021 ;; Offset load and broadcast
3022 (define_expand "lsx_vldrepl_<lsxfmt_f>"
3023   [(match_operand:LSX 0 "register_operand")
3024    (match_operand 1 "pmode_register_operand")
3025    (match_operand 2 "aq12<lsxfmt>_operand")]
3026   "ISA_HAS_LSX"
3027 {
3028   emit_insn (gen_lsx_vldrepl_<lsxfmt_f>_insn
3029              (operands[0], operands[1], operands[2]));
3030   DONE;
3031 })
3032
3033 (define_insn "lsx_vldrepl_<lsxfmt_f>_insn"
3034   [(set (match_operand:LSX 0 "register_operand" "=f")
3035         (vec_duplicate:LSX
3036           (mem:<UNITMODE> (plus:DI (match_operand:DI 1 "register_operand" "r")
3037                                    (match_operand 2 "aq12<lsxfmt>_operand")))))]
3038   "ISA_HAS_LSX"
3039 {
3040     return "vldrepl.<lsxfmt>\t%w0,%1,%2";
3041 }
3042   [(set_attr "type" "simd_load")
3043    (set_attr "mode" "<MODE>")
3044    (set_attr "length" "4")])
3045
3046 (define_insn "lsx_vldrepl_<lsxfmt_f>_insn_0"
3047   [(set (match_operand:LSX 0 "register_operand" "=f")
3048     (vec_duplicate:LSX
3049       (mem:<UNITMODE> (match_operand:DI 1 "register_operand" "r"))))]
3050   "ISA_HAS_LSX"
3051 {
3052     return "vldrepl.<lsxfmt>\t%w0,%1,0";
3053 }
3054   [(set_attr "type" "simd_load")
3055    (set_attr "mode" "<MODE>")
3056    (set_attr "length" "4")])
3057
3058 ;; Offset store by sel
3059 (define_expand "lsx_vstelm_<lsxfmt_f>"
3060   [(match_operand:LSX 0 "register_operand")
3061    (match_operand 3 "const_<indeximm>_operand")
3062    (match_operand 2 "aq8<lsxfmt>_operand")
3063    (match_operand 1 "pmode_register_operand")]
3064   "ISA_HAS_LSX"
3065 {
3066   emit_insn (gen_lsx_vstelm_<lsxfmt_f>_insn
3067              (operands[1], operands[2], operands[0], operands[3]));
3068   DONE;
3069 })
3070
3071 (define_insn "lsx_vstelm_<lsxfmt_f>_insn"
3072   [(set (mem:<UNITMODE> (plus:DI (match_operand:DI 0 "register_operand" "r")
3073                                  (match_operand 1 "aq8<lsxfmt>_operand")))
3074         (vec_select:<UNITMODE>
3075           (match_operand:LSX 2 "register_operand" "f")
3076           (parallel [(match_operand 3 "const_<indeximm>_operand" "")])))]
3077
3078   "ISA_HAS_LSX"
3079 {
3080   return "vstelm.<lsxfmt>\t%w2,%0,%1,%3";
3081 }
3082   [(set_attr "type" "simd_store")
3083    (set_attr "mode" "<MODE>")
3084    (set_attr "length" "4")])
3085
3086 ;; Offset is "0"
3087 (define_insn "lsx_vstelm_<lsxfmt_f>_insn_0"
3088   [(set (mem:<UNITMODE> (match_operand:DI 0 "register_operand" "r"))
3089     (vec_select:<UNITMODE>
3090       (match_operand:LSX 1 "register_operand" "f")
3091       (parallel [(match_operand:SI 2 "const_<indeximm>_operand")])))]
3092   "ISA_HAS_LSX"
3093 {
3094     return "vstelm.<lsxfmt>\t%w1,%0,0,%2";
3095 }
3096   [(set_attr "type" "simd_store")
3097    (set_attr "mode" "<MODE>")
3098    (set_attr "length" "4")])
3099
3100 (define_expand "lsx_vld"
3101   [(match_operand:V16QI 0 "register_operand")
3102    (match_operand 1 "pmode_register_operand")
3103    (match_operand 2 "aq12b_operand")]
3104   "ISA_HAS_LSX"
3105 {
3106   rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
3107                             INTVAL (operands[2]));
3108   loongarch_emit_move (operands[0], gen_rtx_MEM (V16QImode, addr));
3109   DONE;
3110 })
3111
3112 (define_expand "lsx_vst"
3113   [(match_operand:V16QI 0 "register_operand")
3114    (match_operand 1 "pmode_register_operand")
3115    (match_operand 2 "aq12b_operand")]
3116   "ISA_HAS_LSX"
3117 {
3118   rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
3119                             INTVAL (operands[2]));
3120   loongarch_emit_move (gen_rtx_MEM (V16QImode, addr), operands[0]);
3121   DONE;
3122 })
3123
3124 (define_insn "lsx_vssrln_<hlsxfmt>_<lsxfmt>"
3125   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
3126         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
3127                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
3128                          UNSPEC_LSX_VSSRLN))]
3129   "ISA_HAS_LSX"
3130   "vssrln.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
3131   [(set_attr "type" "simd_int_arith")
3132    (set_attr "mode" "<MODE>")])
3133
3134
3135 (define_insn "lsx_vssrlrn_<hlsxfmt>_<lsxfmt>"
3136   [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
3137         (unspec:<VHMODE> [(match_operand:ILSX_DWH 1 "register_operand" "f")
3138                           (match_operand:ILSX_DWH 2 "register_operand" "f")]
3139                          UNSPEC_LSX_VSSRLRN))]
3140   "ISA_HAS_LSX"
3141   "vssrlrn.<hlsxfmt>.<lsxfmt>\t%w0,%w1,%w2"
3142   [(set_attr "type" "simd_int_arith")
3143    (set_attr "mode" "<MODE>")])
3144
3145 (define_insn "vorn<mode>3"
3146   [(set (match_operand:ILSX 0 "register_operand" "=f")
3147         (ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f"))
3148                   (match_operand:ILSX 1 "register_operand" "f")))]
3149   "ISA_HAS_LSX"
3150   "vorn.v\t%w0,%w1,%w2"
3151   [(set_attr "type" "simd_logic")
3152    (set_attr "mode" "<MODE>")])
3153
3154 (define_insn "lsx_vldi"
3155   [(set (match_operand:V2DI 0 "register_operand" "=f")
3156         (unspec:V2DI [(match_operand 1 "const_imm13_operand")]
3157                     UNSPEC_LSX_VLDI))]
3158   "ISA_HAS_LSX"
3159 {
3160   HOST_WIDE_INT val = INTVAL (operands[1]);
3161   if (val < 0)
3162   {
3163     HOST_WIDE_INT modeVal = (val & 0xf00) >> 8;
3164     if (modeVal < 13)
3165       return  "vldi\t%w0,%1";
3166     else
3167       sorry ("imm13 only support 0000 ~ 1100 in bits 9 ~ 12 when bit '13' is 1");
3168     return "#";
3169   }
3170   else
3171     return "vldi\t%w0,%1";
3172 }
3173   [(set_attr "type" "simd_load")
3174    (set_attr "mode" "V2DI")])
3175
3176 (define_insn "lsx_vshuf_b"
3177   [(set (match_operand:V16QI 0 "register_operand" "=f")
3178         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "f")
3179                        (match_operand:V16QI 2 "register_operand" "f")
3180                        (match_operand:V16QI 3 "register_operand" "f")]
3181                       UNSPEC_LSX_VSHUF_B))]
3182   "ISA_HAS_LSX"
3183   "vshuf.b\t%w0,%w1,%w2,%w3"
3184   [(set_attr "type" "simd_shf")
3185    (set_attr "mode" "V16QI")])
3186
3187 (define_insn "lsx_vldx"
3188   [(set (match_operand:V16QI 0 "register_operand" "=f")
3189         (unspec:V16QI [(match_operand:DI 1 "register_operand" "r")
3190                        (match_operand:DI 2 "reg_or_0_operand" "rJ")]
3191                       UNSPEC_LSX_VLDX))]
3192   "ISA_HAS_LSX"
3193 {
3194   return "vldx\t%w0,%1,%z2";
3195 }
3196   [(set_attr "type" "simd_load")
3197    (set_attr "mode" "V16QI")])
3198
3199 (define_insn "lsx_vstx"
3200   [(set (mem:V16QI (plus:DI (match_operand:DI 1 "register_operand" "r")
3201                             (match_operand:DI 2 "reg_or_0_operand" "rJ")))
3202         (unspec: V16QI [(match_operand:V16QI 0 "register_operand" "f")]
3203                       UNSPEC_LSX_VSTX))]
3204
3205   "ISA_HAS_LSX"
3206 {
3207   return "vstx\t%w0,%1,%z2";
3208 }
3209   [(set_attr "type" "simd_store")
3210    (set_attr "mode" "DI")])
3211
3212 (define_insn "lsx_vextl_qu_du"
3213   [(set (match_operand:V2DI 0 "register_operand" "=f")
3214         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")]
3215                      UNSPEC_LSX_VEXTL_QU_DU))]
3216   "ISA_HAS_LSX"
3217   "vextl.qu.du\t%w0,%w1"
3218   [(set_attr "type" "simd_bit")
3219    (set_attr "mode" "V2DI")])
3220
3221 (define_insn "lsx_vseteqz_v"
3222   [(set (match_operand:FCC 0 "register_operand" "=z")
3223         (eq:FCC
3224           (unspec:SI [(match_operand:V16QI 1 "register_operand" "f")]
3225                      UNSPEC_LSX_VSETEQZ_V)
3226           (match_operand:SI 2 "const_0_operand")))]
3227   "ISA_HAS_LSX"
3228 {
3229   return "vseteqz.v\t%0,%1";
3230 }
3231   [(set_attr "type" "simd_fcmp")
3232    (set_attr "mode" "FCC")])
3233
3234 ;; Vector reduction operation
3235 (define_expand "reduc_plus_scal_v2di"
3236   [(match_operand:DI 0 "register_operand")
3237    (match_operand:V2DI 1 "register_operand")]
3238   "ISA_HAS_LSX"
3239 {
3240   rtx tmp = gen_reg_rtx (V2DImode);
3241   emit_insn (gen_lsx_vhaddw_q_d (tmp, operands[1], operands[1]));
3242   emit_insn (gen_vec_extractv2didi (operands[0], tmp, const0_rtx));
3243   DONE;
3244 })
3245
3246 (define_expand "reduc_plus_scal_v4si"
3247   [(match_operand:SI 0 "register_operand")
3248    (match_operand:V4SI 1 "register_operand")]
3249   "ISA_HAS_LSX"
3250 {
3251   rtx tmp = gen_reg_rtx (V2DImode);
3252   rtx tmp1 = gen_reg_rtx (V2DImode);
3253   emit_insn (gen_lsx_vhaddw_d_w (tmp, operands[1], operands[1]));
3254   emit_insn (gen_lsx_vhaddw_q_d (tmp1, tmp, tmp));
3255   emit_insn (gen_vec_extractv4sisi (operands[0], gen_lowpart (V4SImode,tmp1),
3256                                     const0_rtx));
3257   DONE;
3258 })
3259
3260 (define_expand "reduc_plus_scal_<mode>"
3261   [(match_operand:<UNITMODE> 0 "register_operand")
3262    (match_operand:FLSX 1 "register_operand")]
3263   "ISA_HAS_LSX"
3264 {
3265   rtx tmp = gen_reg_rtx (<MODE>mode);
3266   loongarch_expand_vector_reduc (gen_add<mode>3, tmp, operands[1]);
3267   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3268                                               const0_rtx));
3269   DONE;
3270 })
3271
3272 (define_expand "reduc_<optab>_scal_<mode>"
3273   [(any_bitwise:<UNITMODE>
3274       (match_operand:<UNITMODE> 0 "register_operand")
3275       (match_operand:ILSX 1 "register_operand"))]
3276   "ISA_HAS_LSX"
3277 {
3278   rtx tmp = gen_reg_rtx (<MODE>mode);
3279   loongarch_expand_vector_reduc (gen_<optab><mode>3, tmp, operands[1]);
3280   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3281                                               const0_rtx));
3282   DONE;
3283 })
3284
3285 (define_expand "reduc_smax_scal_<mode>"
3286   [(match_operand:<UNITMODE> 0 "register_operand")
3287    (match_operand:LSX 1 "register_operand")]
3288   "ISA_HAS_LSX"
3289 {
3290   rtx tmp = gen_reg_rtx (<MODE>mode);
3291   loongarch_expand_vector_reduc (gen_smax<mode>3, tmp, operands[1]);
3292   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3293                                               const0_rtx));
3294   DONE;
3295 })
3296
3297 (define_expand "reduc_smin_scal_<mode>"
3298   [(match_operand:<UNITMODE> 0 "register_operand")
3299    (match_operand:LSX 1 "register_operand")]
3300   "ISA_HAS_LSX"
3301 {
3302   rtx tmp = gen_reg_rtx (<MODE>mode);
3303   loongarch_expand_vector_reduc (gen_smin<mode>3, tmp, operands[1]);
3304   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3305                                               const0_rtx));
3306   DONE;
3307 })
3308
3309 (define_expand "reduc_umax_scal_<mode>"
3310   [(match_operand:<UNITMODE> 0 "register_operand")
3311    (match_operand:ILSX 1 "register_operand")]
3312   "ISA_HAS_LSX"
3313 {
3314   rtx tmp = gen_reg_rtx (<MODE>mode);
3315   loongarch_expand_vector_reduc (gen_umax<mode>3, tmp, operands[1]);
3316   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3317                                               const0_rtx));
3318   DONE;
3319 })
3320
3321 (define_expand "reduc_umin_scal_<mode>"
3322   [(match_operand:<UNITMODE> 0 "register_operand")
3323    (match_operand:ILSX 1 "register_operand")]
3324   "ISA_HAS_LSX"
3325 {
3326   rtx tmp = gen_reg_rtx (<MODE>mode);
3327   loongarch_expand_vector_reduc (gen_umin<mode>3, tmp, operands[1]);
3328   emit_insn (gen_vec_extract<mode><unitmode> (operands[0], tmp,
3329                                               const0_rtx));
3330   DONE;
3331 })
3332
3333 (define_expand "avg<mode>3_ceil"
3334   [(match_operand:ILSX_WHB 0 "register_operand")
3335    (match_operand:ILSX_WHB 1 "register_operand")
3336    (match_operand:ILSX_WHB 2 "register_operand")]
3337   "ISA_HAS_LSX"
3338 {
3339   emit_insn (gen_lsx_vavgr_s_<lsxfmt> (operands[0],
3340         operands[1], operands[2]));
3341   DONE;
3342 })
3343
3344 (define_expand "uavg<mode>3_ceil"
3345   [(match_operand:ILSX_WHB 0 "register_operand")
3346    (match_operand:ILSX_WHB 1 "register_operand")
3347    (match_operand:ILSX_WHB 2 "register_operand")]
3348   "ISA_HAS_LSX"
3349 {
3350   emit_insn (gen_lsx_vavgr_u_<lsxfmt_u> (operands[0],
3351         operands[1], operands[2]));
3352   DONE;
3353 })
3354
3355 (define_expand "avg<mode>3_floor"
3356   [(match_operand:ILSX_WHB 0 "register_operand")
3357    (match_operand:ILSX_WHB 1 "register_operand")
3358    (match_operand:ILSX_WHB 2 "register_operand")]
3359   "ISA_HAS_LSX"
3360 {
3361   emit_insn (gen_lsx_vavg_s_<lsxfmt> (operands[0],
3362         operands[1], operands[2]));
3363   DONE;
3364 })
3365
3366 (define_expand "uavg<mode>3_floor"
3367   [(match_operand:ILSX_WHB 0 "register_operand")
3368    (match_operand:ILSX_WHB 1 "register_operand")
3369    (match_operand:ILSX_WHB 2 "register_operand")]
3370   "ISA_HAS_LSX"
3371 {
3372   emit_insn (gen_lsx_vavg_u_<lsxfmt_u> (operands[0],
3373         operands[1], operands[2]));
3374   DONE;
3375 })
3376
3377 (define_expand "usadv16qi"
3378   [(match_operand:V4SI 0 "register_operand")
3379    (match_operand:V16QI 1 "register_operand")
3380    (match_operand:V16QI 2 "register_operand")
3381    (match_operand:V4SI 3 "register_operand")]
3382   "ISA_HAS_LSX"
3383 {
3384   rtx t1 = gen_reg_rtx (V16QImode);
3385   rtx t2 = gen_reg_rtx (V8HImode);
3386   rtx t3 = gen_reg_rtx (V4SImode);
3387   emit_insn (gen_lsx_vabsd_u_bu (t1, operands[1], operands[2]));
3388   emit_insn (gen_lsx_vhaddw_hu_bu (t2, t1, t1));
3389   emit_insn (gen_lsx_vhaddw_wu_hu (t3, t2, t2));
3390   emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
3391   DONE;
3392 })
3393
3394 (define_expand "ssadv16qi"
3395   [(match_operand:V4SI 0 "register_operand")
3396    (match_operand:V16QI 1 "register_operand")
3397    (match_operand:V16QI 2 "register_operand")
3398    (match_operand:V4SI 3 "register_operand")]
3399   "ISA_HAS_LSX"
3400 {
3401   rtx t1 = gen_reg_rtx (V16QImode);
3402   rtx t2 = gen_reg_rtx (V8HImode);
3403   rtx t3 = gen_reg_rtx (V4SImode);
3404   emit_insn (gen_lsx_vabsd_s_b (t1, operands[1], operands[2]));
3405   emit_insn (gen_lsx_vhaddw_hu_bu (t2, t1, t1));
3406   emit_insn (gen_lsx_vhaddw_wu_hu (t3, t2, t2));
3407   emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
3408   DONE;
3409 })
3410
3411 (define_insn "lsx_v<optab>wev_d_w<u>"
3412   [(set (match_operand:V2DI 0 "register_operand" "=f")
3413         (addsubmul:V2DI
3414           (any_extend:V2DI
3415             (vec_select:V2SI
3416               (match_operand:V4SI 1 "register_operand" "%f")
3417               (parallel [(const_int 0) (const_int 2)])))
3418           (any_extend:V2DI
3419             (vec_select:V2SI
3420               (match_operand:V4SI 2 "register_operand" "f")
3421               (parallel [(const_int 0) (const_int 2)])))))]
3422   "ISA_HAS_LSX"
3423   "v<optab>wev.d.w<u>\t%w0,%w1,%w2"
3424   [(set_attr "type" "simd_int_arith")
3425    (set_attr "mode" "V2DI")])
3426
3427 (define_insn "lsx_v<optab>wev_w_h<u>"
3428   [(set (match_operand:V4SI 0 "register_operand" "=f")
3429         (addsubmul:V4SI
3430           (any_extend:V4SI
3431             (vec_select:V4HI
3432               (match_operand:V8HI 1 "register_operand" "%f")
3433               (parallel [(const_int 0) (const_int 2)
3434                          (const_int 4) (const_int 6)])))
3435           (any_extend:V4SI
3436             (vec_select:V4HI
3437               (match_operand:V8HI 2 "register_operand" "f")
3438               (parallel [(const_int 0) (const_int 2)
3439                          (const_int 4) (const_int 6)])))))]
3440   "ISA_HAS_LSX"
3441   "v<optab>wev.w.h<u>\t%w0,%w1,%w2"
3442   [(set_attr "type" "simd_int_arith")
3443    (set_attr "mode" "V4SI")])
3444
3445 (define_insn "lsx_v<optab>wev_h_b<u>"
3446   [(set (match_operand:V8HI 0 "register_operand" "=f")
3447         (addsubmul:V8HI
3448           (any_extend:V8HI
3449             (vec_select:V8QI
3450               (match_operand:V16QI 1 "register_operand" "%f")
3451               (parallel [(const_int 0) (const_int 2)
3452                          (const_int 4) (const_int 6)
3453                          (const_int 8) (const_int 10)
3454                          (const_int 12) (const_int 14)])))
3455           (any_extend:V8HI
3456             (vec_select:V8QI
3457               (match_operand:V16QI 2 "register_operand" "f")
3458               (parallel [(const_int 0) (const_int 2)
3459                          (const_int 4) (const_int 6)
3460                          (const_int 8) (const_int 10)
3461                          (const_int 12) (const_int 14)])))))]
3462   "ISA_HAS_LSX"
3463   "v<optab>wev.h.b<u>\t%w0,%w1,%w2"
3464   [(set_attr "type" "simd_int_arith")
3465    (set_attr "mode" "V8HI")])
3466
3467 (define_insn "lsx_v<optab>wod_d_w<u>"
3468   [(set (match_operand:V2DI 0 "register_operand" "=f")
3469         (addsubmul:V2DI
3470           (any_extend:V2DI
3471             (vec_select:V2SI
3472               (match_operand:V4SI 1 "register_operand" "%f")
3473               (parallel [(const_int 1) (const_int 3)])))
3474           (any_extend:V2DI
3475             (vec_select:V2SI
3476               (match_operand:V4SI 2 "register_operand" "f")
3477               (parallel [(const_int 1) (const_int 3)])))))]
3478   "ISA_HAS_LSX"
3479   "v<optab>wod.d.w<u>\t%w0,%w1,%w2"
3480   [(set_attr "type" "simd_int_arith")
3481    (set_attr "mode" "V2DI")])
3482
3483 (define_insn "lsx_v<optab>wod_w_h<u>"
3484   [(set (match_operand:V4SI 0 "register_operand" "=f")
3485         (addsubmul:V4SI
3486           (any_extend:V4SI
3487             (vec_select:V4HI
3488               (match_operand:V8HI 1 "register_operand" "%f")
3489               (parallel [(const_int 1) (const_int 3)
3490                          (const_int 5) (const_int 7)])))
3491           (any_extend:V4SI
3492             (vec_select:V4HI
3493               (match_operand:V8HI 2 "register_operand" "f")
3494               (parallel [(const_int 1) (const_int 3)
3495                          (const_int 5) (const_int 7)])))))]
3496   "ISA_HAS_LSX"
3497   "v<optab>wod.w.h<u>\t%w0,%w1,%w2"
3498   [(set_attr "type" "simd_int_arith")
3499    (set_attr "mode" "V4SI")])
3500
3501 (define_insn "lsx_v<optab>wod_h_b<u>"
3502   [(set (match_operand:V8HI 0 "register_operand" "=f")
3503         (addsubmul:V8HI
3504           (any_extend:V8HI
3505             (vec_select:V8QI
3506               (match_operand:V16QI 1 "register_operand" "%f")
3507               (parallel [(const_int 1) (const_int 3)
3508                          (const_int 5) (const_int 7)
3509                          (const_int 9) (const_int 11)
3510                          (const_int 13) (const_int 15)])))
3511           (any_extend:V8HI
3512             (vec_select:V8QI
3513               (match_operand:V16QI 2 "register_operand" "f")
3514               (parallel [(const_int 1) (const_int 3)
3515                          (const_int 5) (const_int 7)
3516                          (const_int 9) (const_int 11)
3517                          (const_int 13) (const_int 15)])))))]
3518   "ISA_HAS_LSX"
3519   "v<optab>wod.h.b<u>\t%w0,%w1,%w2"
3520   [(set_attr "type" "simd_int_arith")
3521    (set_attr "mode" "V8HI")])
3522
3523 (define_insn "lsx_v<optab>wev_d_wu_w"
3524   [(set (match_operand:V2DI 0 "register_operand" "=f")
3525         (addmul:V2DI
3526           (zero_extend:V2DI
3527             (vec_select:V2SI
3528               (match_operand:V4SI 1 "register_operand" "%f")
3529               (parallel [(const_int 0) (const_int 2)])))
3530           (sign_extend:V2DI
3531             (vec_select:V2SI
3532               (match_operand:V4SI 2 "register_operand" "f")
3533               (parallel [(const_int 0) (const_int 2)])))))]
3534   "ISA_HAS_LSX"
3535   "v<optab>wev.d.wu.w\t%w0,%w1,%w2"
3536   [(set_attr "type" "simd_int_arith")
3537    (set_attr "mode" "V2DI")])
3538
3539 (define_insn "lsx_v<optab>wev_w_hu_h"
3540   [(set (match_operand:V4SI 0 "register_operand" "=f")
3541         (addmul:V4SI
3542           (zero_extend:V4SI
3543             (vec_select:V4HI
3544               (match_operand:V8HI 1 "register_operand" "%f")
3545               (parallel [(const_int 0) (const_int 2)
3546                          (const_int 4) (const_int 6)])))
3547           (sign_extend:V4SI
3548             (vec_select:V4HI
3549               (match_operand:V8HI 2 "register_operand" "f")
3550               (parallel [(const_int 0) (const_int 2)
3551                          (const_int 4) (const_int 6)])))))]
3552   "ISA_HAS_LSX"
3553   "v<optab>wev.w.hu.h\t%w0,%w1,%w2"
3554   [(set_attr "type" "simd_int_arith")
3555    (set_attr "mode" "V4SI")])
3556
3557 (define_insn "lsx_v<optab>wev_h_bu_b"
3558   [(set (match_operand:V8HI 0 "register_operand" "=f")
3559         (addmul:V8HI
3560           (zero_extend:V8HI
3561             (vec_select:V8QI
3562               (match_operand:V16QI 1 "register_operand" "%f")
3563               (parallel [(const_int 0) (const_int 2)
3564                          (const_int 4) (const_int 6)
3565                          (const_int 8) (const_int 10)
3566                          (const_int 12) (const_int 14)])))
3567           (sign_extend:V8HI
3568             (vec_select:V8QI
3569               (match_operand:V16QI 2 "register_operand" "f")
3570               (parallel [(const_int 0) (const_int 2)
3571                          (const_int 4) (const_int 6)
3572                          (const_int 8) (const_int 10)
3573                          (const_int 12) (const_int 14)])))))]
3574   "ISA_HAS_LSX"
3575   "v<optab>wev.h.bu.b\t%w0,%w1,%w2"
3576   [(set_attr "type" "simd_int_arith")
3577    (set_attr "mode" "V8HI")])
3578
3579 (define_insn "lsx_v<optab>wod_d_wu_w"
3580   [(set (match_operand:V2DI 0 "register_operand" "=f")
3581         (addmul:V2DI
3582           (zero_extend:V2DI
3583             (vec_select:V2SI
3584               (match_operand:V4SI 1 "register_operand" "%f")
3585               (parallel [(const_int 1) (const_int 3)])))
3586           (sign_extend:V2DI
3587             (vec_select:V2SI
3588               (match_operand:V4SI 2 "register_operand" "f")
3589               (parallel [(const_int 1) (const_int 3)])))))]
3590   "ISA_HAS_LSX"
3591   "v<optab>wod.d.wu.w\t%w0,%w1,%w2"
3592   [(set_attr "type" "simd_int_arith")
3593    (set_attr "mode" "V2DI")])
3594
3595 (define_insn "lsx_v<optab>wod_w_hu_h"
3596   [(set (match_operand:V4SI 0 "register_operand" "=f")
3597         (addmul:V4SI
3598           (zero_extend:V4SI
3599             (vec_select:V4HI
3600               (match_operand:V8HI 1 "register_operand" "%f")
3601               (parallel [(const_int 1) (const_int 3)
3602                          (const_int 5) (const_int 7)])))
3603           (sign_extend:V4SI
3604             (vec_select:V4HI
3605               (match_operand:V8HI 2 "register_operand" "f")
3606               (parallel [(const_int 1) (const_int 3)
3607                          (const_int 5) (const_int 7)])))))]
3608   "ISA_HAS_LSX"
3609   "v<optab>wod.w.hu.h\t%w0,%w1,%w2"
3610   [(set_attr "type" "simd_int_arith")
3611    (set_attr "mode" "V4SI")])
3612
3613 (define_insn "lsx_v<optab>wod_h_bu_b"
3614   [(set (match_operand:V8HI 0 "register_operand" "=f")
3615         (addmul:V8HI
3616           (zero_extend:V8HI
3617             (vec_select:V8QI
3618               (match_operand:V16QI 1 "register_operand" "%f")
3619               (parallel [(const_int 1) (const_int 3)
3620                          (const_int 5) (const_int 7)
3621                          (const_int 9) (const_int 11)
3622                          (const_int 13) (const_int 15)])))
3623           (sign_extend:V8HI
3624             (vec_select:V8QI
3625               (match_operand:V16QI 2 "register_operand" "f")
3626               (parallel [(const_int 1) (const_int 3)
3627                          (const_int 5) (const_int 7)
3628                          (const_int 9) (const_int 11)
3629                          (const_int 13) (const_int 15)])))))]
3630   "ISA_HAS_LSX"
3631   "v<optab>wod.h.bu.b\t%w0,%w1,%w2"
3632   [(set_attr "type" "simd_int_arith")
3633    (set_attr "mode" "V8HI")])
3634
3635 (define_insn "lsx_vaddwev_q_d"
3636   [(set (match_operand:V2DI 0 "register_operand" "=f")
3637         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3638                       (match_operand:V2DI 2 "register_operand" "f")]
3639                      UNSPEC_LSX_VADDWEV))]
3640   "ISA_HAS_LSX"
3641   "vaddwev.q.d\t%w0,%w1,%w2"
3642   [(set_attr "type" "simd_int_arith")
3643    (set_attr "mode" "V2DI")])
3644
3645 (define_insn "lsx_vaddwev_q_du"
3646   [(set (match_operand:V2DI 0 "register_operand" "=f")
3647         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3648                       (match_operand:V2DI 2 "register_operand" "f")]
3649                      UNSPEC_LSX_VADDWEV2))]
3650   "ISA_HAS_LSX"
3651   "vaddwev.q.du\t%w0,%w1,%w2"
3652   [(set_attr "type" "simd_int_arith")
3653    (set_attr "mode" "V2DI")])
3654
3655 (define_insn "lsx_vaddwod_q_d"
3656   [(set (match_operand:V2DI 0 "register_operand" "=f")
3657         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3658                       (match_operand:V2DI 2 "register_operand" "f")]
3659                      UNSPEC_LSX_VADDWOD))]
3660   "ISA_HAS_LSX"
3661   "vaddwod.q.d\t%w0,%w1,%w2"
3662   [(set_attr "type" "simd_int_arith")
3663    (set_attr "mode" "V2DI")])
3664
3665 (define_insn "lsx_vaddwod_q_du"
3666   [(set (match_operand:V2DI 0 "register_operand" "=f")
3667         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3668                       (match_operand:V2DI 2 "register_operand" "f")]
3669                      UNSPEC_LSX_VADDWOD2))]
3670   "ISA_HAS_LSX"
3671   "vaddwod.q.du\t%w0,%w1,%w2"
3672   [(set_attr "type" "simd_int_arith")
3673    (set_attr "mode" "V2DI")])
3674
3675 (define_insn "lsx_vsubwev_q_d"
3676   [(set (match_operand:V2DI 0 "register_operand" "=f")
3677         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3678                       (match_operand:V2DI 2 "register_operand" "f")]
3679                      UNSPEC_LSX_VSUBWEV))]
3680   "ISA_HAS_LSX"
3681   "vsubwev.q.d\t%w0,%w1,%w2"
3682   [(set_attr "type" "simd_int_arith")
3683    (set_attr "mode" "V2DI")])
3684
3685 (define_insn "lsx_vsubwev_q_du"
3686   [(set (match_operand:V2DI 0 "register_operand" "=f")
3687         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3688                       (match_operand:V2DI 2 "register_operand" "f")]
3689                      UNSPEC_LSX_VSUBWEV2))]
3690   "ISA_HAS_LSX"
3691   "vsubwev.q.du\t%w0,%w1,%w2"
3692   [(set_attr "type" "simd_int_arith")
3693    (set_attr "mode" "V2DI")])
3694
3695 (define_insn "lsx_vsubwod_q_d"
3696   [(set (match_operand:V2DI 0 "register_operand" "=f")
3697         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3698                       (match_operand:V2DI 2 "register_operand" "f")]
3699                      UNSPEC_LSX_VSUBWOD))]
3700   "ISA_HAS_LSX"
3701   "vsubwod.q.d\t%w0,%w1,%w2"
3702   [(set_attr "type" "simd_int_arith")
3703    (set_attr "mode" "V2DI")])
3704
3705 (define_insn "lsx_vsubwod_q_du"
3706   [(set (match_operand:V2DI 0 "register_operand" "=f")
3707         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3708                       (match_operand:V2DI 2 "register_operand" "f")]
3709                      UNSPEC_LSX_VSUBWOD2))]
3710   "ISA_HAS_LSX"
3711   "vsubwod.q.du\t%w0,%w1,%w2"
3712   [(set_attr "type" "simd_int_arith")
3713    (set_attr "mode" "V2DI")])
3714
3715 (define_insn "lsx_vaddwev_q_du_d"
3716   [(set (match_operand:V2DI 0 "register_operand" "=f")
3717         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3718                       (match_operand:V2DI 2 "register_operand" "f")]
3719                      UNSPEC_LSX_VADDWEV3))]
3720   "ISA_HAS_LSX"
3721   "vaddwev.q.du.d\t%w0,%w1,%w2"
3722   [(set_attr "type" "simd_int_arith")
3723    (set_attr "mode" "V2DI")])
3724
3725 (define_insn "lsx_vaddwod_q_du_d"
3726   [(set (match_operand:V2DI 0 "register_operand" "=f")
3727         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3728                       (match_operand:V2DI 2 "register_operand" "f")]
3729                      UNSPEC_LSX_VADDWOD3))]
3730   "ISA_HAS_LSX"
3731   "vaddwod.q.du.d\t%w0,%w1,%w2"
3732   [(set_attr "type" "simd_int_arith")
3733    (set_attr "mode" "V2DI")])
3734
3735 (define_insn "lsx_vmulwev_q_du_d"
3736   [(set (match_operand:V2DI 0 "register_operand" "=f")
3737         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3738                       (match_operand:V2DI 2 "register_operand" "f")]
3739                      UNSPEC_LSX_VMULWEV3))]
3740   "ISA_HAS_LSX"
3741   "vmulwev.q.du.d\t%w0,%w1,%w2"
3742   [(set_attr "type" "simd_int_arith")
3743    (set_attr "mode" "V2DI")])
3744
3745 (define_insn "lsx_vmulwod_q_du_d"
3746   [(set (match_operand:V2DI 0 "register_operand" "=f")
3747         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3748                       (match_operand:V2DI 2 "register_operand" "f")]
3749                      UNSPEC_LSX_VMULWOD3))]
3750   "ISA_HAS_LSX"
3751   "vmulwod.q.du.d\t%w0,%w1,%w2"
3752   [(set_attr "type" "simd_int_arith")
3753    (set_attr "mode" "V2DI")])
3754
3755 (define_insn "lsx_vmulwev_q_d"
3756   [(set (match_operand:V2DI 0 "register_operand" "=f")
3757         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3758                       (match_operand:V2DI 2 "register_operand" "f")]
3759                      UNSPEC_LSX_VMULWEV))]
3760   "ISA_HAS_LSX"
3761   "vmulwev.q.d\t%w0,%w1,%w2"
3762   [(set_attr "type" "simd_int_arith")
3763    (set_attr "mode" "V2DI")])
3764
3765 (define_insn "lsx_vmulwev_q_du"
3766   [(set (match_operand:V2DI 0 "register_operand" "=f")
3767         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3768                       (match_operand:V2DI 2 "register_operand" "f")]
3769                      UNSPEC_LSX_VMULWEV2))]
3770   "ISA_HAS_LSX"
3771   "vmulwev.q.du\t%w0,%w1,%w2"
3772   [(set_attr "type" "simd_int_arith")
3773    (set_attr "mode" "V2DI")])
3774
3775 (define_insn "lsx_vmulwod_q_d"
3776   [(set (match_operand:V2DI 0 "register_operand" "=f")
3777         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3778                       (match_operand:V2DI 2 "register_operand" "f")]
3779                      UNSPEC_LSX_VMULWOD))]
3780   "ISA_HAS_LSX"
3781   "vmulwod.q.d\t%w0,%w1,%w2"
3782   [(set_attr "type" "simd_int_arith")
3783    (set_attr "mode" "V2DI")])
3784
3785 (define_insn "lsx_vmulwod_q_du"
3786   [(set (match_operand:V2DI 0 "register_operand" "=f")
3787         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3788                       (match_operand:V2DI 2 "register_operand" "f")]
3789                      UNSPEC_LSX_VMULWOD2))]
3790   "ISA_HAS_LSX"
3791   "vmulwod.q.du\t%w0,%w1,%w2"
3792   [(set_attr "type" "simd_int_arith")
3793    (set_attr "mode" "V2DI")])
3794
3795 (define_insn "lsx_vhaddw_q_d"
3796   [(set (match_operand:V2DI 0 "register_operand" "=f")
3797         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3798                       (match_operand:V2DI 2 "register_operand" "f")]
3799                      UNSPEC_LSX_VHADDW_Q_D))]
3800   "ISA_HAS_LSX"
3801   "vhaddw.q.d\t%w0,%w1,%w2"
3802   [(set_attr "type" "simd_int_arith")
3803    (set_attr "mode" "V2DI")])
3804
3805 (define_insn "lsx_vhaddw_qu_du"
3806   [(set (match_operand:V2DI 0 "register_operand" "=f")
3807         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3808                       (match_operand:V2DI 2 "register_operand" "f")]
3809                      UNSPEC_LSX_VHADDW_QU_DU))]
3810   "ISA_HAS_LSX"
3811   "vhaddw.qu.du\t%w0,%w1,%w2"
3812   [(set_attr "type" "simd_int_arith")
3813    (set_attr "mode" "V2DI")])
3814
3815 (define_insn "lsx_vhsubw_q_d"
3816   [(set (match_operand:V2DI 0 "register_operand" "=f")
3817         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3818                       (match_operand:V2DI 2 "register_operand" "f")]
3819                      UNSPEC_LSX_VHSUBW_Q_D))]
3820   "ISA_HAS_LSX"
3821   "vhsubw.q.d\t%w0,%w1,%w2"
3822   [(set_attr "type" "simd_int_arith")
3823    (set_attr "mode" "V2DI")])
3824
3825 (define_insn "lsx_vhsubw_qu_du"
3826   [(set (match_operand:V2DI 0 "register_operand" "=f")
3827         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
3828                       (match_operand:V2DI 2 "register_operand" "f")]
3829                      UNSPEC_LSX_VHSUBW_QU_DU))]
3830   "ISA_HAS_LSX"
3831   "vhsubw.qu.du\t%w0,%w1,%w2"
3832   [(set_attr "type" "simd_int_arith")
3833    (set_attr "mode" "V2DI")])
3834
3835 (define_insn "lsx_vmaddwev_d_w<u>"
3836   [(set (match_operand:V2DI 0 "register_operand" "=f")
3837         (plus:V2DI
3838           (match_operand:V2DI 1 "register_operand" "0")
3839           (mult:V2DI
3840             (any_extend:V2DI
3841               (vec_select:V2SI
3842                 (match_operand:V4SI 2 "register_operand" "%f")
3843                 (parallel [(const_int 0) (const_int 2)])))
3844             (any_extend:V2DI
3845               (vec_select:V2SI
3846                 (match_operand:V4SI 3 "register_operand" "f")
3847                 (parallel [(const_int 0) (const_int 2)]))))))]
3848   "ISA_HAS_LSX"
3849   "vmaddwev.d.w<u>\t%w0,%w2,%w3"
3850   [(set_attr "type" "simd_fmadd")
3851    (set_attr "mode" "V2DI")])
3852
3853 (define_insn "lsx_vmaddwev_w_h<u>"
3854   [(set (match_operand:V4SI 0 "register_operand" "=f")
3855         (plus:V4SI
3856           (match_operand:V4SI 1 "register_operand" "0")
3857           (mult:V4SI
3858             (any_extend:V4SI
3859               (vec_select:V4HI
3860                 (match_operand:V8HI 2 "register_operand" "%f")
3861                 (parallel [(const_int 0) (const_int 2)
3862                            (const_int 4) (const_int 6)])))
3863             (any_extend:V4SI
3864               (vec_select:V4HI
3865                 (match_operand:V8HI 3 "register_operand" "f")
3866                 (parallel [(const_int 0) (const_int 2)
3867                            (const_int 4) (const_int 6)]))))))]
3868   "ISA_HAS_LSX"
3869   "vmaddwev.w.h<u>\t%w0,%w2,%w3"
3870   [(set_attr "type" "simd_fmadd")
3871    (set_attr "mode" "V4SI")])
3872
3873 (define_insn "lsx_vmaddwev_h_b<u>"
3874   [(set (match_operand:V8HI 0 "register_operand" "=f")
3875         (plus:V8HI
3876           (match_operand:V8HI 1 "register_operand" "0")
3877           (mult:V8HI
3878             (any_extend:V8HI
3879               (vec_select:V8QI
3880                 (match_operand:V16QI 2 "register_operand" "%f")
3881                 (parallel [(const_int 0) (const_int 2)
3882                            (const_int 4) (const_int 6)
3883                            (const_int 8) (const_int 10)
3884                            (const_int 12) (const_int 14)])))
3885             (any_extend:V8HI
3886               (vec_select:V8QI
3887                 (match_operand:V16QI 3 "register_operand" "f")
3888                 (parallel [(const_int 0) (const_int 2)
3889                            (const_int 4) (const_int 6)
3890                            (const_int 8) (const_int 10)
3891                            (const_int 12) (const_int 14)]))))))]
3892   "ISA_HAS_LSX"
3893   "vmaddwev.h.b<u>\t%w0,%w2,%w3"
3894   [(set_attr "type" "simd_fmadd")
3895    (set_attr "mode" "V8HI")])
3896
3897 (define_insn "lsx_vmaddwod_d_w<u>"
3898   [(set (match_operand:V2DI 0 "register_operand" "=f")
3899         (plus:V2DI
3900           (match_operand:V2DI 1 "register_operand" "0")
3901           (mult:V2DI
3902             (any_extend:V2DI
3903               (vec_select:V2SI
3904                 (match_operand:V4SI 2 "register_operand" "%f")
3905                 (parallel [(const_int 1) (const_int 3)])))
3906             (any_extend:V2DI
3907               (vec_select:V2SI
3908                 (match_operand:V4SI 3 "register_operand" "f")
3909                 (parallel [(const_int 1) (const_int 3)]))))))]
3910   "ISA_HAS_LSX"
3911   "vmaddwod.d.w<u>\t%w0,%w2,%w3"
3912   [(set_attr "type" "simd_fmadd")
3913    (set_attr "mode" "V2DI")])
3914
3915 (define_insn "lsx_vmaddwod_w_h<u>"
3916   [(set (match_operand:V4SI 0 "register_operand" "=f")
3917         (plus:V4SI
3918           (match_operand:V4SI 1 "register_operand" "0")
3919           (mult:V4SI
3920             (any_extend:V4SI
3921               (vec_select:V4HI
3922                 (match_operand:V8HI 2 "register_operand" "%f")
3923                 (parallel [(const_int 1) (const_int 3)
3924                            (const_int 5) (const_int 7)])))
3925             (any_extend:V4SI
3926               (vec_select:V4HI
3927                 (match_operand:V8HI 3 "register_operand" "f")
3928                 (parallel [(const_int 1) (const_int 3)
3929                            (const_int 5) (const_int 7)]))))))]
3930   "ISA_HAS_LSX"
3931   "vmaddwod.w.h<u>\t%w0,%w2,%w3"
3932   [(set_attr "type" "simd_fmadd")
3933    (set_attr "mode" "V4SI")])
3934
3935 (define_insn "lsx_vmaddwod_h_b<u>"
3936   [(set (match_operand:V8HI 0 "register_operand" "=f")
3937         (plus:V8HI
3938           (match_operand:V8HI 1 "register_operand" "0")
3939           (mult:V8HI
3940             (any_extend:V8HI
3941               (vec_select:V8QI
3942                 (match_operand:V16QI 2 "register_operand" "%f")
3943                 (parallel [(const_int 1) (const_int 3)
3944                            (const_int 5) (const_int 7)
3945                            (const_int 9) (const_int 11)
3946                            (const_int 13) (const_int 15)])))
3947             (any_extend:V8HI
3948               (vec_select:V8QI
3949                 (match_operand:V16QI 3 "register_operand" "f")
3950                 (parallel [(const_int 1) (const_int 3)
3951                            (const_int 5) (const_int 7)
3952                            (const_int 9) (const_int 11)
3953                            (const_int 13) (const_int 15)]))))))]
3954   "ISA_HAS_LSX"
3955   "vmaddwod.h.b<u>\t%w0,%w2,%w3"
3956   [(set_attr "type" "simd_fmadd")
3957    (set_attr "mode" "V8HI")])
3958
3959 (define_insn "lsx_vmaddwev_d_wu_w"
3960   [(set (match_operand:V2DI 0 "register_operand" "=f")
3961         (plus:V2DI
3962           (match_operand:V2DI 1 "register_operand" "0")
3963           (mult:V2DI
3964             (zero_extend:V2DI
3965               (vec_select:V2SI
3966                 (match_operand:V4SI 2 "register_operand" "%f")
3967                 (parallel [(const_int 0) (const_int 2)])))
3968             (sign_extend:V2DI
3969               (vec_select:V2SI
3970                 (match_operand:V4SI 3 "register_operand" "f")
3971                 (parallel [(const_int 0) (const_int 2)]))))))]
3972   "ISA_HAS_LSX"
3973   "vmaddwev.d.wu.w\t%w0,%w2,%w3"
3974   [(set_attr "type" "simd_fmadd")
3975    (set_attr "mode" "V2DI")])
3976
3977 (define_insn "lsx_vmaddwev_w_hu_h"
3978   [(set (match_operand:V4SI 0 "register_operand" "=f")
3979         (plus:V4SI
3980           (match_operand:V4SI 1 "register_operand" "0")
3981           (mult:V4SI
3982             (zero_extend:V4SI
3983               (vec_select:V4HI
3984                 (match_operand:V8HI 2 "register_operand" "%f")
3985                 (parallel [(const_int 0) (const_int 2)
3986                            (const_int 4) (const_int 6)])))
3987             (sign_extend:V4SI
3988               (vec_select:V4HI
3989                 (match_operand:V8HI 3 "register_operand" "f")
3990                 (parallel [(const_int 0) (const_int 2)
3991                            (const_int 4) (const_int 6)]))))))]
3992   "ISA_HAS_LSX"
3993   "vmaddwev.w.hu.h\t%w0,%w2,%w3"
3994   [(set_attr "type" "simd_fmadd")
3995    (set_attr "mode" "V4SI")])
3996
3997 (define_insn "lsx_vmaddwev_h_bu_b"
3998   [(set (match_operand:V8HI 0 "register_operand" "=f")
3999         (plus:V8HI
4000           (match_operand:V8HI 1 "register_operand" "0")
4001           (mult:V8HI
4002             (zero_extend:V8HI
4003               (vec_select:V8QI
4004                 (match_operand:V16QI 2 "register_operand" "%f")
4005                 (parallel [(const_int 0) (const_int 2)
4006                            (const_int 4) (const_int 6)
4007                            (const_int 8) (const_int 10)
4008                            (const_int 12) (const_int 14)])))
4009             (sign_extend:V8HI
4010               (vec_select:V8QI
4011                 (match_operand:V16QI 3 "register_operand" "f")
4012                 (parallel [(const_int 0) (const_int 2)
4013                            (const_int 4) (const_int 6)
4014                            (const_int 8) (const_int 10)
4015                            (const_int 12) (const_int 14)]))))))]
4016   "ISA_HAS_LSX"
4017   "vmaddwev.h.bu.b\t%w0,%w2,%w3"
4018   [(set_attr "type" "simd_fmadd")
4019    (set_attr "mode" "V8HI")])
4020
4021 (define_insn "lsx_vmaddwod_d_wu_w"
4022   [(set (match_operand:V2DI 0 "register_operand" "=f")
4023         (plus:V2DI
4024           (match_operand:V2DI 1 "register_operand" "0")
4025           (mult:V2DI
4026             (zero_extend:V2DI
4027               (vec_select:V2SI
4028                 (match_operand:V4SI 2 "register_operand" "%f")
4029                 (parallel [(const_int 1) (const_int 3)])))
4030             (sign_extend:V2DI
4031               (vec_select:V2SI
4032                 (match_operand:V4SI 3 "register_operand" "f")
4033                 (parallel [(const_int 1) (const_int 3)]))))))]
4034   "ISA_HAS_LSX"
4035   "vmaddwod.d.wu.w\t%w0,%w2,%w3"
4036   [(set_attr "type" "simd_fmadd")
4037    (set_attr "mode" "V2DI")])
4038
4039 (define_insn "lsx_vmaddwod_w_hu_h"
4040   [(set (match_operand:V4SI 0 "register_operand" "=f")
4041         (plus:V4SI
4042           (match_operand:V4SI 1 "register_operand" "0")
4043           (mult:V4SI
4044             (zero_extend:V4SI
4045               (vec_select:V4HI
4046                 (match_operand:V8HI 2 "register_operand" "%f")
4047                 (parallel [(const_int 1) (const_int 3)
4048                            (const_int 5) (const_int 7)])))
4049             (sign_extend:V4SI
4050               (vec_select:V4HI
4051                 (match_operand:V8HI 3 "register_operand" "f")
4052                 (parallel [(const_int 1) (const_int 3)
4053                            (const_int 5) (const_int 7)]))))))]
4054   "ISA_HAS_LSX"
4055   "vmaddwod.w.hu.h\t%w0,%w2,%w3"
4056   [(set_attr "type" "simd_fmadd")
4057    (set_attr "mode" "V4SI")])
4058
4059 (define_insn "lsx_vmaddwod_h_bu_b"
4060   [(set (match_operand:V8HI 0 "register_operand" "=f")
4061         (plus:V8HI
4062           (match_operand:V8HI 1 "register_operand" "0")
4063           (mult:V8HI
4064             (zero_extend:V8HI
4065               (vec_select:V8QI
4066                 (match_operand:V16QI 2 "register_operand" "%f")
4067                 (parallel [(const_int 1) (const_int 3)
4068                            (const_int 5) (const_int 7)
4069                            (const_int 9) (const_int 11)
4070                            (const_int 13) (const_int 15)])))
4071             (sign_extend:V8HI
4072               (vec_select:V8QI
4073                 (match_operand:V16QI 3 "register_operand" "f")
4074                 (parallel [(const_int 1) (const_int 3)
4075                            (const_int 5) (const_int 7)
4076                            (const_int 9) (const_int 11)
4077                            (const_int 13) (const_int 15)]))))))]
4078   "ISA_HAS_LSX"
4079   "vmaddwod.h.bu.b\t%w0,%w2,%w3"
4080   [(set_attr "type" "simd_fmadd")
4081    (set_attr "mode" "V8HI")])
4082
4083 (define_insn "lsx_vmaddwev_q_d"
4084   [(set (match_operand:V2DI 0 "register_operand" "=f")
4085         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4086                       (match_operand:V2DI 2 "register_operand" "f")
4087                       (match_operand:V2DI 3 "register_operand" "f")]
4088                      UNSPEC_LSX_VMADDWEV))]
4089   "ISA_HAS_LSX"
4090   "vmaddwev.q.d\t%w0,%w2,%w3"
4091   [(set_attr "type" "simd_int_arith")
4092    (set_attr "mode" "V2DI")])
4093
4094 (define_insn "lsx_vmaddwod_q_d"
4095   [(set (match_operand:V2DI 0 "register_operand" "=f")
4096         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4097                       (match_operand:V2DI 2 "register_operand" "f")
4098                       (match_operand:V2DI 3 "register_operand" "f")]
4099                      UNSPEC_LSX_VMADDWOD))]
4100   "ISA_HAS_LSX"
4101   "vmaddwod.q.d\t%w0,%w2,%w3"
4102   [(set_attr "type" "simd_int_arith")
4103    (set_attr "mode" "V2DI")])
4104
4105 (define_insn "lsx_vmaddwev_q_du"
4106   [(set (match_operand:V2DI 0 "register_operand" "=f")
4107         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4108                       (match_operand:V2DI 2 "register_operand" "f")
4109                       (match_operand:V2DI 3 "register_operand" "f")]
4110                      UNSPEC_LSX_VMADDWEV2))]
4111   "ISA_HAS_LSX"
4112   "vmaddwev.q.du\t%w0,%w2,%w3"
4113   [(set_attr "type" "simd_int_arith")
4114    (set_attr "mode" "V2DI")])
4115
4116 (define_insn "lsx_vmaddwod_q_du"
4117   [(set (match_operand:V2DI 0 "register_operand" "=f")
4118         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4119                       (match_operand:V2DI 2 "register_operand" "f")
4120                       (match_operand:V2DI 3 "register_operand" "f")]
4121                      UNSPEC_LSX_VMADDWOD2))]
4122   "ISA_HAS_LSX"
4123   "vmaddwod.q.du\t%w0,%w2,%w3"
4124   [(set_attr "type" "simd_int_arith")
4125    (set_attr "mode" "V2DI")])
4126
4127 (define_insn "lsx_vmaddwev_q_du_d"
4128   [(set (match_operand:V2DI 0 "register_operand" "=f")
4129         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4130                       (match_operand:V2DI 2 "register_operand" "f")
4131                       (match_operand:V2DI 3 "register_operand" "f")]
4132                      UNSPEC_LSX_VMADDWEV3))]
4133   "ISA_HAS_LSX"
4134   "vmaddwev.q.du.d\t%w0,%w2,%w3"
4135   [(set_attr "type" "simd_int_arith")
4136    (set_attr "mode" "V2DI")])
4137
4138 (define_insn "lsx_vmaddwod_q_du_d"
4139   [(set (match_operand:V2DI 0 "register_operand" "=f")
4140         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
4141                       (match_operand:V2DI 2 "register_operand" "f")
4142                       (match_operand:V2DI 3 "register_operand" "f")]
4143                      UNSPEC_LSX_VMADDWOD3))]
4144   "ISA_HAS_LSX"
4145   "vmaddwod.q.du.d\t%w0,%w2,%w3"
4146   [(set_attr "type" "simd_int_arith")
4147    (set_attr "mode" "V2DI")])
4148
4149 (define_insn "lsx_vadd_q"
4150   [(set (match_operand:V2DI 0 "register_operand" "=f")
4151         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
4152                       (match_operand:V2DI 2 "register_operand" "f")]
4153                      UNSPEC_LSX_VADD_Q))]
4154   "ISA_HAS_LSX"
4155   "vadd.q\t%w0,%w1,%w2"
4156   [(set_attr "type" "simd_int_arith")
4157    (set_attr "mode" "V2DI")])
4158
4159 (define_insn "lsx_vsub_q"
4160   [(set (match_operand:V2DI 0 "register_operand" "=f")
4161         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")
4162                       (match_operand:V2DI 2 "register_operand" "f")]
4163                      UNSPEC_LSX_VSUB_Q))]
4164   "ISA_HAS_LSX"
4165   "vsub.q\t%w0,%w1,%w2"
4166   [(set_attr "type" "simd_int_arith")
4167    (set_attr "mode" "V2DI")])
4168
4169 (define_insn "lsx_vmskgez_b"
4170   [(set (match_operand:V16QI 0 "register_operand" "=f")
4171         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "f")]
4172                       UNSPEC_LSX_VMSKGEZ))]
4173   "ISA_HAS_LSX"
4174   "vmskgez.b\t%w0,%w1"
4175   [(set_attr "type" "simd_bit")
4176    (set_attr "mode" "V16QI")])
4177
4178 (define_insn "lsx_vmsknz_b"
4179   [(set (match_operand:V16QI 0 "register_operand" "=f")
4180         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "f")]
4181                       UNSPEC_LSX_VMSKNZ))]
4182   "ISA_HAS_LSX"
4183   "vmsknz.b\t%w0,%w1"
4184   [(set_attr "type" "simd_bit")
4185    (set_attr "mode" "V16QI")])
4186
4187 (define_insn "lsx_vexth_h<u>_b<u>"
4188   [(set (match_operand:V8HI 0 "register_operand" "=f")
4189         (any_extend:V8HI
4190           (vec_select:V8QI
4191             (match_operand:V16QI 1 "register_operand" "f")
4192             (parallel [(const_int 8) (const_int 9)
4193                        (const_int 10) (const_int 11)
4194                        (const_int 12) (const_int 13)
4195                        (const_int 14) (const_int 15)]))))]
4196   "ISA_HAS_LSX"
4197   "vexth.h<u>.b<u>\t%w0,%w1"
4198   [(set_attr "type" "simd_fcvt")
4199    (set_attr "mode" "V8HI")])
4200
4201 (define_insn "lsx_vexth_w<u>_h<u>"
4202   [(set (match_operand:V4SI 0 "register_operand" "=f")
4203         (any_extend:V4SI
4204           (vec_select:V4HI
4205             (match_operand:V8HI 1 "register_operand" "f")
4206             (parallel [(const_int 4) (const_int 5)
4207                        (const_int 6) (const_int 7)]))))]
4208   "ISA_HAS_LSX"
4209   "vexth.w<u>.h<u>\t%w0,%w1"
4210   [(set_attr "type" "simd_fcvt")
4211    (set_attr "mode" "V4SI")])
4212
4213 (define_insn "lsx_vexth_d<u>_w<u>"
4214   [(set (match_operand:V2DI 0 "register_operand" "=f")
4215         (any_extend:V2DI
4216           (vec_select:V2SI
4217             (match_operand:V4SI 1 "register_operand" "f")
4218             (parallel [(const_int 2) (const_int 3)]))))]
4219   "ISA_HAS_LSX"
4220   "vexth.d<u>.w<u>\t%w0,%w1"
4221   [(set_attr "type" "simd_fcvt")
4222    (set_attr "mode" "V2DI")])
4223
4224 (define_insn "lsx_vexth_q_d"
4225   [(set (match_operand:V2DI 0 "register_operand" "=f")
4226         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")]
4227                      UNSPEC_LSX_VEXTH_Q_D))]
4228   "ISA_HAS_LSX"
4229   "vexth.q.d\t%w0,%w1"
4230   [(set_attr "type" "simd_fcvt")
4231    (set_attr "mode" "V2DI")])
4232
4233 (define_insn "lsx_vexth_qu_du"
4234   [(set (match_operand:V2DI 0 "register_operand" "=f")
4235         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")]
4236                      UNSPEC_LSX_VEXTH_QU_DU))]
4237   "ISA_HAS_LSX"
4238   "vexth.qu.du\t%w0,%w1"
4239   [(set_attr "type" "simd_fcvt")
4240    (set_attr "mode" "V2DI")])
4241
4242 (define_insn "lsx_vextl_q_d"
4243   [(set (match_operand:V2DI 0 "register_operand" "=f")
4244         (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "f")]
4245                      UNSPEC_LSX_VEXTL_Q_D))]
4246   "ISA_HAS_LSX"
4247   "vextl.q.d\t%w0,%w1"
4248   [(set_attr "type" "simd_fcvt")
4249    (set_attr "mode" "V2DI")])
4250
4251 (define_insn "lsx_vsrlni_<lsxfmt>_<dlsxfmt>"
4252   [(set (match_operand:ILSX 0 "register_operand" "=f")
4253         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4254                       (match_operand:ILSX 2 "register_operand" "f")
4255                       (match_operand 3 "const_uimm8_operand" "")]
4256                      UNSPEC_LSX_VSRLNI))]
4257   "ISA_HAS_LSX"
4258   "vsrlni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4259   [(set_attr "type" "simd_shift")
4260    (set_attr "mode" "<MODE>")])
4261
4262 (define_insn "lsx_vsrlrni_<lsxfmt>_<dlsxfmt>"
4263   [(set (match_operand:ILSX 0 "register_operand" "=f")
4264         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4265                       (match_operand:ILSX 2 "register_operand" "f")
4266                       (match_operand 3 "const_uimm8_operand" "")]
4267                      UNSPEC_LSX_VSRLRNI))]
4268   "ISA_HAS_LSX"
4269   "vsrlrni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4270   [(set_attr "type" "simd_shift")
4271    (set_attr "mode" "<MODE>")])
4272
4273 (define_insn "lsx_vssrlni_<lsxfmt>_<dlsxfmt>"
4274   [(set (match_operand:ILSX 0 "register_operand" "=f")
4275         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4276                       (match_operand:ILSX 2 "register_operand" "f")
4277                       (match_operand 3 "const_uimm8_operand" "")]
4278                      UNSPEC_LSX_VSSRLNI))]
4279   "ISA_HAS_LSX"
4280   "vssrlni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4281   [(set_attr "type" "simd_shift")
4282    (set_attr "mode" "<MODE>")])
4283
4284 (define_insn "lsx_vssrlni_<lsxfmt_u>_<dlsxfmt>"
4285   [(set (match_operand:ILSX 0 "register_operand" "=f")
4286         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4287                       (match_operand:ILSX 2 "register_operand" "f")
4288                       (match_operand 3 "const_uimm8_operand" "")]
4289                      UNSPEC_LSX_VSSRLNI2))]
4290   "ISA_HAS_LSX"
4291   "vssrlni.<lsxfmt_u>.<dlsxfmt>\t%w0,%w2,%3"
4292   [(set_attr "type" "simd_shift")
4293    (set_attr "mode" "<MODE>")])
4294
4295 (define_insn "lsx_vssrlrni_<lsxfmt>_<dlsxfmt>"
4296   [(set (match_operand:ILSX 0 "register_operand" "=f")
4297         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4298                       (match_operand:ILSX 2 "register_operand" "f")
4299                       (match_operand 3 "const_uimm8_operand" "")]
4300                      UNSPEC_LSX_VSSRLRNI))]
4301   "ISA_HAS_LSX"
4302   "vssrlrni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4303   [(set_attr "type" "simd_shift")
4304    (set_attr "mode" "<MODE>")])
4305
4306 (define_insn "lsx_vssrlrni_<lsxfmt_u>_<dlsxfmt>"
4307   [(set (match_operand:ILSX 0 "register_operand" "=f")
4308         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4309                       (match_operand:ILSX 2 "register_operand" "f")
4310                       (match_operand 3 "const_uimm8_operand" "")]
4311                      UNSPEC_LSX_VSSRLRNI2))]
4312   "ISA_HAS_LSX"
4313   "vssrlrni.<lsxfmt_u>.<dlsxfmt>\t%w0,%w2,%3"
4314   [(set_attr "type" "simd_shift")
4315    (set_attr "mode" "<MODE>")])
4316
4317 (define_insn "lsx_vsrani_<lsxfmt>_<dlsxfmt>"
4318   [(set (match_operand:ILSX 0 "register_operand" "=f")
4319         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4320                       (match_operand:ILSX 2 "register_operand" "f")
4321                       (match_operand 3 "const_uimm8_operand" "")]
4322                      UNSPEC_LSX_VSRANI))]
4323   "ISA_HAS_LSX"
4324   "vsrani.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4325   [(set_attr "type" "simd_shift")
4326    (set_attr "mode" "<MODE>")])
4327
4328 (define_insn "lsx_vsrarni_<lsxfmt>_<dlsxfmt>"
4329   [(set (match_operand:ILSX 0 "register_operand" "=f")
4330         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4331                       (match_operand:ILSX 2 "register_operand" "f")
4332                       (match_operand 3 "const_uimm8_operand" "")]
4333                      UNSPEC_LSX_VSRARNI))]
4334   "ISA_HAS_LSX"
4335   "vsrarni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4336   [(set_attr "type" "simd_shift")
4337    (set_attr "mode" "<MODE>")])
4338
4339 (define_insn "lsx_vssrani_<lsxfmt>_<dlsxfmt>"
4340   [(set (match_operand:ILSX 0 "register_operand" "=f")
4341         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4342                       (match_operand:ILSX 2 "register_operand" "f")
4343                       (match_operand 3 "const_uimm8_operand" "")]
4344                     UNSPEC_LSX_VSSRANI))]
4345   "ISA_HAS_LSX"
4346   "vssrani.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4347   [(set_attr "type" "simd_shift")
4348    (set_attr "mode" "<MODE>")])
4349
4350 (define_insn "lsx_vssrani_<lsxfmt_u>_<dlsxfmt>"
4351   [(set (match_operand:ILSX 0 "register_operand" "=f")
4352         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4353                       (match_operand:ILSX 2 "register_operand" "f")
4354                       (match_operand 3 "const_uimm8_operand" "")]
4355                      UNSPEC_LSX_VSSRANI2))]
4356   "ISA_HAS_LSX"
4357   "vssrani.<lsxfmt_u>.<dlsxfmt>\t%w0,%w2,%3"
4358   [(set_attr "type" "simd_shift")
4359    (set_attr "mode" "<MODE>")])
4360
4361 (define_insn "lsx_vssrarni_<lsxfmt>_<dlsxfmt>"
4362   [(set (match_operand:ILSX 0 "register_operand" "=f")
4363         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4364                       (match_operand:ILSX 2 "register_operand" "f")
4365                       (match_operand 3 "const_uimm8_operand" "")]
4366                      UNSPEC_LSX_VSSRARNI))]
4367   "ISA_HAS_LSX"
4368   "vssrarni.<lsxfmt>.<dlsxfmt>\t%w0,%w2,%3"
4369   [(set_attr "type" "simd_shift")
4370    (set_attr "mode" "<MODE>")])
4371
4372 (define_insn "lsx_vssrarni_<lsxfmt_u>_<dlsxfmt>"
4373   [(set (match_operand:ILSX 0 "register_operand" "=f")
4374         (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "0")
4375                       (match_operand:ILSX 2 "register_operand" "f")
4376                       (match_operand 3 "const_uimm8_operand" "")]
4377                      UNSPEC_LSX_VSSRARNI2))]
4378   "ISA_HAS_LSX"
4379   "vssrarni.<lsxfmt_u>.<dlsxfmt>\t%w0,%w2,%3"
4380   [(set_attr "type" "simd_shift")
4381    (set_attr "mode" "<MODE>")])
4382
4383 (define_insn "lsx_vpermi_w"
4384   [(set (match_operand:V4SI 0 "register_operand" "=f")
4385         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
4386                       (match_operand:V4SI 2 "register_operand" "f")
4387                       (match_operand 3 "const_uimm8_operand" "")]
4388                      UNSPEC_LSX_VPERMI))]
4389   "ISA_HAS_LSX"
4390   "vpermi.w\t%w0,%w2,%3"
4391   [(set_attr "type" "simd_bit")
4392    (set_attr "mode" "V4SI")])
4393
4394 ;; Delete one of two instructions that exactly play the same role.
4395 (define_peephole2
4396   [(set (match_operand:V2DI 0 "register_operand")
4397         (vec_duplicate:V2DI (match_operand:DI 1 "register_operand")))
4398    (set (match_operand:V2DI 2 "register_operand")
4399         (vec_merge:V2DI
4400           (vec_duplicate:V2DI (match_operand:DI 3 "register_operand"))
4401           (match_operand:V2DI 4 "register_operand")
4402           (match_operand 5 "const_int_operand")))]
4403   "operands[0] == operands[2] &&
4404    operands[1] == operands[3] &&
4405    operands[2] == operands[4] &&
4406    INTVAL (operands[5]) == 2"
4407   [(set (match_dup 0)
4408         (vec_duplicate:V2DI (match_dup 1)))]
4409   "")