1 ;; Predicate definitions for LoongArch target.
2 ;; Copyright (C) 2021-2024 Free Software Foundation, Inc.
3 ;; Contributed by Loongson Ltd.
4 ;; Based on MIPS target for GNU compiler.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_predicate "const_uns_arith_operand"
23 (and (match_code "const_int")
24 (match_test "IMM12_OPERAND_UNSIGNED (INTVAL (op))")))
26 (define_predicate "uns_arith_operand"
27 (ior (match_operand 0 "const_uns_arith_operand")
28 (match_operand 0 "register_operand")))
30 (define_predicate "const_lu32i_operand"
31 (and (match_code "const_int")
32 (match_test "LU32I_OPERAND (INTVAL (op))")))
34 (define_predicate "const_lu52i_operand"
35 (and (match_code "const_int")
36 (match_test "LU52I_OPERAND (INTVAL (op))")))
38 (define_predicate "const_arith_operand"
39 (and (match_code "const_int")
40 (match_test "IMM12_OPERAND (INTVAL (op))")))
42 (define_predicate "const_dual_imm12_operand"
43 (and (match_code "const_int")
44 (match_test "DUAL_IMM12_OPERAND (INTVAL (op))")))
46 (define_predicate "const_imm16_operand"
47 (and (match_code "const_int")
48 (match_test "IMM16_OPERAND (INTVAL (op))")))
50 (define_predicate "const_addu16i_operand"
51 (and (match_code "const_int")
52 (match_test "ADDU16I_OPERAND (INTVAL (op))")))
54 (define_predicate "const_addu16i_imm12_di_operand"
55 (and (match_code "const_int")
56 (match_test "loongarch_addu16i_imm12_operand_p (INTVAL (op), DImode)")))
58 (define_predicate "const_addu16i_imm12_si_operand"
59 (and (match_code "const_int")
60 (match_test "loongarch_addu16i_imm12_operand_p (INTVAL (op), SImode)")))
62 (define_predicate "const_dual_addu16i_operand"
63 (and (match_code "const_int")
64 (match_test "DUAL_ADDU16I_OPERAND (INTVAL (op))")))
66 (define_predicate "arith_operand"
67 (ior (match_operand 0 "const_arith_operand")
68 (match_operand 0 "register_operand")))
70 (define_predicate "plus_di_operand"
71 (ior (match_operand 0 "arith_operand")
72 (match_operand 0 "const_dual_imm12_operand")
73 (match_operand 0 "const_addu16i_operand")
74 (match_operand 0 "const_addu16i_imm12_di_operand")
75 (match_operand 0 "const_dual_addu16i_operand")))
77 (define_predicate "plus_si_extend_operand"
78 (ior (match_operand 0 "arith_operand")
79 (match_operand 0 "const_dual_imm12_operand")
80 (match_operand 0 "const_addu16i_imm12_si_operand")))
82 (define_predicate "plus_si_operand"
83 (ior (match_operand 0 "plus_si_extend_operand")
84 (match_operand 0 "const_addu16i_operand")))
86 (define_predicate "const_immalsl_operand"
87 (and (match_code "const_int")
88 (match_test "IN_RANGE (INTVAL (op), 1, 4)")))
90 (define_predicate "const_lsx_branch_operand"
91 (and (match_code "const_int")
92 (match_test "IN_RANGE (INTVAL (op), -1024, 1023)")))
94 (define_predicate "const_uimm3_operand"
95 (and (match_code "const_int")
96 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
98 (define_predicate "const_8_to_11_operand"
99 (and (match_code "const_int")
100 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
102 (define_predicate "const_12_to_15_operand"
103 (and (match_code "const_int")
104 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
106 (define_predicate "const_uimm4_operand"
107 (and (match_code "const_int")
108 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
110 (define_predicate "const_uimm5_operand"
111 (and (match_code "const_int")
112 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
114 (define_predicate "const_uimm6_operand"
115 (and (match_code "const_int")
116 (match_test "UIMM6_OPERAND (INTVAL (op))")))
118 (define_predicate "const_uimm7_operand"
119 (and (match_code "const_int")
120 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
122 (define_predicate "const_uimm8_operand"
123 (and (match_code "const_int")
124 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
126 (define_predicate "const_uimm14_operand"
127 (and (match_code "const_int")
128 (match_test "IN_RANGE (INTVAL (op), 0, 16383)")))
130 (define_predicate "const_uimm15_operand"
131 (and (match_code "const_int")
132 (match_test "IN_RANGE (INTVAL (op), 0, 32767)")))
134 (define_predicate "const_imm5_operand"
135 (and (match_code "const_int")
136 (match_test "IN_RANGE (INTVAL (op), -16, 15)")))
138 (define_predicate "const_imm10_operand"
139 (and (match_code "const_int")
140 (match_test "IMM10_OPERAND (INTVAL (op))")))
142 (define_predicate "const_imm12_operand"
143 (and (match_code "const_int")
144 (match_test "IMM12_OPERAND (INTVAL (op))")))
146 (define_predicate "const_imm13_operand"
147 (and (match_code "const_int")
148 (match_test "IMM13_OPERAND (INTVAL (op))")))
150 (define_predicate "reg_imm10_operand"
151 (ior (match_operand 0 "const_imm10_operand")
152 (match_operand 0 "register_operand")))
154 (define_predicate "aq8b_operand"
155 (and (match_code "const_int")
156 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 0)")))
158 (define_predicate "aq8h_operand"
159 (and (match_code "const_int")
160 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 1)")))
162 (define_predicate "aq8w_operand"
163 (and (match_code "const_int")
164 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 2)")))
166 (define_predicate "aq8d_operand"
167 (and (match_code "const_int")
168 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 3)")))
170 (define_predicate "aq10b_operand"
171 (and (match_code "const_int")
172 (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 0)")))
174 (define_predicate "aq10h_operand"
175 (and (match_code "const_int")
176 (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 1)")))
178 (define_predicate "aq10w_operand"
179 (and (match_code "const_int")
180 (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 2)")))
182 (define_predicate "aq10d_operand"
183 (and (match_code "const_int")
184 (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 3)")))
186 (define_predicate "aq12b_operand"
187 (and (match_code "const_int")
188 (match_test "loongarch_signed_immediate_p (INTVAL (op), 12, 0)")))
190 (define_predicate "aq12h_operand"
191 (and (match_code "const_int")
192 (match_test "loongarch_signed_immediate_p (INTVAL (op), 11, 1)")))
194 (define_predicate "aq12w_operand"
195 (and (match_code "const_int")
196 (match_test "loongarch_signed_immediate_p (INTVAL (op), 10, 2)")))
198 (define_predicate "aq12d_operand"
199 (and (match_code "const_int")
200 (match_test "loongarch_signed_immediate_p (INTVAL (op), 9, 3)")))
202 (define_predicate "sle_operand"
203 (and (match_code "const_int")
204 (match_test "IMM12_OPERAND (INTVAL (op) + 1)")))
206 (define_predicate "sleu_operand"
207 (and (match_operand 0 "sle_operand")
208 (match_test "INTVAL (op) + 1 != 0")))
210 (define_predicate "const_0_operand"
211 (and (match_code "const_int,const_wide_int,const_double,const_vector")
212 (match_test "op == CONST0_RTX (GET_MODE (op))")))
214 (define_predicate "const_m1_operand"
215 (and (match_code "const_int,const_wide_int,const_double,const_vector")
216 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
218 (define_predicate "reg_or_m1_operand"
219 (ior (match_operand 0 "const_m1_operand")
220 (match_operand 0 "register_operand")))
222 (define_predicate "reg_or_0_operand"
223 (ior (match_operand 0 "const_0_operand")
224 (match_operand 0 "register_operand")))
226 (define_predicate "const_1_operand"
227 (and (match_code "const_int,const_wide_int,const_double,const_vector")
228 (match_test "op == CONST1_RTX (GET_MODE (op))")))
230 (define_predicate "const_vector_1_operand"
231 (and (match_code "const_vector")
232 (match_test "op == CONST1_RTX (GET_MODE (op))")))
234 (define_predicate "reg_or_1_operand"
235 (ior (match_operand 0 "const_1_operand")
236 (match_operand 0 "register_operand")))
238 (define_predicate "reg_or_vecotr_1_operand"
239 (ior (match_operand 0 "const_vector_1_operand")
240 (match_operand 0 "register_operand")))
242 ;; These are used in vec_merge, hence accept bitmask as const_int.
243 (define_predicate "const_exp_2_operand"
244 (and (match_code "const_int")
245 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 1)")))
247 (define_predicate "const_exp_4_operand"
248 (and (match_code "const_int")
249 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 3)")))
251 (define_predicate "const_exp_8_operand"
252 (and (match_code "const_int")
253 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 7)")))
255 (define_predicate "const_exp_16_operand"
256 (and (match_code "const_int")
257 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 15)")))
259 (define_predicate "const_exp_32_operand"
260 (and (match_code "const_int")
261 (match_test "IN_RANGE (exact_log2 (INTVAL (op)), 0, 31)")))
263 ;; This is used for indexing into vectors, and hence only accepts const_int.
264 (define_predicate "const_0_or_1_operand"
265 (and (match_code "const_int")
266 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
268 (define_predicate "const_0_to_3_operand"
269 (and (match_code "const_int")
270 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
272 (define_predicate "const_0_to_7_operand"
273 (and (match_code "const_int")
274 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
276 (define_predicate "const_2_or_3_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
280 (define_predicate "const_4_to_7_operand"
281 (and (match_code "const_int")
282 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
284 (define_predicate "const_8_to_15_operand"
285 (and (match_code "const_int")
286 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
288 (define_predicate "const_16_to_31_operand"
289 (and (match_code "const_int")
290 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
292 (define_predicate "qi_mask_operand"
293 (and (match_code "const_int")
294 (match_test "UINTVAL (op) == 0xff")))
296 (define_predicate "hi_mask_operand"
297 (and (match_code "const_int")
298 (match_test "UINTVAL (op) == 0xffff")))
300 (define_predicate "lu52i_mask_operand"
301 (and (match_code "const_int")
302 (match_test "UINTVAL (op) == 0xfffffffffffff")))
304 (define_predicate "si_mask_operand"
305 (and (match_code "const_int")
306 (match_test "UINTVAL (op) == 0xffffffff")))
308 (define_predicate "low_bitmask_operand"
309 (and (match_code "const_int")
310 (match_test "low_bitmask_len (mode, INTVAL (op)) > 12")))
312 (define_predicate "d_operand"
313 (and (match_code "reg")
314 (match_test "GP_REG_P (REGNO (op))")))
316 (define_predicate "db4_operand"
317 (and (match_code "const_int")
318 (match_test "loongarch_unsigned_immediate_p (INTVAL (op) + 1, 4, 0)")))
320 (define_predicate "db7_operand"
321 (and (match_code "const_int")
322 (match_test "loongarch_unsigned_immediate_p (INTVAL (op) + 1, 7, 0)")))
324 (define_predicate "db8_operand"
325 (and (match_code "const_int")
326 (match_test "loongarch_unsigned_immediate_p (INTVAL (op) + 1, 8, 0)")))
328 (define_predicate "ib3_operand"
329 (and (match_code "const_int")
330 (match_test "loongarch_unsigned_immediate_p (INTVAL (op) - 1, 3, 0)")))
332 (define_predicate "sb4_operand"
333 (and (match_code "const_int")
334 (match_test "loongarch_signed_immediate_p (INTVAL (op), 4, 0)")))
336 (define_predicate "sb5_operand"
337 (and (match_code "const_int")
338 (match_test "loongarch_signed_immediate_p (INTVAL (op), 5, 0)")))
340 (define_predicate "sb8_operand"
341 (and (match_code "const_int")
342 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 0)")))
344 (define_predicate "sd8_operand"
345 (and (match_code "const_int")
346 (match_test "loongarch_signed_immediate_p (INTVAL (op), 8, 3)")))
348 (define_predicate "ub4_operand"
349 (and (match_code "const_int")
350 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 4, 0)")))
352 (define_predicate "ub8_operand"
353 (and (match_code "const_int")
354 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 8, 0)")))
356 (define_predicate "uh4_operand"
357 (and (match_code "const_int")
358 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 4, 1)")))
360 (define_predicate "uw4_operand"
361 (and (match_code "const_int")
362 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 4, 2)")))
364 (define_predicate "uw5_operand"
365 (and (match_code "const_int")
366 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 5, 2)")))
368 (define_predicate "uw6_operand"
369 (and (match_code "const_int")
370 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 6, 2)")))
372 (define_predicate "uw8_operand"
373 (and (match_code "const_int")
374 (match_test "loongarch_unsigned_immediate_p (INTVAL (op), 8, 2)")))
376 (define_predicate "addiur2_operand"
377 (and (match_code "const_int")
378 (ior (match_test "INTVAL (op) == -1")
379 (match_test "INTVAL (op) == 1")
380 (match_test "INTVAL (op) == 4")
381 (match_test "INTVAL (op) == 8")
382 (match_test "INTVAL (op) == 12")
383 (match_test "INTVAL (op) == 16")
384 (match_test "INTVAL (op) == 20")
385 (match_test "INTVAL (op) == 24"))))
387 (define_predicate "addiusp_operand"
388 (and (match_code "const_int")
389 (ior (match_test "(IN_RANGE (INTVAL (op), 2, 257))")
390 (match_test "(IN_RANGE (INTVAL (op), -258, -3))"))))
392 (define_predicate "andi16_operand"
393 (and (match_code "const_int")
394 (ior (match_test "IN_RANGE (INTVAL (op), 1, 4)")
395 (match_test "IN_RANGE (INTVAL (op), 7, 8)")
396 (match_test "IN_RANGE (INTVAL (op), 15, 16)")
397 (match_test "IN_RANGE (INTVAL (op), 31, 32)")
398 (match_test "IN_RANGE (INTVAL (op), 63, 64)")
399 (match_test "INTVAL (op) == 255")
400 (match_test "INTVAL (op) == 32768")
401 (match_test "INTVAL (op) == 65535"))))
403 (define_predicate "movep_src_register"
404 (and (match_code "reg")
405 (ior (match_test ("IN_RANGE (REGNO (op), 2, 3)"))
406 (match_test ("IN_RANGE (REGNO (op), 16, 20)")))))
408 (define_predicate "movep_src_operand"
409 (ior (match_operand 0 "const_0_operand")
410 (match_operand 0 "movep_src_register")))
412 (define_predicate "fcc_reload_operand"
413 (and (match_code "reg,subreg")
414 (match_test "FCC_REG_P (true_regnum (op))")))
416 (define_predicate "muldiv_target_operand"
417 (match_operand 0 "register_operand"))
419 (define_predicate "ins_zero_bitmask_operand"
420 (and (match_code "const_int")
421 (match_test "INTVAL (op) != -1")
422 (match_test "INTVAL (op) & 1")
423 (match_test "low_bitmask_len (mode, \
424 ~UINTVAL (op) | (~UINTVAL(op) - 1)) \
427 (define_predicate "const_call_insn_operand"
428 (match_code "const,symbol_ref,label_ref")
430 /* Split symbol to high and low if return false.
431 If defined TARGET_CMODEL_EXTREME, all symbol would be splited,
432 else if offset is not zero, the symbol would be splited. */
434 enum loongarch_symbol_type symbol_type;
435 loongarch_symbolic_constant_p (op, &symbol_type);
438 split_const (x, &x, &offset);
440 if (offset != const0_rtx)
443 /* When compiling with '-mcmodel=medium -mexplicit-relocs'
444 symbols are splited in loongarch_legitimize_call_address.
446 When compiling with '-mcmodel=medium -mno-explicit-relocs',
447 first obtain the symbolic address or the address of the
448 plt entry, and then perform an indirect jump, so return false. */
453 if (TARGET_CMODEL_EXTREME
454 || (TARGET_CMODEL_MEDIUM
455 && (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)))
460 case SYMBOL_GOT_DISP:
461 if (TARGET_CMODEL_EXTREME
463 || (flag_plt && TARGET_CMODEL_MEDIUM
464 && (la_opt_explicit_relocs == EXPLICIT_RELOCS_NONE)))
474 (define_predicate "call_insn_operand"
475 (ior (match_operand 0 "const_call_insn_operand")
476 (match_operand 0 "register_operand")))
478 (define_predicate "is_const_call_local_symbol"
479 (and (match_operand 0 "const_call_insn_operand")
480 (ior (match_test "loongarch_global_symbol_p (op) == 0")
481 (match_test "loongarch_symbol_binds_local_p (op) != 0"))
482 (match_test "CONSTANT_P (op)")))
484 (define_predicate "is_const_call_no_local_symbol"
485 (and (match_operand 0 "const_call_insn_operand")
486 (ior (match_test "loongarch_global_symbol_p (op) != 0")
487 (match_test "loongarch_symbol_binds_local_p (op) == 0")
488 (match_test "loongarch_weak_symbol_p (op) != 0"))
489 (match_test "CONSTANT_P (op)")))
491 ;; A legitimate CONST_INT operand that takes more than one instruction
493 (define_predicate "splittable_const_int_operand"
494 (match_code "const_int")
496 /* Don't handle multi-word moves this way; we don't want to introduce
497 the individual word-mode moves until after reload. */
498 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
501 /* Otherwise check whether the constant can be loaded in a single
503 return !LU12I_INT (op) && !IMM12_INT (op) && !IMM12_INT_UNSIGNED (op)
507 (define_predicate "move_operand"
508 (match_operand 0 "general_operand")
510 enum loongarch_symbol_type symbol_type;
512 /* The thinking here is as follows:
514 (1) The move expanders should split complex load sequences into
515 individual instructions. Those individual instructions can
516 then be optimized by all rtl passes.
518 (2) The target of pre-reload load sequences should not be used
519 to store temporary results. If the target register is only
520 assigned one value, reload can rematerialize that value
521 on demand, rather than spill it to the stack.
523 (3) If we allowed pre-reload passes like combine and cse to recreate
524 complex load sequences, we would want to be able to split the
525 sequences before reload as well, so that the pre-reload scheduler
526 can see the individual instructions. This falls foul of (2);
527 the splitter would be forced to reuse the target register for
528 intermediate results.
530 (4) We want to define complex load splitters for combine. These
531 splitters can request a temporary scratch register, which avoids
532 the problem in (2). They allow things like:
534 (set (reg T1) (high SYM))
535 (set (reg T2) (low (reg T1) SYM))
536 (set (reg X) (plus (reg T2) (const_int OFFSET)))
540 (set (reg T3) (high SYM+OFFSET))
541 (set (reg X) (lo_sum (reg T3) SYM+OFFSET))
543 if T2 is only used this once. */
544 switch (GET_CODE (op))
552 return (loongarch_symbolic_constant_p (op, &symbol_type)
553 && (!loongarch_explicit_relocs_p (symbol_type)
554 || !loongarch_split_symbol_type (symbol_type)));
559 return (loongarch_symbolic_constant_p (op, &symbol_type)
560 && loongarch_explicit_relocs_p (symbol_type)
561 && loongarch_split_symbol_type (symbol_type));
568 (define_predicate "symbolic_operand"
569 (match_code "const,symbol_ref,label_ref")
571 enum loongarch_symbol_type type;
572 return loongarch_symbolic_constant_p (op, &type);
575 (define_predicate "symbolic_pcrel_operand"
576 (match_code "const,symbol_ref,label_ref")
578 enum loongarch_symbol_type type;
579 return loongarch_symbolic_constant_p (op, &type) && type == SYMBOL_PCREL;
582 (define_predicate "symbolic_pcrel_offset_operand"
583 (and (match_code "plus")
584 (match_operand 0 "symbolic_pcrel_operand")
585 (match_operand 1 "const_int_operand")))
587 (define_predicate "mem_simple_ldst_operand"
591 return (symbolic_pcrel_operand (op, Pmode)
592 || symbolic_pcrel_offset_operand (op, Pmode));
595 (define_predicate "equality_operator"
596 (match_code "eq,ne"))
598 (define_predicate "order_operator"
599 (match_code "lt,ltu,le,leu,ge,geu,gt,gtu"))
601 ;; For NE, cstore uses sltu instructions in which the first operand is $0.
603 (define_predicate "loongarch_cstore_operator"
604 (match_code "ne,eq,gt,gtu,ge,geu,lt,ltu,le,leu"))
606 (define_predicate "loongarch_fcmp_operator"
608 "unordered,uneq,unlt,unle,eq,lt,le,ordered,ltgt,ne,ge,gt,unge,ungt"))
610 (define_predicate "small_data_pattern"
611 (and (match_code "set,parallel,unspec,unspec_volatile,prefetch")
612 (match_test "loongarch_small_data_pattern_p (op)")))
614 ;; Return 1 if the operand is in non-volatile memory.
615 (define_predicate "non_volatile_mem_operand"
616 (and (match_operand 0 "memory_operand")
617 (not (match_test "MEM_VOLATILE_P (op)"))))
619 (define_predicate "const_vector_same_val_operand"
620 (match_code "const_vector")
622 return loongarch_const_vector_same_val_p (op, mode);
625 (define_predicate "const_vector_same_simm5_operand"
626 (match_code "const_vector")
628 return loongarch_const_vector_same_int_p (op, mode, -16, 15);
631 (define_predicate "const_vector_same_uimm5_operand"
632 (match_code "const_vector")
634 return loongarch_const_vector_same_int_p (op, mode, 0, 31);
637 (define_predicate "const_vector_same_ximm5_operand"
638 (match_code "const_vector")
640 return loongarch_const_vector_same_int_p (op, mode, -31, 31);
643 (define_predicate "const_vector_same_uimm6_operand"
644 (match_code "const_vector")
646 return loongarch_const_vector_same_int_p (op, mode, 0, 63);
649 (define_predicate "par_const_vector_shf_set_operand"
650 (match_code "parallel")
652 return loongarch_const_vector_shuffle_set_p (op, mode);
655 (define_predicate "reg_or_vector_same_val_operand"
656 (ior (match_operand 0 "register_operand")
657 (match_operand 0 "const_vector_same_val_operand")))
659 (define_predicate "reg_or_vector_same_simm5_operand"
660 (ior (match_operand 0 "register_operand")
661 (match_operand 0 "const_vector_same_simm5_operand")))
663 (define_predicate "reg_or_vector_same_uimm5_operand"
664 (ior (match_operand 0 "register_operand")
665 (match_operand 0 "const_vector_same_uimm5_operand")))
667 (define_predicate "reg_or_vector_same_ximm5_operand"
668 (ior (match_operand 0 "register_operand")
669 (match_operand 0 "const_vector_same_ximm5_operand")))
671 (define_predicate "reg_or_vector_same_uimm6_operand"
672 (ior (match_operand 0 "register_operand")
673 (match_operand 0 "const_vector_same_uimm6_operand")))