gcc/config/m32c/cond.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005-2019 Free Software Foundation, Inc.
   3 ;; Contributed by Red Hat.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ; conditionals - cmp, jcc, setcc, etc.
  22
  23 ; Special note about conditional instructions: GCC always emits the
  24 ; compare right before the insn, which is good, because m32c's mov
  25 ; insns modify the flags.  However, this means that any conditional
  26 ; insn that may require reloading must be kept with its compare until
  27 ; after reload finishes, else the reload insns might clobber the
  28 ; flags.  Thus, these rules:
  29 ;
  30 ; * the cmp* expanders just save the operands in compare_op0 and
  31 ;   compare_op1 via m32c_pend_compare.
  32 ; * conditional insns that won't need reload can call
  33 ;   m32c_unpend_compare before their expansion.
  34 ; * other insns must expand to include the compare operands within,
  35 ;   then split after reload to a separate compare and conditional.
  36
  37 ; Until support for relaxing is supported in gas, we must assume that
  38 ; short labels won't reach, so we must use long labels.
  39 ; Unfortunately, there aren't any conditional jumps with long labels,
  40 ; so instead we invert the conditional and jump around a regular jump.
  41
  42 ; Note that we can, at some point in the future, add code to omit the
  43 ; "cmp" portion of the insn if the preceding insn happened to set the
  44 ; right flags already.  For example, a mov followed by a "cmp *,0" is
  45 ; redundant; the move already set the Z flag.
  46
  47 (define_insn_and_split "cbranch<mode>4"
  48   [(set (pc) (if_then_else
  49               (match_operator 0 "m32c_cmp_operator"
  50                               [(match_operand:QHPSI 1 "mra_operand" "RraSd")
  51                                (match_operand:QHPSI 2 "mrai_operand" "iRraSd")])
  52               (label_ref (match_operand 3 "" ""))
  53               (pc)))]
  54   ""
  55   "#"
  56   "reload_completed"
  57   [(set (reg:CC FLG_REGNO)
  58         (compare (match_dup 1)
  59                  (match_dup 2)))
  60    (set (pc) (if_then_else (match_op_dup 0 [(reg:CC FLG_REGNO) (const_int 0)])
  61                            (label_ref (match_dup 3))
  62                            (pc)))]
  63   ""
  64   )
  65
  66 (define_insn "bcc_op"
  67   [(set (pc)
  68         (if_then_else (match_operator 0 "ordered_comparison_operator"
  69                        [(reg:CC FLG_REGNO) (const_int 0)])
  70                       (label_ref (match_operand 1 ""))
  71                       (pc)))]
  72   ""
  73   "j%c0\t%l1"
  74   [(set_attr "flags" "n")]
  75 )
  76
  77 (define_insn "stzx_16"
  78   [(set (match_operand:QI 0 "register_operand" "=R0w,R0w,R0w")
  79         (if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
  80                          (match_operand:QI 1 "const_int_operand" "i,i,0")
  81                          (match_operand:QI 2 "const_int_operand" "i,0,i")))]
  82   "TARGET_A16 && reload_completed"
  83   "@
  84    stzx\t%1,%2,%0
  85    stz\t%1,%0
  86    stnz\t%2,%0"
  87   [(set_attr "flags" "n,n,n")]
  88 )
  89
  90 (define_insn "stzx_24_<mode>"
  91   [(set (match_operand:QHI 0 "mra_operand" "=RraSd,RraSd,RraSd")
  92         (if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
  93                          (match_operand:QHI 1 "const_int_operand" "i,i,0")
  94                          (match_operand:QHI 2 "const_int_operand" "i,0,i")))]
  95   "TARGET_A24 && reload_completed"
  96   "@
  97    stzx.<bwl>\t%1,%2,%0
  98    stz.<bwl>\t%1,%0
  99    stnz.<bwl>\t%2,%0"
 100   [(set_attr "flags" "n,n,n")])
 101
 102 (define_insn_and_split "stzx_reversed_<mode>"
 103   [(set (match_operand:QHI 0 "m32c_r0_operand" "=R0w")
 104         (if_then_else:QHI (ne (reg:CC FLG_REGNO) (const_int 0))
 105                          (match_operand:QHI 1 "const_int_operand" "")
 106                          (match_operand:QHI 2 "const_int_operand" "")))]
 107   "(TARGET_A24 || GET_MODE (operands[0]) == QImode) && reload_completed"
 108   "#"
 109   ""
 110   [(set (match_dup 0)
 111         (if_then_else:QHI (eq (reg:CC FLG_REGNO) (const_int 0))
 112                       (match_dup 2)
 113                       (match_dup 1)))]
 114   ""
 115   )
 116
 117
 118 (define_insn "cmp<mode>_op"
 119   [(set (reg:CC FLG_REGNO)
 120         (compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
 121                  (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
 122   ""
 123   "* return m32c_output_compare(insn, operands); "
 124   [(set_attr "flags" "oszc")])
 125
 126 ;; m32c_conditional_register_usage changes the setcc_gen_code array to
 127 ;; point to the _24 variants if needed.
 128
 129 ;; We need to keep the compare and conditional sets together through
 130 ;; reload, because reload might need to add address reloads to the
 131 ;; set, which would clobber the flags.  By keeping them together, the
 132 ;; reloads get put before the compare, thus preserving the flags.
 133
 134 ;; These are the post-split patterns for the conditional sets.
 135
 136 (define_insn "scc_op"
 137   [(set (match_operand:QI 0 "register_operand" "=Rqi")
 138         (match_operator:QI 1 "ordered_comparison_operator"
 139          [(reg:CC FLG_REGNO) (const_int 0)]))]
 140   "TARGET_A16 && reload_completed"
 141   "* return m32c_scc_pattern(operands, GET_CODE (operands[1]));")
 142
 143 (define_insn "scc_24_op"
 144   [(set (match_operand:HI 0 "mra_operand" "=RhiSd")
 145         (match_operator:HI 1 "ordered_comparison_operator"
 146          [(reg:CC FLG_REGNO) (const_int 0)]))]
 147   "TARGET_A24 && reload_completed"
 148   "sc%c1\t%0"
 149   [(set_attr "flags" "n")]
 150 )
 151
 152 ;; These are the pre-split patterns for the conditional sets.
 153
 154 (define_expand "cstore<mode>4"
 155   [(set (match_operand:QI 0 "register_operand")
 156         (match_operator:QI 1 "ordered_comparison_operator"
 157          [(match_operand:QHPSI 2 "mra_operand")
 158           (match_operand:QHPSI 3 "mrai_operand")]))]
 159   ""
 160 {
 161   if (TARGET_A24)
 162     {
 163       rtx o = gen_reg_rtx (HImode);
 164       emit_insn (gen_cstore<mode>4_24 (o, operands[1],
 165                                        operands[2], operands[3]));
 166       emit_move_insn (operands[0], gen_lowpart (QImode, o));
 167       DONE;
 168     }
 169 })
 170
 171 (define_insn_and_split "*cstore<mode>4_16"
 172   [(set (match_operand:QI 0 "register_operand" "=Rqi")
 173         (match_operator:QI 1 "ordered_comparison_operator"
 174          [(match_operand:QHPSI 2 "mra_operand" "RraSd")
 175           (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
 176   "TARGET_A16"
 177   "#"
 178   "&& reload_completed"
 179   [(set (reg:CC FLG_REGNO)
 180         (compare (match_dup 2)
 181                  (match_dup 3)))
 182    (set (match_dup 0)
 183         (match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
 184   ""
 185   [(set_attr "flags" "x")]
 186 )
 187
 188 (define_insn_and_split "cstore<mode>4_24"
 189   [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
 190         (match_operator:HI 1 "ordered_comparison_operator"
 191          [(match_operand:QHPSI 2 "mra_operand" "RraSd")
 192           (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
 193   "TARGET_A24"
 194   "#"
 195   "&& reload_completed"
 196   [(set (reg:CC FLG_REGNO)
 197         (compare (match_dup 2)
 198                  (match_dup 3)))
 199    (set (match_dup 0)
 200         (match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
 201   ""
 202   [(set_attr "flags" "x")]
 203 )
 204
 205 (define_insn_and_split "movqicc_<code>_<mode>"
 206   [(set (match_operand:QI 0 "register_operand" "=R0w")
 207         (if_then_else:QI (eqne_cond (match_operand:QHPSI 1 "mra_operand" "RraSd")
 208                                     (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
 209                           (match_operand:QI 3 "const_int_operand" "")
 210                           (match_operand:QI 4 "const_int_operand" "")))]
 211   ""
 212   "#"
 213   "reload_completed"
 214   [(set (reg:CC FLG_REGNO)
 215         (compare (match_dup 1)
 216                  (match_dup 2)))
 217    (set (match_dup 0)
 218         (if_then_else:QI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))
 219                          (match_dup 3)
 220                          (match_dup 4)))]
 221   ""
 222   [(set_attr "flags" "x")]
 223   )
 224
 225 (define_insn_and_split "movhicc_<code>_<mode>"
 226   [(set (match_operand:HI 0 "register_operand" "=R0w")
 227         (if_then_else:HI (eqne_cond (match_operand:QHPSI 1 "mra_operand" "RraSd")
 228                                     (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
 229                           (match_operand:HI 3 "const_int_operand" "")
 230                           (match_operand:HI 4 "const_int_operand" "")))]
 231   "TARGET_A24"
 232   "#"
 233   "reload_completed"
 234   [(set (reg:CC FLG_REGNO)
 235         (compare (match_dup 1)
 236                  (match_dup 2)))
 237    (set (match_dup 0)
 238         (if_then_else:HI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))
 239                          (match_dup 3)
 240                          (match_dup 4)))]
 241   ""
 242   [(set_attr "flags" "x")]
 243   )
 244
 245 ;; And these are the expanders.
 246
 247 (define_expand "movqicc"
 248   [(set (match_operand:QI 0 "register_operand" "")
 249         (if_then_else:QI (match_operand 1 "m32c_eqne_operator" "")
 250                          (match_operand:QI 2 "const_int_operand" "")
 251                          (match_operand:QI 3 "const_int_operand" "")))]
 252   ""
 253   "if (m32c_expand_movcc(operands))
 254      FAIL;
 255    DONE;"
 256 )
 257
 258 (define_expand "movhicc"
 259   [(set (match_operand:HI 0 "mra_operand" "")
 260         (if_then_else:HI (match_operand 1 "m32c_eqne_operator" "")
 261                          (match_operand:HI 2 "const_int_operand" "")
 262                          (match_operand:HI 3 "const_int_operand" "")))]
 263   "TARGET_A24"
 264   "if (m32c_expand_movcc(operands))
 265      FAIL;
 266    DONE;"
 267 )
 268
 269
 270 ;; CMP opcodes subtract two values, set the flags, and discard the
 271 ;; value.  This pattern recovers the sign of the discarded value based
 272 ;; on the flags.  Operand 0 is set to -1, 0, or 1.  This is used for
 273 ;; the cmpstr pattern.  For optimal code, this should be removed if
 274 ;; followed by a suitable CMP insn (see the peephole following).  This
 275 ;; pattern is 7 bytes and 5 cycles.  If you don't need specific
 276 ;; values, a 5/4 pattern can be made with SCGT and BMLT to set the
 277 ;; appropriate bits.
 278
 279 (define_insn "cond_to_int"
 280   [(set (match_operand:HI 0 "mra_qi_operand" "=Rqi")
 281         (if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
 282                          (const_int -1)
 283                          (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
 284                                           (const_int 0)
 285                                           (const_int -1))))]
 286   "TARGET_A24"
 287   "sceq\t%0\n\tbmgt\t1,%h0\n\tdec.w\t%0"
 288   [(set_attr "flags" "x")]
 289   )
 290
 291 ;; A cond_to_int followed by a compare against zero is essentially a
 292 ;; no-op.  However, the result of the cond_to_int may be used by later
 293 ;; insns, so make sure it's dead before deleting its set.
 294
 295 (define_peephole2
 296   [(set (match_operand:HI 0 "mra_qi_operand" "")
 297         (if_then_else:HI (lt (reg:CC FLG_REGNO) (const_int 0))
 298                          (const_int -1)
 299                          (if_then_else:HI (eq (reg:CC FLG_REGNO) (const_int 0))
 300                                           (const_int 0)
 301                                           (const_int -1))))
 302    (set (reg:CC FLG_REGNO)
 303         (compare (match_operand:HI 1 "mra_qi_operand" "")
 304                  (const_int 0)))
 305    ]
 306   "rtx_equal_p (operands[0], operands[1])
 307      && dead_or_set_p (peep2_next_insn (1), operands[0])"
 308   [(const_int 1)]
 309   "")