gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_M32C_H
  23 #define GCC_M32C_H
  24
  25 /* Controlling the Compilation Driver, `gcc'.  */
  26
  27 #undef  STARTFILE_SPEC
  28 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  29
  30 #undef  ENDFILE_SPEC
  31 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  32
  33 #undef  LINK_SPEC
  34 #define LINK_SPEC "%{h*} %{v:-V} \
  35                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  36
  37 /* There are four CPU series we support, but they basically break down
  38    into two families - the R8C/M16C families, with 16-bit address
  39    registers and one set of opcodes, and the M32CM/M32C group, with
  40    24-bit address registers and a different set of opcodes.  The
  41    assembler doesn't care except for which opcode set is needed; the
  42    big difference is in the memory maps, which we cover in
  43    LIB_SPEC.  */
  44
  45 #undef  ASM_SPEC
  46 #define ASM_SPEC "\
  47 %{mcpu=r8c:--m16c} \
  48 %{mcpu=m16c:--m16c} \
  49 %{mcpu=m32cm:--m32c} \
  50 %{mcpu=m32c:--m32c} "
  51
  52 /* The default is R8C hardware.  We support a simulator, which has its
  53    own libgloss and link map, plus one default link map for each chip
  54    family.  Most of the logic here is making sure we do the right
  55    thing when no CPU is specified, which defaults to R8C.  */
  56 #undef  LIB_SPEC
  57 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \
  58 %{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
  59        %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
  60 %{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \
  61                %{mcpu=m32cm:%Tm32cm.ld} \
  62                %{mcpu=m32c:%Tm32c.ld} \
  63                %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
  64 "
  65
  66 /* Run-time Target Specification */
  67
  68 /* Nothing unusual here.  */
  69 #define TARGET_CPU_CPP_BUILTINS() \
  70   { \
  71     builtin_assert ("cpu=m32c"); \
  72     builtin_assert ("machine=m32c"); \
  73     builtin_define ("__m32c__=1"); \
  74     if (TARGET_R8C) \
  75       builtin_define ("__r8c_cpu__=1"); \
  76     if (TARGET_M16C) \
  77       builtin_define ("__m16c_cpu__=1"); \
  78     if (TARGET_M32CM) \
  79       builtin_define ("__m32cm_cpu__=1"); \
  80     if (TARGET_M32C) \
  81       builtin_define ("__m32c_cpu__=1"); \
  82   }
  83
  84 /* The pragma handlers need to know if we've started processing
  85    functions yet, as the memregs pragma should only be given at the
  86    beginning of the file.  This variable starts off TRUE and later
  87    becomes FALSE.  */
  88 extern int ok_to_change_target_memregs;
  89
  90 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  91    use enums or defines for this, this and m32c.opt are the only
  92    places that know (or care) what values are being used.  */
  93 #define TARGET_R8C      (target_cpu == 'r')
  94 #define TARGET_M16C     (target_cpu == '6')
  95 #define TARGET_M32CM    (target_cpu == 'm')
  96 #define TARGET_M32C     (target_cpu == '3')
  97
  98 /* Address register sizes.  Warning: these are used all over the place
  99    to select between the two CPU families in general.  */
 100 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
 101 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
 102
 103 /* Defining data structures for per-function information */
 104
 105 typedef struct GTY (()) machine_function
 106 {
 107   /* How much we adjust the stack when returning from an exception
 108      handler.  */
 109   rtx eh_stack_adjust;
 110
 111   /* TRUE if the current function is an interrupt handler.  */
 112   int is_interrupt;
 113
 114   /* TRUE if the current function is a leaf function.  Currently, this
 115      only affects saving $a0 in interrupt functions.  */
 116   int is_leaf;
 117
 118   /* Bitmask that keeps track of which registers are used in an
 119      interrupt function, so we know which ones need to be saved and
 120      restored.  */
 121   int intr_pushm;
 122   /* Likewise, one element for each memreg that needs to be saved.  */
 123   char intr_pushmem[16];
 124
 125   /* TRUE if the current function can use a simple RTS to return, instead
 126      of the longer ENTER/EXIT pair.  */
 127   int use_rts;
 128 }
 129 machine_function;
 130
 131 #define INIT_EXPANDERS m32c_init_expanders ()
 132
 133 /* Storage Layout */
 134
 135 #define BITS_BIG_ENDIAN 0
 136 #define BYTES_BIG_ENDIAN 0
 137 #define WORDS_BIG_ENDIAN 0
 138
 139 /* We can do QI, HI, and SI operations pretty much equally well, but
 140    GCC expects us to have a "native" format, so we pick the one that
 141    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 142    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 143    24-bit pointers are stored in 32-bit words.  */
 144 #define BITS_PER_UNIT 8
 145 #define UNITS_PER_WORD 2
 146 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 147 #define POINTERS_EXTEND_UNSIGNED 1
 148 /* We have a problem with libgcc2.  It only defines two versions of
 149    each function, one for "int" and one for "long long".  Ie it assumes
 150    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 151    and we need a third set of functions.  We explicitly define
 152    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 153    to get the SI and DI versions from the libgcc2.c sources, and we
 154    provide our own set of HI functions in m32c-lib2.c, which is why this
 155    definition is surrounded by #ifndef..#endif.  */
 156 #ifndef LIBGCC2_UNITS_PER_WORD
 157 #define LIBGCC2_UNITS_PER_WORD 4
 158 #endif
 159
 160 /* These match the alignment enforced by the two types of stack operations.  */
 161 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 162 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 163
 164 /* We do this because we care more about space than about speed.  For
 165    the chips with 16-bit busses, we could set these to 16 if
 166    desired.  */
 167 #define FUNCTION_BOUNDARY 8
 168 #define BIGGEST_ALIGNMENT 8
 169
 170 /* Since we have a maximum structure alignment of 8 there
 171    is no need to enforce any alignment of bitfield types.  */
 172 #undef  PCC_BITFIELD_TYPE_MATTERS
 173 #define PCC_BITFIELD_TYPE_MATTERS 0
 174
 175 #define STRICT_ALIGNMENT 0
 176 #define SLOW_BYTE_ACCESS 1
 177
 178 /* Layout of Source Language Data Types */
 179
 180 #define INT_TYPE_SIZE 16
 181 #define SHORT_TYPE_SIZE 16
 182 #define LONG_TYPE_SIZE 32
 183 #define LONG_LONG_TYPE_SIZE 64
 184
 185 #define FLOAT_TYPE_SIZE 32
 186 #define DOUBLE_TYPE_SIZE 64
 187 #define LONG_DOUBLE_TYPE_SIZE 64
 188
 189 #define DEFAULT_SIGNED_CHAR 1
 190
 191 #undef PTRDIFF_TYPE
 192 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 193
 194 #undef UINTPTR_TYPE
 195 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
 196
 197 #undef  SIZE_TYPE
 198 #define SIZE_TYPE "unsigned int"
 199
 200 #undef  WCHAR_TYPE
 201 #define WCHAR_TYPE "long int"
 202
 203 #undef  WCHAR_TYPE_SIZE
 204 #define WCHAR_TYPE_SIZE 32
 205
 206 /* REGISTER USAGE */
 207
 208 /* Register Basics */
 209
 210 /* Register layout:
 211
 212         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 213         [--------]  $r2  (16 bits)
 214         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 215         [--------]  $r3  (16 bits)
 216    [---][--------]  $a0  (might be 24 bits)
 217    [---][--------]  $a1  (might be 24 bits)
 218    [---][--------]  $sb  (might be 24 bits)
 219    [---][--------]  $fb  (might be 24 bits)
 220    [---][--------]  $sp  (might be 24 bits)
 221    [-------------]  $pc  (20 or 24 bits)
 222              [---]  $flg (CPU flags)
 223    [---][--------]  $argp (virtual)
 224         [--------]  $mem0 (all 16 bits)
 225           . . .
 226         [--------]  $mem14
 227 */
 228
 229 #define FIRST_PSEUDO_REGISTER   20
 230
 231 /* Note that these two tables are modified based on which CPU family
 232    you select; see m32c_conditional_register_usage for details.  */
 233
 234 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 235 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 236                               0, 0, 1, 0, \
 237                               1, 1, 0, 1, \
 238                               0, 0, 0, 0, 0, 0, 0, 0 }
 239 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 240                               1, 1, 1, 0, \
 241                               1, 1, 1, 1, \
 242                               1, 1, 1, 1, 1, 1, 1, 1 }
 243
 244 /* The *_REGNO theme matches m32c.md and most register number
 245    arguments; the PC_REGNUM is the odd one out.  */
 246 #ifndef PC_REGNO
 247 #define PC_REGNO 9
 248 #endif
 249 #define PC_REGNUM PC_REGNO
 250
 251 /* Order of Allocation of Registers */
 252
 253 #define REG_ALLOC_ORDER { \
 254         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 255         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 256         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 257
 258 /* How Values Fit in Registers */
 259
 260 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 261 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 262 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 263 #define AVOID_CCMODE_COPIES
 264
 265 /* Register Classes */
 266
 267 /* Most registers are special purpose in some form or another, so this
 268    table is pretty big.  Class names are used for constraints also;
 269    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 270    See m32c_reg_class_from_constraint for the mapping.  There's some
 271    duplication so that we can better isolate the reason for using
 272    constraints in the md files from the actual registers used; for
 273    example we may want to exclude a1a0 from SI_REGS in the future,
 274    without precluding their use as HImode registers.  */
 275
 276 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 277 /*       mmPAR */
 278 #define REG_CLASS_CONTENTS \
 279 { { 0x00000000 }, /* NO */\
 280   { 0x00000100 }, /* SP  - sp */\
 281   { 0x00000080 }, /* FB  - fb */\
 282   { 0x00000040 }, /* SB  - sb */\
 283   { 0x000001c0 }, /* CR  - sb fb sp */\
 284   { 0x00000001 }, /* R0  - r0 */\
 285   { 0x00000004 }, /* R1  - r1 */\
 286   { 0x00000002 }, /* R2  - r2 */\
 287   { 0x00000008 }, /* R3  - r3 */\
 288   { 0x00000003 }, /* R02 - r0r2 */\
 289   { 0x0000000c }, /* R13 - r1r3 */\
 290   { 0x00000005 }, /* HL  - r0 r1 */\
 291   { 0x0000000a }, /* R23 - r2 r3 */\
 292   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 293   { 0x00000010 }, /* A0  - a0 */\
 294   { 0x00000020 }, /* A1  - a1 */\
 295   { 0x00000030 }, /* A   - a0 a1 */\
 296   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 297   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 298   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 299   { 0x0000003f }, /* RA  - r0 r1 r2 r3 a0 a1 */\
 300   { 0x0000007f }, /* GENERAL */\
 301   { 0x00000400 }, /* FLG */\
 302   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 303   { 0x000ff000 }, /* MEM */\
 304   { 0x000ff003 }, /* R02_A_MEM */\
 305   { 0x000ff005 }, /* A_HL_MEM */\
 306   { 0x000ff00c }, /* R1_R3_A_MEM */\
 307   { 0x000ff00f }, /* R03_MEM */\
 308   { 0x000ff03f }, /* A_HI_MEM */\
 309   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 310   { 0x000ff5ff }, /* ALL */\
 311 }
 312
 313 #define QI_REGS HL_REGS
 314 #define HI_REGS RA_REGS
 315 #define SI_REGS R03_REGS
 316 #define DI_REGS R03_REGS
 317
 318 enum reg_class
 319 {
 320   NO_REGS,
 321   SP_REGS,
 322   FB_REGS,
 323   SB_REGS,
 324   CR_REGS,
 325   R0_REGS,
 326   R1_REGS,
 327   R2_REGS,
 328   R3_REGS,
 329   R02_REGS,
 330   R13_REGS,
 331   HL_REGS,
 332   R23_REGS,
 333   R03_REGS,
 334   A0_REGS,
 335   A1_REGS,
 336   A_REGS,
 337   AD_REGS,
 338   PS_REGS,
 339   R02A_REGS,
 340   RA_REGS,
 341   GENERAL_REGS,
 342   FLG_REGS,
 343   HC_REGS,
 344   MEM_REGS,
 345   R02_A_MEM_REGS,
 346   A_HL_MEM_REGS,
 347   R1_R3_A_MEM_REGS,
 348   R03_MEM_REGS,
 349   A_HI_MEM_REGS,
 350   A_AD_CR_MEM_SI_REGS,
 351   ALL_REGS,
 352   LIM_REG_CLASSES
 353 };
 354
 355 #define N_REG_CLASSES LIM_REG_CLASSES
 356
 357 #define REG_CLASS_NAMES {\
 358 "NO_REGS", \
 359 "SP_REGS", \
 360 "FB_REGS", \
 361 "SB_REGS", \
 362 "CR_REGS", \
 363 "R0_REGS", \
 364 "R1_REGS", \
 365 "R2_REGS", \
 366 "R3_REGS", \
 367 "R02_REGS", \
 368 "R13_REGS", \
 369 "HL_REGS", \
 370 "R23_REGS", \
 371 "R03_REGS", \
 372 "A0_REGS", \
 373 "A1_REGS", \
 374 "A_REGS", \
 375 "AD_REGS", \
 376 "PS_REGS", \
 377 "R02A_REGS", \
 378 "RA_REGS", \
 379 "GENERAL_REGS", \
 380 "FLG_REGS", \
 381 "HC_REGS", \
 382 "MEM_REGS", \
 383 "R02_A_MEM_REGS", \
 384 "A_HL_MEM_REGS", \
 385 "R1_R3_A_MEM_REGS", \
 386 "R03_MEM_REGS", \
 387 "A_HI_MEM_REGS", \
 388 "A_AD_CR_MEM_SI_REGS", \
 389 "ALL_REGS", \
 390 }
 391
 392 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 393
 394 /* We support simple displacements off address registers, nothing else.  */
 395 #define BASE_REG_CLASS A_REGS
 396 #define INDEX_REG_CLASS NO_REGS
 397
 398 /* We primarily use the new "long" constraint names, with the initial
 399    letter classifying the constraint type and following letters
 400    specifying which.  The types are:
 401
 402    I - integer values
 403    R - register classes
 404    S - memory references (M was used)
 405    A - addresses (currently unused)
 406 */
 407
 408 #define CONSTRAINT_LEN(CHAR,STR) \
 409         ((CHAR) == 'I' ? 3 \
 410          : (CHAR) == 'R' ? 3 \
 411          : (CHAR) == 'S' ? 2 \
 412          : (CHAR) == 'A' ? 2 \
 413          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 414 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 415         (enum reg_class) m32c_reg_class_from_constraint (CHAR, STR)
 416
 417 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 418 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 419
 420 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 421 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 422 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
 423   (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
 424
 425 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
 426   (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
 427
 428 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 429
 430 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 431
 432 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 433
 434 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 435         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 436 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 437 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 438         m32c_extra_constraint_p (VALUE, C, STR)
 439 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 440         m32c_extra_memory_constraint (C, STR)
 441 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 442         m32c_extra_address_constraint (C, STR)
 443
 444 /* STACK AND CALLING */
 445
 446 /* Frame Layout */
 447
 448 /* Standard push/pop stack, no surprises here.  */
 449
 450 #define STACK_GROWS_DOWNWARD 1
 451 #define STACK_PUSH_CODE PRE_DEC
 452 #define FRAME_GROWS_DOWNWARD 1
 453
 454 #define STARTING_FRAME_OFFSET 0
 455 #define FIRST_PARM_OFFSET(F) 0
 456
 457 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 458
 459 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 460 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 461
 462 /* Exception Handling Support */
 463
 464 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 465 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 466
 467 /* Registers That Address the Stack Frame */
 468
 469 #ifndef FP_REGNO
 470 #define FP_REGNO 7
 471 #endif
 472 #ifndef SP_REGNO
 473 #define SP_REGNO 8
 474 #endif
 475 #define AP_REGNO 11
 476
 477 #define STACK_POINTER_REGNUM    SP_REGNO
 478 #define FRAME_POINTER_REGNUM    FP_REGNO
 479 #define ARG_POINTER_REGNUM      AP_REGNO
 480
 481 /* The static chain must be pointer-capable.  */
 482 #define STATIC_CHAIN_REGNUM A0_REGNO
 483
 484 #define DWARF_FRAME_REGISTERS 20
 485 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 486 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 487
 488 #undef ASM_PREFERRED_EH_DATA_FORMAT
 489 /* This is the same as the default in practice, except that by making
 490    it explicit we tell binutils what size pointers to use.  */
 491 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 492   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 493
 494 /* Eliminating Frame Pointer and Arg Pointer */
 495
 496 #define ELIMINABLE_REGS \
 497   {{AP_REGNO, SP_REGNO}, \
 498    {AP_REGNO, FB_REGNO}, \
 499    {FB_REGNO, SP_REGNO}}
 500
 501 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 502         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 503
 504 /* Passing Function Arguments on the Stack */
 505
 506 #define PUSH_ARGS 1
 507 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 508 #define CALL_POPS_ARGS(C) 0
 509
 510 /* Passing Arguments in Registers */
 511
 512 typedef struct m32c_cumulative_args
 513 {
 514   /* For address of return value buffer (structures are returned by
 515      passing the address of a buffer as an invisible first argument.
 516      This identifies it).  If set, the current parameter will be put
 517      on the stack, regardless of type.  */
 518   int force_mem;
 519   /* First parm is 1, parm 0 is hidden pointer for returning
 520      aggregates.  */
 521   int parm_num;
 522 } m32c_cumulative_args;
 523
 524 #define CUMULATIVE_ARGS m32c_cumulative_args
 525 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 526         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 527 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 528
 529 /* How Large Values Are Returned */
 530
 531 #define DEFAULT_PCC_STRUCT_RETURN 1
 532
 533 /* Function Entry and Exit */
 534
 535 #define EXIT_IGNORE_STACK 0
 536 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 537 #define EH_USES(REGNO) 0        /* FIXME */
 538
 539 /* Generating Code for Profiling */
 540
 541 #define FUNCTION_PROFILER(FILE,LABELNO)
 542
 543 /* Implementing the Varargs Macros */
 544
 545 /* Trampolines for Nested Functions */
 546
 547 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 548 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 549
 550 /* Addressing Modes */
 551
 552 #define HAVE_PRE_DECREMENT 1
 553 #define HAVE_POST_INCREMENT 1
 554 #define MAX_REGS_PER_ADDRESS 1
 555
 556 /* This is passed to the macros below, so that they can be implemented
 557    in m32c.c.  */
 558 #ifdef REG_OK_STRICT
 559 #define REG_OK_STRICT_V 1
 560 #else
 561 #define REG_OK_STRICT_V 0
 562 #endif
 563
 564 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 565 #define REG_OK_FOR_INDEX_P(X) 0
 566
 567 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 568
 569 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 570         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 571           goto WIN;
 572
 573 /* Address spaces.  */
 574 #define ADDR_SPACE_FAR  1
 575
 576
 577 /* Condition Code Status */
 578
 579 #define REVERSIBLE_CC_MODE(MODE) 1
 580
 581 /* Dividing the Output into Sections (Texts, Data, ...) */
 582
 583 #define TEXT_SECTION_ASM_OP ".text"
 584 #define DATA_SECTION_ASM_OP ".data"
 585 #define BSS_SECTION_ASM_OP ".bss"
 586
 587 #define CTOR_LIST_BEGIN
 588 #define CTOR_LIST_END
 589 #define DTOR_LIST_BEGIN
 590 #define DTOR_LIST_END
 591 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 592 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 593 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 594 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 595
 596 /* The Overall Framework of an Assembler File */
 597
 598 #define ASM_COMMENT_START ";"
 599 #define ASM_APP_ON ""
 600 #define ASM_APP_OFF ""
 601
 602 /* Output and Generation of Labels */
 603
 604 #define GLOBAL_ASM_OP "\t.global\t"
 605
 606 /* Output of Assembler Instructions */
 607
 608 #define REGISTER_NAMES {        \
 609   "r0", "r2", "r1", "r3", \
 610   "a0", "a1", "sb", "fb", "sp", \
 611   "pc", "flg", "argp", \
 612   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 613 }
 614
 615 #define ADDITIONAL_REGISTER_NAMES { \
 616   {"r0l", 0}, \
 617   {"r1l", 2}, \
 618   {"r0r2", 0}, \
 619   {"r1r3", 2}, \
 620   {"a0a1", 4}, \
 621   {"r0r2r1r3", 0} }
 622
 623 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 624 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 625 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 626
 627 #undef USER_LABEL_PREFIX
 628 #define USER_LABEL_PREFIX "_"
 629
 630 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 631 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 632
 633 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 634         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 635
 636 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 637         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 638
 639
 640 /* Output of Dispatch Tables */
 641
 642 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 643         fprintf (S, "\t.word L%d\n", V)
 644
 645 /* Assembler Commands for Exception Regions */
 646
 647 #define DWARF_CIE_DATA_ALIGNMENT -1
 648
 649 /* Assembler Commands for Alignment */
 650
 651 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 652         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 653
 654 /* Controlling Debugging Information Format */
 655
 656 #define DWARF2_ADDR_SIZE        4
 657
 658 /* Miscellaneous Parameters */
 659
 660 #define HAS_LONG_COND_BRANCH false
 661 #define HAS_LONG_UNCOND_BRANCH true
 662 #define CASE_VECTOR_MODE SImode
 663 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 664
 665 #define MOVE_MAX 4
 666 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 667
 668 #define STORE_FLAG_VALUE 1
 669
 670 /* 16- or 24-bit pointers */
 671 #define Pmode (TARGET_A16 ? HImode : PSImode)
 672 #define FUNCTION_MODE QImode
 673
 674 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 675
 676 #endif