gcc/config/m32c/mov.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 2, or (at your
  11 ;; option) any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21 ;; 02110-1301, USA.
  22
  23 ;; move, push, extend, etc.
  24
  25 ;; Be careful to never create an alternative that has memory as both
  26 ;; src and dest, as that makes gcc think that mem-mem moves in general
  27 ;; are supported.  While the chip does support this, it only has two
  28 ;; address registers and sometimes gcc requires more than that.  One
  29 ;; example is code like this: a = *b where both a and b are spilled to
  30 ;; the stack.
  31
  32 ;; Match push/pop before mov.b for passing char as arg,
  33 ;; e.g. stdlib/efgcvt.c.
  34 (define_insn "movqi_op"
  35   [(set (match_operand:QI 0 "m32c_nonimmediate_operand"
  36                           "=Rqi*Rmm, <,          RqiSd*Rmm, SdSs,    Rqi*Rmm, Sd")
  37         (match_operand:QI 1 "m32c_any_operand"
  38                           "iRqi*Rmm, iRqiSd*Rmm, >,         Rqi*Rmm, SdSs,    i"))]
  39   "m32c_mov_ok (operands, QImode)"
  40   "@
  41     mov.b\t%1,%0
  42     push.b\t%1
  43     pop.b\t%0
  44     mov.b\t%1,%0
  45     mov.b\t%1,%0
  46     mov.b\t%1,%0"
  47   [(set_attr "flags" "sz,*,*,sz,sz,sz")]
  48   )
  49
  50 (define_expand "movqi"
  51   [(set (match_operand:QI 0 "nonimmediate_operand" "=RqiSd*Rmm")
  52         (match_operand:QI 1 "general_operand" "iRqiSd*Rmm"))]
  53   ""
  54   "if (m32c_prepare_move (operands, QImode)) DONE;"
  55   )
  56
  57
  58 (define_insn "movhi_op"
  59   [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
  60                           "=Rhi*Rmm,     Sd, SdSs,   *Rcr, RhiSd*Rmm, <, RhiSd*Rmm, <, *Rcr")
  61         (match_operand:HI 1 "m32c_any_operand"
  62                           "iRhi*RmmSdSs, i, Rhi*Rmm, RhiSd*Rmm, *Rcr, iRhiSd*Rmm, >, *Rcr, >"))]
  63   "m32c_mov_ok (operands, HImode)"
  64   "@
  65    mov.w\t%1,%0
  66    mov.w\t%1,%0
  67    mov.w\t%1,%0
  68    ldc\t%1,%0
  69    stc\t%1,%0
  70    push.w\t%1
  71    pop.w\t%0
  72    pushc\t%1
  73    popc\t%0"
  74   [(set_attr "flags" "sz,sz,sz,n,n,n,n,n,n")]
  75   )
  76
  77 (define_expand "movhi"
  78   [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhiSd*Rmm")
  79         (match_operand:HI 1 "m32c_any_operand" "iRhiSd*Rmm"))]
  80   ""
  81   "if (m32c_prepare_move (operands, HImode)) DONE;"
  82   )
  83
  84
  85 (define_insn "movpsi_op"
  86   [(set (match_operand:PSI 0 "m32c_nonimmediate_operand"
  87                            "=Raa, SdRmmRpi,  Rcl,  RpiSd*Rmm, <,       <, Rcl, RpiRaa*Rmm")
  88         (match_operand:PSI 1 "m32c_any_operand"
  89                            "sIU3, iSdRmmRpi, iRpiSd*Rmm, Rcl, Rpi*Rmm, Rcl, >, >"))]
  90   "TARGET_A24 && m32c_mov_ok (operands, PSImode)"
  91   "@
  92    mov.l:s\t%1,%0
  93    mov.l\t%1,%0
  94    ldc\t%1,%0
  95    stc\t%1,%0
  96    push.l\t%1
  97    pushc\t%1
  98    popc\t%0
  99    #"
 100   [(set_attr "flags" "sz,sz,n,n,n,n,n,*")]
 101   )
 102
 103
 104 ;; The intention here is to combine the add with the move to create an
 105 ;; indexed move.  GCC doesn't always figure this out itself.
 106
 107 (define_peephole2
 108   [(set (match_operand:HPSI 0 "register_operand" "")
 109         (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
 110                    (match_operand:HPSI 2 "immediate_operand" "")))
 111    (set (match_operand:QHSI 3 "nonimmediate_operand" "")
 112         (mem:QHSI (match_operand:HPSI 4 "register_operand" "")))]
 113   "REGNO (operands[0]) == REGNO (operands[1])
 114    && REGNO (operands[0]) == REGNO (operands[4])
 115    && (rtx_equal_p (operands[0], operands[3])
 116        || (dead_or_set_p (peep2_next_insn (1), operands[4])
 117           && ! reg_mentioned_p (operands[0], operands[3])))"
 118   [(set (match_dup 3)
 119         (mem:QHSI (plus:HPSI (match_dup 1)
 120                              (match_dup 2))))]
 121   "")
 122
 123 (define_peephole2
 124   [(set (match_operand:HPSI 0 "register_operand" "")
 125         (plus:HPSI (match_operand:HPSI 1 "register_operand" "")
 126                    (match_operand:HPSI 2 "immediate_operand" "")))
 127    (set (mem:QHSI (match_operand:HPSI 4 "register_operand" ""))
 128         (match_operand:QHSI 3 "m32c_any_operand" ""))]
 129   "REGNO (operands[0]) == REGNO (operands[1])
 130    && REGNO (operands[0]) == REGNO (operands[4])
 131    && dead_or_set_p (peep2_next_insn (1), operands[4])
 132    && ! reg_mentioned_p (operands[0], operands[3])"
 133   [(set (mem:QHSI (plus:HPSI (match_dup 1)
 134                              (match_dup 2)))
 135         (match_dup 3))]
 136   "")
 137
 138
 139 ; Some PSI moves must be split.
 140 (define_split
 141   [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
 142         (match_operand:PSI 1 "m32c_any_operand" ""))]
 143   "reload_completed && m32c_split_psi_p (operands)"
 144   [(set (match_dup 2)
 145         (match_dup 3))
 146    (set (match_dup 4)
 147         (match_dup 5))]
 148   "m32c_split_move (operands, PSImode, 3);"
 149   )
 150
 151 (define_expand "movpsi"
 152   [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "")
 153         (match_operand:PSI 1 "m32c_any_operand" ""))]
 154   ""
 155   "if (m32c_prepare_move (operands, PSImode)) DONE;"
 156   )
 157
 158
 159
 160 (define_expand "movsi"
 161   [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd*Rmm")
 162         (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm"))]
 163   ""
 164   "if (m32c_split_move (operands, SImode, 0)) DONE;"
 165   )
 166
 167 ; All SI moves are split if TARGET_A16
 168 (define_insn_and_split "movsi_splittable"
 169   [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=Rsi<*Rmm,RsiSd*Rmm,Ss")
 170         (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm,iRsi>*Rmm,Rsi*Rmm"))]
 171   "TARGET_A16"
 172   "#"
 173   "TARGET_A16 && reload_completed"
 174   [(pc)]
 175   "m32c_split_move (operands, SImode, 1); DONE;"
 176   )
 177
 178 ; The movsi pattern doesn't always match because sometimes the modes
 179 ; don't match.
 180 (define_insn "push_a01_l"
 181   [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
 182         (match_operand 0 "a_operand" "Raa"))]
 183   ""
 184   "push.l\t%0"
 185   [(set_attr "flags" "n")]
 186   )
 187
 188 (define_insn "movsi_24"
 189   [(set (match_operand:SI 0 "m32c_nonimmediate_operand"  "=Rsi*Rmm,   Sd,       RsiSd*Rmm,     <")
 190         (match_operand:SI 1 "m32c_any_operand" "iRsiSd*Rmm, iRsi*Rmm, >, iRsiRaaSd*Rmm"))]
 191   "TARGET_A24"
 192   "@
 193    mov.l\t%1,%0
 194    mov.l\t%1,%0
 195    #
 196    push.l\t%1"
 197   [(set_attr "flags" "sz,sz,*,n")]
 198   )
 199
 200 (define_expand "movdi"
 201   [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=RdiSd*Rmm")
 202         (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm"))]
 203   ""
 204   "if (m32c_split_move (operands, DImode, 0)) DONE;"
 205   )
 206
 207 (define_insn_and_split "movdi_splittable"
 208   [(set (match_operand:DI 0 "m32c_nonimmediate_operand" "=Rdi<*Rmm,RdiSd*Rmm")
 209         (match_operand:DI 1 "m32c_any_operand" "iRdiSd*Rmm,iRdi>*Rmm"))]
 210   ""
 211   "#"
 212   "reload_completed"
 213   [(pc)]
 214   "m32c_split_move (operands, DImode, 1); DONE;"
 215   )
 216
 217
 218
 219
 220 (define_insn "pushqi"
 221   [(set (mem:QI (pre_dec:PSI (reg:PSI SP_REGNO)))
 222         (match_operand:QI 0 "mrai_operand" "iRqiSd*Rmm"))]
 223   ""
 224   "push.b\t%0"
 225   [(set_attr "flags" "n")]
 226   )
 227
 228 (define_expand "pushhi"
 229   [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
 230         (match_operand:HI 0 "" ""))]
 231   ""
 232   "if (TARGET_A16)
 233      gen_pushhi_16 (operands[0]);
 234    else
 235      gen_pushhi_24 (operands[0]);
 236    DONE;"
 237   )
 238
 239 (define_insn "pushhi_16"
 240   [(set (mem:HI (pre_dec:HI (reg:HI SP_REGNO)))
 241         (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm,Rcr"))]
 242   "TARGET_A16"
 243   "@
 244    push.w\t%0
 245    pushc\t%0"
 246   [(set_attr "flags" "n,n")]
 247   )
 248
 249 (define_insn "pushhi_24"
 250   [(set (mem:HI (pre_dec:PSI (reg:PSI SP_REGNO)))
 251         (match_operand:HI 0 "mrai_operand" "iRhiSd*Rmm"))]
 252   "TARGET_A24"
 253   "push.w\t%0"
 254   [(set_attr "flags" "n")]
 255   )
 256
 257 ;(define_insn "pushpi"
 258 ;  [(set (mem:PSI (pre_dec:PSI (reg:PSI SP_REGNO)))
 259 ;        (match_operand:PI 0 "mrai_operand" "iRaa,Rcr"))]
 260 ;  "TARGET_A24"
 261 ;  "@
 262 ;   push.l\t%0
 263 ;   pushc\t%0"
 264 ;  )
 265
 266 (define_insn "pushsi"
 267   [(set (mem:SI (pre_dec:PSI (reg:PSI SP_REGNO)))
 268         (match_operand:SI 0 "mrai_operand" "iRsiSd*Rmm"))]
 269   "TARGET_A24"
 270   "push.l\t%0"
 271   [(set_attr "flags" "n")]
 272   )
 273
 274 (define_expand "pophi"
 275   [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
 276         (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
 277   ""
 278   "if (TARGET_A16)
 279      gen_pophi_16 (operands[0]);
 280    else
 281      gen_pophi_24 (operands[0]);
 282    DONE;"
 283   )
 284
 285 (define_insn "pophi_16"
 286   [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,Rcr")
 287         (mem:HI (post_inc:HI (reg:HI SP_REGNO))))]
 288   "TARGET_A16"
 289   "@
 290    pop.w\t%0
 291    popc\t%0"
 292   [(set_attr "flags" "n,n")]
 293   )
 294
 295 (define_insn "pophi_24"
 296   [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm")
 297         (mem:HI (post_inc:PSI (reg:PSI SP_REGNO))))]
 298   "TARGET_A24"
 299   "pop.w\t%0"
 300   [(set_attr "flags" "n")]
 301   )
 302
 303 (define_insn "poppsi"
 304   [(set (match_operand:PSI 0 "cr_operand" "=Rcl")
 305         (mem:PSI (post_inc:PSI (reg:PSI SP_REGNO))))]
 306   "TARGET_A24"
 307   "popc\t%0"
 308   [(set_attr "flags" "n")]
 309   )
 310
 311
 312 ;; Rhl used here as an HI-mode Rxl
 313 (define_insn "extendqihi2"
 314 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=RhlSd*Rmm")
 315         (sign_extend:HI (match_operand:QI 1 "mra_operand" "0")))]
 316   ""
 317   "exts.b\t%1"
 318   [(set_attr "flags" "sz")]
 319   )
 320
 321 (define_insn "extendhisi2"
 322   [(set (match_operand:SI 0 "register_operand" "=R03")
 323         (sign_extend:SI (match_operand:HI 1 "r0123_operand" "0")))]
 324   ""
 325   "*
 326    if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
 327    else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
 328   [(set_attr "flags" "x")]
 329   )
 330
 331 (define_insn "extendpsisi2"
 332   [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
 333         (sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
 334   ""
 335   "; expand psi %1 to si %0"
 336   [(set_attr "flags" "n")]
 337   )
 338
 339 (define_insn "zero_extendpsisi2"
 340   [(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
 341         (zero_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
 342   ""
 343   "; expand psi %1 to si %0"
 344   [(set_attr "flags" "n")]
 345   )
 346
 347 (define_insn "zero_extendhipsi2"
 348   [(set (match_operand:PSI 0 "register_operand" "=Raa")
 349         (truncate:PSI (zero_extend:SI (match_operand:HI 1 "register_operand" "R03"))))]
 350   ""
 351   "mov.w\t%1,%0"
 352   [(set_attr "flags" "sz")]
 353   )
 354
 355 (define_insn "zero_extendhisi2"
 356   [(set (match_operand:SI 0 "m32c_nonimmediate_operand" "=RsiSd")
 357         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))]
 358   ""
 359   "mov.w\t#0,%H0"
 360   [(set_attr "flags" "x")]
 361   )
 362
 363 (define_insn "zero_extendqihi2"
 364   [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=Rhl,RhiSd*Rmm")
 365         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
 366   ""
 367   "@
 368    mov.b\t#0,%H0
 369    and.w\t#255,%0"
 370   [(set_attr "flags" "x,x")]
 371   )
 372
 373 (define_insn "truncsipsi2_16"
 374   [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
 375         (truncate:PSI (match_operand:SI 1 "nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
 376   "TARGET_A16"
 377   "@
 378    ; no-op trunc si %1 to psi %0
 379    #
 380    ldc\t%1,%0
 381    stc\t%1,%0"
 382   [(set_attr "flags" "n,*,n,n")]
 383   )
 384
 385 (define_insn "trunchiqi2"
 386   [(set (match_operand:QI 0 "m32c_nonimmediate_operand" "=RqiRmmSd")
 387         (truncate:QI (match_operand:HI 1 "mra_qi_operand" "0")))]
 388   ""
 389   "; no-op trunc hi %1 to qi %0"
 390   [(set_attr "flags" "n")]
 391   )
 392
 393 (define_insn "truncsipsi2_24"
 394   [(set (match_operand:PSI 0              "m32c_nonimmediate_operand" "=RsiSd*Rmm,Raa,!Rcl,RsiSd*Rmm")
 395         (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,!Rcl")))]
 396   "TARGET_A24"
 397   "@
 398    ; no-op trunc si %1 to psi %0
 399    mov.l\t%1,%0
 400    ldc\t%1,%0
 401    stc\t%1,%0"
 402   [(set_attr "flags" "n,sz,n,n")]
 403   )
 404
 405 (define_expand "truncsipsi2"
 406   [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=RsiRadSd*Rmm,Raa,Rcr,RsiSd*Rmm")
 407         (truncate:PSI (match_operand:SI 1 "m32c_nonimmediate_operand" "0,RsiSd*Rmm,RsiSd*Rmm,Rcr")))]
 408   ""
 409   ""
 410   )
 411
 412 (define_expand "reload_inqi"
 413   [(set (match_operand:QI 2 "" "=&Rqi")
 414         (match_operand:QI 1 "" ""))
 415    (set (match_operand:QI 0 "" "")
 416         (match_dup 2))
 417    ]
 418   ""
 419   "")
 420
 421 (define_expand "reload_outqi"
 422   [(set (match_operand:QI 2 "" "=&Rqi")
 423         (match_operand:QI 1 "" ""))
 424    (set (match_operand:QI 0 "" "")
 425         (match_dup 2))
 426    ]
 427   ""
 428   "")
 429
 430 (define_expand "reload_inhi"
 431   [(set (match_operand:HI 2 "" "=&Rhi")
 432         (match_operand:HI 1 "" ""))
 433    (set (match_operand:HI 0 "" "")
 434         (match_dup 2))
 435    ]
 436   ""
 437   "")
 438
 439 (define_expand "reload_outhi"
 440   [(set (match_operand:HI 2 "" "=&Rhi")
 441         (match_operand:HI 1 "" ""))
 442    (set (match_operand:HI 0 "" "")
 443         (match_dup 2))
 444    ]
 445   ""
 446   "")