gcc/config/m32c/muldiv.md

   1 ;; Machine Descriptions for R8C/M16C/M32C
   2 ;; Copyright (C) 2005
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Red Hat.
   5 ;;
   6 ;; This file is part of GCC.
   7 ;;
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published
  10 ;; by the Free Software Foundation; either version 2, or (at your
  11 ;; option) any later version.
  12 ;;
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17 ;;
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING.  If not, write to the Free
  20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  21 ;; 02110-1301, USA.
  22
  23 ;; multiply and divide
  24
  25 ; Here is the pattern for the const_int.
  26 (define_insn "mulqihi3_c"
  27   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
  28         (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
  29                  (match_operand 2 "immediate_operand" "i,i")))]
  30   ""
  31   "mul.b\t%2,%1"
  32 )
  33
  34 ; Here is the pattern for registers and such.
  35 (define_insn "mulqihi3_r"
  36   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
  37         (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
  38                  (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
  39   ""
  40   "mul.b\t%2,%1"
  41 )
  42
  43 ; Don't try to sign_extend a const_int.  Same for all other multiplies.
  44 (define_expand "mulqihi3"
  45   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
  46         (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
  47                  (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
  48   ""
  49   "{ if (GET_MODE (operands[2]) != VOIDmode)
  50       operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
  51 )
  52
  53 (define_insn "umulqihi3_c"
  54   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
  55         (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
  56                  (match_operand 2 "immediate_operand" "i,i")))]
  57   ""
  58   "mulu.b\t%U2,%1"
  59 )
  60
  61 (define_insn "umulqihi3_r"
  62   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
  63         (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
  64                  (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
  65   ""
  66   "mulu.b\t%U2,%1"
  67 )
  68
  69 (define_expand "umulqihi3"
  70   [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
  71         (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
  72                  (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
  73   ""
  74   "{ if (GET_MODE (operands[2]) != VOIDmode)
  75       operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
  76 )
  77
  78 (define_insn "mulhisi3_c"
  79   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
  80         (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
  81                  (match_operand 2 "immediate_operand" "i,i")))]
  82   ""
  83   "mul.w\t%2,%1"
  84 )
  85
  86 (define_insn "mulhisi3_r"
  87   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
  88         (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
  89                  (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
  90   ""
  91   "mul.w\t%2,%1"
  92 )
  93
  94 (define_expand "mulhisi3"
  95   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
  96         (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
  97                  (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
  98   ""
  99   "{ if (GET_MODE (operands[2]) != VOIDmode)
 100       operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
 101 )
 102
 103 (define_insn "umulhisi3_c"
 104   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
 105         (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
 106                  (match_operand 2 "immediate_operand" "i,i")))]
 107   ""
 108   "mulu.w\t%u2,%1"
 109 )
 110
 111 (define_insn "umulhisi3_r"
 112   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
 113         (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
 114                  (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm"))))]
 115   ""
 116   "mulu.w\t%u2,%1"
 117 )
 118
 119 (define_expand "umulhisi3"
 120   [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
 121         (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
 122                  (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
 123   ""
 124   "{ if (GET_MODE (operands[2]) != VOIDmode)
 125       operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
 126 )
 127
 128
 129 ; GCC expects to be able to multiply pointer-sized integers too, but
 130 ; fortunately it only multiplies by powers of two, although sometimes
 131 ; they're negative.
 132 (define_insn "mulpsi3_op"
 133   [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
 134         (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
 135                   (match_operand 2 "m32c_psi_scale" "Ilb")))]
 136   "TARGET_A24"
 137   "shl.l\t%b2,%0"
 138   [(set_attr "flags" "szc")]
 139   )
 140
 141 (define_expand "mulpsi3"
 142   [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
 143         (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
 144                   (match_operand 2 "m32c_psi_scale" "Ilb")))]
 145   "TARGET_A24"
 146   "if (INTVAL(operands[2]) < 0)
 147      {
 148        m32c_expand_neg_mulpsi3 (operands);
 149        DONE;
 150      }"
 151   )
 152
 153
 154
 155 (define_expand "divmodqi4"
 156   [(set (match_dup 4)
 157         (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
 158    (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
 159                    (div:QI (match_dup 4)
 160                            (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
 161               (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
 162                    (mod:QI (match_dup 4) (match_dup 2)))
 163               ])]
 164   "0"
 165   "operands[4] = gen_reg_rtx (HImode);"
 166   )
 167
 168 (define_insn "divmodqi4_n"
 169   [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
 170         (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
 171                 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
 172    (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
 173         (mod:QI (match_dup 1) (match_dup 2)))
 174    ]
 175   "0"
 176   "div.b\t%2"
 177   )
 178
 179 (define_expand "udivmodqi4"
 180   [(set (match_dup 4)
 181         (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
 182    (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
 183                    (udiv:QI (match_dup 4)
 184                            (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
 185               (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
 186                    (umod:QI (match_dup 4) (match_dup 2)))
 187               ])]
 188   "0"
 189   "operands[4] = gen_reg_rtx (HImode);"
 190   )
 191
 192 (define_insn "udivmodqi4_n"
 193   [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
 194         (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
 195                 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
 196    (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
 197         (umod:QI (match_dup 1) (match_dup 2)))
 198    ]
 199   "0"
 200   "divu.b\t%2"
 201   )
 202
 203 (define_expand "divmodhi4"
 204   [(set (match_dup 4)
 205         (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
 206    (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
 207                    (div:HI (match_dup 4)
 208                            (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
 209               (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
 210                    (mod:HI (match_dup 4) (match_dup 2)))
 211               ])]
 212   ""
 213   "operands[4] = gen_reg_rtx (SImode);"
 214   )
 215
 216 (define_insn "divmodhi4_n"
 217   [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
 218         (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
 219                 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
 220    (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
 221         (mod:HI (match_dup 1) (match_dup 2)))
 222    ]
 223   ""
 224   "div.w\t%2"
 225   )
 226
 227 (define_expand "udivmodhi4"
 228   [(set (match_dup 4)
 229         (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
 230    (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
 231                    (udiv:HI (match_dup 4)
 232                            (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
 233               (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
 234                    (umod:HI (match_dup 4) (match_dup 2)))
 235               ])]
 236   ""
 237   "operands[4] = gen_reg_rtx (SImode);"
 238   )
 239
 240 (define_insn "udivmodhi4_n"
 241   [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
 242         (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
 243                 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
 244    (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
 245         (umod:HI (match_dup 1) (match_dup 2)))
 246    ]
 247   ""
 248   "divu.w\t%2"
 249   )