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[thirdparty/gcc.git] / gcc / config / m32c / predicates.md
1 ;; Machine Descriptions for R8C/M16C/M32C
2 ;; Copyright (C) 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 2, or (at your
11 ;; option) any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to the Free
20 ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
21 ;; 02110-1301, USA.
22
23 ;; Predicates
24
25 ; TRUE for any valid operand. We do this because general_operand
26 ; refuses to match volatile memory refs.
27
28 (define_predicate "m32c_any_operand"
29 (ior (match_operand 0 "general_operand")
30 (match_operand 1 "memory_operand")))
31
32 ; Likewise for nonimmediate_operand.
33
34 (define_predicate "m32c_nonimmediate_operand"
35 (ior (match_operand 0 "nonimmediate_operand")
36 (match_operand 1 "memory_operand")))
37
38 ; TRUE if the operand is a pseudo-register.
39 (define_predicate "m32c_pseudo"
40 (ior (and (match_code "reg")
41 (match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
42 (and (match_code "subreg")
43 (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
44 (match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
45
46
47 ; Returning true causes many predicates to NOT match. We allow
48 ; subregs for type changing, but not for size changing.
49 (define_predicate "m32c_wide_subreg"
50 (and (match_code "subreg")
51 (not (match_operand 0 "m32c_pseudo")))
52 {
53 unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op));
54 unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0)));
55 sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
56 sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
57 return sizeo != sizei;
58 })
59
60 ; TRUE for r0 through r3, or a pseudo that reload could put in r0
61 ; through r3 (likewise for the next couple too)
62 (define_predicate "r0123_operand"
63 (ior (match_operand 0 "m32c_pseudo" "")
64 (and (match_code "reg")
65 (match_test "REGNO(op) <= R3_REGNO"))))
66
67 ; TRUE for r0
68 (define_predicate "m32c_r0_operand"
69 (ior (match_operand 0 "m32c_pseudo" "")
70 (and (match_code "reg")
71 (match_test "REGNO(op) == R0_REGNO"))))
72
73 ; TRUE for r1
74 (define_predicate "m32c_r1_operand"
75 (ior (match_operand 0 "m32c_pseudo" "")
76 (and (match_code "reg")
77 (match_test "REGNO(op) == R1_REGNO"))))
78
79 ; TRUE for HL_CLASS (r0 or r1)
80 (define_predicate "m32c_hl_operand"
81 (ior (match_operand 0 "m32c_pseudo" "")
82 (and (match_code "reg")
83 (match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO"))))
84
85
86 ; TRUE for r2
87 (define_predicate "m32c_r2_operand"
88 (ior (match_operand 0 "m32c_pseudo" "")
89 (and (match_code "reg")
90 (match_test "REGNO(op) == R2_REGNO"))))
91
92 ; TRUE for r3
93 (define_predicate "m32c_r3_operand"
94 (ior (match_operand 0 "m32c_pseudo" "")
95 (and (match_code "reg")
96 (match_test "REGNO(op) == R3_REGNO"))))
97
98 ; TRUE for any general operand except r2.
99 (define_predicate "m32c_notr2_operand"
100 (and (match_operand 0 "general_operand")
101 (ior (not (match_code "reg"))
102 (match_test "REGNO(op) != R2_REGNO"))))
103
104 ; TRUE for the stack pointer.
105 (define_predicate "m32c_sp_operand"
106 (ior (match_operand 0 "m32c_pseudo" "")
107 (and (match_code "reg")
108 (match_test "REGNO(op) == SP_REGNO"))))
109
110 ; TRUE for control registers.
111 (define_predicate "cr_operand"
112 (match_code "reg")
113 "return (REGNO (op) >= SB_REGNO
114 && REGNO (op) <= FLG_REGNO);")
115
116 ; TRUE for $a0 or $a1.
117 (define_predicate "a_operand"
118 (and (match_code "reg")
119 (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))
120
121 ; TRUE for $a0 or $a1 or a pseudo
122 (define_predicate "ap_operand"
123 (ior (match_operand 0 "m32c_pseudo" "")
124 (and (match_code "reg")
125 (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))))
126
127 ; TRUE for r0 through r3, or a0 or a1.
128 (define_predicate "ra_operand"
129 (and (and (match_operand 0 "register_operand" "")
130 (not (match_operand 1 "cr_operand" "")))
131 (not (match_operand 2 "m32c_wide_subreg" ""))))
132
133 ; Likewise, plus TRUE for memory references.
134 (define_predicate "mra_operand"
135 (and (and (match_operand 0 "nonimmediate_operand" "")
136 (not (match_operand 1 "cr_operand" "")))
137 (not (match_operand 2 "m32c_wide_subreg" ""))))
138
139 ; Likewise, plus TRUE for subregs.
140 (define_predicate "mras_operand"
141 (and (match_operand 0 "nonimmediate_operand" "")
142 (not (match_operand 1 "cr_operand" ""))))
143
144 ; TRUE for memory, r0..r3, a0..a1, or immediates.
145 (define_predicate "mrai_operand"
146 (and (and (match_operand 0 "m32c_any_operand" "")
147 (not (match_operand 1 "cr_operand" "")))
148 (not (match_operand 2 "m32c_wide_subreg" ""))))
149
150 ; Likewise, plus true for subregs.
151 (define_predicate "mrasi_operand"
152 (and (match_operand 0 "general_operand" "")
153 (not (match_operand 1 "cr_operand" ""))))
154
155 ; TRUE for r0..r3 or memory.
156 (define_predicate "mr_operand"
157 (and (match_operand 0 "mra_operand" "")
158 (not (match_operand 1 "a_operand" ""))))
159
160 ; TRUE for a0..a1 or memory.
161 (define_predicate "ma_operand"
162 (ior (match_operand 0 "a_operand" "")
163 (match_operand 1 "memory_operand" "")))
164
165 ; TRUE for memory operands that are not indexed
166 (define_predicate "memsym_operand"
167 (and (match_operand 0 "memory_operand" "")
168 (match_test "m32c_extra_constraint_p (op, 'S', \"Si\")")))
169
170 ; TRUE for memory operands with small integer addresses
171 (define_predicate "memimmed_operand"
172 (and (match_operand 0 "memory_operand" "")
173 (match_test "m32c_extra_constraint_p (op, 'S', \"Sp\")")))
174
175 ; TRUE for r1h. This is complicated since r1h isn't a register GCC
176 ; normally knows about.
177 (define_predicate "r1h_operand"
178 (match_code "zero_extract")
179 {
180 rtx reg = XEXP (op, 0);
181 rtx size = XEXP (op, 1);
182 rtx pos = XEXP (op, 2);
183 return (GET_CODE (reg) == REG
184 && REGNO (reg) == R1_REGNO
185 && GET_CODE (size) == CONST_INT
186 && INTVAL (size) == 8
187 && GET_CODE (pos) == CONST_INT
188 && INTVAL (pos) == 8);
189 })
190
191 ; TRUE if we can shift by this amount. Constant shift counts have a
192 ; limited range.
193 (define_predicate "shiftcount_operand"
194 (ior (match_operand 0 "mra_operand" "")
195 (and (match_operand 2 "const_int_operand" "")
196 (match_test "-8 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 8"))))
197 (define_predicate "longshiftcount_operand"
198 (ior (match_operand 0 "mra_operand" "")
199 (and (match_operand 2 "const_int_operand" "")
200 (match_test "-32 <= INTVAL (op) && INTVAL (op) && INTVAL (op) <= 32"))))
201
202 ; TRUE for r0..r3, a0..a1, or sp.
203 (define_predicate "mra_or_sp_operand"
204 (and (ior (match_operand 0 "mra_operand")
205 (match_operand 1 "m32c_sp_operand"))
206 (not (match_operand 2 "m32c_wide_subreg" ""))))
207
208
209 ; TRUE for r2 or r3.
210 (define_predicate "m32c_r2r3_operand"
211 (ior (and (match_code "reg")
212 (ior (match_test "REGNO(op) == R2_REGNO")
213 (match_test "REGNO(op) == R3_REGNO")))
214 (and (match_code "subreg")
215 (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
216
217 ; Likewise, plus TRUE for a0..a1.
218 (define_predicate "m32c_r2r3a_operand"
219 (ior (match_operand 0 "m32c_r2r3_operand" "")
220 (match_operand 0 "a_operand" "")))
221
222 ; These two are only for movqi - no subreg limit
223 (define_predicate "mra_qi_operand"
224 (and (and (match_operand 0 "m32c_nonimmediate_operand" "")
225 (not (match_operand 1 "cr_operand" "")))
226 (not (match_operand 1 "m32c_r2r3a_operand" ""))))
227
228 (define_predicate "mrai_qi_operand"
229 (and (and (match_operand 0 "m32c_any_operand" "")
230 (not (match_operand 1 "cr_operand" "")))
231 (not (match_operand 1 "m32c_r2r3a_operand" ""))))
232
233 (define_predicate "a_qi_operand"
234 (ior (match_operand 0 "m32c_pseudo" "")
235 (match_operand 1 "a_operand" "")))
236
237 ; TRUE for comparisons we support.
238 (define_predicate "m32c_cmp_operator"
239 (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu"))
240
241 (define_predicate "m32c_eqne_operator"
242 (match_code "eq,ne"))
243
244 ; TRUE for mem0
245 (define_predicate "m32c_mem0_operand"
246 (ior (match_operand 0 "m32c_pseudo" "")
247 (and (match_code "reg")
248 (match_test "REGNO(op) == MEM0_REGNO"))))
249
250 ; TRUE for things the call patterns can return.
251 (define_predicate "m32c_return_operand"
252 (ior (match_operand 0 "m32c_r0_operand")
253 (ior (match_operand 0 "m32c_mem0_operand")
254 (match_code "parallel"))))
255
256 ; TRUE for constants we can multiply pointers by
257 (define_predicate "m32c_psi_scale"
258 (and (match_operand 0 "const_int_operand")
259 (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
260
261 ; TRUE for one bit set (bit) or clear (mask) out of N bits.
262
263 (define_predicate "m32c_1bit8_operand"
264 (and (match_operand 0 "const_int_operand")
265 (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilb\")")))
266
267 (define_predicate "m32c_1bit16_operand"
268 (and (match_operand 0 "const_int_operand")
269 (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Ilw\")")))
270
271 (define_predicate "m32c_1mask8_operand"
272 (and (match_operand 0 "const_int_operand")
273 (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imb\")")))
274
275 (define_predicate "m32c_1mask16_operand"
276 (and (match_operand 0 "const_int_operand")
277 (match_test "m32c_const_ok_for_constraint_p(INTVAL(op), 'I', \"Imw\")")))