1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
41 #include "integrate.h"
44 #include "target-def.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0
, m32r_compare_op1
;
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars
[256];
53 /* Selected code model. */
54 enum m32r_model m32r_model
= M32R_MODEL_DEFAULT
;
56 /* Selected SDA support. */
57 enum m32r_sdata m32r_sdata
= M32R_SDATA_DEFAULT
;
59 /* Machine-specific symbol_ref flags. */
60 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
61 #define SYMBOL_REF_MODEL(X) \
62 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
64 /* For string literals, etc. */
65 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
67 /* Forward declaration. */
68 static bool m32r_handle_option (size_t, const char *, int);
69 static void init_reg_tables (void);
70 static void block_move_call (rtx
, rtx
, rtx
);
71 static int m32r_is_insn (rtx
);
72 const struct attribute_spec m32r_attribute_table
[];
73 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
74 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
75 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
77 static void m32r_file_start (void);
79 static int m32r_adjust_priority (rtx
, int);
80 static int m32r_issue_rate (void);
82 static void m32r_encode_section_info (tree
, rtx
, int);
83 static bool m32r_in_small_data_p (tree
);
84 static bool m32r_return_in_memory (tree
, tree
);
85 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
87 static void init_idents (void);
88 static bool m32r_rtx_costs (rtx
, int, int, int *);
89 static bool m32r_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
91 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
94 /* Initialize the GCC target structure. */
95 #undef TARGET_ATTRIBUTE_TABLE
96 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
108 #undef TARGET_ASM_FILE_START
109 #define TARGET_ASM_FILE_START m32r_file_start
111 #undef TARGET_SCHED_ADJUST_PRIORITY
112 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
113 #undef TARGET_SCHED_ISSUE_RATE
114 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
116 #undef TARGET_DEFAULT_TARGET_FLAGS
117 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
118 #undef TARGET_HANDLE_OPTION
119 #define TARGET_HANDLE_OPTION m32r_handle_option
121 #undef TARGET_ENCODE_SECTION_INFO
122 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
123 #undef TARGET_IN_SMALL_DATA_P
124 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
126 #undef TARGET_RTX_COSTS
127 #define TARGET_RTX_COSTS m32r_rtx_costs
128 #undef TARGET_ADDRESS_COST
129 #define TARGET_ADDRESS_COST hook_int_rtx_0
131 #undef TARGET_PROMOTE_PROTOTYPES
132 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
133 #undef TARGET_RETURN_IN_MEMORY
134 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
135 #undef TARGET_SETUP_INCOMING_VARARGS
136 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
137 #undef TARGET_MUST_PASS_IN_STACK
138 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
139 #undef TARGET_PASS_BY_REFERENCE
140 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
141 #undef TARGET_ARG_PARTIAL_BYTES
142 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
144 struct gcc_target targetm
= TARGET_INITIALIZER
;
146 /* Implement TARGET_HANDLE_OPTION. */
149 m32r_handle_option (size_t code
, const char *arg
, int value
)
154 target_flags
&= ~(MASK_M32R2
| MASK_M32RX
);
158 if (strcmp (arg
, "small") == 0)
159 m32r_model
= M32R_MODEL_SMALL
;
160 else if (strcmp (arg
, "medium") == 0)
161 m32r_model
= M32R_MODEL_MEDIUM
;
162 else if (strcmp (arg
, "large") == 0)
163 m32r_model
= M32R_MODEL_LARGE
;
169 if (strcmp (arg
, "none") == 0)
170 m32r_sdata
= M32R_SDATA_NONE
;
171 else if (strcmp (arg
, "sdata") == 0)
172 m32r_sdata
= M32R_SDATA_SDATA
;
173 else if (strcmp (arg
, "use") == 0)
174 m32r_sdata
= M32R_SDATA_USE
;
179 case OPT_mno_flush_func
:
180 m32r_cache_flush_func
= NULL
;
183 case OPT_mflush_trap_
:
186 case OPT_mno_flush_trap
:
187 m32r_cache_flush_trap
= -1;
195 /* Called by OVERRIDE_OPTIONS to initialize various things. */
202 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
203 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
204 m32r_punct_chars
['#'] = 1;
205 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
207 /* Provide default value if not specified. */
209 g_switch_value
= SDATA_DEFAULT_SIZE
;
212 /* Vectors to keep interesting information about registers where it can easily
213 be got. We use to use the actual mode value as the bit number, but there
214 is (or may be) more than 32 modes now. Instead we use two tables: one
215 indexed by hard register number, and one indexed by mode. */
217 /* The purpose of m32r_mode_class is to shrink the range of modes so that
218 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
219 mapped into one m32r_mode_class mode. */
224 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
225 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
228 /* Modes for condition codes. */
229 #define C_MODES (1 << (int) C_MODE)
231 /* Modes for single-word and smaller quantities. */
232 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
234 /* Modes for double-word and smaller quantities. */
235 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
237 /* Modes for quad-word and smaller quantities. */
238 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
240 /* Modes for accumulators. */
241 #define A_MODES (1 << (int) A_MODE)
243 /* Value is 1 if register/mode pair is acceptable on arc. */
245 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
247 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
248 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
249 S_MODES
, C_MODES
, A_MODES
, A_MODES
252 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
254 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
257 init_reg_tables (void)
261 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
263 switch (GET_MODE_CLASS (i
))
266 case MODE_PARTIAL_INT
:
267 case MODE_COMPLEX_INT
:
268 if (GET_MODE_SIZE (i
) <= 4)
269 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
270 else if (GET_MODE_SIZE (i
) == 8)
271 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
272 else if (GET_MODE_SIZE (i
) == 16)
273 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
274 else if (GET_MODE_SIZE (i
) == 32)
275 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
277 m32r_mode_class
[i
] = 0;
280 case MODE_COMPLEX_FLOAT
:
281 if (GET_MODE_SIZE (i
) <= 4)
282 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
283 else if (GET_MODE_SIZE (i
) == 8)
284 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
285 else if (GET_MODE_SIZE (i
) == 16)
286 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
287 else if (GET_MODE_SIZE (i
) == 32)
288 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
290 m32r_mode_class
[i
] = 0;
293 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
296 m32r_mode_class
[i
] = 0;
301 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
304 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
305 else if (i
== ARG_POINTER_REGNUM
)
306 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
308 m32r_regno_reg_class
[i
] = NO_REGS
;
312 /* M32R specific attribute support.
314 interrupt - for interrupt functions
316 model - select code model used to access object
318 small: addresses use 24 bits, use bl to make calls
319 medium: addresses use 32 bits, use bl to make calls
320 large: addresses use 32 bits, use seth/add3/jl to make calls
322 Grep for MODEL in m32r.h for more info. */
324 static tree small_ident1
;
325 static tree small_ident2
;
326 static tree medium_ident1
;
327 static tree medium_ident2
;
328 static tree large_ident1
;
329 static tree large_ident2
;
334 if (small_ident1
== 0)
336 small_ident1
= get_identifier ("small");
337 small_ident2
= get_identifier ("__small__");
338 medium_ident1
= get_identifier ("medium");
339 medium_ident2
= get_identifier ("__medium__");
340 large_ident1
= get_identifier ("large");
341 large_ident2
= get_identifier ("__large__");
345 const struct attribute_spec m32r_attribute_table
[] =
347 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
348 { "interrupt", 0, 0, true, false, false, NULL
},
349 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
},
350 { NULL
, 0, 0, false, false, false, NULL
}
354 /* Handle an "model" attribute; arguments as in
355 struct attribute_spec.handler. */
357 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
358 tree args
, int flags ATTRIBUTE_UNUSED
,
364 arg
= TREE_VALUE (args
);
366 if (arg
!= small_ident1
367 && arg
!= small_ident2
368 && arg
!= medium_ident1
369 && arg
!= medium_ident2
370 && arg
!= large_ident1
371 && arg
!= large_ident2
)
373 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
374 IDENTIFIER_POINTER (name
));
375 *no_add_attrs
= true;
381 /* Encode section information of DECL, which is either a VAR_DECL,
382 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
384 For the M32R we want to record:
386 - whether the object lives in .sdata/.sbss.
387 - what code model should be used to access the object
391 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
395 enum m32r_model model
;
397 default_encode_section_info (decl
, rtl
, first
);
402 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
409 id
= TREE_VALUE (TREE_VALUE (model_attr
));
411 if (id
== small_ident1
|| id
== small_ident2
)
412 model
= M32R_MODEL_SMALL
;
413 else if (id
== medium_ident1
|| id
== medium_ident2
)
414 model
= M32R_MODEL_MEDIUM
;
415 else if (id
== large_ident1
|| id
== large_ident2
)
416 model
= M32R_MODEL_LARGE
;
418 gcc_unreachable (); /* shouldn't happen */
422 if (TARGET_MODEL_SMALL
)
423 model
= M32R_MODEL_SMALL
;
424 else if (TARGET_MODEL_MEDIUM
)
425 model
= M32R_MODEL_MEDIUM
;
426 else if (TARGET_MODEL_LARGE
)
427 model
= M32R_MODEL_LARGE
;
429 gcc_unreachable (); /* shouldn't happen */
431 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
434 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
437 /* Only mark the object as being small data area addressable if
438 it hasn't been explicitly marked with a code model.
440 The user can explicitly put an object in the small data area with the
441 section attribute. If the object is in sdata/sbss and marked with a
442 code model do both [put the object in .sdata and mark it as being
443 addressed with a specific code model - don't mark it as being addressed
444 with an SDA reloc though]. This is ok and might be useful at times. If
445 the object doesn't fit the linker will give an error. */
448 m32r_in_small_data_p (tree decl
)
452 if (TREE_CODE (decl
) != VAR_DECL
)
455 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
458 section
= DECL_SECTION_NAME (decl
);
461 char *name
= (char *) TREE_STRING_POINTER (section
);
462 if (strcmp (name
, ".sdata") == 0 || strcmp (name
, ".sbss") == 0)
467 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
469 int size
= int_size_in_bytes (TREE_TYPE (decl
));
471 if (size
> 0 && (unsigned HOST_WIDE_INT
) size
<= g_switch_value
)
479 /* Do anything needed before RTL is emitted for each function. */
482 m32r_init_expanders (void)
484 /* ??? At one point there was code here. The function is left in
485 to make it easy to experiment. */
489 call_operand (rtx op
, enum machine_mode mode
)
491 if (GET_CODE (op
) != MEM
)
494 return call_address_operand (op
, mode
);
497 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
500 small_data_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
502 if (! TARGET_SDATA_USE
)
505 if (GET_CODE (op
) == SYMBOL_REF
)
506 return SYMBOL_REF_SMALL_P (op
);
508 if (GET_CODE (op
) == CONST
509 && GET_CODE (XEXP (op
, 0)) == PLUS
510 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
511 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
512 && INT16_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
513 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
518 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
521 addr24_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
528 if (GET_CODE (op
) == LABEL_REF
)
529 return TARGET_ADDR24
;
531 if (GET_CODE (op
) == SYMBOL_REF
)
533 else if (GET_CODE (op
) == CONST
534 && GET_CODE (XEXP (op
, 0)) == PLUS
535 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
536 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
537 && UINT24_P (INTVAL (XEXP (XEXP (op
, 0), 1))))
538 sym
= XEXP (XEXP (op
, 0), 0);
542 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
546 && (CONSTANT_POOL_ADDRESS_P (sym
)
547 || LIT_NAME_P (XSTR (sym
, 0))))
553 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
556 addr32_operand (rtx op
, enum machine_mode mode
)
560 if (GET_CODE (op
) == LABEL_REF
)
561 return TARGET_ADDR32
;
563 if (GET_CODE (op
) == SYMBOL_REF
)
565 else if (GET_CODE (op
) == CONST
566 && GET_CODE (XEXP (op
, 0)) == PLUS
567 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
568 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST_INT
570 sym
= XEXP (XEXP (op
, 0), 0);
574 return (! addr24_operand (sym
, mode
)
575 && ! small_data_operand (sym
, mode
));
578 /* Return 1 if OP is a function that can be called with the `bl' insn. */
581 call26_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
586 if (GET_CODE (op
) == SYMBOL_REF
)
587 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
589 return TARGET_CALL26
;
592 /* Return 1 if OP is a DImode const we want to handle inline.
593 This must match the code in the movdi pattern.
594 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
597 easy_di_const (rtx op
)
599 rtx high_rtx
, low_rtx
;
600 HOST_WIDE_INT high
, low
;
602 split_double (op
, &high_rtx
, &low_rtx
);
603 high
= INTVAL (high_rtx
);
604 low
= INTVAL (low_rtx
);
605 /* Pick constants loadable with 2 16 bit `ldi' insns. */
606 if (high
>= -128 && high
<= 127
607 && low
>= -128 && low
<= 127)
612 /* Return 1 if OP is a DFmode const we want to handle inline.
613 This must match the code in the movdf pattern.
614 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
617 easy_df_const (rtx op
)
622 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
623 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
624 if (l
[0] == 0 && l
[1] == 0)
626 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
631 /* Return 1 if OP is (mem (reg ...)).
632 This is used in insn length calcs. */
635 memreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
637 return GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == REG
;
640 /* Return nonzero if TYPE must be passed by indirect reference. */
643 m32r_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
644 enum machine_mode mode
, tree type
,
645 bool named ATTRIBUTE_UNUSED
)
650 size
= int_size_in_bytes (type
);
652 size
= GET_MODE_SIZE (mode
);
654 return (size
< 0 || size
> 8);
659 /* X and Y are two things to compare using CODE. Emit the compare insn and
660 return the rtx for compare [arg0 of the if_then_else].
661 If need_compare is true then the comparison insn must be generated, rather
662 than being subsumed into the following branch instruction. */
665 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
667 enum rtx_code compare_code
;
668 enum rtx_code branch_code
;
669 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
674 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
675 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
676 case LT
: compare_code
= LT
; branch_code
= NE
; break;
677 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
678 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
679 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
680 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
681 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
682 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
683 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
691 switch (compare_code
)
694 if (GET_CODE (y
) == CONST_INT
695 && CMP_INT16_P (INTVAL (y
)) /* Reg equal to small const. */
698 rtx tmp
= gen_reg_rtx (SImode
);
700 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
704 else if (CONSTANT_P (y
)) /* Reg equal to const. */
706 rtx tmp
= force_reg (GET_MODE (x
), y
);
710 if (register_operand (y
, SImode
) /* Reg equal to reg. */
711 || y
== const0_rtx
) /* Reg equal to zero. */
713 emit_insn (gen_cmp_eqsi_insn (x
, y
));
715 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
720 if (register_operand (y
, SImode
)
721 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
723 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
728 emit_insn (gen_cmp_ltsi_insn (x
, y
));
735 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
736 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
740 if (GET_CODE (y
) == CONST_INT
)
741 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
743 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
744 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
748 emit_insn (gen_cmp_ltsi_insn (x
, y
));
755 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
760 if (register_operand (y
, SImode
)
761 || (GET_CODE (y
) == CONST_INT
&& CMP_INT16_P (INTVAL (y
))))
763 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
768 emit_insn (gen_cmp_ltusi_insn (x
, y
));
775 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
776 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
780 if (GET_CODE (y
) == CONST_INT
)
781 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
783 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
784 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
788 emit_insn (gen_cmp_ltusi_insn (x
, y
));
795 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
805 /* Reg/reg equal comparison. */
806 if (compare_code
== EQ
807 && register_operand (y
, SImode
))
808 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
810 /* Reg/zero signed comparison. */
811 if ((compare_code
== EQ
|| compare_code
== LT
)
813 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
815 /* Reg/smallconst equal comparison. */
816 if (compare_code
== EQ
817 && GET_CODE (y
) == CONST_INT
818 && CMP_INT16_P (INTVAL (y
)))
820 rtx tmp
= gen_reg_rtx (SImode
);
822 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
823 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
826 /* Reg/const equal comparison. */
827 if (compare_code
== EQ
830 rtx tmp
= force_reg (GET_MODE (x
), y
);
832 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
839 y
= force_reg (GET_MODE (x
), y
);
842 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
845 y
= force_reg (GET_MODE (x
), y
);
849 switch (compare_code
)
852 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
855 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
858 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
865 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
868 /* Split a 2 word move (DI or DF) into component parts. */
871 gen_split_move_double (rtx operands
[])
873 enum machine_mode mode
= GET_MODE (operands
[0]);
874 rtx dest
= operands
[0];
875 rtx src
= operands
[1];
878 /* We might have (SUBREG (MEM)) here, so just get rid of the
879 subregs to make this code simpler. It is safe to call
880 alter_subreg any time after reload. */
881 if (GET_CODE (dest
) == SUBREG
)
882 alter_subreg (&dest
);
883 if (GET_CODE (src
) == SUBREG
)
887 if (GET_CODE (dest
) == REG
)
889 int dregno
= REGNO (dest
);
892 if (GET_CODE (src
) == REG
)
894 int sregno
= REGNO (src
);
896 int reverse
= (dregno
== sregno
+ 1);
898 /* We normally copy the low-numbered register first. However, if
899 the first register operand 0 is the same as the second register of
900 operand 1, we must copy in the opposite order. */
901 emit_insn (gen_rtx_SET (VOIDmode
,
902 operand_subword (dest
, reverse
, TRUE
, mode
),
903 operand_subword (src
, reverse
, TRUE
, mode
)));
905 emit_insn (gen_rtx_SET (VOIDmode
,
906 operand_subword (dest
, !reverse
, TRUE
, mode
),
907 operand_subword (src
, !reverse
, TRUE
, mode
)));
910 /* Reg = constant. */
911 else if (GET_CODE (src
) == CONST_INT
|| GET_CODE (src
) == CONST_DOUBLE
)
914 split_double (src
, &words
[0], &words
[1]);
915 emit_insn (gen_rtx_SET (VOIDmode
,
916 operand_subword (dest
, 0, TRUE
, mode
),
919 emit_insn (gen_rtx_SET (VOIDmode
,
920 operand_subword (dest
, 1, TRUE
, mode
),
925 else if (GET_CODE (src
) == MEM
)
927 /* If the high-address word is used in the address, we must load it
928 last. Otherwise, load it first. */
930 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
932 /* We used to optimize loads from single registers as
936 if r3 were not used subsequently. However, the REG_NOTES aren't
937 propagated correctly by the reload phase, and it can cause bad
938 code to be generated. We could still try:
940 ld r1,r3+; ld r2,r3; addi r3,-4
942 which saves 2 bytes and doesn't force longword alignment. */
943 emit_insn (gen_rtx_SET (VOIDmode
,
944 operand_subword (dest
, reverse
, TRUE
, mode
),
945 adjust_address (src
, SImode
,
946 reverse
* UNITS_PER_WORD
)));
948 emit_insn (gen_rtx_SET (VOIDmode
,
949 operand_subword (dest
, !reverse
, TRUE
, mode
),
950 adjust_address (src
, SImode
,
951 !reverse
* UNITS_PER_WORD
)));
958 /* We used to optimize loads from single registers as
962 if r3 were not used subsequently. However, the REG_NOTES aren't
963 propagated correctly by the reload phase, and it can cause bad
964 code to be generated. We could still try:
966 st r1,r3; st r2,+r3; addi r3,-4
968 which saves 2 bytes and doesn't force longword alignment. */
969 else if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
971 emit_insn (gen_rtx_SET (VOIDmode
,
972 adjust_address (dest
, SImode
, 0),
973 operand_subword (src
, 0, TRUE
, mode
)));
975 emit_insn (gen_rtx_SET (VOIDmode
,
976 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
977 operand_subword (src
, 1, TRUE
, mode
)));
990 m32r_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
991 tree type
, bool named ATTRIBUTE_UNUSED
)
995 (((mode
== BLKmode
&& type
)
996 ? (unsigned int) int_size_in_bytes (type
)
997 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1000 if (*cum
>= M32R_MAX_PARM_REGS
)
1002 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1003 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1007 return words
* UNITS_PER_WORD
;
1010 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1013 m32r_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
1015 return m32r_pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
1018 /* Do any needed setup for a variadic function. For the M32R, we must
1019 create a register parameter block, and then copy any anonymous arguments
1020 in registers to memory.
1022 CUM has not been updated for the last named argument which has type TYPE
1023 and mode MODE, and we rely on this fact. */
1026 m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1027 tree type
, int *pretend_size
, int no_rtl
)
1034 /* All BLKmode values are passed by reference. */
1035 gcc_assert (mode
!= BLKmode
);
1037 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1038 + ROUND_ADVANCE_ARG (mode
, type
));
1040 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1042 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1043 int first_reg_offset
= first_anon_arg
;
1044 /* Size in words to "pretend" allocate. */
1045 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1048 regblock
= gen_rtx_MEM (BLKmode
,
1049 plus_constant (arg_pointer_rtx
,
1050 FIRST_PARM_OFFSET (0)));
1051 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1052 move_block_from_reg (first_reg_offset
, regblock
, size
);
1054 *pretend_size
= (size
* UNITS_PER_WORD
);
1059 /* Return true if INSN is real instruction bearing insn. */
1062 m32r_is_insn (rtx insn
)
1064 return (INSN_P (insn
)
1065 && GET_CODE (PATTERN (insn
)) != USE
1066 && GET_CODE (PATTERN (insn
)) != CLOBBER
1067 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1070 /* Increase the priority of long instructions so that the
1071 short instructions are scheduled ahead of the long ones. */
1074 m32r_adjust_priority (rtx insn
, int priority
)
1076 if (m32r_is_insn (insn
)
1077 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1084 /* Indicate how many instructions can be issued at the same time.
1085 This is sort of a lie. The m32r can issue only 1 long insn at
1086 once, but it can issue 2 short insns. The default therefore is
1087 set at 2, but this can be overridden by the command line option
1091 m32r_issue_rate (void)
1093 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1096 /* Cost functions. */
1099 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int *total
)
1103 /* Small integers are as cheap as registers. 4 byte values can be
1104 fetched as immediate constants - let's give that the cost of an
1107 if (INT16_P (INTVAL (x
)))
1117 *total
= COSTS_N_INSNS (1);
1124 split_double (x
, &high
, &low
);
1125 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1126 + !INT16_P (INTVAL (low
)));
1131 *total
= COSTS_N_INSNS (3);
1138 *total
= COSTS_N_INSNS (10);
1146 /* Type of function DECL.
1148 The result is cached. To reset the cache at the end of a function,
1149 call with DECL = NULL_TREE. */
1151 enum m32r_function_type
1152 m32r_compute_function_type (tree decl
)
1155 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1156 /* Last function we were called for. */
1157 static tree last_fn
= NULL_TREE
;
1159 /* Resetting the cached value? */
1160 if (decl
== NULL_TREE
)
1162 fn_type
= M32R_FUNCTION_UNKNOWN
;
1163 last_fn
= NULL_TREE
;
1167 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1170 /* Compute function type. */
1171 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1172 ? M32R_FUNCTION_INTERRUPT
1173 : M32R_FUNCTION_NORMAL
);
1178 \f/* Function prologue/epilogue handlers. */
1180 /* M32R stack frames look like:
1182 Before call After call
1183 +-----------------------+ +-----------------------+
1185 high | local variables, | | local variables, |
1186 mem | reg save area, etc. | | reg save area, etc. |
1188 +-----------------------+ +-----------------------+
1190 | arguments on stack. | | arguments on stack. |
1192 SP+0->+-----------------------+ +-----------------------+
1193 | reg parm save area, |
1194 | only created for |
1195 | variable argument |
1197 +-----------------------+
1198 | previous frame ptr |
1199 +-----------------------+
1201 | register save area |
1203 +-----------------------+
1205 +-----------------------+
1209 +-----------------------+
1211 | alloca allocations |
1213 +-----------------------+
1215 low | arguments on stack |
1217 SP+0->+-----------------------+
1220 1) The "reg parm save area" does not exist for non variable argument fns.
1221 2) The "reg parm save area" can be eliminated completely if we saved regs
1222 containing anonymous args separately but that complicates things too
1223 much (so it's not done).
1224 3) The return address is saved after the register save area so as to have as
1225 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1227 /* Structure to be filled in by m32r_compute_frame_size with register
1228 save masks, and offsets for the current function. */
1229 struct m32r_frame_info
1231 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1232 unsigned int extra_size
; /* # bytes of extra stuff. */
1233 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1234 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1235 unsigned int reg_size
; /* # bytes needed to store regs. */
1236 unsigned int var_size
; /* # bytes that variables take up. */
1237 unsigned int gmask
; /* Mask of saved gp registers. */
1238 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1239 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1240 int initialized
; /* Nonzero if frame size already calculated. */
1243 /* Current frame information calculated by m32r_compute_frame_size. */
1244 static struct m32r_frame_info current_frame_info
;
1246 /* Zero structure to initialize current_frame_info. */
1247 static struct m32r_frame_info zero_frame_info
;
1249 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1250 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1252 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1253 The return address and frame pointer are treated separately.
1254 Don't consider them here. */
1255 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1256 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1257 && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1259 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1260 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1262 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1263 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1265 /* Return the bytes needed to compute the frame pointer from the current
1268 SIZE is the size needed for local variables. */
1271 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1274 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1275 unsigned int reg_size
, frame_size
;
1277 enum m32r_function_type fn_type
;
1279 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
);
1281 var_size
= M32R_STACK_ALIGN (size
);
1282 args_size
= M32R_STACK_ALIGN (current_function_outgoing_args_size
);
1283 pretend_size
= current_function_pretend_args_size
;
1284 extra_size
= FIRST_PARM_OFFSET (0);
1285 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1289 /* See if this is an interrupt handler. Call used registers must be saved
1291 fn_type
= m32r_compute_function_type (current_function_decl
);
1292 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1294 /* Calculate space needed for registers. */
1295 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1297 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1298 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1300 reg_size
+= UNITS_PER_WORD
;
1301 gmask
|= 1 << regno
;
1305 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1306 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1308 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1310 total_size
+= reg_size
;
1312 /* ??? Not sure this is necessary, and I don't think the epilogue
1313 handler will do the right thing if this changes total_size. */
1314 total_size
= M32R_STACK_ALIGN (total_size
);
1316 frame_size
= total_size
- (pretend_size
+ reg_size
);
1318 /* Save computed information. */
1319 current_frame_info
.total_size
= total_size
;
1320 current_frame_info
.extra_size
= extra_size
;
1321 current_frame_info
.pretend_size
= pretend_size
;
1322 current_frame_info
.var_size
= var_size
;
1323 current_frame_info
.args_size
= args_size
;
1324 current_frame_info
.reg_size
= reg_size
;
1325 current_frame_info
.gmask
= gmask
;
1326 current_frame_info
.initialized
= reload_completed
;
1328 /* Ok, we're done. */
1332 /* The table we use to reference PIC data. */
1333 static rtx global_offset_table
;
1336 m32r_reload_lr (rtx sp
, int size
)
1338 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1341 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
, sp
)));
1342 else if (size
<= 32768)
1343 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
,
1344 gen_rtx_PLUS (Pmode
, sp
,
1348 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1350 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1351 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1352 emit_insn (gen_movsi (lr
, gen_rtx_MEM (Pmode
, tmp
)));
1355 emit_insn (gen_rtx_USE (VOIDmode
, lr
));
1359 m32r_load_pic_register (void)
1361 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1362 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1363 GEN_INT (TARGET_MODEL_SMALL
)));
1365 /* Need to emit this whether or not we obey regdecls,
1366 since setjmp/longjmp can cause life info to screw up. */
1367 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1370 /* Expand the m32r prologue as a series of insns. */
1373 m32r_expand_prologue (void)
1378 int pic_reg_used
= flag_pic
&& (current_function_uses_pic_offset_table
);
1380 if (! current_frame_info
.initialized
)
1381 m32r_compute_frame_size (get_frame_size ());
1383 gmask
= current_frame_info
.gmask
;
1385 /* These cases shouldn't happen. Catch them now. */
1386 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1388 /* Allocate space for register arguments if this is a variadic function. */
1389 if (current_frame_info
.pretend_size
!= 0)
1391 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1392 the wrong result on a 64-bit host. */
1393 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1394 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1396 GEN_INT (-pretend_size
)));
1399 /* Save any registers we need to and set up fp. */
1400 if (current_frame_info
.save_fp
)
1401 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1403 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1405 /* Save any needed call-saved regs (and call-used if this is an
1406 interrupt handler). */
1407 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1409 if ((gmask
& (1 << regno
)) != 0)
1410 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1411 gen_rtx_REG (Pmode
, regno
)));
1414 if (current_frame_info
.save_lr
)
1415 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1416 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1418 /* Allocate the stack frame. */
1419 frame_size
= (current_frame_info
.total_size
1420 - (current_frame_info
.pretend_size
1421 + current_frame_info
.reg_size
));
1423 if (frame_size
== 0)
1424 ; /* Nothing to do. */
1425 else if (frame_size
<= 32768)
1426 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1427 GEN_INT (-frame_size
)));
1430 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1432 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1433 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1436 if (frame_pointer_needed
)
1437 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1439 if (current_function_profile
)
1440 /* Push lr for mcount (form_pc, x). */
1441 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1442 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1446 m32r_load_pic_register ();
1447 m32r_reload_lr (stack_pointer_rtx
,
1448 (current_function_profile
? 0 : frame_size
));
1451 if (current_function_profile
&& !pic_reg_used
)
1452 emit_insn (gen_blockage ());
1456 /* Set up the stack and frame pointer (if desired) for the function.
1457 Note, if this is changed, you need to mirror the changes in
1458 m32r_compute_frame_size which calculates the prolog size. */
1461 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1463 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1465 /* If this is an interrupt handler, mark it as such. */
1466 if (M32R_INTERRUPT_P (fn_type
))
1467 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1469 if (! current_frame_info
.initialized
)
1470 m32r_compute_frame_size (size
);
1472 /* This is only for the human reader. */
1474 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1476 current_frame_info
.var_size
,
1477 current_frame_info
.reg_size
/ 4,
1478 current_frame_info
.args_size
,
1479 current_frame_info
.extra_size
);
1482 /* Do any necessary cleanup after a function to restore stack, frame,
1486 m32r_output_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1489 int noepilogue
= FALSE
;
1491 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1493 /* This is only for the human reader. */
1494 fprintf (file
, "\t%s EPILOGUE\n", ASM_COMMENT_START
);
1496 gcc_assert (current_frame_info
.initialized
);
1497 total_size
= current_frame_info
.total_size
;
1499 if (total_size
== 0)
1501 rtx insn
= get_last_insn ();
1503 /* If the last insn was a BARRIER, we don't have to write any code
1504 because a jump (aka return) was put there. */
1505 if (GET_CODE (insn
) == NOTE
)
1506 insn
= prev_nonnote_insn (insn
);
1507 if (insn
&& GET_CODE (insn
) == BARRIER
)
1513 unsigned int var_size
= current_frame_info
.var_size
;
1514 unsigned int args_size
= current_frame_info
.args_size
;
1515 unsigned int gmask
= current_frame_info
.gmask
;
1516 int can_trust_sp_p
= !current_function_calls_alloca
;
1517 const char * sp_str
= reg_names
[STACK_POINTER_REGNUM
];
1518 const char * fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
1520 /* The first thing to do is point the sp at the bottom of the register
1524 unsigned int reg_offset
= var_size
+ args_size
;
1525 if (reg_offset
== 0)
1526 ; /* Nothing to do. */
1527 else if (reg_offset
< 128)
1528 fprintf (file
, "\taddi %s,%s%d\n",
1529 sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1530 else if (reg_offset
< 32768)
1531 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1532 sp_str
, sp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1534 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1535 reg_names
[PROLOGUE_TMP_REGNUM
],
1536 IMMEDIATE_PREFIX
, reg_offset
,
1537 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1539 else if (frame_pointer_needed
)
1541 unsigned int reg_offset
= var_size
+ args_size
;
1543 if (reg_offset
== 0)
1544 fprintf (file
, "\tmv %s,%s\n", sp_str
, fp_str
);
1545 else if (reg_offset
< 32768)
1546 fprintf (file
, "\tadd3 %s,%s,%s%d\n",
1547 sp_str
, fp_str
, IMMEDIATE_PREFIX
, reg_offset
);
1549 fprintf (file
, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1550 reg_names
[PROLOGUE_TMP_REGNUM
],
1551 IMMEDIATE_PREFIX
, reg_offset
,
1552 sp_str
, reg_names
[PROLOGUE_TMP_REGNUM
]);
1557 if (current_frame_info
.save_lr
)
1558 fprintf (file
, "\tpop %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1560 /* Restore any saved registers, in reverse order of course. */
1561 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1562 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1564 if ((gmask
& (1L << regno
)) != 0)
1565 fprintf (file
, "\tpop %s\n", reg_names
[regno
]);
1568 if (current_frame_info
.save_fp
)
1569 fprintf (file
, "\tpop %s\n", fp_str
);
1571 /* Remove varargs area if present. */
1572 if (current_frame_info
.pretend_size
!= 0)
1573 fprintf (file
, "\taddi %s,%s%d\n",
1574 sp_str
, IMMEDIATE_PREFIX
, current_frame_info
.pretend_size
);
1576 /* Emit the return instruction. */
1577 if (M32R_INTERRUPT_P (fn_type
))
1578 fprintf (file
, "\trte\n");
1580 fprintf (file
, "\tjmp %s\n", reg_names
[RETURN_ADDR_REGNUM
]);
1583 /* Reset state info for each function. */
1584 current_frame_info
= zero_frame_info
;
1585 m32r_compute_function_type (NULL_TREE
);
1588 /* Return nonzero if this function is known to have a null or 1 instruction
1592 direct_return (void)
1594 if (!reload_completed
)
1597 if (! current_frame_info
.initialized
)
1598 m32r_compute_frame_size (get_frame_size ());
1600 return current_frame_info
.total_size
== 0;
1607 m32r_legitimate_pic_operand_p (rtx x
)
1609 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1612 if (GET_CODE (x
) == CONST
1613 && GET_CODE (XEXP (x
, 0)) == PLUS
1614 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1615 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1616 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
1623 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1626 printf("m32r_legitimize_pic_address()\n");
1629 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1631 rtx pic_ref
, address
;
1637 gcc_assert (!reload_in_progress
&& !reload_completed
);
1638 reg
= gen_reg_rtx (Pmode
);
1644 address
= gen_reg_rtx (Pmode
);
1648 current_function_uses_pic_offset_table
= 1;
1650 if (GET_CODE (orig
) == LABEL_REF
1651 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1653 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1654 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1658 emit_insn (gen_pic_load_addr (address
, orig
));
1660 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1661 pic_ref
= gen_const_mem (Pmode
, address
);
1662 insn
= emit_move_insn (reg
, pic_ref
);
1664 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1666 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
1671 else if (GET_CODE (orig
) == CONST
)
1675 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1676 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1681 gcc_assert (!reload_in_progress
&& !reload_completed
);
1682 reg
= gen_reg_rtx (Pmode
);
1685 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1687 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
1689 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
1691 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
1696 if (GET_CODE (offset
) == CONST_INT
)
1698 if (INT16_P (INTVAL (offset
)))
1699 return plus_constant (base
, INTVAL (offset
));
1702 gcc_assert (! reload_in_progress
&& ! reload_completed
);
1703 offset
= force_reg (Pmode
, offset
);
1707 return gen_rtx_PLUS (Pmode
, base
, offset
);
1713 /* Emit special PIC prologues and epilogues. */
1716 m32r_finalize_pic (void)
1718 current_function_uses_pic_offset_table
|= current_function_profile
;
1721 /* Nested function support. */
1723 /* Emit RTL insns to initialize the variable parts of a trampoline.
1724 FNADDR is an RTX for the address of the function's pure code.
1725 CXT is an RTX for the static chain value for the function. */
1728 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
1729 rtx fnaddr ATTRIBUTE_UNUSED
,
1730 rtx cxt ATTRIBUTE_UNUSED
)
1735 m32r_file_start (void)
1737 default_file_start ();
1739 if (flag_verbose_asm
)
1740 fprintf (asm_out_file
,
1741 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
1742 ASM_COMMENT_START
, g_switch_value
);
1744 if (TARGET_LITTLE_ENDIAN
)
1745 fprintf (asm_out_file
, "\t.little\n");
1748 /* Print operand X (an rtx) in assembler syntax to file FILE.
1749 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1750 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1753 m32r_print_operand (FILE * file
, rtx x
, int code
)
1759 /* The 's' and 'p' codes are used by output_block_move() to
1760 indicate post-increment 's'tores and 'p're-increment loads. */
1762 if (GET_CODE (x
) == REG
)
1763 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
1765 output_operand_lossage ("invalid operand to %%s code");
1769 if (GET_CODE (x
) == REG
)
1770 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
1772 output_operand_lossage ("invalid operand to %%p code");
1776 /* Write second word of DImode or DFmode reference,
1777 register or memory. */
1778 if (GET_CODE (x
) == REG
)
1779 fputs (reg_names
[REGNO (x
)+1], file
);
1780 else if (GET_CODE (x
) == MEM
)
1782 fprintf (file
, "@(");
1783 /* Handle possible auto-increment. Since it is pre-increment and
1784 we have already done it, we can just use an offset of four. */
1785 /* ??? This is taken from rs6000.c I think. I don't think it is
1786 currently necessary, but keep it around. */
1787 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1788 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1789 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
1791 output_address (plus_constant (XEXP (x
, 0), 4));
1795 output_operand_lossage ("invalid operand to %%R code");
1798 case 'H' : /* High word. */
1799 case 'L' : /* Low word. */
1800 if (GET_CODE (x
) == REG
)
1802 /* L = least significant word, H = most significant word. */
1803 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
1804 fputs (reg_names
[REGNO (x
)], file
);
1806 fputs (reg_names
[REGNO (x
)+1], file
);
1808 else if (GET_CODE (x
) == CONST_INT
1809 || GET_CODE (x
) == CONST_DOUBLE
)
1813 split_double (x
, &first
, &second
);
1814 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1815 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
1818 output_operand_lossage ("invalid operand to %%H/%%L code");
1825 if (GET_CODE (x
) != CONST_DOUBLE
1826 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
1827 fatal_insn ("bad insn for 'A'", x
);
1829 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
1830 fprintf (file
, "%s", str
);
1834 case 'B' : /* Bottom half. */
1835 case 'T' : /* Top half. */
1836 /* Output the argument to a `seth' insn (sets the Top half-word).
1837 For constants output arguments to a seth/or3 pair to set Top and
1838 Bottom halves. For symbols output arguments to a seth/add3 pair to
1839 set Top and Bottom halves. The difference exists because for
1840 constants seth/or3 is more readable but for symbols we need to use
1841 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1842 switch (GET_CODE (x
))
1849 split_double (x
, &first
, &second
);
1850 x
= WORDS_BIG_ENDIAN
? second
: first
;
1851 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1853 ? INTVAL (x
) & 0xffff
1854 : (INTVAL (x
) >> 16) & 0xffff));
1860 && small_data_operand (x
, VOIDmode
))
1862 fputs ("sda(", file
);
1863 output_addr_const (file
, x
);
1869 fputs (code
== 'T' ? "shigh(" : "low(", file
);
1870 output_addr_const (file
, x
);
1874 output_operand_lossage ("invalid operand to %%T/%%B code");
1881 /* Output a load/store with update indicator if appropriate. */
1882 if (GET_CODE (x
) == MEM
)
1884 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
1885 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
1889 output_operand_lossage ("invalid operand to %%U code");
1893 /* Print a constant value negated. */
1894 if (GET_CODE (x
) == CONST_INT
)
1895 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
1897 output_operand_lossage ("invalid operand to %%N code");
1901 /* Print a const_int in hex. Used in comments. */
1902 if (GET_CODE (x
) == CONST_INT
)
1903 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
1907 fputs (IMMEDIATE_PREFIX
, file
);
1911 /* Do nothing special. */
1916 output_operand_lossage ("invalid operand output code");
1919 switch (GET_CODE (x
))
1922 fputs (reg_names
[REGNO (x
)], file
);
1927 if (GET_CODE (addr
) == PRE_INC
)
1929 if (GET_CODE (XEXP (addr
, 0)) != REG
)
1930 fatal_insn ("pre-increment address is not a register", x
);
1932 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
1934 else if (GET_CODE (addr
) == PRE_DEC
)
1936 if (GET_CODE (XEXP (addr
, 0)) != REG
)
1937 fatal_insn ("pre-decrement address is not a register", x
);
1939 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
1941 else if (GET_CODE (addr
) == POST_INC
)
1943 if (GET_CODE (XEXP (addr
, 0)) != REG
)
1944 fatal_insn ("post-increment address is not a register", x
);
1946 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
1951 output_address (XEXP (x
, 0));
1957 /* We handle SFmode constants here as output_addr_const doesn't. */
1958 if (GET_MODE (x
) == SFmode
)
1963 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1964 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
1965 fprintf (file
, "0x%08lx", l
);
1969 /* Fall through. Let output_addr_const deal with it. */
1972 output_addr_const (file
, x
);
1977 /* Print a memory address as an operand to reference that memory location. */
1980 m32r_print_operand_address (FILE * file
, rtx addr
)
1986 switch (GET_CODE (addr
))
1989 fputs (reg_names
[REGNO (addr
)], file
);
1993 if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
1994 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
1995 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1996 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
1998 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
1999 if (GET_CODE (base
) == REG
)
2001 /* Print the offset first (if present) to conform to the manual. */
2005 fprintf (file
, "%d,", offset
);
2006 fputs (reg_names
[REGNO (base
)], file
);
2008 /* The chip doesn't support this, but left in for generality. */
2009 else if (GET_CODE (index
) == REG
)
2010 fprintf (file
, "%s,%s",
2011 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2012 /* Not sure this can happen, but leave in for now. */
2013 else if (GET_CODE (index
) == SYMBOL_REF
)
2015 output_addr_const (file
, index
);
2017 fputs (reg_names
[REGNO (base
)], file
);
2020 fatal_insn ("bad address", addr
);
2022 else if (GET_CODE (base
) == LO_SUM
)
2024 gcc_assert (!index
&& GET_CODE (XEXP (base
, 0)) == REG
);
2025 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2026 fputs ("sda(", file
);
2028 fputs ("low(", file
);
2029 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2031 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2034 fatal_insn ("bad address", addr
);
2038 if (GET_CODE (XEXP (addr
, 0)) != REG
)
2039 fatal_insn ("lo_sum not of register", addr
);
2040 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2041 fputs ("sda(", file
);
2043 fputs ("low(", file
);
2044 output_addr_const (file
, XEXP (addr
, 1));
2046 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2049 case PRE_INC
: /* Assume SImode. */
2050 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2053 case PRE_DEC
: /* Assume SImode. */
2054 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2057 case POST_INC
: /* Assume SImode. */
2058 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2062 output_addr_const (file
, addr
);
2067 /* Return true if the operands are the constants 0 and 1. */
2070 zero_and_one (rtx operand1
, rtx operand2
)
2073 GET_CODE (operand1
) == CONST_INT
2074 && GET_CODE (operand2
) == CONST_INT
2075 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2076 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2079 /* Generate the correct assembler code to handle the conditional loading of a
2080 value into a register. It is known that the operands satisfy the
2081 conditional_move_operand() function above. The destination is operand[0].
2082 The condition is operand [1]. The 'true' value is operand [2] and the
2083 'false' value is operand [3]. */
2086 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2088 static char buffer
[100];
2089 const char * dest
= reg_names
[REGNO (operands
[0])];
2093 /* Destination must be a register. */
2094 gcc_assert (GET_CODE (operands
[0]) == REG
);
2095 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2096 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2098 /* Check to see if the test is reversed. */
2099 if (GET_CODE (operands
[1]) == NE
)
2101 rtx tmp
= operands
[2];
2102 operands
[2] = operands
[3];
2106 sprintf (buffer
, "mvfc %s, cbr", dest
);
2108 /* If the true value was '0' then we need to invert the results of the move. */
2109 if (INTVAL (operands
[2]) == 0)
2110 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2116 /* Returns true if the registers contained in the two
2117 rtl expressions are different. */
2120 m32r_not_same_reg (rtx a
, rtx b
)
2125 while (GET_CODE (a
) == SUBREG
)
2128 if (GET_CODE (a
) == REG
)
2131 while (GET_CODE (b
) == SUBREG
)
2134 if (GET_CODE (b
) == REG
)
2137 return reg_a
!= reg_b
;
2142 m32r_function_symbol (const char *name
)
2144 int extra_flags
= 0;
2145 enum m32r_model model
;
2146 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2148 if (TARGET_MODEL_SMALL
)
2149 model
= M32R_MODEL_SMALL
;
2150 else if (TARGET_MODEL_MEDIUM
)
2151 model
= M32R_MODEL_MEDIUM
;
2152 else if (TARGET_MODEL_LARGE
)
2153 model
= M32R_MODEL_LARGE
;
2155 gcc_unreachable (); /* Shouldn't happen. */
2156 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2159 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2164 /* Use a library function to move some bytes. */
2167 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2169 /* We want to pass the size as Pmode, which will normally be SImode
2170 but will be DImode if we are using 64 bit longs and pointers. */
2171 if (GET_MODE (bytes_rtx
) != VOIDmode
2172 && GET_MODE (bytes_rtx
) != Pmode
)
2173 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2175 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2176 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2177 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2178 TYPE_UNSIGNED (sizetype
)),
2179 TYPE_MODE (sizetype
));
2182 /* Expand string/block move operations.
2184 operands[0] is the pointer to the destination.
2185 operands[1] is the pointer to the source.
2186 operands[2] is the number of bytes to move.
2187 operands[3] is the alignment.
2189 Returns 1 upon success, 0 otherwise. */
2192 m32r_expand_block_move (rtx operands
[])
2194 rtx orig_dst
= operands
[0];
2195 rtx orig_src
= operands
[1];
2196 rtx bytes_rtx
= operands
[2];
2197 rtx align_rtx
= operands
[3];
2198 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2199 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2200 int align
= INTVAL (align_rtx
);
2205 if (constp
&& bytes
<= 0)
2208 /* Move the address into scratch registers. */
2209 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2210 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2212 if (align
> UNITS_PER_WORD
)
2213 align
= UNITS_PER_WORD
;
2215 /* If we prefer size over speed, always use a function call.
2216 If we do not know the size, use a function call.
2217 If the blocks are not word aligned, use a function call. */
2218 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2220 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2224 leftover
= bytes
% MAX_MOVE_BYTES
;
2227 /* If necessary, generate a loop to handle the bulk of the copy. */
2230 rtx label
= NULL_RTX
;
2231 rtx final_src
= NULL_RTX
;
2232 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2233 rtx rounded_total
= GEN_INT (bytes
);
2234 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2235 rtx new_src_reg
= gen_reg_rtx (SImode
);
2237 /* If we are going to have to perform this loop more than
2238 once, then generate a label and compute the address the
2239 source register will contain upon completion of the final
2241 if (bytes
> MAX_MOVE_BYTES
)
2243 final_src
= gen_reg_rtx (Pmode
);
2246 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2249 emit_insn (gen_movsi (final_src
, rounded_total
));
2250 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2253 label
= gen_label_rtx ();
2257 /* It is known that output_block_move() will update src_reg to point
2258 to the word after the end of the source block, and dst_reg to point
2259 to the last word of the destination block, provided that the block
2260 is MAX_MOVE_BYTES long. */
2261 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2262 new_dst_reg
, new_src_reg
));
2263 emit_move_insn (dst_reg
, new_dst_reg
);
2264 emit_move_insn (src_reg
, new_src_reg
);
2265 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2267 if (bytes
> MAX_MOVE_BYTES
)
2269 emit_insn (gen_cmpsi (src_reg
, final_src
));
2270 emit_jump_insn (gen_bne (label
));
2275 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2276 gen_reg_rtx (SImode
),
2277 gen_reg_rtx (SImode
)));
2282 /* Emit load/stores for a small constant word aligned block_move.
2284 operands[0] is the memory address of the destination.
2285 operands[1] is the memory address of the source.
2286 operands[2] is the number of bytes to move.
2287 operands[3] is a temp register.
2288 operands[4] is a temp register. */
2291 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2293 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2297 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2299 /* We do not have a post-increment store available, so the first set of
2300 stores are done without any increment, then the remaining ones can use
2301 the pre-increment addressing mode.
2303 Note: expand_block_move() also relies upon this behavior when building
2304 loops to copy large blocks. */
2313 output_asm_insn ("ld\t%5, %p1", operands
);
2314 output_asm_insn ("ld\t%6, %p1", operands
);
2315 output_asm_insn ("st\t%5, @%0", operands
);
2316 output_asm_insn ("st\t%6, %s0", operands
);
2320 output_asm_insn ("ld\t%5, %p1", operands
);
2321 output_asm_insn ("ld\t%6, %p1", operands
);
2322 output_asm_insn ("st\t%5, %s0", operands
);
2323 output_asm_insn ("st\t%6, %s0", operands
);
2328 else if (bytes
>= 4)
2333 output_asm_insn ("ld\t%5, %p1", operands
);
2336 output_asm_insn ("ld\t%6, %p1", operands
);
2339 output_asm_insn ("st\t%5, @%0", operands
);
2341 output_asm_insn ("st\t%5, %s0", operands
);
2347 /* Get the entire next word, even though we do not want all of it.
2348 The saves us from doing several smaller loads, and we assume that
2349 we cannot cause a page fault when at least part of the word is in
2350 valid memory [since we don't get called if things aren't properly
2352 int dst_offset
= first_time
? 0 : 4;
2353 /* The amount of increment we have to make to the
2354 destination pointer. */
2355 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2356 /* The same for the source pointer. */
2357 int src_inc_amount
= bytes
;
2361 /* If got_extra is true then we have already loaded
2362 the next word as part of loading and storing the previous word. */
2364 output_asm_insn ("ld\t%6, @%1", operands
);
2370 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2371 my_operands
[0] = operands
[5];
2372 my_operands
[1] = GEN_INT (dst_offset
);
2373 my_operands
[2] = operands
[0];
2374 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2376 /* If there is a byte left to store then increment the
2377 destination address and shift the contents of the source
2378 register down by 8 bits. We could not do the address
2379 increment in the store half word instruction, because it does
2380 not have an auto increment mode. */
2381 if (bytes
> 0) /* assert (bytes == 1) */
2392 my_operands
[0] = operands
[6];
2393 my_operands
[1] = GEN_INT (last_shift
);
2394 output_asm_insn ("srai\t%0, #%1", my_operands
);
2395 my_operands
[0] = operands
[6];
2396 my_operands
[1] = GEN_INT (dst_offset
);
2397 my_operands
[2] = operands
[0];
2398 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2401 /* Update the destination pointer if needed. We have to do
2402 this so that the patterns matches what we output in this
2405 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2407 my_operands
[0] = operands
[0];
2408 my_operands
[1] = GEN_INT (dst_inc_amount
);
2409 output_asm_insn ("addi\t%0, #%1", my_operands
);
2412 /* Update the source pointer if needed. We have to do this
2413 so that the patterns matches what we output in this
2416 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2418 my_operands
[0] = operands
[1];
2419 my_operands
[1] = GEN_INT (src_inc_amount
);
2420 output_asm_insn ("addi\t%0, #%1", my_operands
);
2430 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2433 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2434 unsigned int new_reg
)
2436 /* Interrupt routines can't clobber any register that isn't already used. */
2437 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2438 && !regs_ever_live
[new_reg
])
2441 /* We currently emit epilogues as text, not rtl, so the liveness
2442 of the return address register isn't visible. */
2443 if (current_function_is_leaf
&& new_reg
== RETURN_ADDR_REGNUM
)
2450 m32r_return_addr (int count
)
2455 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);