1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
37 #include "diagnostic-core.h"
39 #include "integrate.h"
43 #include "target-def.h"
44 #include "tm-constrs.h"
46 /* Array of valid operand punctuation characters. */
47 static char m32r_punct_chars
[256];
49 /* Selected code model. */
50 enum m32r_model m32r_model
= M32R_MODEL_DEFAULT
;
52 /* Selected SDA support. */
53 enum m32r_sdata m32r_sdata
= M32R_SDATA_DEFAULT
;
55 /* Machine-specific symbol_ref flags. */
56 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
57 #define SYMBOL_REF_MODEL(X) \
58 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
60 /* For string literals, etc. */
61 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
63 /* Forward declaration. */
64 static bool m32r_handle_option (size_t, const char *, int);
65 static void m32r_option_override (void);
66 static void init_reg_tables (void);
67 static void block_move_call (rtx
, rtx
, rtx
);
68 static int m32r_is_insn (rtx
);
69 static bool m32r_legitimate_address_p (enum machine_mode
, rtx
, bool);
70 static rtx
m32r_legitimize_address (rtx
, rtx
, enum machine_mode
);
71 static bool m32r_mode_dependent_address_p (const_rtx
);
72 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
73 static void m32r_print_operand (FILE *, rtx
, int);
74 static void m32r_print_operand_address (FILE *, rtx
);
75 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
76 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
77 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
79 static void m32r_file_start (void);
81 static int m32r_adjust_priority (rtx
, int);
82 static int m32r_issue_rate (void);
84 static void m32r_encode_section_info (tree
, rtx
, int);
85 static bool m32r_in_small_data_p (const_tree
);
86 static bool m32r_return_in_memory (const_tree
, const_tree
);
87 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
88 static rtx
m32r_libcall_value (enum machine_mode
, const_rtx
);
89 static bool m32r_function_value_regno_p (const unsigned int);
90 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
92 static void init_idents (void);
93 static bool m32r_rtx_costs (rtx
, int, int, int *, bool speed
);
94 static int m32r_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
95 static bool m32r_pass_by_reference (CUMULATIVE_ARGS
*, enum machine_mode
,
97 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS
*, enum machine_mode
,
99 static rtx
m32r_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
101 static void m32r_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
103 static bool m32r_can_eliminate (const int, const int);
104 static void m32r_conditional_register_usage (void);
105 static void m32r_trampoline_init (rtx
, tree
, rtx
);
107 /* M32R specific attributes. */
109 static const struct attribute_spec m32r_attribute_table
[] =
111 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
112 { "interrupt", 0, 0, true, false, false, NULL
},
113 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
},
114 { NULL
, 0, 0, false, false, false, NULL
}
117 static const struct default_options m32r_option_optimization_table
[] =
119 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
120 { OPT_LEVELS_1_PLUS
, OPT_fregmove
, NULL
, 1 },
121 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
124 /* Initialize the GCC target structure. */
125 #undef TARGET_ATTRIBUTE_TABLE
126 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
128 #undef TARGET_LEGITIMATE_ADDRESS_P
129 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
130 #undef TARGET_LEGITIMIZE_ADDRESS
131 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
132 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
133 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
135 #undef TARGET_ASM_ALIGNED_HI_OP
136 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
137 #undef TARGET_ASM_ALIGNED_SI_OP
138 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
140 #undef TARGET_PRINT_OPERAND
141 #define TARGET_PRINT_OPERAND m32r_print_operand
142 #undef TARGET_PRINT_OPERAND_ADDRESS
143 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
144 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
145 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
147 #undef TARGET_ASM_FUNCTION_PROLOGUE
148 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
149 #undef TARGET_ASM_FUNCTION_EPILOGUE
150 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
152 #undef TARGET_ASM_FILE_START
153 #define TARGET_ASM_FILE_START m32r_file_start
155 #undef TARGET_SCHED_ADJUST_PRIORITY
156 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
157 #undef TARGET_SCHED_ISSUE_RATE
158 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
160 #undef TARGET_DEFAULT_TARGET_FLAGS
161 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
162 #undef TARGET_HANDLE_OPTION
163 #define TARGET_HANDLE_OPTION m32r_handle_option
164 #undef TARGET_OPTION_OVERRIDE
165 #define TARGET_OPTION_OVERRIDE m32r_option_override
166 #undef TARGET_OPTION_OPTIMIZATION_TABLE
167 #define TARGET_OPTION_OPTIMIZATION_TABLE m32r_option_optimization_table
169 #undef TARGET_ENCODE_SECTION_INFO
170 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
171 #undef TARGET_IN_SMALL_DATA_P
172 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
175 #undef TARGET_MEMORY_MOVE_COST
176 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS m32r_rtx_costs
179 #undef TARGET_ADDRESS_COST
180 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
182 #undef TARGET_PROMOTE_PROTOTYPES
183 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
184 #undef TARGET_RETURN_IN_MEMORY
185 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
187 #undef TARGET_FUNCTION_VALUE
188 #define TARGET_FUNCTION_VALUE m32r_function_value
189 #undef TARGET_LIBCALL_VALUE
190 #define TARGET_LIBCALL_VALUE m32r_libcall_value
191 #undef TARGET_FUNCTION_VALUE_REGNO_P
192 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
194 #undef TARGET_SETUP_INCOMING_VARARGS
195 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
196 #undef TARGET_MUST_PASS_IN_STACK
197 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
198 #undef TARGET_PASS_BY_REFERENCE
199 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
200 #undef TARGET_ARG_PARTIAL_BYTES
201 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
202 #undef TARGET_FUNCTION_ARG
203 #define TARGET_FUNCTION_ARG m32r_function_arg
204 #undef TARGET_FUNCTION_ARG_ADVANCE
205 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
207 #undef TARGET_CAN_ELIMINATE
208 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
210 #undef TARGET_CONDITIONAL_REGISTER_USAGE
211 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
213 #undef TARGET_TRAMPOLINE_INIT
214 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
216 #undef TARGET_EXCEPT_UNWIND_INFO
217 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
219 struct gcc_target targetm
= TARGET_INITIALIZER
;
221 /* Implement TARGET_HANDLE_OPTION. */
224 m32r_handle_option (size_t code
, const char *arg
, int value
)
229 target_flags
&= ~(MASK_M32R2
| MASK_M32RX
);
233 if (strcmp (arg
, "small") == 0)
234 m32r_model
= M32R_MODEL_SMALL
;
235 else if (strcmp (arg
, "medium") == 0)
236 m32r_model
= M32R_MODEL_MEDIUM
;
237 else if (strcmp (arg
, "large") == 0)
238 m32r_model
= M32R_MODEL_LARGE
;
244 if (strcmp (arg
, "none") == 0)
245 m32r_sdata
= M32R_SDATA_NONE
;
246 else if (strcmp (arg
, "sdata") == 0)
247 m32r_sdata
= M32R_SDATA_SDATA
;
248 else if (strcmp (arg
, "use") == 0)
249 m32r_sdata
= M32R_SDATA_USE
;
254 case OPT_mno_flush_func
:
255 m32r_cache_flush_func
= NULL
;
258 case OPT_mflush_trap_
:
261 case OPT_mno_flush_trap
:
262 m32r_cache_flush_trap
= -1;
270 /* Called by m32r_option_override to initialize various things. */
277 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
278 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
279 m32r_punct_chars
['#'] = 1;
280 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
282 /* Provide default value if not specified. */
283 if (!global_options_set
.x_g_switch_value
)
284 g_switch_value
= SDATA_DEFAULT_SIZE
;
288 m32r_option_override (void)
290 /* These need to be done at start up.
291 It's convenient to do them here. */
293 SUBTARGET_OVERRIDE_OPTIONS
;
296 /* Vectors to keep interesting information about registers where it can easily
297 be got. We use to use the actual mode value as the bit number, but there
298 is (or may be) more than 32 modes now. Instead we use two tables: one
299 indexed by hard register number, and one indexed by mode. */
301 /* The purpose of m32r_mode_class is to shrink the range of modes so that
302 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
303 mapped into one m32r_mode_class mode. */
308 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
309 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
312 /* Modes for condition codes. */
313 #define C_MODES (1 << (int) C_MODE)
315 /* Modes for single-word and smaller quantities. */
316 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
318 /* Modes for double-word and smaller quantities. */
319 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
321 /* Modes for quad-word and smaller quantities. */
322 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
324 /* Modes for accumulators. */
325 #define A_MODES (1 << (int) A_MODE)
327 /* Value is 1 if register/mode pair is acceptable on arc. */
329 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
331 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
332 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
333 S_MODES
, C_MODES
, A_MODES
, A_MODES
336 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
338 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
341 init_reg_tables (void)
345 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
347 switch (GET_MODE_CLASS (i
))
350 case MODE_PARTIAL_INT
:
351 case MODE_COMPLEX_INT
:
352 if (GET_MODE_SIZE (i
) <= 4)
353 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
354 else if (GET_MODE_SIZE (i
) == 8)
355 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
356 else if (GET_MODE_SIZE (i
) == 16)
357 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
358 else if (GET_MODE_SIZE (i
) == 32)
359 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
361 m32r_mode_class
[i
] = 0;
364 case MODE_COMPLEX_FLOAT
:
365 if (GET_MODE_SIZE (i
) <= 4)
366 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
367 else if (GET_MODE_SIZE (i
) == 8)
368 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
369 else if (GET_MODE_SIZE (i
) == 16)
370 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
371 else if (GET_MODE_SIZE (i
) == 32)
372 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
374 m32r_mode_class
[i
] = 0;
377 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
380 m32r_mode_class
[i
] = 0;
385 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
388 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
389 else if (i
== ARG_POINTER_REGNUM
)
390 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
392 m32r_regno_reg_class
[i
] = NO_REGS
;
396 /* M32R specific attribute support.
398 interrupt - for interrupt functions
400 model - select code model used to access object
402 small: addresses use 24 bits, use bl to make calls
403 medium: addresses use 32 bits, use bl to make calls
404 large: addresses use 32 bits, use seth/add3/jl to make calls
406 Grep for MODEL in m32r.h for more info. */
408 static tree small_ident1
;
409 static tree small_ident2
;
410 static tree medium_ident1
;
411 static tree medium_ident2
;
412 static tree large_ident1
;
413 static tree large_ident2
;
418 if (small_ident1
== 0)
420 small_ident1
= get_identifier ("small");
421 small_ident2
= get_identifier ("__small__");
422 medium_ident1
= get_identifier ("medium");
423 medium_ident2
= get_identifier ("__medium__");
424 large_ident1
= get_identifier ("large");
425 large_ident2
= get_identifier ("__large__");
429 /* Handle an "model" attribute; arguments as in
430 struct attribute_spec.handler. */
432 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
433 tree args
, int flags ATTRIBUTE_UNUSED
,
439 arg
= TREE_VALUE (args
);
441 if (arg
!= small_ident1
442 && arg
!= small_ident2
443 && arg
!= medium_ident1
444 && arg
!= medium_ident2
445 && arg
!= large_ident1
446 && arg
!= large_ident2
)
448 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
449 IDENTIFIER_POINTER (name
));
450 *no_add_attrs
= true;
456 /* Encode section information of DECL, which is either a VAR_DECL,
457 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
459 For the M32R we want to record:
461 - whether the object lives in .sdata/.sbss.
462 - what code model should be used to access the object
466 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
470 enum m32r_model model
;
472 default_encode_section_info (decl
, rtl
, first
);
477 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
484 id
= TREE_VALUE (TREE_VALUE (model_attr
));
486 if (id
== small_ident1
|| id
== small_ident2
)
487 model
= M32R_MODEL_SMALL
;
488 else if (id
== medium_ident1
|| id
== medium_ident2
)
489 model
= M32R_MODEL_MEDIUM
;
490 else if (id
== large_ident1
|| id
== large_ident2
)
491 model
= M32R_MODEL_LARGE
;
493 gcc_unreachable (); /* shouldn't happen */
497 if (TARGET_MODEL_SMALL
)
498 model
= M32R_MODEL_SMALL
;
499 else if (TARGET_MODEL_MEDIUM
)
500 model
= M32R_MODEL_MEDIUM
;
501 else if (TARGET_MODEL_LARGE
)
502 model
= M32R_MODEL_LARGE
;
504 gcc_unreachable (); /* shouldn't happen */
506 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
509 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
512 /* Only mark the object as being small data area addressable if
513 it hasn't been explicitly marked with a code model.
515 The user can explicitly put an object in the small data area with the
516 section attribute. If the object is in sdata/sbss and marked with a
517 code model do both [put the object in .sdata and mark it as being
518 addressed with a specific code model - don't mark it as being addressed
519 with an SDA reloc though]. This is ok and might be useful at times. If
520 the object doesn't fit the linker will give an error. */
523 m32r_in_small_data_p (const_tree decl
)
527 if (TREE_CODE (decl
) != VAR_DECL
)
530 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
533 section
= DECL_SECTION_NAME (decl
);
536 const char *const name
= TREE_STRING_POINTER (section
);
537 if (strcmp (name
, ".sdata") == 0 || strcmp (name
, ".sbss") == 0)
542 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
544 int size
= int_size_in_bytes (TREE_TYPE (decl
));
546 if (size
> 0 && size
<= g_switch_value
)
554 /* Do anything needed before RTL is emitted for each function. */
557 m32r_init_expanders (void)
559 /* ??? At one point there was code here. The function is left in
560 to make it easy to experiment. */
564 call_operand (rtx op
, enum machine_mode mode
)
569 return call_address_operand (op
, mode
);
572 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
575 small_data_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
577 if (! TARGET_SDATA_USE
)
580 if (GET_CODE (op
) == SYMBOL_REF
)
581 return SYMBOL_REF_SMALL_P (op
);
583 if (GET_CODE (op
) == CONST
584 && GET_CODE (XEXP (op
, 0)) == PLUS
585 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
586 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
587 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
592 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
595 addr24_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
602 if (GET_CODE (op
) == LABEL_REF
)
603 return TARGET_ADDR24
;
605 if (GET_CODE (op
) == SYMBOL_REF
)
607 else if (GET_CODE (op
) == CONST
608 && GET_CODE (XEXP (op
, 0)) == PLUS
609 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
610 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
611 sym
= XEXP (XEXP (op
, 0), 0);
615 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
619 && (CONSTANT_POOL_ADDRESS_P (sym
)
620 || LIT_NAME_P (XSTR (sym
, 0))))
626 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
629 addr32_operand (rtx op
, enum machine_mode mode
)
633 if (GET_CODE (op
) == LABEL_REF
)
634 return TARGET_ADDR32
;
636 if (GET_CODE (op
) == SYMBOL_REF
)
638 else if (GET_CODE (op
) == CONST
639 && GET_CODE (XEXP (op
, 0)) == PLUS
640 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
641 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
643 sym
= XEXP (XEXP (op
, 0), 0);
647 return (! addr24_operand (sym
, mode
)
648 && ! small_data_operand (sym
, mode
));
651 /* Return 1 if OP is a function that can be called with the `bl' insn. */
654 call26_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
659 if (GET_CODE (op
) == SYMBOL_REF
)
660 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
662 return TARGET_CALL26
;
665 /* Return 1 if OP is a DImode const we want to handle inline.
666 This must match the code in the movdi pattern.
667 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
670 easy_di_const (rtx op
)
672 rtx high_rtx
, low_rtx
;
673 HOST_WIDE_INT high
, low
;
675 split_double (op
, &high_rtx
, &low_rtx
);
676 high
= INTVAL (high_rtx
);
677 low
= INTVAL (low_rtx
);
678 /* Pick constants loadable with 2 16-bit `ldi' insns. */
679 if (high
>= -128 && high
<= 127
680 && low
>= -128 && low
<= 127)
685 /* Return 1 if OP is a DFmode const we want to handle inline.
686 This must match the code in the movdf pattern.
687 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
690 easy_df_const (rtx op
)
695 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
696 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
697 if (l
[0] == 0 && l
[1] == 0)
699 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
704 /* Return 1 if OP is (mem (reg ...)).
705 This is used in insn length calcs. */
708 memreg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
710 return MEM_P (op
) && REG_P (XEXP (op
, 0));
713 /* Return nonzero if TYPE must be passed by indirect reference. */
716 m32r_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
717 enum machine_mode mode
, const_tree type
,
718 bool named ATTRIBUTE_UNUSED
)
723 size
= int_size_in_bytes (type
);
725 size
= GET_MODE_SIZE (mode
);
727 return (size
< 0 || size
> 8);
732 /* X and Y are two things to compare using CODE. Emit the compare insn and
733 return the rtx for compare [arg0 of the if_then_else].
734 If need_compare is true then the comparison insn must be generated, rather
735 than being subsumed into the following branch instruction. */
738 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
740 enum rtx_code compare_code
;
741 enum rtx_code branch_code
;
742 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
747 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
748 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
749 case LT
: compare_code
= LT
; branch_code
= NE
; break;
750 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
751 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
752 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
753 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
754 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
755 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
756 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
764 switch (compare_code
)
767 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
770 rtx tmp
= gen_reg_rtx (SImode
);
772 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
776 else if (CONSTANT_P (y
)) /* Reg equal to const. */
778 rtx tmp
= force_reg (GET_MODE (x
), y
);
782 if (register_operand (y
, SImode
) /* Reg equal to reg. */
783 || y
== const0_rtx
) /* Reg equal to zero. */
785 emit_insn (gen_cmp_eqsi_insn (x
, y
));
787 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
792 if (register_operand (y
, SImode
)
793 || satisfies_constraint_P (y
))
795 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
800 emit_insn (gen_cmp_ltsi_insn (x
, y
));
807 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
808 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
813 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
815 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
816 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
820 emit_insn (gen_cmp_ltsi_insn (x
, y
));
827 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
832 if (register_operand (y
, SImode
)
833 || satisfies_constraint_P (y
))
835 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
840 emit_insn (gen_cmp_ltusi_insn (x
, y
));
847 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
848 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
853 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
855 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
856 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
860 emit_insn (gen_cmp_ltusi_insn (x
, y
));
867 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
877 /* Reg/reg equal comparison. */
878 if (compare_code
== EQ
879 && register_operand (y
, SImode
))
880 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
882 /* Reg/zero signed comparison. */
883 if ((compare_code
== EQ
|| compare_code
== LT
)
885 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
887 /* Reg/smallconst equal comparison. */
888 if (compare_code
== EQ
889 && satisfies_constraint_P (y
))
891 rtx tmp
= gen_reg_rtx (SImode
);
893 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
894 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
897 /* Reg/const equal comparison. */
898 if (compare_code
== EQ
901 rtx tmp
= force_reg (GET_MODE (x
), y
);
903 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
910 y
= force_reg (GET_MODE (x
), y
);
913 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
916 y
= force_reg (GET_MODE (x
), y
);
920 switch (compare_code
)
923 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
926 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
929 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
936 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
940 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
942 enum machine_mode mode
= GET_MODE (op0
);
944 gcc_assert (mode
== SImode
);
948 if (!register_operand (op1
, mode
))
949 op1
= force_reg (mode
, op1
);
951 if (TARGET_M32RX
|| TARGET_M32R2
)
953 if (!reg_or_zero_operand (op2
, mode
))
954 op2
= force_reg (mode
, op2
);
956 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
959 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
961 emit_insn (gen_seq_zero_insn (op0
, op1
));
965 if (!reg_or_eq_int16_operand (op2
, mode
))
966 op2
= force_reg (mode
, op2
);
968 emit_insn (gen_seq_insn (op0
, op1
, op2
));
972 if (!CONST_INT_P (op2
)
973 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
977 if (reload_completed
|| reload_in_progress
)
980 reg
= gen_reg_rtx (SImode
);
981 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
984 if (!register_operand (op1
, mode
))
985 op1
= force_reg (mode
, op1
);
987 emit_insn (gen_sne_zero_insn (op0
, op1
));
1002 if (!register_operand (op1
, mode
))
1003 op1
= force_reg (mode
, op1
);
1005 if (!reg_or_int16_operand (op2
, mode
))
1006 op2
= force_reg (mode
, op2
);
1008 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1021 if (!register_operand (op1
, mode
))
1022 op1
= force_reg (mode
, op1
);
1024 if (!reg_or_int16_operand (op2
, mode
))
1025 op2
= force_reg (mode
, op2
);
1027 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1032 if (!register_operand (op1
, mode
))
1033 op1
= force_reg (mode
, op1
);
1035 if (!reg_or_int16_operand (op2
, mode
))
1036 op2
= force_reg (mode
, op2
);
1039 emit_insn (gen_sge_insn (op0
, op1
, op2
));
1041 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
1046 if (!register_operand (op1
, mode
))
1047 op1
= force_reg (mode
, op1
);
1049 if (CONST_INT_P (op2
))
1051 HOST_WIDE_INT value
= INTVAL (op2
);
1052 if (value
>= 2147483647)
1054 emit_move_insn (op0
, const1_rtx
);
1058 op2
= GEN_INT (value
+ 1);
1059 if (value
< -32768 || value
>= 32767)
1060 op2
= force_reg (mode
, op2
);
1063 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1065 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1069 if (!register_operand (op2
, mode
))
1070 op2
= force_reg (mode
, op2
);
1073 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1075 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1084 /* Split a 2 word move (DI or DF) into component parts. */
1087 gen_split_move_double (rtx operands
[])
1089 enum machine_mode mode
= GET_MODE (operands
[0]);
1090 rtx dest
= operands
[0];
1091 rtx src
= operands
[1];
1094 /* We might have (SUBREG (MEM)) here, so just get rid of the
1095 subregs to make this code simpler. It is safe to call
1096 alter_subreg any time after reload. */
1097 if (GET_CODE (dest
) == SUBREG
)
1098 alter_subreg (&dest
);
1099 if (GET_CODE (src
) == SUBREG
)
1100 alter_subreg (&src
);
1105 int dregno
= REGNO (dest
);
1110 int sregno
= REGNO (src
);
1112 int reverse
= (dregno
== sregno
+ 1);
1114 /* We normally copy the low-numbered register first. However, if
1115 the first register operand 0 is the same as the second register of
1116 operand 1, we must copy in the opposite order. */
1117 emit_insn (gen_rtx_SET (VOIDmode
,
1118 operand_subword (dest
, reverse
, TRUE
, mode
),
1119 operand_subword (src
, reverse
, TRUE
, mode
)));
1121 emit_insn (gen_rtx_SET (VOIDmode
,
1122 operand_subword (dest
, !reverse
, TRUE
, mode
),
1123 operand_subword (src
, !reverse
, TRUE
, mode
)));
1126 /* Reg = constant. */
1127 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1130 split_double (src
, &words
[0], &words
[1]);
1131 emit_insn (gen_rtx_SET (VOIDmode
,
1132 operand_subword (dest
, 0, TRUE
, mode
),
1135 emit_insn (gen_rtx_SET (VOIDmode
,
1136 operand_subword (dest
, 1, TRUE
, mode
),
1141 else if (MEM_P (src
))
1143 /* If the high-address word is used in the address, we must load it
1144 last. Otherwise, load it first. */
1146 = (refers_to_regno_p (dregno
, dregno
+ 1, XEXP (src
, 0), 0) != 0);
1148 /* We used to optimize loads from single registers as
1152 if r3 were not used subsequently. However, the REG_NOTES aren't
1153 propagated correctly by the reload phase, and it can cause bad
1154 code to be generated. We could still try:
1156 ld r1,r3+; ld r2,r3; addi r3,-4
1158 which saves 2 bytes and doesn't force longword alignment. */
1159 emit_insn (gen_rtx_SET (VOIDmode
,
1160 operand_subword (dest
, reverse
, TRUE
, mode
),
1161 adjust_address (src
, SImode
,
1162 reverse
* UNITS_PER_WORD
)));
1164 emit_insn (gen_rtx_SET (VOIDmode
,
1165 operand_subword (dest
, !reverse
, TRUE
, mode
),
1166 adjust_address (src
, SImode
,
1167 !reverse
* UNITS_PER_WORD
)));
1174 /* We used to optimize loads from single registers as
1178 if r3 were not used subsequently. However, the REG_NOTES aren't
1179 propagated correctly by the reload phase, and it can cause bad
1180 code to be generated. We could still try:
1182 st r1,r3; st r2,+r3; addi r3,-4
1184 which saves 2 bytes and doesn't force longword alignment. */
1185 else if (MEM_P (dest
) && REG_P (src
))
1187 emit_insn (gen_rtx_SET (VOIDmode
,
1188 adjust_address (dest
, SImode
, 0),
1189 operand_subword (src
, 0, TRUE
, mode
)));
1191 emit_insn (gen_rtx_SET (VOIDmode
,
1192 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1193 operand_subword (src
, 1, TRUE
, mode
)));
1206 m32r_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1207 tree type
, bool named ATTRIBUTE_UNUSED
)
1211 (((mode
== BLKmode
&& type
)
1212 ? (unsigned int) int_size_in_bytes (type
)
1213 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1216 if (*cum
>= M32R_MAX_PARM_REGS
)
1218 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1219 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1223 return words
* UNITS_PER_WORD
;
1226 /* The ROUND_ADVANCE* macros are local to this file. */
1227 /* Round SIZE up to a word boundary. */
1228 #define ROUND_ADVANCE(SIZE) \
1229 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1231 /* Round arg MODE/TYPE up to the next word boundary. */
1232 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1233 ((MODE) == BLKmode \
1234 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1235 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1237 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1238 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1240 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1241 a reg. This includes arguments that have to be passed by reference as the
1242 pointer to them is passed in a reg if one is available (and that is what
1244 This macro is only used in this file. */
1245 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1246 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1248 /* Determine where to put an argument to a function.
1249 Value is zero to push the argument on the stack,
1250 or a hard register in which to store the argument.
1252 MODE is the argument's machine mode.
1253 TYPE is the data type of the argument (as a tree).
1254 This is null for libcalls where that information may
1256 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1257 the preceding args and about the function being called.
1258 NAMED is nonzero if this argument is a named parameter
1259 (otherwise it is an extra parameter matching an ellipsis). */
1260 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1261 and the rest are pushed. */
1264 m32r_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1265 const_tree type ATTRIBUTE_UNUSED
,
1266 bool named ATTRIBUTE_UNUSED
)
1268 return (PASS_IN_REG_P (*cum
, mode
, type
)
1269 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1273 /* Update the data in CUM to advance over an argument
1274 of mode MODE and data type TYPE.
1275 (TYPE is null for libcalls where that information may not be available.) */
1278 m32r_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1279 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1281 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1282 + ROUND_ADVANCE_ARG (mode
, type
));
1285 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1288 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1290 return m32r_pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
1293 /* Worker function for TARGET_FUNCTION_VALUE. */
1296 m32r_function_value (const_tree valtype
,
1297 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1298 bool outgoing ATTRIBUTE_UNUSED
)
1300 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1303 /* Worker function for TARGET_LIBCALL_VALUE. */
1306 m32r_libcall_value (enum machine_mode mode
,
1307 const_rtx fun ATTRIBUTE_UNUSED
)
1309 return gen_rtx_REG (mode
, 0);
1312 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1314 ??? What about r1 in DI/DF values. */
1317 m32r_function_value_regno_p (const unsigned int regno
)
1319 return (regno
== 0);
1322 /* Do any needed setup for a variadic function. For the M32R, we must
1323 create a register parameter block, and then copy any anonymous arguments
1324 in registers to memory.
1326 CUM has not been updated for the last named argument which has type TYPE
1327 and mode MODE, and we rely on this fact. */
1330 m32r_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1331 tree type
, int *pretend_size
, int no_rtl
)
1338 /* All BLKmode values are passed by reference. */
1339 gcc_assert (mode
!= BLKmode
);
1341 first_anon_arg
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1342 + ROUND_ADVANCE_ARG (mode
, type
));
1344 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1346 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1347 int first_reg_offset
= first_anon_arg
;
1348 /* Size in words to "pretend" allocate. */
1349 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1352 regblock
= gen_frame_mem (BLKmode
,
1353 plus_constant (arg_pointer_rtx
,
1354 FIRST_PARM_OFFSET (0)));
1355 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1356 move_block_from_reg (first_reg_offset
, regblock
, size
);
1358 *pretend_size
= (size
* UNITS_PER_WORD
);
1363 /* Return true if INSN is real instruction bearing insn. */
1366 m32r_is_insn (rtx insn
)
1368 return (NONDEBUG_INSN_P (insn
)
1369 && GET_CODE (PATTERN (insn
)) != USE
1370 && GET_CODE (PATTERN (insn
)) != CLOBBER
1371 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
);
1374 /* Increase the priority of long instructions so that the
1375 short instructions are scheduled ahead of the long ones. */
1378 m32r_adjust_priority (rtx insn
, int priority
)
1380 if (m32r_is_insn (insn
)
1381 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1388 /* Indicate how many instructions can be issued at the same time.
1389 This is sort of a lie. The m32r can issue only 1 long insn at
1390 once, but it can issue 2 short insns. The default therefore is
1391 set at 2, but this can be overridden by the command line option
1395 m32r_issue_rate (void)
1397 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1400 /* Cost functions. */
1402 /* Implement TARGET_HANDLE_OPTION.
1404 Memory is 3 times as expensive as registers.
1405 ??? Is that the right way to look at it? */
1408 m32r_memory_move_cost (enum machine_mode mode
,
1409 reg_class_t rclass ATTRIBUTE_UNUSED
,
1410 bool in ATTRIBUTE_UNUSED
)
1412 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1419 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
, int *total
,
1420 bool speed ATTRIBUTE_UNUSED
)
1424 /* Small integers are as cheap as registers. 4 byte values can be
1425 fetched as immediate constants - let's give that the cost of an
1428 if (INT16_P (INTVAL (x
)))
1438 *total
= COSTS_N_INSNS (1);
1445 split_double (x
, &high
, &low
);
1446 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1447 + !INT16_P (INTVAL (low
)));
1452 *total
= COSTS_N_INSNS (3);
1459 *total
= COSTS_N_INSNS (10);
1467 /* Type of function DECL.
1469 The result is cached. To reset the cache at the end of a function,
1470 call with DECL = NULL_TREE. */
1472 enum m32r_function_type
1473 m32r_compute_function_type (tree decl
)
1476 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1477 /* Last function we were called for. */
1478 static tree last_fn
= NULL_TREE
;
1480 /* Resetting the cached value? */
1481 if (decl
== NULL_TREE
)
1483 fn_type
= M32R_FUNCTION_UNKNOWN
;
1484 last_fn
= NULL_TREE
;
1488 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1491 /* Compute function type. */
1492 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1493 ? M32R_FUNCTION_INTERRUPT
1494 : M32R_FUNCTION_NORMAL
);
1499 \f/* Function prologue/epilogue handlers. */
1501 /* M32R stack frames look like:
1503 Before call After call
1504 +-----------------------+ +-----------------------+
1506 high | local variables, | | local variables, |
1507 mem | reg save area, etc. | | reg save area, etc. |
1509 +-----------------------+ +-----------------------+
1511 | arguments on stack. | | arguments on stack. |
1513 SP+0->+-----------------------+ +-----------------------+
1514 | reg parm save area, |
1515 | only created for |
1516 | variable argument |
1518 +-----------------------+
1519 | previous frame ptr |
1520 +-----------------------+
1522 | register save area |
1524 +-----------------------+
1526 +-----------------------+
1530 +-----------------------+
1532 | alloca allocations |
1534 +-----------------------+
1536 low | arguments on stack |
1538 SP+0->+-----------------------+
1541 1) The "reg parm save area" does not exist for non variable argument fns.
1542 2) The "reg parm save area" can be eliminated completely if we saved regs
1543 containing anonymous args separately but that complicates things too
1544 much (so it's not done).
1545 3) The return address is saved after the register save area so as to have as
1546 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1548 /* Structure to be filled in by m32r_compute_frame_size with register
1549 save masks, and offsets for the current function. */
1550 struct m32r_frame_info
1552 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1553 unsigned int extra_size
; /* # bytes of extra stuff. */
1554 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1555 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1556 unsigned int reg_size
; /* # bytes needed to store regs. */
1557 unsigned int var_size
; /* # bytes that variables take up. */
1558 unsigned int gmask
; /* Mask of saved gp registers. */
1559 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1560 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1561 int initialized
; /* Nonzero if frame size already calculated. */
1564 /* Current frame information calculated by m32r_compute_frame_size. */
1565 static struct m32r_frame_info current_frame_info
;
1567 /* Zero structure to initialize current_frame_info. */
1568 static struct m32r_frame_info zero_frame_info
;
1570 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1571 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1573 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1574 The return address and frame pointer are treated separately.
1575 Don't consider them here. */
1576 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1577 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1578 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1580 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1581 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1583 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1584 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1586 /* Return the bytes needed to compute the frame pointer from the current
1589 SIZE is the size needed for local variables. */
1592 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1595 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1596 unsigned int reg_size
;
1598 enum m32r_function_type fn_type
;
1600 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1603 var_size
= M32R_STACK_ALIGN (size
);
1604 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1605 pretend_size
= crtl
->args
.pretend_args_size
;
1606 extra_size
= FIRST_PARM_OFFSET (0);
1607 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1611 /* See if this is an interrupt handler. Call used registers must be saved
1613 fn_type
= m32r_compute_function_type (current_function_decl
);
1614 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1616 /* Calculate space needed for registers. */
1617 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1619 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1620 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1622 reg_size
+= UNITS_PER_WORD
;
1623 gmask
|= 1 << regno
;
1627 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1628 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1630 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1632 total_size
+= reg_size
;
1634 /* ??? Not sure this is necessary, and I don't think the epilogue
1635 handler will do the right thing if this changes total_size. */
1636 total_size
= M32R_STACK_ALIGN (total_size
);
1638 /* frame_size = total_size - (pretend_size + reg_size); */
1640 /* Save computed information. */
1641 current_frame_info
.total_size
= total_size
;
1642 current_frame_info
.extra_size
= extra_size
;
1643 current_frame_info
.pretend_size
= pretend_size
;
1644 current_frame_info
.var_size
= var_size
;
1645 current_frame_info
.args_size
= args_size
;
1646 current_frame_info
.reg_size
= reg_size
;
1647 current_frame_info
.gmask
= gmask
;
1648 current_frame_info
.initialized
= reload_completed
;
1650 /* Ok, we're done. */
1654 /* Worker function for TARGET_CAN_ELIMINATE. */
1657 m32r_can_eliminate (const int from
, const int to
)
1659 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1660 ? ! frame_pointer_needed
1665 /* The table we use to reference PIC data. */
1666 static rtx global_offset_table
;
1669 m32r_reload_lr (rtx sp
, int size
)
1671 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1674 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1675 else if (size
< 32768)
1676 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1677 gen_rtx_PLUS (Pmode
, sp
,
1681 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1683 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1684 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1685 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1692 m32r_load_pic_register (void)
1694 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1695 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1696 GEN_INT (TARGET_MODEL_SMALL
)));
1698 /* Need to emit this whether or not we obey regdecls,
1699 since setjmp/longjmp can cause life info to screw up. */
1700 emit_use (pic_offset_table_rtx
);
1703 /* Expand the m32r prologue as a series of insns. */
1706 m32r_expand_prologue (void)
1711 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1714 if (! current_frame_info
.initialized
)
1715 m32r_compute_frame_size (get_frame_size ());
1717 gmask
= current_frame_info
.gmask
;
1719 /* These cases shouldn't happen. Catch them now. */
1720 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1722 /* Allocate space for register arguments if this is a variadic function. */
1723 if (current_frame_info
.pretend_size
!= 0)
1725 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1726 the wrong result on a 64-bit host. */
1727 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1728 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1730 GEN_INT (-pretend_size
)));
1733 /* Save any registers we need to and set up fp. */
1734 if (current_frame_info
.save_fp
)
1735 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1737 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1739 /* Save any needed call-saved regs (and call-used if this is an
1740 interrupt handler). */
1741 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1743 if ((gmask
& (1 << regno
)) != 0)
1744 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1745 gen_rtx_REG (Pmode
, regno
)));
1748 if (current_frame_info
.save_lr
)
1749 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1750 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1752 /* Allocate the stack frame. */
1753 frame_size
= (current_frame_info
.total_size
1754 - (current_frame_info
.pretend_size
1755 + current_frame_info
.reg_size
));
1757 if (frame_size
== 0)
1758 ; /* Nothing to do. */
1759 else if (frame_size
<= 32768)
1760 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1761 GEN_INT (-frame_size
)));
1764 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1766 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1767 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1770 if (frame_pointer_needed
)
1771 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1774 /* Push lr for mcount (form_pc, x). */
1775 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1776 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1780 m32r_load_pic_register ();
1781 m32r_reload_lr (stack_pointer_rtx
,
1782 (crtl
->profile
? 0 : frame_size
));
1785 if (crtl
->profile
&& !pic_reg_used
)
1786 emit_insn (gen_blockage ());
1790 /* Set up the stack and frame pointer (if desired) for the function.
1791 Note, if this is changed, you need to mirror the changes in
1792 m32r_compute_frame_size which calculates the prolog size. */
1795 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1797 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1799 /* If this is an interrupt handler, mark it as such. */
1800 if (M32R_INTERRUPT_P (fn_type
))
1801 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1803 if (! current_frame_info
.initialized
)
1804 m32r_compute_frame_size (size
);
1806 /* This is only for the human reader. */
1808 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1810 current_frame_info
.var_size
,
1811 current_frame_info
.reg_size
/ 4,
1812 current_frame_info
.args_size
,
1813 current_frame_info
.extra_size
);
1816 /* Output RTL to pop register REGNO from the stack. */
1823 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1824 stack_pointer_rtx
));
1825 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1828 /* Expand the m32r epilogue as a series of insns. */
1831 m32r_expand_epilogue (void)
1834 int noepilogue
= FALSE
;
1837 gcc_assert (current_frame_info
.initialized
);
1838 total_size
= current_frame_info
.total_size
;
1840 if (total_size
== 0)
1842 rtx insn
= get_last_insn ();
1844 /* If the last insn was a BARRIER, we don't have to write any code
1845 because a jump (aka return) was put there. */
1846 if (insn
&& NOTE_P (insn
))
1847 insn
= prev_nonnote_insn (insn
);
1848 if (insn
&& BARRIER_P (insn
))
1854 unsigned int var_size
= current_frame_info
.var_size
;
1855 unsigned int args_size
= current_frame_info
.args_size
;
1856 unsigned int gmask
= current_frame_info
.gmask
;
1857 int can_trust_sp_p
= !cfun
->calls_alloca
;
1859 if (flag_exceptions
)
1860 emit_insn (gen_blockage ());
1862 /* The first thing to do is point the sp at the bottom of the register
1866 unsigned int reg_offset
= var_size
+ args_size
;
1868 if (reg_offset
== 0)
1869 ; /* Nothing to do. */
1870 else if (reg_offset
< 32768)
1871 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1872 GEN_INT (reg_offset
)));
1875 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1877 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1878 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1882 else if (frame_pointer_needed
)
1884 unsigned int reg_offset
= var_size
+ args_size
;
1886 if (reg_offset
== 0)
1887 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1888 else if (reg_offset
< 32768)
1889 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1890 GEN_INT (reg_offset
)));
1893 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1895 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1896 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1897 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1904 if (current_frame_info
.save_lr
)
1905 pop (RETURN_ADDR_REGNUM
);
1907 /* Restore any saved registers, in reverse order of course. */
1908 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1909 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1911 if ((gmask
& (1L << regno
)) != 0)
1915 if (current_frame_info
.save_fp
)
1916 pop (FRAME_POINTER_REGNUM
);
1918 /* Remove varargs area if present. */
1919 if (current_frame_info
.pretend_size
!= 0)
1920 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1921 GEN_INT (current_frame_info
.pretend_size
)));
1923 emit_insn (gen_blockage ());
1927 /* Do any necessary cleanup after a function to restore stack, frame,
1931 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED
,
1932 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1934 /* Reset state info for each function. */
1935 current_frame_info
= zero_frame_info
;
1936 m32r_compute_function_type (NULL_TREE
);
1939 /* Return nonzero if this function is known to have a null or 1 instruction
1943 direct_return (void)
1945 if (!reload_completed
)
1948 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1951 if (! current_frame_info
.initialized
)
1952 m32r_compute_frame_size (get_frame_size ());
1954 return current_frame_info
.total_size
== 0;
1961 m32r_legitimate_pic_operand_p (rtx x
)
1963 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1966 if (GET_CODE (x
) == CONST
1967 && GET_CODE (XEXP (x
, 0)) == PLUS
1968 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1969 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1970 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1977 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1980 printf("m32r_legitimize_pic_address()\n");
1983 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1985 rtx pic_ref
, address
;
1990 gcc_assert (!reload_in_progress
&& !reload_completed
);
1991 reg
= gen_reg_rtx (Pmode
);
1997 address
= gen_reg_rtx (Pmode
);
2001 crtl
->uses_pic_offset_table
= 1;
2003 if (GET_CODE (orig
) == LABEL_REF
2004 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
2006 emit_insn (gen_gotoff_load_addr (reg
, orig
));
2007 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
2011 emit_insn (gen_pic_load_addr (address
, orig
));
2013 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
2014 pic_ref
= gen_const_mem (Pmode
, address
);
2015 emit_move_insn (reg
, pic_ref
);
2018 else if (GET_CODE (orig
) == CONST
)
2022 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2023 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
2028 gcc_assert (!reload_in_progress
&& !reload_completed
);
2029 reg
= gen_reg_rtx (Pmode
);
2032 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2034 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
2036 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
2038 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
2043 if (CONST_INT_P (offset
))
2045 if (INT16_P (INTVAL (offset
)))
2046 return plus_constant (base
, INTVAL (offset
));
2049 gcc_assert (! reload_in_progress
&& ! reload_completed
);
2050 offset
= force_reg (Pmode
, offset
);
2054 return gen_rtx_PLUS (Pmode
, base
, offset
);
2061 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2062 enum machine_mode mode ATTRIBUTE_UNUSED
)
2065 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2070 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2073 m32r_mode_dependent_address_p (const_rtx addr
)
2075 if (GET_CODE (addr
) == LO_SUM
)
2081 /* Nested function support. */
2083 /* Emit RTL insns to initialize the variable parts of a trampoline.
2084 FNADDR is an RTX for the address of the function's pure code.
2085 CXT is an RTX for the static chain value for the function. */
2088 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2089 rtx fnaddr ATTRIBUTE_UNUSED
,
2090 rtx cxt ATTRIBUTE_UNUSED
)
2095 m32r_file_start (void)
2097 default_file_start ();
2099 if (flag_verbose_asm
)
2100 fprintf (asm_out_file
,
2101 "%s M32R/D special options: -G %d\n",
2102 ASM_COMMENT_START
, g_switch_value
);
2104 if (TARGET_LITTLE_ENDIAN
)
2105 fprintf (asm_out_file
, "\t.little\n");
2108 /* Print operand X (an rtx) in assembler syntax to file FILE.
2109 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2110 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2113 m32r_print_operand (FILE * file
, rtx x
, int code
)
2119 /* The 's' and 'p' codes are used by output_block_move() to
2120 indicate post-increment 's'tores and 'p're-increment loads. */
2123 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2125 output_operand_lossage ("invalid operand to %%s code");
2130 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2132 output_operand_lossage ("invalid operand to %%p code");
2136 /* Write second word of DImode or DFmode reference,
2137 register or memory. */
2139 fputs (reg_names
[REGNO (x
)+1], file
);
2142 fprintf (file
, "@(");
2143 /* Handle possible auto-increment. Since it is pre-increment and
2144 we have already done it, we can just use an offset of four. */
2145 /* ??? This is taken from rs6000.c I think. I don't think it is
2146 currently necessary, but keep it around. */
2147 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2148 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2149 output_address (plus_constant (XEXP (XEXP (x
, 0), 0), 4));
2151 output_address (plus_constant (XEXP (x
, 0), 4));
2155 output_operand_lossage ("invalid operand to %%R code");
2158 case 'H' : /* High word. */
2159 case 'L' : /* Low word. */
2162 /* L = least significant word, H = most significant word. */
2163 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2164 fputs (reg_names
[REGNO (x
)], file
);
2166 fputs (reg_names
[REGNO (x
)+1], file
);
2168 else if (CONST_INT_P (x
)
2169 || GET_CODE (x
) == CONST_DOUBLE
)
2173 split_double (x
, &first
, &second
);
2174 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2175 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2178 output_operand_lossage ("invalid operand to %%H/%%L code");
2185 if (GET_CODE (x
) != CONST_DOUBLE
2186 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2187 fatal_insn ("bad insn for 'A'", x
);
2189 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2190 fprintf (file
, "%s", str
);
2194 case 'B' : /* Bottom half. */
2195 case 'T' : /* Top half. */
2196 /* Output the argument to a `seth' insn (sets the Top half-word).
2197 For constants output arguments to a seth/or3 pair to set Top and
2198 Bottom halves. For symbols output arguments to a seth/add3 pair to
2199 set Top and Bottom halves. The difference exists because for
2200 constants seth/or3 is more readable but for symbols we need to use
2201 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2202 switch (GET_CODE (x
))
2209 split_double (x
, &first
, &second
);
2210 x
= WORDS_BIG_ENDIAN
? second
: first
;
2211 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2213 ? INTVAL (x
) & 0xffff
2214 : (INTVAL (x
) >> 16) & 0xffff));
2220 && small_data_operand (x
, VOIDmode
))
2222 fputs ("sda(", file
);
2223 output_addr_const (file
, x
);
2229 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2230 output_addr_const (file
, x
);
2234 output_operand_lossage ("invalid operand to %%T/%%B code");
2241 /* Output a load/store with update indicator if appropriate. */
2244 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2245 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2249 output_operand_lossage ("invalid operand to %%U code");
2253 /* Print a constant value negated. */
2254 if (CONST_INT_P (x
))
2255 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2257 output_operand_lossage ("invalid operand to %%N code");
2261 /* Print a const_int in hex. Used in comments. */
2262 if (CONST_INT_P (x
))
2263 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2267 fputs (IMMEDIATE_PREFIX
, file
);
2271 /* Do nothing special. */
2276 output_operand_lossage ("invalid operand output code");
2279 switch (GET_CODE (x
))
2282 fputs (reg_names
[REGNO (x
)], file
);
2287 if (GET_CODE (addr
) == PRE_INC
)
2289 if (!REG_P (XEXP (addr
, 0)))
2290 fatal_insn ("pre-increment address is not a register", x
);
2292 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2294 else if (GET_CODE (addr
) == PRE_DEC
)
2296 if (!REG_P (XEXP (addr
, 0)))
2297 fatal_insn ("pre-decrement address is not a register", x
);
2299 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2301 else if (GET_CODE (addr
) == POST_INC
)
2303 if (!REG_P (XEXP (addr
, 0)))
2304 fatal_insn ("post-increment address is not a register", x
);
2306 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2311 output_address (XEXP (x
, 0));
2317 /* We handle SFmode constants here as output_addr_const doesn't. */
2318 if (GET_MODE (x
) == SFmode
)
2323 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2324 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2325 fprintf (file
, "0x%08lx", l
);
2329 /* Fall through. Let output_addr_const deal with it. */
2332 output_addr_const (file
, x
);
2337 /* Print a memory address as an operand to reference that memory location. */
2340 m32r_print_operand_address (FILE * file
, rtx addr
)
2346 switch (GET_CODE (addr
))
2349 fputs (reg_names
[REGNO (addr
)], file
);
2353 if (CONST_INT_P (XEXP (addr
, 0)))
2354 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2355 else if (CONST_INT_P (XEXP (addr
, 1)))
2356 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2358 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2361 /* Print the offset first (if present) to conform to the manual. */
2365 fprintf (file
, "%d,", offset
);
2366 fputs (reg_names
[REGNO (base
)], file
);
2368 /* The chip doesn't support this, but left in for generality. */
2369 else if (REG_P (index
))
2370 fprintf (file
, "%s,%s",
2371 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2372 /* Not sure this can happen, but leave in for now. */
2373 else if (GET_CODE (index
) == SYMBOL_REF
)
2375 output_addr_const (file
, index
);
2377 fputs (reg_names
[REGNO (base
)], file
);
2380 fatal_insn ("bad address", addr
);
2382 else if (GET_CODE (base
) == LO_SUM
)
2384 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2385 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2386 fputs ("sda(", file
);
2388 fputs ("low(", file
);
2389 output_addr_const (file
, plus_constant (XEXP (base
, 1), offset
));
2391 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2394 fatal_insn ("bad address", addr
);
2398 if (!REG_P (XEXP (addr
, 0)))
2399 fatal_insn ("lo_sum not of register", addr
);
2400 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2401 fputs ("sda(", file
);
2403 fputs ("low(", file
);
2404 output_addr_const (file
, XEXP (addr
, 1));
2406 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2409 case PRE_INC
: /* Assume SImode. */
2410 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2413 case PRE_DEC
: /* Assume SImode. */
2414 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2417 case POST_INC
: /* Assume SImode. */
2418 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2422 output_addr_const (file
, addr
);
2428 m32r_print_operand_punct_valid_p (unsigned char code
)
2430 return m32r_punct_chars
[code
];
2433 /* Return true if the operands are the constants 0 and 1. */
2436 zero_and_one (rtx operand1
, rtx operand2
)
2439 CONST_INT_P (operand1
)
2440 && CONST_INT_P (operand2
)
2441 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2442 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2445 /* Generate the correct assembler code to handle the conditional loading of a
2446 value into a register. It is known that the operands satisfy the
2447 conditional_move_operand() function above. The destination is operand[0].
2448 The condition is operand [1]. The 'true' value is operand [2] and the
2449 'false' value is operand [3]. */
2452 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2454 static char buffer
[100];
2455 const char * dest
= reg_names
[REGNO (operands
[0])];
2459 /* Destination must be a register. */
2460 gcc_assert (REG_P (operands
[0]));
2461 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2462 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2464 /* Check to see if the test is reversed. */
2465 if (GET_CODE (operands
[1]) == NE
)
2467 rtx tmp
= operands
[2];
2468 operands
[2] = operands
[3];
2472 sprintf (buffer
, "mvfc %s, cbr", dest
);
2474 /* If the true value was '0' then we need to invert the results of the move. */
2475 if (INTVAL (operands
[2]) == 0)
2476 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2482 /* Returns true if the registers contained in the two
2483 rtl expressions are different. */
2486 m32r_not_same_reg (rtx a
, rtx b
)
2491 while (GET_CODE (a
) == SUBREG
)
2497 while (GET_CODE (b
) == SUBREG
)
2503 return reg_a
!= reg_b
;
2508 m32r_function_symbol (const char *name
)
2510 int extra_flags
= 0;
2511 enum m32r_model model
;
2512 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2514 if (TARGET_MODEL_SMALL
)
2515 model
= M32R_MODEL_SMALL
;
2516 else if (TARGET_MODEL_MEDIUM
)
2517 model
= M32R_MODEL_MEDIUM
;
2518 else if (TARGET_MODEL_LARGE
)
2519 model
= M32R_MODEL_LARGE
;
2521 gcc_unreachable (); /* Shouldn't happen. */
2522 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2525 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2530 /* Use a library function to move some bytes. */
2533 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2535 /* We want to pass the size as Pmode, which will normally be SImode
2536 but will be DImode if we are using 64-bit longs and pointers. */
2537 if (GET_MODE (bytes_rtx
) != VOIDmode
2538 && GET_MODE (bytes_rtx
) != Pmode
)
2539 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2541 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2542 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2543 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2544 TYPE_UNSIGNED (sizetype
)),
2545 TYPE_MODE (sizetype
));
2548 /* Expand string/block move operations.
2550 operands[0] is the pointer to the destination.
2551 operands[1] is the pointer to the source.
2552 operands[2] is the number of bytes to move.
2553 operands[3] is the alignment.
2555 Returns 1 upon success, 0 otherwise. */
2558 m32r_expand_block_move (rtx operands
[])
2560 rtx orig_dst
= operands
[0];
2561 rtx orig_src
= operands
[1];
2562 rtx bytes_rtx
= operands
[2];
2563 rtx align_rtx
= operands
[3];
2564 int constp
= CONST_INT_P (bytes_rtx
);
2565 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2566 int align
= INTVAL (align_rtx
);
2571 if (constp
&& bytes
<= 0)
2574 /* Move the address into scratch registers. */
2575 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2576 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2578 if (align
> UNITS_PER_WORD
)
2579 align
= UNITS_PER_WORD
;
2581 /* If we prefer size over speed, always use a function call.
2582 If we do not know the size, use a function call.
2583 If the blocks are not word aligned, use a function call. */
2584 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2586 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2590 leftover
= bytes
% MAX_MOVE_BYTES
;
2593 /* If necessary, generate a loop to handle the bulk of the copy. */
2596 rtx label
= NULL_RTX
;
2597 rtx final_src
= NULL_RTX
;
2598 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2599 rtx rounded_total
= GEN_INT (bytes
);
2600 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2601 rtx new_src_reg
= gen_reg_rtx (SImode
);
2603 /* If we are going to have to perform this loop more than
2604 once, then generate a label and compute the address the
2605 source register will contain upon completion of the final
2607 if (bytes
> MAX_MOVE_BYTES
)
2609 final_src
= gen_reg_rtx (Pmode
);
2612 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2615 emit_insn (gen_movsi (final_src
, rounded_total
));
2616 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2619 label
= gen_label_rtx ();
2623 /* It is known that output_block_move() will update src_reg to point
2624 to the word after the end of the source block, and dst_reg to point
2625 to the last word of the destination block, provided that the block
2626 is MAX_MOVE_BYTES long. */
2627 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2628 new_dst_reg
, new_src_reg
));
2629 emit_move_insn (dst_reg
, new_dst_reg
);
2630 emit_move_insn (src_reg
, new_src_reg
);
2631 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2633 if (bytes
> MAX_MOVE_BYTES
)
2635 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2636 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2641 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2642 gen_reg_rtx (SImode
),
2643 gen_reg_rtx (SImode
)));
2648 /* Emit load/stores for a small constant word aligned block_move.
2650 operands[0] is the memory address of the destination.
2651 operands[1] is the memory address of the source.
2652 operands[2] is the number of bytes to move.
2653 operands[3] is a temp register.
2654 operands[4] is a temp register. */
2657 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2659 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2663 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2665 /* We do not have a post-increment store available, so the first set of
2666 stores are done without any increment, then the remaining ones can use
2667 the pre-increment addressing mode.
2669 Note: expand_block_move() also relies upon this behavior when building
2670 loops to copy large blocks. */
2679 output_asm_insn ("ld\t%5, %p1", operands
);
2680 output_asm_insn ("ld\t%6, %p1", operands
);
2681 output_asm_insn ("st\t%5, @%0", operands
);
2682 output_asm_insn ("st\t%6, %s0", operands
);
2686 output_asm_insn ("ld\t%5, %p1", operands
);
2687 output_asm_insn ("ld\t%6, %p1", operands
);
2688 output_asm_insn ("st\t%5, %s0", operands
);
2689 output_asm_insn ("st\t%6, %s0", operands
);
2694 else if (bytes
>= 4)
2699 output_asm_insn ("ld\t%5, %p1", operands
);
2702 output_asm_insn ("ld\t%6, %p1", operands
);
2705 output_asm_insn ("st\t%5, @%0", operands
);
2707 output_asm_insn ("st\t%5, %s0", operands
);
2713 /* Get the entire next word, even though we do not want all of it.
2714 The saves us from doing several smaller loads, and we assume that
2715 we cannot cause a page fault when at least part of the word is in
2716 valid memory [since we don't get called if things aren't properly
2718 int dst_offset
= first_time
? 0 : 4;
2719 /* The amount of increment we have to make to the
2720 destination pointer. */
2721 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2722 /* The same for the source pointer. */
2723 int src_inc_amount
= bytes
;
2727 /* If got_extra is true then we have already loaded
2728 the next word as part of loading and storing the previous word. */
2730 output_asm_insn ("ld\t%6, @%1", operands
);
2736 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2737 my_operands
[0] = operands
[5];
2738 my_operands
[1] = GEN_INT (dst_offset
);
2739 my_operands
[2] = operands
[0];
2740 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2742 /* If there is a byte left to store then increment the
2743 destination address and shift the contents of the source
2744 register down by 8 bits. We could not do the address
2745 increment in the store half word instruction, because it does
2746 not have an auto increment mode. */
2747 if (bytes
> 0) /* assert (bytes == 1) */
2758 my_operands
[0] = operands
[6];
2759 my_operands
[1] = GEN_INT (last_shift
);
2760 output_asm_insn ("srai\t%0, #%1", my_operands
);
2761 my_operands
[0] = operands
[6];
2762 my_operands
[1] = GEN_INT (dst_offset
);
2763 my_operands
[2] = operands
[0];
2764 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2767 /* Update the destination pointer if needed. We have to do
2768 this so that the patterns matches what we output in this
2771 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2773 my_operands
[0] = operands
[0];
2774 my_operands
[1] = GEN_INT (dst_inc_amount
);
2775 output_asm_insn ("addi\t%0, #%1", my_operands
);
2778 /* Update the source pointer if needed. We have to do this
2779 so that the patterns matches what we output in this
2782 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2784 my_operands
[0] = operands
[1];
2785 my_operands
[1] = GEN_INT (src_inc_amount
);
2786 output_asm_insn ("addi\t%0, #%1", my_operands
);
2796 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2799 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2800 unsigned int new_reg
)
2802 /* Interrupt routines can't clobber any register that isn't already used. */
2803 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2804 && !df_regs_ever_live_p (new_reg
))
2811 m32r_return_addr (int count
)
2816 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2820 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2822 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2823 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2824 0x017e8e17 : 0x178e7e01, SImode
));
2825 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2826 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2827 0x0c00ae86 : 0x86ae000c, SImode
));
2828 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2829 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2830 0xe627871e : 0x1e8727e6, SImode
));
2831 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2832 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2833 0xc616c626 : 0x26c61fc6, SImode
));
2834 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2836 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2837 XEXP (DECL_RTL (fndecl
), 0));
2839 if (m32r_cache_flush_trap
>= 0)
2840 emit_insn (gen_flush_icache
2841 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2842 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2843 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2844 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2845 LCT_NORMAL
, VOIDmode
, 3, XEXP (m_tramp
, 0), Pmode
,
2846 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2847 GEN_INT (3), SImode
);
2850 /* True if X is a reg that can be used as a base reg. */
2853 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2860 if (GPR_P (REGNO (x
)))
2865 if (GPR_P (REGNO (x
))
2866 || REGNO (x
) == ARG_POINTER_REGNUM
2867 || ! HARD_REGISTER_P (x
))
2875 m32r_rtx_ok_for_offset_p (const_rtx x
)
2877 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2881 m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2882 const_rtx x
, bool strict
)
2884 if (GET_CODE (x
) == PLUS
2885 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2886 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2892 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2893 since more than one instruction will be required. */
2896 m32r_legitimate_lo_sum_addres_p (enum machine_mode mode
, const_rtx x
,
2899 if (GET_CODE (x
) == LO_SUM
2900 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2901 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2902 && CONSTANT_P (XEXP (x
, 1)))
2908 /* Is this a load and increment operation. */
2911 m32r_load_postinc_p (enum machine_mode mode
, const_rtx x
, bool strict
)
2913 if ((mode
== SImode
|| mode
== SFmode
)
2914 && GET_CODE (x
) == POST_INC
2915 && REG_P (XEXP (x
, 0))
2916 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2922 /* Is this an increment/decrement and store operation. */
2925 m32r_store_preinc_predec_p (enum machine_mode mode
, const_rtx x
, bool strict
)
2927 if ((mode
== SImode
|| mode
== SFmode
)
2928 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2929 && REG_P (XEXP (x
, 0)) \
2930 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2936 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2939 m32r_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
2941 if (m32r_rtx_ok_for_base_p (x
, strict
)
2942 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2943 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2944 || m32r_load_postinc_p (mode
, x
, strict
)
2945 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2952 m32r_conditional_register_usage (void)
2956 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2957 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;