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* config/m32r/m32r.h (OPTIMIZATION_OPTIONS): Remove reference to flag_strength_reduce.
[thirdparty/gcc.git] / gcc / config / m32r / m32r.c
1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "ggc.h"
41 #include "integrate.h"
42 #include "tm_p.h"
43 #include "target.h"
44 #include "target-def.h"
45
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0, m32r_compare_op1;
49
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars[256];
52
53 /* Selected code model. */
54 enum m32r_model m32r_model = M32R_MODEL_DEFAULT;
55
56 /* Selected SDA support. */
57 enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT;
58
59 /* Machine-specific symbol_ref flags. */
60 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
61 #define SYMBOL_REF_MODEL(X) \
62 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
63
64 /* For string literals, etc. */
65 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
66
67 /* Forward declaration. */
68 static bool m32r_handle_option (size_t, const char *, int);
69 static void init_reg_tables (void);
70 static void block_move_call (rtx, rtx, rtx);
71 static int m32r_is_insn (rtx);
72 const struct attribute_spec m32r_attribute_table[];
73 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
74 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
75 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
76
77 static void m32r_file_start (void);
78
79 static int m32r_adjust_priority (rtx, int);
80 static int m32r_issue_rate (void);
81
82 static void m32r_encode_section_info (tree, rtx, int);
83 static bool m32r_in_small_data_p (tree);
84 static bool m32r_return_in_memory (tree, tree);
85 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
86 tree, int *, int);
87 static void init_idents (void);
88 static bool m32r_rtx_costs (rtx, int, int, int *);
89 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
90 tree, bool);
91 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
92 tree, bool);
93 \f
94 /* Initialize the GCC target structure. */
95 #undef TARGET_ATTRIBUTE_TABLE
96 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
97
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
102
103 #undef TARGET_ASM_FUNCTION_PROLOGUE
104 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
105 #undef TARGET_ASM_FUNCTION_EPILOGUE
106 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
107
108 #undef TARGET_ASM_FILE_START
109 #define TARGET_ASM_FILE_START m32r_file_start
110
111 #undef TARGET_SCHED_ADJUST_PRIORITY
112 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
113 #undef TARGET_SCHED_ISSUE_RATE
114 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
115
116 #undef TARGET_DEFAULT_TARGET_FLAGS
117 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
118 #undef TARGET_HANDLE_OPTION
119 #define TARGET_HANDLE_OPTION m32r_handle_option
120
121 #undef TARGET_ENCODE_SECTION_INFO
122 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
123 #undef TARGET_IN_SMALL_DATA_P
124 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
125
126 #undef TARGET_RTX_COSTS
127 #define TARGET_RTX_COSTS m32r_rtx_costs
128 #undef TARGET_ADDRESS_COST
129 #define TARGET_ADDRESS_COST hook_int_rtx_0
130
131 #undef TARGET_PROMOTE_PROTOTYPES
132 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
133 #undef TARGET_RETURN_IN_MEMORY
134 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
135 #undef TARGET_SETUP_INCOMING_VARARGS
136 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
137 #undef TARGET_MUST_PASS_IN_STACK
138 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
139 #undef TARGET_PASS_BY_REFERENCE
140 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
141 #undef TARGET_ARG_PARTIAL_BYTES
142 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
143
144 struct gcc_target targetm = TARGET_INITIALIZER;
145 \f
146 /* Implement TARGET_HANDLE_OPTION. */
147
148 static bool
149 m32r_handle_option (size_t code, const char *arg, int value)
150 {
151 switch (code)
152 {
153 case OPT_m32r:
154 target_flags &= ~(MASK_M32R2 | MASK_M32RX);
155 return true;
156
157 case OPT_mmodel_:
158 if (strcmp (arg, "small") == 0)
159 m32r_model = M32R_MODEL_SMALL;
160 else if (strcmp (arg, "medium") == 0)
161 m32r_model = M32R_MODEL_MEDIUM;
162 else if (strcmp (arg, "large") == 0)
163 m32r_model = M32R_MODEL_LARGE;
164 else
165 return false;
166 return true;
167
168 case OPT_msdata_:
169 if (strcmp (arg, "none") == 0)
170 m32r_sdata = M32R_SDATA_NONE;
171 else if (strcmp (arg, "sdata") == 0)
172 m32r_sdata = M32R_SDATA_SDATA;
173 else if (strcmp (arg, "use") == 0)
174 m32r_sdata = M32R_SDATA_USE;
175 else
176 return false;
177 return true;
178
179 case OPT_mno_flush_func:
180 m32r_cache_flush_func = NULL;
181 return true;
182
183 case OPT_mflush_trap_:
184 return value <= 15;
185
186 case OPT_mno_flush_trap:
187 m32r_cache_flush_trap = -1;
188 return true;
189
190 default:
191 return true;
192 }
193 }
194
195 /* Called by OVERRIDE_OPTIONS to initialize various things. */
196
197 void
198 m32r_init (void)
199 {
200 init_reg_tables ();
201
202 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
203 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
204 m32r_punct_chars['#'] = 1;
205 m32r_punct_chars['@'] = 1; /* ??? no longer used */
206
207 /* Provide default value if not specified. */
208 if (!g_switch_set)
209 g_switch_value = SDATA_DEFAULT_SIZE;
210 }
211
212 /* Vectors to keep interesting information about registers where it can easily
213 be got. We use to use the actual mode value as the bit number, but there
214 is (or may be) more than 32 modes now. Instead we use two tables: one
215 indexed by hard register number, and one indexed by mode. */
216
217 /* The purpose of m32r_mode_class is to shrink the range of modes so that
218 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
219 mapped into one m32r_mode_class mode. */
220
221 enum m32r_mode_class
222 {
223 C_MODE,
224 S_MODE, D_MODE, T_MODE, O_MODE,
225 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
226 };
227
228 /* Modes for condition codes. */
229 #define C_MODES (1 << (int) C_MODE)
230
231 /* Modes for single-word and smaller quantities. */
232 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
233
234 /* Modes for double-word and smaller quantities. */
235 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
236
237 /* Modes for quad-word and smaller quantities. */
238 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
239
240 /* Modes for accumulators. */
241 #define A_MODES (1 << (int) A_MODE)
242
243 /* Value is 1 if register/mode pair is acceptable on arc. */
244
245 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
246 {
247 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
248 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
249 S_MODES, C_MODES, A_MODES, A_MODES
250 };
251
252 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
253
254 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
255
256 static void
257 init_reg_tables (void)
258 {
259 int i;
260
261 for (i = 0; i < NUM_MACHINE_MODES; i++)
262 {
263 switch (GET_MODE_CLASS (i))
264 {
265 case MODE_INT:
266 case MODE_PARTIAL_INT:
267 case MODE_COMPLEX_INT:
268 if (GET_MODE_SIZE (i) <= 4)
269 m32r_mode_class[i] = 1 << (int) S_MODE;
270 else if (GET_MODE_SIZE (i) == 8)
271 m32r_mode_class[i] = 1 << (int) D_MODE;
272 else if (GET_MODE_SIZE (i) == 16)
273 m32r_mode_class[i] = 1 << (int) T_MODE;
274 else if (GET_MODE_SIZE (i) == 32)
275 m32r_mode_class[i] = 1 << (int) O_MODE;
276 else
277 m32r_mode_class[i] = 0;
278 break;
279 case MODE_FLOAT:
280 case MODE_COMPLEX_FLOAT:
281 if (GET_MODE_SIZE (i) <= 4)
282 m32r_mode_class[i] = 1 << (int) SF_MODE;
283 else if (GET_MODE_SIZE (i) == 8)
284 m32r_mode_class[i] = 1 << (int) DF_MODE;
285 else if (GET_MODE_SIZE (i) == 16)
286 m32r_mode_class[i] = 1 << (int) TF_MODE;
287 else if (GET_MODE_SIZE (i) == 32)
288 m32r_mode_class[i] = 1 << (int) OF_MODE;
289 else
290 m32r_mode_class[i] = 0;
291 break;
292 case MODE_CC:
293 m32r_mode_class[i] = 1 << (int) C_MODE;
294 break;
295 default:
296 m32r_mode_class[i] = 0;
297 break;
298 }
299 }
300
301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
302 {
303 if (GPR_P (i))
304 m32r_regno_reg_class[i] = GENERAL_REGS;
305 else if (i == ARG_POINTER_REGNUM)
306 m32r_regno_reg_class[i] = GENERAL_REGS;
307 else
308 m32r_regno_reg_class[i] = NO_REGS;
309 }
310 }
311 \f
312 /* M32R specific attribute support.
313
314 interrupt - for interrupt functions
315
316 model - select code model used to access object
317
318 small: addresses use 24 bits, use bl to make calls
319 medium: addresses use 32 bits, use bl to make calls
320 large: addresses use 32 bits, use seth/add3/jl to make calls
321
322 Grep for MODEL in m32r.h for more info. */
323
324 static tree small_ident1;
325 static tree small_ident2;
326 static tree medium_ident1;
327 static tree medium_ident2;
328 static tree large_ident1;
329 static tree large_ident2;
330
331 static void
332 init_idents (void)
333 {
334 if (small_ident1 == 0)
335 {
336 small_ident1 = get_identifier ("small");
337 small_ident2 = get_identifier ("__small__");
338 medium_ident1 = get_identifier ("medium");
339 medium_ident2 = get_identifier ("__medium__");
340 large_ident1 = get_identifier ("large");
341 large_ident2 = get_identifier ("__large__");
342 }
343 }
344
345 const struct attribute_spec m32r_attribute_table[] =
346 {
347 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
348 { "interrupt", 0, 0, true, false, false, NULL },
349 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
350 { NULL, 0, 0, false, false, false, NULL }
351 };
352
353
354 /* Handle an "model" attribute; arguments as in
355 struct attribute_spec.handler. */
356 static tree
357 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
358 tree args, int flags ATTRIBUTE_UNUSED,
359 bool *no_add_attrs)
360 {
361 tree arg;
362
363 init_idents ();
364 arg = TREE_VALUE (args);
365
366 if (arg != small_ident1
367 && arg != small_ident2
368 && arg != medium_ident1
369 && arg != medium_ident2
370 && arg != large_ident1
371 && arg != large_ident2)
372 {
373 warning (OPT_Wattributes, "invalid argument of %qs attribute",
374 IDENTIFIER_POINTER (name));
375 *no_add_attrs = true;
376 }
377
378 return NULL_TREE;
379 }
380 \f
381 /* Encode section information of DECL, which is either a VAR_DECL,
382 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
383
384 For the M32R we want to record:
385
386 - whether the object lives in .sdata/.sbss.
387 - what code model should be used to access the object
388 */
389
390 static void
391 m32r_encode_section_info (tree decl, rtx rtl, int first)
392 {
393 int extra_flags = 0;
394 tree model_attr;
395 enum m32r_model model;
396
397 default_encode_section_info (decl, rtl, first);
398
399 if (!DECL_P (decl))
400 return;
401
402 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
403 if (model_attr)
404 {
405 tree id;
406
407 init_idents ();
408
409 id = TREE_VALUE (TREE_VALUE (model_attr));
410
411 if (id == small_ident1 || id == small_ident2)
412 model = M32R_MODEL_SMALL;
413 else if (id == medium_ident1 || id == medium_ident2)
414 model = M32R_MODEL_MEDIUM;
415 else if (id == large_ident1 || id == large_ident2)
416 model = M32R_MODEL_LARGE;
417 else
418 gcc_unreachable (); /* shouldn't happen */
419 }
420 else
421 {
422 if (TARGET_MODEL_SMALL)
423 model = M32R_MODEL_SMALL;
424 else if (TARGET_MODEL_MEDIUM)
425 model = M32R_MODEL_MEDIUM;
426 else if (TARGET_MODEL_LARGE)
427 model = M32R_MODEL_LARGE;
428 else
429 gcc_unreachable (); /* shouldn't happen */
430 }
431 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
432
433 if (extra_flags)
434 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
435 }
436
437 /* Only mark the object as being small data area addressable if
438 it hasn't been explicitly marked with a code model.
439
440 The user can explicitly put an object in the small data area with the
441 section attribute. If the object is in sdata/sbss and marked with a
442 code model do both [put the object in .sdata and mark it as being
443 addressed with a specific code model - don't mark it as being addressed
444 with an SDA reloc though]. This is ok and might be useful at times. If
445 the object doesn't fit the linker will give an error. */
446
447 static bool
448 m32r_in_small_data_p (tree decl)
449 {
450 tree section;
451
452 if (TREE_CODE (decl) != VAR_DECL)
453 return false;
454
455 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
456 return false;
457
458 section = DECL_SECTION_NAME (decl);
459 if (section)
460 {
461 char *name = (char *) TREE_STRING_POINTER (section);
462 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
463 return true;
464 }
465 else
466 {
467 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
468 {
469 int size = int_size_in_bytes (TREE_TYPE (decl));
470
471 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
472 return true;
473 }
474 }
475
476 return false;
477 }
478
479 /* Do anything needed before RTL is emitted for each function. */
480
481 void
482 m32r_init_expanders (void)
483 {
484 /* ??? At one point there was code here. The function is left in
485 to make it easy to experiment. */
486 }
487 \f
488 int
489 call_operand (rtx op, enum machine_mode mode)
490 {
491 if (GET_CODE (op) != MEM)
492 return 0;
493 op = XEXP (op, 0);
494 return call_address_operand (op, mode);
495 }
496
497 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
498
499 int
500 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
501 {
502 if (! TARGET_SDATA_USE)
503 return 0;
504
505 if (GET_CODE (op) == SYMBOL_REF)
506 return SYMBOL_REF_SMALL_P (op);
507
508 if (GET_CODE (op) == CONST
509 && GET_CODE (XEXP (op, 0)) == PLUS
510 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
511 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
512 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
513 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
514
515 return 0;
516 }
517
518 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
519
520 int
521 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
522 {
523 rtx sym;
524
525 if (flag_pic)
526 return 0;
527
528 if (GET_CODE (op) == LABEL_REF)
529 return TARGET_ADDR24;
530
531 if (GET_CODE (op) == SYMBOL_REF)
532 sym = op;
533 else if (GET_CODE (op) == CONST
534 && GET_CODE (XEXP (op, 0)) == PLUS
535 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
536 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
537 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
538 sym = XEXP (XEXP (op, 0), 0);
539 else
540 return 0;
541
542 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
543 return 1;
544
545 if (TARGET_ADDR24
546 && (CONSTANT_POOL_ADDRESS_P (sym)
547 || LIT_NAME_P (XSTR (sym, 0))))
548 return 1;
549
550 return 0;
551 }
552
553 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
554
555 int
556 addr32_operand (rtx op, enum machine_mode mode)
557 {
558 rtx sym;
559
560 if (GET_CODE (op) == LABEL_REF)
561 return TARGET_ADDR32;
562
563 if (GET_CODE (op) == SYMBOL_REF)
564 sym = op;
565 else if (GET_CODE (op) == CONST
566 && GET_CODE (XEXP (op, 0)) == PLUS
567 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
568 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
569 && ! flag_pic)
570 sym = XEXP (XEXP (op, 0), 0);
571 else
572 return 0;
573
574 return (! addr24_operand (sym, mode)
575 && ! small_data_operand (sym, mode));
576 }
577
578 /* Return 1 if OP is a function that can be called with the `bl' insn. */
579
580 int
581 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
582 {
583 if (flag_pic)
584 return 1;
585
586 if (GET_CODE (op) == SYMBOL_REF)
587 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
588
589 return TARGET_CALL26;
590 }
591
592 /* Return 1 if OP is a DImode const we want to handle inline.
593 This must match the code in the movdi pattern.
594 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
595
596 int
597 easy_di_const (rtx op)
598 {
599 rtx high_rtx, low_rtx;
600 HOST_WIDE_INT high, low;
601
602 split_double (op, &high_rtx, &low_rtx);
603 high = INTVAL (high_rtx);
604 low = INTVAL (low_rtx);
605 /* Pick constants loadable with 2 16 bit `ldi' insns. */
606 if (high >= -128 && high <= 127
607 && low >= -128 && low <= 127)
608 return 1;
609 return 0;
610 }
611
612 /* Return 1 if OP is a DFmode const we want to handle inline.
613 This must match the code in the movdf pattern.
614 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
615
616 int
617 easy_df_const (rtx op)
618 {
619 REAL_VALUE_TYPE r;
620 long l[2];
621
622 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
623 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
624 if (l[0] == 0 && l[1] == 0)
625 return 1;
626 if ((l[0] & 0xffff) == 0 && l[1] == 0)
627 return 1;
628 return 0;
629 }
630
631 /* Return 1 if OP is (mem (reg ...)).
632 This is used in insn length calcs. */
633
634 int
635 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
636 {
637 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
638 }
639
640 /* Return nonzero if TYPE must be passed by indirect reference. */
641
642 static bool
643 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
644 enum machine_mode mode, tree type,
645 bool named ATTRIBUTE_UNUSED)
646 {
647 int size;
648
649 if (type)
650 size = int_size_in_bytes (type);
651 else
652 size = GET_MODE_SIZE (mode);
653
654 return (size < 0 || size > 8);
655 }
656 \f
657 /* Comparisons. */
658
659 /* X and Y are two things to compare using CODE. Emit the compare insn and
660 return the rtx for compare [arg0 of the if_then_else].
661 If need_compare is true then the comparison insn must be generated, rather
662 than being subsumed into the following branch instruction. */
663
664 rtx
665 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
666 {
667 enum rtx_code compare_code;
668 enum rtx_code branch_code;
669 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
670 int must_swap = 0;
671
672 switch (code)
673 {
674 case EQ: compare_code = EQ; branch_code = NE; break;
675 case NE: compare_code = EQ; branch_code = EQ; break;
676 case LT: compare_code = LT; branch_code = NE; break;
677 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
678 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
679 case GE: compare_code = LT; branch_code = EQ; break;
680 case LTU: compare_code = LTU; branch_code = NE; break;
681 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
682 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
683 case GEU: compare_code = LTU; branch_code = EQ; break;
684
685 default:
686 gcc_unreachable ();
687 }
688
689 if (need_compare)
690 {
691 switch (compare_code)
692 {
693 case EQ:
694 if (GET_CODE (y) == CONST_INT
695 && UINT16_P (INTVAL (y)) /* Reg equal to small const. */
696 && y != const0_rtx)
697 {
698 rtx tmp = gen_reg_rtx (SImode);
699
700 emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
701 x = tmp;
702 y = const0_rtx;
703 }
704 #if 0 /* Removed for miss optimizing at simplify_relational_operation(). */
705 else if (GET_CODE (y) == CONST_INT
706 && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
707 && y != const0_rtx)
708 {
709 rtx tmp = gen_reg_rtx (SImode);
710
711 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
712 x = tmp;
713 y = const0_rtx;
714 }
715 #endif
716 else if (CONSTANT_P (y)) /* Reg equal to const. */
717 {
718 rtx tmp = force_reg (GET_MODE (x), y);
719 y = tmp;
720 }
721
722 if (register_operand (y, SImode) /* Reg equal to reg. */
723 || y == const0_rtx) /* Reg equal to zero. */
724 {
725 emit_insn (gen_cmp_eqsi_insn (x, y));
726
727 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
728 }
729 break;
730
731 case LT:
732 if (register_operand (y, SImode)
733 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
734 {
735 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
736
737 switch (code)
738 {
739 case LT:
740 emit_insn (gen_cmp_ltsi_insn (x, y));
741 code = EQ;
742 break;
743 case LE:
744 if (y == const0_rtx)
745 tmp = const1_rtx;
746 else
747 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
748 emit_insn (gen_cmp_ltsi_insn (x, tmp));
749 code = EQ;
750 break;
751 case GT:
752 if (GET_CODE (y) == CONST_INT)
753 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
754 else
755 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
756 emit_insn (gen_cmp_ltsi_insn (x, tmp));
757 code = NE;
758 break;
759 case GE:
760 emit_insn (gen_cmp_ltsi_insn (x, y));
761 code = NE;
762 break;
763 default:
764 gcc_unreachable ();
765 }
766
767 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
768 }
769 break;
770
771 case LTU:
772 if (register_operand (y, SImode)
773 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
774 {
775 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
776
777 switch (code)
778 {
779 case LTU:
780 emit_insn (gen_cmp_ltusi_insn (x, y));
781 code = EQ;
782 break;
783 case LEU:
784 if (y == const0_rtx)
785 tmp = const1_rtx;
786 else
787 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
788 emit_insn (gen_cmp_ltusi_insn (x, tmp));
789 code = EQ;
790 break;
791 case GTU:
792 if (GET_CODE (y) == CONST_INT)
793 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
794 else
795 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
796 emit_insn (gen_cmp_ltusi_insn (x, tmp));
797 code = NE;
798 break;
799 case GEU:
800 emit_insn (gen_cmp_ltusi_insn (x, y));
801 code = NE;
802 break;
803 default:
804 gcc_unreachable ();
805 }
806
807 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
808 }
809 break;
810
811 default:
812 gcc_unreachable ();
813 }
814 }
815 else
816 {
817 /* Reg/reg equal comparison. */
818 if (compare_code == EQ
819 && register_operand (y, SImode))
820 return gen_rtx_fmt_ee (code, CCmode, x, y);
821
822 /* Reg/zero signed comparison. */
823 if ((compare_code == EQ || compare_code == LT)
824 && y == const0_rtx)
825 return gen_rtx_fmt_ee (code, CCmode, x, y);
826
827 /* Reg/smallconst equal comparison. */
828 if (compare_code == EQ
829 && GET_CODE (y) == CONST_INT
830 && UINT16_P (INTVAL (y)))
831 {
832 rtx tmp = gen_reg_rtx (SImode);
833
834 emit_insn (gen_xorsi3 (tmp, x, GEN_INT (INTVAL (y))));
835 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
836 }
837
838 #if 0 /* Removed for miss optimizing at simplify_relational_operation(). */
839 if (compare_code == EQ
840 && GET_CODE (y) == CONST_INT
841 && CMP_INT16_P (INTVAL (y)))
842 {
843 rtx tmp = gen_reg_rtx (SImode);
844
845 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
846 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
847 }
848 #endif
849
850 /* Reg/const equal comparison. */
851 if (compare_code == EQ
852 && CONSTANT_P (y))
853 {
854 rtx tmp = force_reg (GET_MODE (x), y);
855
856 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
857 }
858 }
859
860 if (CONSTANT_P (y))
861 {
862 if (must_swap)
863 y = force_reg (GET_MODE (x), y);
864 else
865 {
866 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
867
868 if (! ok_const)
869 y = force_reg (GET_MODE (x), y);
870 }
871 }
872
873 switch (compare_code)
874 {
875 case EQ :
876 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
877 break;
878 case LT :
879 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
880 break;
881 case LTU :
882 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
883 break;
884
885 default:
886 gcc_unreachable ();
887 }
888
889 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
890 }
891 \f
892 /* Split a 2 word move (DI or DF) into component parts. */
893
894 rtx
895 gen_split_move_double (rtx operands[])
896 {
897 enum machine_mode mode = GET_MODE (operands[0]);
898 rtx dest = operands[0];
899 rtx src = operands[1];
900 rtx val;
901
902 /* We might have (SUBREG (MEM)) here, so just get rid of the
903 subregs to make this code simpler. It is safe to call
904 alter_subreg any time after reload. */
905 if (GET_CODE (dest) == SUBREG)
906 alter_subreg (&dest);
907 if (GET_CODE (src) == SUBREG)
908 alter_subreg (&src);
909
910 start_sequence ();
911 if (GET_CODE (dest) == REG)
912 {
913 int dregno = REGNO (dest);
914
915 /* Reg = reg. */
916 if (GET_CODE (src) == REG)
917 {
918 int sregno = REGNO (src);
919
920 int reverse = (dregno == sregno + 1);
921
922 /* We normally copy the low-numbered register first. However, if
923 the first register operand 0 is the same as the second register of
924 operand 1, we must copy in the opposite order. */
925 emit_insn (gen_rtx_SET (VOIDmode,
926 operand_subword (dest, reverse, TRUE, mode),
927 operand_subword (src, reverse, TRUE, mode)));
928
929 emit_insn (gen_rtx_SET (VOIDmode,
930 operand_subword (dest, !reverse, TRUE, mode),
931 operand_subword (src, !reverse, TRUE, mode)));
932 }
933
934 /* Reg = constant. */
935 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
936 {
937 rtx words[2];
938 split_double (src, &words[0], &words[1]);
939 emit_insn (gen_rtx_SET (VOIDmode,
940 operand_subword (dest, 0, TRUE, mode),
941 words[0]));
942
943 emit_insn (gen_rtx_SET (VOIDmode,
944 operand_subword (dest, 1, TRUE, mode),
945 words[1]));
946 }
947
948 /* Reg = mem. */
949 else if (GET_CODE (src) == MEM)
950 {
951 /* If the high-address word is used in the address, we must load it
952 last. Otherwise, load it first. */
953 int reverse
954 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
955
956 /* We used to optimize loads from single registers as
957
958 ld r1,r3+; ld r2,r3
959
960 if r3 were not used subsequently. However, the REG_NOTES aren't
961 propagated correctly by the reload phase, and it can cause bad
962 code to be generated. We could still try:
963
964 ld r1,r3+; ld r2,r3; addi r3,-4
965
966 which saves 2 bytes and doesn't force longword alignment. */
967 emit_insn (gen_rtx_SET (VOIDmode,
968 operand_subword (dest, reverse, TRUE, mode),
969 adjust_address (src, SImode,
970 reverse * UNITS_PER_WORD)));
971
972 emit_insn (gen_rtx_SET (VOIDmode,
973 operand_subword (dest, !reverse, TRUE, mode),
974 adjust_address (src, SImode,
975 !reverse * UNITS_PER_WORD)));
976 }
977 else
978 gcc_unreachable ();
979 }
980
981 /* Mem = reg. */
982 /* We used to optimize loads from single registers as
983
984 st r1,r3; st r2,+r3
985
986 if r3 were not used subsequently. However, the REG_NOTES aren't
987 propagated correctly by the reload phase, and it can cause bad
988 code to be generated. We could still try:
989
990 st r1,r3; st r2,+r3; addi r3,-4
991
992 which saves 2 bytes and doesn't force longword alignment. */
993 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
994 {
995 emit_insn (gen_rtx_SET (VOIDmode,
996 adjust_address (dest, SImode, 0),
997 operand_subword (src, 0, TRUE, mode)));
998
999 emit_insn (gen_rtx_SET (VOIDmode,
1000 adjust_address (dest, SImode, UNITS_PER_WORD),
1001 operand_subword (src, 1, TRUE, mode)));
1002 }
1003
1004 else
1005 gcc_unreachable ();
1006
1007 val = get_insns ();
1008 end_sequence ();
1009 return val;
1010 }
1011
1012 \f
1013 static int
1014 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1015 tree type, bool named ATTRIBUTE_UNUSED)
1016 {
1017 int words;
1018 unsigned int size =
1019 (((mode == BLKmode && type)
1020 ? (unsigned int) int_size_in_bytes (type)
1021 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1022 / UNITS_PER_WORD;
1023
1024 if (*cum >= M32R_MAX_PARM_REGS)
1025 words = 0;
1026 else if (*cum + size > M32R_MAX_PARM_REGS)
1027 words = (*cum + size) - M32R_MAX_PARM_REGS;
1028 else
1029 words = 0;
1030
1031 return words * UNITS_PER_WORD;
1032 }
1033
1034 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1035
1036 static bool
1037 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1038 {
1039 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1040 }
1041
1042 /* Do any needed setup for a variadic function. For the M32R, we must
1043 create a register parameter block, and then copy any anonymous arguments
1044 in registers to memory.
1045
1046 CUM has not been updated for the last named argument which has type TYPE
1047 and mode MODE, and we rely on this fact. */
1048
1049 static void
1050 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1051 tree type, int *pretend_size, int no_rtl)
1052 {
1053 int first_anon_arg;
1054
1055 if (no_rtl)
1056 return;
1057
1058 /* All BLKmode values are passed by reference. */
1059 gcc_assert (mode != BLKmode);
1060
1061 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1062 + ROUND_ADVANCE_ARG (mode, type));
1063
1064 if (first_anon_arg < M32R_MAX_PARM_REGS)
1065 {
1066 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1067 int first_reg_offset = first_anon_arg;
1068 /* Size in words to "pretend" allocate. */
1069 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1070 rtx regblock;
1071
1072 regblock = gen_rtx_MEM (BLKmode,
1073 plus_constant (arg_pointer_rtx,
1074 FIRST_PARM_OFFSET (0)));
1075 set_mem_alias_set (regblock, get_varargs_alias_set ());
1076 move_block_from_reg (first_reg_offset, regblock, size);
1077
1078 *pretend_size = (size * UNITS_PER_WORD);
1079 }
1080 }
1081
1082 \f
1083 /* Return true if INSN is real instruction bearing insn. */
1084
1085 static int
1086 m32r_is_insn (rtx insn)
1087 {
1088 return (INSN_P (insn)
1089 && GET_CODE (PATTERN (insn)) != USE
1090 && GET_CODE (PATTERN (insn)) != CLOBBER
1091 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1092 }
1093
1094 /* Increase the priority of long instructions so that the
1095 short instructions are scheduled ahead of the long ones. */
1096
1097 static int
1098 m32r_adjust_priority (rtx insn, int priority)
1099 {
1100 if (m32r_is_insn (insn)
1101 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1102 priority <<= 3;
1103
1104 return priority;
1105 }
1106
1107 \f
1108 /* Indicate how many instructions can be issued at the same time.
1109 This is sort of a lie. The m32r can issue only 1 long insn at
1110 once, but it can issue 2 short insns. The default therefore is
1111 set at 2, but this can be overridden by the command line option
1112 -missue-rate=1. */
1113
1114 static int
1115 m32r_issue_rate (void)
1116 {
1117 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1118 }
1119 \f
1120 /* Cost functions. */
1121
1122 static bool
1123 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1124 {
1125 switch (code)
1126 {
1127 /* Small integers are as cheap as registers. 4 byte values can be
1128 fetched as immediate constants - let's give that the cost of an
1129 extra insn. */
1130 case CONST_INT:
1131 if (INT16_P (INTVAL (x)))
1132 {
1133 *total = 0;
1134 return true;
1135 }
1136 /* FALLTHRU */
1137
1138 case CONST:
1139 case LABEL_REF:
1140 case SYMBOL_REF:
1141 *total = COSTS_N_INSNS (1);
1142 return true;
1143
1144 case CONST_DOUBLE:
1145 {
1146 rtx high, low;
1147
1148 split_double (x, &high, &low);
1149 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1150 + !INT16_P (INTVAL (low)));
1151 return true;
1152 }
1153
1154 case MULT:
1155 *total = COSTS_N_INSNS (3);
1156 return true;
1157
1158 case DIV:
1159 case UDIV:
1160 case MOD:
1161 case UMOD:
1162 *total = COSTS_N_INSNS (10);
1163 return true;
1164
1165 default:
1166 return false;
1167 }
1168 }
1169 \f
1170 /* Type of function DECL.
1171
1172 The result is cached. To reset the cache at the end of a function,
1173 call with DECL = NULL_TREE. */
1174
1175 enum m32r_function_type
1176 m32r_compute_function_type (tree decl)
1177 {
1178 /* Cached value. */
1179 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1180 /* Last function we were called for. */
1181 static tree last_fn = NULL_TREE;
1182
1183 /* Resetting the cached value? */
1184 if (decl == NULL_TREE)
1185 {
1186 fn_type = M32R_FUNCTION_UNKNOWN;
1187 last_fn = NULL_TREE;
1188 return fn_type;
1189 }
1190
1191 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1192 return fn_type;
1193
1194 /* Compute function type. */
1195 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1196 ? M32R_FUNCTION_INTERRUPT
1197 : M32R_FUNCTION_NORMAL);
1198
1199 last_fn = decl;
1200 return fn_type;
1201 }
1202 \f/* Function prologue/epilogue handlers. */
1203
1204 /* M32R stack frames look like:
1205
1206 Before call After call
1207 +-----------------------+ +-----------------------+
1208 | | | |
1209 high | local variables, | | local variables, |
1210 mem | reg save area, etc. | | reg save area, etc. |
1211 | | | |
1212 +-----------------------+ +-----------------------+
1213 | | | |
1214 | arguments on stack. | | arguments on stack. |
1215 | | | |
1216 SP+0->+-----------------------+ +-----------------------+
1217 | reg parm save area, |
1218 | only created for |
1219 | variable argument |
1220 | functions |
1221 +-----------------------+
1222 | previous frame ptr |
1223 +-----------------------+
1224 | |
1225 | register save area |
1226 | |
1227 +-----------------------+
1228 | return address |
1229 +-----------------------+
1230 | |
1231 | local variables |
1232 | |
1233 +-----------------------+
1234 | |
1235 | alloca allocations |
1236 | |
1237 +-----------------------+
1238 | |
1239 low | arguments on stack |
1240 memory | |
1241 SP+0->+-----------------------+
1242
1243 Notes:
1244 1) The "reg parm save area" does not exist for non variable argument fns.
1245 2) The "reg parm save area" can be eliminated completely if we saved regs
1246 containing anonymous args separately but that complicates things too
1247 much (so it's not done).
1248 3) The return address is saved after the register save area so as to have as
1249 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1250
1251 /* Structure to be filled in by m32r_compute_frame_size with register
1252 save masks, and offsets for the current function. */
1253 struct m32r_frame_info
1254 {
1255 unsigned int total_size; /* # bytes that the entire frame takes up. */
1256 unsigned int extra_size; /* # bytes of extra stuff. */
1257 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1258 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1259 unsigned int reg_size; /* # bytes needed to store regs. */
1260 unsigned int var_size; /* # bytes that variables take up. */
1261 unsigned int gmask; /* Mask of saved gp registers. */
1262 unsigned int save_fp; /* Nonzero if fp must be saved. */
1263 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1264 int initialized; /* Nonzero if frame size already calculated. */
1265 };
1266
1267 /* Current frame information calculated by m32r_compute_frame_size. */
1268 static struct m32r_frame_info current_frame_info;
1269
1270 /* Zero structure to initialize current_frame_info. */
1271 static struct m32r_frame_info zero_frame_info;
1272
1273 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1274 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1275
1276 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1277 The return address and frame pointer are treated separately.
1278 Don't consider them here. */
1279 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1280 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1281 && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1282
1283 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1284 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1285
1286 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1287 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1288
1289 /* Return the bytes needed to compute the frame pointer from the current
1290 stack pointer.
1291
1292 SIZE is the size needed for local variables. */
1293
1294 unsigned int
1295 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1296 {
1297 int regno;
1298 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1299 unsigned int reg_size, frame_size;
1300 unsigned int gmask;
1301 enum m32r_function_type fn_type;
1302 int interrupt_p;
1303 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1304 | current_function_profile);
1305
1306 var_size = M32R_STACK_ALIGN (size);
1307 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1308 pretend_size = current_function_pretend_args_size;
1309 extra_size = FIRST_PARM_OFFSET (0);
1310 total_size = extra_size + pretend_size + args_size + var_size;
1311 reg_size = 0;
1312 gmask = 0;
1313
1314 /* See if this is an interrupt handler. Call used registers must be saved
1315 for them too. */
1316 fn_type = m32r_compute_function_type (current_function_decl);
1317 interrupt_p = M32R_INTERRUPT_P (fn_type);
1318
1319 /* Calculate space needed for registers. */
1320 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1321 {
1322 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1323 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1324 {
1325 reg_size += UNITS_PER_WORD;
1326 gmask |= 1 << regno;
1327 }
1328 }
1329
1330 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1331 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1332
1333 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1334 * UNITS_PER_WORD);
1335 total_size += reg_size;
1336
1337 /* ??? Not sure this is necessary, and I don't think the epilogue
1338 handler will do the right thing if this changes total_size. */
1339 total_size = M32R_STACK_ALIGN (total_size);
1340
1341 frame_size = total_size - (pretend_size + reg_size);
1342
1343 /* Save computed information. */
1344 current_frame_info.total_size = total_size;
1345 current_frame_info.extra_size = extra_size;
1346 current_frame_info.pretend_size = pretend_size;
1347 current_frame_info.var_size = var_size;
1348 current_frame_info.args_size = args_size;
1349 current_frame_info.reg_size = reg_size;
1350 current_frame_info.gmask = gmask;
1351 current_frame_info.initialized = reload_completed;
1352
1353 /* Ok, we're done. */
1354 return total_size;
1355 }
1356 \f
1357 /* The table we use to reference PIC data. */
1358 static rtx global_offset_table;
1359
1360 static void
1361 m32r_reload_lr (rtx sp, int size)
1362 {
1363 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1364
1365 if (size == 0)
1366 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1367 else if (size < 32768)
1368 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1369 gen_rtx_PLUS (Pmode, sp,
1370 GEN_INT (size)))));
1371 else
1372 {
1373 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1374
1375 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1376 emit_insn (gen_addsi3 (tmp, tmp, sp));
1377 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1378 }
1379
1380 emit_insn (gen_rtx_USE (VOIDmode, lr));
1381 }
1382
1383 void
1384 m32r_load_pic_register (void)
1385 {
1386 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1387 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1388 GEN_INT (TARGET_MODEL_SMALL)));
1389
1390 /* Need to emit this whether or not we obey regdecls,
1391 since setjmp/longjmp can cause life info to screw up. */
1392 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1393 }
1394
1395 /* Expand the m32r prologue as a series of insns. */
1396
1397 void
1398 m32r_expand_prologue (void)
1399 {
1400 int regno;
1401 int frame_size;
1402 unsigned int gmask;
1403 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table
1404 | current_function_profile);
1405
1406 if (! current_frame_info.initialized)
1407 m32r_compute_frame_size (get_frame_size ());
1408
1409 gmask = current_frame_info.gmask;
1410
1411 /* These cases shouldn't happen. Catch them now. */
1412 gcc_assert (current_frame_info.total_size || !gmask);
1413
1414 /* Allocate space for register arguments if this is a variadic function. */
1415 if (current_frame_info.pretend_size != 0)
1416 {
1417 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1418 the wrong result on a 64-bit host. */
1419 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1420 emit_insn (gen_addsi3 (stack_pointer_rtx,
1421 stack_pointer_rtx,
1422 GEN_INT (-pretend_size)));
1423 }
1424
1425 /* Save any registers we need to and set up fp. */
1426 if (current_frame_info.save_fp)
1427 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1428
1429 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1430
1431 /* Save any needed call-saved regs (and call-used if this is an
1432 interrupt handler). */
1433 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1434 {
1435 if ((gmask & (1 << regno)) != 0)
1436 emit_insn (gen_movsi_push (stack_pointer_rtx,
1437 gen_rtx_REG (Pmode, regno)));
1438 }
1439
1440 if (current_frame_info.save_lr)
1441 emit_insn (gen_movsi_push (stack_pointer_rtx,
1442 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1443
1444 /* Allocate the stack frame. */
1445 frame_size = (current_frame_info.total_size
1446 - (current_frame_info.pretend_size
1447 + current_frame_info.reg_size));
1448
1449 if (frame_size == 0)
1450 ; /* Nothing to do. */
1451 else if (frame_size <= 32768)
1452 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1453 GEN_INT (-frame_size)));
1454 else
1455 {
1456 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1457
1458 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1459 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1460 }
1461
1462 if (frame_pointer_needed)
1463 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1464
1465 if (current_function_profile)
1466 /* Push lr for mcount (form_pc, x). */
1467 emit_insn (gen_movsi_push (stack_pointer_rtx,
1468 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1469
1470 if (pic_reg_used)
1471 {
1472 m32r_load_pic_register ();
1473 m32r_reload_lr (stack_pointer_rtx,
1474 (current_function_profile ? 0 : frame_size));
1475 }
1476
1477 if (current_function_profile && !pic_reg_used)
1478 emit_insn (gen_blockage ());
1479 }
1480
1481 \f
1482 /* Set up the stack and frame pointer (if desired) for the function.
1483 Note, if this is changed, you need to mirror the changes in
1484 m32r_compute_frame_size which calculates the prolog size. */
1485
1486 static void
1487 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1488 {
1489 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1490
1491 /* If this is an interrupt handler, mark it as such. */
1492 if (M32R_INTERRUPT_P (fn_type))
1493 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1494
1495 if (! current_frame_info.initialized)
1496 m32r_compute_frame_size (size);
1497
1498 /* This is only for the human reader. */
1499 fprintf (file,
1500 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1501 ASM_COMMENT_START,
1502 current_frame_info.var_size,
1503 current_frame_info.reg_size / 4,
1504 current_frame_info.args_size,
1505 current_frame_info.extra_size);
1506 }
1507 \f
1508 /* Do any necessary cleanup after a function to restore stack, frame,
1509 and regs. */
1510
1511 static void
1512 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1513 {
1514 int regno;
1515 int noepilogue = FALSE;
1516 int total_size;
1517 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1518
1519 /* This is only for the human reader. */
1520 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1521
1522 gcc_assert (current_frame_info.initialized);
1523 total_size = current_frame_info.total_size;
1524
1525 if (total_size == 0)
1526 {
1527 rtx insn = get_last_insn ();
1528
1529 /* If the last insn was a BARRIER, we don't have to write any code
1530 because a jump (aka return) was put there. */
1531 if (GET_CODE (insn) == NOTE)
1532 insn = prev_nonnote_insn (insn);
1533 if (insn && GET_CODE (insn) == BARRIER)
1534 noepilogue = TRUE;
1535 }
1536
1537 if (!noepilogue)
1538 {
1539 unsigned int var_size = current_frame_info.var_size;
1540 unsigned int args_size = current_frame_info.args_size;
1541 unsigned int gmask = current_frame_info.gmask;
1542 int can_trust_sp_p = !current_function_calls_alloca;
1543 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1544 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1545
1546 /* The first thing to do is point the sp at the bottom of the register
1547 save area. */
1548 if (can_trust_sp_p)
1549 {
1550 unsigned int reg_offset = var_size + args_size;
1551 if (reg_offset == 0)
1552 ; /* Nothing to do. */
1553 else if (reg_offset < 128)
1554 fprintf (file, "\taddi %s,%s%d\n",
1555 sp_str, IMMEDIATE_PREFIX, reg_offset);
1556 else if (reg_offset < 32768)
1557 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1558 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1559 else if (reg_offset < (1 << 24))
1560 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1561 reg_names[PROLOGUE_TMP_REGNUM],
1562 IMMEDIATE_PREFIX, reg_offset,
1563 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1564 else
1565 fprintf (file, "\tseth %s,%s%d\n\tor3 %s,%s,%s%d\n\tadd %s,%s\n",
1566 reg_names[PROLOGUE_TMP_REGNUM],
1567 IMMEDIATE_PREFIX, reg_offset >> 16,
1568 reg_names[PROLOGUE_TMP_REGNUM],
1569 reg_names[PROLOGUE_TMP_REGNUM],
1570 IMMEDIATE_PREFIX, reg_offset & 0xffff,
1571 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1572 }
1573 else if (frame_pointer_needed)
1574 {
1575 unsigned int reg_offset = var_size + args_size;
1576
1577 if (reg_offset == 0)
1578 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1579 else if (reg_offset < 32768)
1580 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1581 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1582 else if (reg_offset < (1 << 24))
1583 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1584 reg_names[PROLOGUE_TMP_REGNUM],
1585 IMMEDIATE_PREFIX, reg_offset,
1586 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1587 else
1588 fprintf (file, "\tseth %s,%s%d\n\tor3 %s,%s,%s%d\n\tadd %s,%s\n",
1589 reg_names[PROLOGUE_TMP_REGNUM],
1590 IMMEDIATE_PREFIX, reg_offset >> 16,
1591 reg_names[PROLOGUE_TMP_REGNUM],
1592 reg_names[PROLOGUE_TMP_REGNUM],
1593 IMMEDIATE_PREFIX, reg_offset & 0xffff,
1594 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1595 }
1596 else
1597 gcc_unreachable ();
1598
1599 if (current_frame_info.save_lr)
1600 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1601
1602 /* Restore any saved registers, in reverse order of course. */
1603 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1604 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1605 {
1606 if ((gmask & (1L << regno)) != 0)
1607 fprintf (file, "\tpop %s\n", reg_names[regno]);
1608 }
1609
1610 if (current_frame_info.save_fp)
1611 fprintf (file, "\tpop %s\n", fp_str);
1612
1613 /* Remove varargs area if present. */
1614 if (current_frame_info.pretend_size != 0)
1615 fprintf (file, "\taddi %s,%s%d\n",
1616 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1617
1618 /* Emit the return instruction. */
1619 if (M32R_INTERRUPT_P (fn_type))
1620 fprintf (file, "\trte\n");
1621 else
1622 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1623 }
1624
1625 /* Reset state info for each function. */
1626 current_frame_info = zero_frame_info;
1627 m32r_compute_function_type (NULL_TREE);
1628 }
1629 \f
1630 /* Return nonzero if this function is known to have a null or 1 instruction
1631 epilogue. */
1632
1633 int
1634 direct_return (void)
1635 {
1636 if (!reload_completed)
1637 return FALSE;
1638
1639 if (! current_frame_info.initialized)
1640 m32r_compute_frame_size (get_frame_size ());
1641
1642 return current_frame_info.total_size == 0;
1643 }
1644
1645 \f
1646 /* PIC. */
1647
1648 int
1649 m32r_legitimate_pic_operand_p (rtx x)
1650 {
1651 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1652 return 0;
1653
1654 if (GET_CODE (x) == CONST
1655 && GET_CODE (XEXP (x, 0)) == PLUS
1656 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1657 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1658 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1659 return 0;
1660
1661 return 1;
1662 }
1663
1664 rtx
1665 m32r_legitimize_pic_address (rtx orig, rtx reg)
1666 {
1667 #ifdef DEBUG_PIC
1668 printf("m32r_legitimize_pic_address()\n");
1669 #endif
1670
1671 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1672 {
1673 rtx pic_ref, address;
1674 rtx insn;
1675 int subregs = 0;
1676
1677 if (reg == 0)
1678 {
1679 gcc_assert (!reload_in_progress && !reload_completed);
1680 reg = gen_reg_rtx (Pmode);
1681
1682 subregs = 1;
1683 }
1684
1685 if (subregs)
1686 address = gen_reg_rtx (Pmode);
1687 else
1688 address = reg;
1689
1690 current_function_uses_pic_offset_table = 1;
1691
1692 if (GET_CODE (orig) == LABEL_REF
1693 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1694 {
1695 emit_insn (gen_gotoff_load_addr (reg, orig));
1696 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1697 return reg;
1698 }
1699
1700 emit_insn (gen_pic_load_addr (address, orig));
1701
1702 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1703 pic_ref = gen_const_mem (Pmode, address);
1704 insn = emit_move_insn (reg, pic_ref);
1705 #if 0
1706 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1707 by loop. */
1708 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1709 REG_NOTES (insn));
1710 #endif
1711 return reg;
1712 }
1713 else if (GET_CODE (orig) == CONST)
1714 {
1715 rtx base, offset;
1716
1717 if (GET_CODE (XEXP (orig, 0)) == PLUS
1718 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1719 return orig;
1720
1721 if (reg == 0)
1722 {
1723 gcc_assert (!reload_in_progress && !reload_completed);
1724 reg = gen_reg_rtx (Pmode);
1725 }
1726
1727 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1728 {
1729 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1730 if (base == reg)
1731 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1732 else
1733 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1734 }
1735 else
1736 return orig;
1737
1738 if (GET_CODE (offset) == CONST_INT)
1739 {
1740 if (INT16_P (INTVAL (offset)))
1741 return plus_constant (base, INTVAL (offset));
1742 else
1743 {
1744 gcc_assert (! reload_in_progress && ! reload_completed);
1745 offset = force_reg (Pmode, offset);
1746 }
1747 }
1748
1749 return gen_rtx_PLUS (Pmode, base, offset);
1750 }
1751
1752 return orig;
1753 }
1754 \f
1755 /* Nested function support. */
1756
1757 /* Emit RTL insns to initialize the variable parts of a trampoline.
1758 FNADDR is an RTX for the address of the function's pure code.
1759 CXT is an RTX for the static chain value for the function. */
1760
1761 void
1762 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1763 rtx fnaddr ATTRIBUTE_UNUSED,
1764 rtx cxt ATTRIBUTE_UNUSED)
1765 {
1766 }
1767 \f
1768 static void
1769 m32r_file_start (void)
1770 {
1771 default_file_start ();
1772
1773 if (flag_verbose_asm)
1774 fprintf (asm_out_file,
1775 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1776 ASM_COMMENT_START, g_switch_value);
1777
1778 if (TARGET_LITTLE_ENDIAN)
1779 fprintf (asm_out_file, "\t.little\n");
1780 }
1781 \f
1782 /* Print operand X (an rtx) in assembler syntax to file FILE.
1783 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1784 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1785
1786 void
1787 m32r_print_operand (FILE * file, rtx x, int code)
1788 {
1789 rtx addr;
1790
1791 switch (code)
1792 {
1793 /* The 's' and 'p' codes are used by output_block_move() to
1794 indicate post-increment 's'tores and 'p're-increment loads. */
1795 case 's':
1796 if (GET_CODE (x) == REG)
1797 fprintf (file, "@+%s", reg_names [REGNO (x)]);
1798 else
1799 output_operand_lossage ("invalid operand to %%s code");
1800 return;
1801
1802 case 'p':
1803 if (GET_CODE (x) == REG)
1804 fprintf (file, "@%s+", reg_names [REGNO (x)]);
1805 else
1806 output_operand_lossage ("invalid operand to %%p code");
1807 return;
1808
1809 case 'R' :
1810 /* Write second word of DImode or DFmode reference,
1811 register or memory. */
1812 if (GET_CODE (x) == REG)
1813 fputs (reg_names[REGNO (x)+1], file);
1814 else if (GET_CODE (x) == MEM)
1815 {
1816 fprintf (file, "@(");
1817 /* Handle possible auto-increment. Since it is pre-increment and
1818 we have already done it, we can just use an offset of four. */
1819 /* ??? This is taken from rs6000.c I think. I don't think it is
1820 currently necessary, but keep it around. */
1821 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1822 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1823 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1824 else
1825 output_address (plus_constant (XEXP (x, 0), 4));
1826 fputc (')', file);
1827 }
1828 else
1829 output_operand_lossage ("invalid operand to %%R code");
1830 return;
1831
1832 case 'H' : /* High word. */
1833 case 'L' : /* Low word. */
1834 if (GET_CODE (x) == REG)
1835 {
1836 /* L = least significant word, H = most significant word. */
1837 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1838 fputs (reg_names[REGNO (x)], file);
1839 else
1840 fputs (reg_names[REGNO (x)+1], file);
1841 }
1842 else if (GET_CODE (x) == CONST_INT
1843 || GET_CODE (x) == CONST_DOUBLE)
1844 {
1845 rtx first, second;
1846
1847 split_double (x, &first, &second);
1848 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1849 code == 'L' ? INTVAL (first) : INTVAL (second));
1850 }
1851 else
1852 output_operand_lossage ("invalid operand to %%H/%%L code");
1853 return;
1854
1855 case 'A' :
1856 {
1857 char str[30];
1858
1859 if (GET_CODE (x) != CONST_DOUBLE
1860 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1861 fatal_insn ("bad insn for 'A'", x);
1862
1863 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1864 fprintf (file, "%s", str);
1865 return;
1866 }
1867
1868 case 'B' : /* Bottom half. */
1869 case 'T' : /* Top half. */
1870 /* Output the argument to a `seth' insn (sets the Top half-word).
1871 For constants output arguments to a seth/or3 pair to set Top and
1872 Bottom halves. For symbols output arguments to a seth/add3 pair to
1873 set Top and Bottom halves. The difference exists because for
1874 constants seth/or3 is more readable but for symbols we need to use
1875 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1876 switch (GET_CODE (x))
1877 {
1878 case CONST_INT :
1879 case CONST_DOUBLE :
1880 {
1881 rtx first, second;
1882
1883 split_double (x, &first, &second);
1884 x = WORDS_BIG_ENDIAN ? second : first;
1885 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1886 (code == 'B'
1887 ? INTVAL (x) & 0xffff
1888 : (INTVAL (x) >> 16) & 0xffff));
1889 }
1890 return;
1891 case CONST :
1892 case SYMBOL_REF :
1893 if (code == 'B'
1894 && small_data_operand (x, VOIDmode))
1895 {
1896 fputs ("sda(", file);
1897 output_addr_const (file, x);
1898 fputc (')', file);
1899 return;
1900 }
1901 /* fall through */
1902 case LABEL_REF :
1903 fputs (code == 'T' ? "shigh(" : "low(", file);
1904 output_addr_const (file, x);
1905 fputc (')', file);
1906 return;
1907 default :
1908 output_operand_lossage ("invalid operand to %%T/%%B code");
1909 return;
1910 }
1911 break;
1912
1913 case 'U' :
1914 /* ??? wip */
1915 /* Output a load/store with update indicator if appropriate. */
1916 if (GET_CODE (x) == MEM)
1917 {
1918 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1919 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1920 fputs (".a", file);
1921 }
1922 else
1923 output_operand_lossage ("invalid operand to %%U code");
1924 return;
1925
1926 case 'N' :
1927 /* Print a constant value negated. */
1928 if (GET_CODE (x) == CONST_INT)
1929 output_addr_const (file, GEN_INT (- INTVAL (x)));
1930 else
1931 output_operand_lossage ("invalid operand to %%N code");
1932 return;
1933
1934 case 'X' :
1935 /* Print a const_int in hex. Used in comments. */
1936 if (GET_CODE (x) == CONST_INT)
1937 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
1938 return;
1939
1940 case '#' :
1941 fputs (IMMEDIATE_PREFIX, file);
1942 return;
1943
1944 case 0 :
1945 /* Do nothing special. */
1946 break;
1947
1948 default :
1949 /* Unknown flag. */
1950 output_operand_lossage ("invalid operand output code");
1951 }
1952
1953 switch (GET_CODE (x))
1954 {
1955 case REG :
1956 fputs (reg_names[REGNO (x)], file);
1957 break;
1958
1959 case MEM :
1960 addr = XEXP (x, 0);
1961 if (GET_CODE (addr) == PRE_INC)
1962 {
1963 if (GET_CODE (XEXP (addr, 0)) != REG)
1964 fatal_insn ("pre-increment address is not a register", x);
1965
1966 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
1967 }
1968 else if (GET_CODE (addr) == PRE_DEC)
1969 {
1970 if (GET_CODE (XEXP (addr, 0)) != REG)
1971 fatal_insn ("pre-decrement address is not a register", x);
1972
1973 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
1974 }
1975 else if (GET_CODE (addr) == POST_INC)
1976 {
1977 if (GET_CODE (XEXP (addr, 0)) != REG)
1978 fatal_insn ("post-increment address is not a register", x);
1979
1980 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
1981 }
1982 else
1983 {
1984 fputs ("@(", file);
1985 output_address (XEXP (x, 0));
1986 fputc (')', file);
1987 }
1988 break;
1989
1990 case CONST_DOUBLE :
1991 /* We handle SFmode constants here as output_addr_const doesn't. */
1992 if (GET_MODE (x) == SFmode)
1993 {
1994 REAL_VALUE_TYPE d;
1995 long l;
1996
1997 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1998 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1999 fprintf (file, "0x%08lx", l);
2000 break;
2001 }
2002
2003 /* Fall through. Let output_addr_const deal with it. */
2004
2005 default :
2006 output_addr_const (file, x);
2007 break;
2008 }
2009 }
2010
2011 /* Print a memory address as an operand to reference that memory location. */
2012
2013 void
2014 m32r_print_operand_address (FILE * file, rtx addr)
2015 {
2016 rtx base;
2017 rtx index = 0;
2018 int offset = 0;
2019
2020 switch (GET_CODE (addr))
2021 {
2022 case REG :
2023 fputs (reg_names[REGNO (addr)], file);
2024 break;
2025
2026 case PLUS :
2027 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2028 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2029 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2030 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2031 else
2032 base = XEXP (addr, 0), index = XEXP (addr, 1);
2033 if (GET_CODE (base) == REG)
2034 {
2035 /* Print the offset first (if present) to conform to the manual. */
2036 if (index == 0)
2037 {
2038 if (offset != 0)
2039 fprintf (file, "%d,", offset);
2040 fputs (reg_names[REGNO (base)], file);
2041 }
2042 /* The chip doesn't support this, but left in for generality. */
2043 else if (GET_CODE (index) == REG)
2044 fprintf (file, "%s,%s",
2045 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2046 /* Not sure this can happen, but leave in for now. */
2047 else if (GET_CODE (index) == SYMBOL_REF)
2048 {
2049 output_addr_const (file, index);
2050 fputc (',', file);
2051 fputs (reg_names[REGNO (base)], file);
2052 }
2053 else
2054 fatal_insn ("bad address", addr);
2055 }
2056 else if (GET_CODE (base) == LO_SUM)
2057 {
2058 gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG);
2059 if (small_data_operand (XEXP (base, 1), VOIDmode))
2060 fputs ("sda(", file);
2061 else
2062 fputs ("low(", file);
2063 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2064 fputs ("),", file);
2065 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2066 }
2067 else
2068 fatal_insn ("bad address", addr);
2069 break;
2070
2071 case LO_SUM :
2072 if (GET_CODE (XEXP (addr, 0)) != REG)
2073 fatal_insn ("lo_sum not of register", addr);
2074 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2075 fputs ("sda(", file);
2076 else
2077 fputs ("low(", file);
2078 output_addr_const (file, XEXP (addr, 1));
2079 fputs ("),", file);
2080 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2081 break;
2082
2083 case PRE_INC : /* Assume SImode. */
2084 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2085 break;
2086
2087 case PRE_DEC : /* Assume SImode. */
2088 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2089 break;
2090
2091 case POST_INC : /* Assume SImode. */
2092 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2093 break;
2094
2095 default :
2096 output_addr_const (file, addr);
2097 break;
2098 }
2099 }
2100
2101 /* Return true if the operands are the constants 0 and 1. */
2102
2103 int
2104 zero_and_one (rtx operand1, rtx operand2)
2105 {
2106 return
2107 GET_CODE (operand1) == CONST_INT
2108 && GET_CODE (operand2) == CONST_INT
2109 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2110 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2111 }
2112
2113 /* Generate the correct assembler code to handle the conditional loading of a
2114 value into a register. It is known that the operands satisfy the
2115 conditional_move_operand() function above. The destination is operand[0].
2116 The condition is operand [1]. The 'true' value is operand [2] and the
2117 'false' value is operand [3]. */
2118
2119 char *
2120 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2121 {
2122 static char buffer [100];
2123 const char * dest = reg_names [REGNO (operands [0])];
2124
2125 buffer [0] = 0;
2126
2127 /* Destination must be a register. */
2128 gcc_assert (GET_CODE (operands [0]) == REG);
2129 gcc_assert (conditional_move_operand (operands [2], SImode));
2130 gcc_assert (conditional_move_operand (operands [3], SImode));
2131
2132 /* Check to see if the test is reversed. */
2133 if (GET_CODE (operands [1]) == NE)
2134 {
2135 rtx tmp = operands [2];
2136 operands [2] = operands [3];
2137 operands [3] = tmp;
2138 }
2139
2140 sprintf (buffer, "mvfc %s, cbr", dest);
2141
2142 /* If the true value was '0' then we need to invert the results of the move. */
2143 if (INTVAL (operands [2]) == 0)
2144 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2145 dest, dest);
2146
2147 return buffer;
2148 }
2149
2150 /* Returns true if the registers contained in the two
2151 rtl expressions are different. */
2152
2153 int
2154 m32r_not_same_reg (rtx a, rtx b)
2155 {
2156 int reg_a = -1;
2157 int reg_b = -2;
2158
2159 while (GET_CODE (a) == SUBREG)
2160 a = SUBREG_REG (a);
2161
2162 if (GET_CODE (a) == REG)
2163 reg_a = REGNO (a);
2164
2165 while (GET_CODE (b) == SUBREG)
2166 b = SUBREG_REG (b);
2167
2168 if (GET_CODE (b) == REG)
2169 reg_b = REGNO (b);
2170
2171 return reg_a != reg_b;
2172 }
2173
2174 \f
2175 rtx
2176 m32r_function_symbol (const char *name)
2177 {
2178 int extra_flags = 0;
2179 enum m32r_model model;
2180 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2181
2182 if (TARGET_MODEL_SMALL)
2183 model = M32R_MODEL_SMALL;
2184 else if (TARGET_MODEL_MEDIUM)
2185 model = M32R_MODEL_MEDIUM;
2186 else if (TARGET_MODEL_LARGE)
2187 model = M32R_MODEL_LARGE;
2188 else
2189 gcc_unreachable (); /* Shouldn't happen. */
2190 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2191
2192 if (extra_flags)
2193 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2194
2195 return sym;
2196 }
2197
2198 /* Use a library function to move some bytes. */
2199
2200 static void
2201 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2202 {
2203 /* We want to pass the size as Pmode, which will normally be SImode
2204 but will be DImode if we are using 64 bit longs and pointers. */
2205 if (GET_MODE (bytes_rtx) != VOIDmode
2206 && GET_MODE (bytes_rtx) != Pmode)
2207 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2208
2209 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2210 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2211 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2212 TYPE_UNSIGNED (sizetype)),
2213 TYPE_MODE (sizetype));
2214 }
2215
2216 /* Expand string/block move operations.
2217
2218 operands[0] is the pointer to the destination.
2219 operands[1] is the pointer to the source.
2220 operands[2] is the number of bytes to move.
2221 operands[3] is the alignment.
2222
2223 Returns 1 upon success, 0 otherwise. */
2224
2225 int
2226 m32r_expand_block_move (rtx operands[])
2227 {
2228 rtx orig_dst = operands[0];
2229 rtx orig_src = operands[1];
2230 rtx bytes_rtx = operands[2];
2231 rtx align_rtx = operands[3];
2232 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2233 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2234 int align = INTVAL (align_rtx);
2235 int leftover;
2236 rtx src_reg;
2237 rtx dst_reg;
2238
2239 if (constp && bytes <= 0)
2240 return 1;
2241
2242 /* Move the address into scratch registers. */
2243 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2244 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2245
2246 if (align > UNITS_PER_WORD)
2247 align = UNITS_PER_WORD;
2248
2249 /* If we prefer size over speed, always use a function call.
2250 If we do not know the size, use a function call.
2251 If the blocks are not word aligned, use a function call. */
2252 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2253 {
2254 block_move_call (dst_reg, src_reg, bytes_rtx);
2255 return 0;
2256 }
2257
2258 leftover = bytes % MAX_MOVE_BYTES;
2259 bytes -= leftover;
2260
2261 /* If necessary, generate a loop to handle the bulk of the copy. */
2262 if (bytes)
2263 {
2264 rtx label = NULL_RTX;
2265 rtx final_src = NULL_RTX;
2266 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2267 rtx rounded_total = GEN_INT (bytes);
2268 rtx new_dst_reg = gen_reg_rtx (SImode);
2269 rtx new_src_reg = gen_reg_rtx (SImode);
2270
2271 /* If we are going to have to perform this loop more than
2272 once, then generate a label and compute the address the
2273 source register will contain upon completion of the final
2274 iteration. */
2275 if (bytes > MAX_MOVE_BYTES)
2276 {
2277 final_src = gen_reg_rtx (Pmode);
2278
2279 if (INT16_P(bytes))
2280 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2281 else
2282 {
2283 emit_insn (gen_movsi (final_src, rounded_total));
2284 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2285 }
2286
2287 label = gen_label_rtx ();
2288 emit_label (label);
2289 }
2290
2291 /* It is known that output_block_move() will update src_reg to point
2292 to the word after the end of the source block, and dst_reg to point
2293 to the last word of the destination block, provided that the block
2294 is MAX_MOVE_BYTES long. */
2295 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2296 new_dst_reg, new_src_reg));
2297 emit_move_insn (dst_reg, new_dst_reg);
2298 emit_move_insn (src_reg, new_src_reg);
2299 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2300
2301 if (bytes > MAX_MOVE_BYTES)
2302 {
2303 emit_insn (gen_cmpsi (src_reg, final_src));
2304 emit_jump_insn (gen_bne (label));
2305 }
2306 }
2307
2308 if (leftover)
2309 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2310 gen_reg_rtx (SImode),
2311 gen_reg_rtx (SImode)));
2312 return 1;
2313 }
2314
2315 \f
2316 /* Emit load/stores for a small constant word aligned block_move.
2317
2318 operands[0] is the memory address of the destination.
2319 operands[1] is the memory address of the source.
2320 operands[2] is the number of bytes to move.
2321 operands[3] is a temp register.
2322 operands[4] is a temp register. */
2323
2324 void
2325 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2326 {
2327 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2328 int first_time;
2329 int got_extra = 0;
2330
2331 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2332
2333 /* We do not have a post-increment store available, so the first set of
2334 stores are done without any increment, then the remaining ones can use
2335 the pre-increment addressing mode.
2336
2337 Note: expand_block_move() also relies upon this behavior when building
2338 loops to copy large blocks. */
2339 first_time = 1;
2340
2341 while (bytes > 0)
2342 {
2343 if (bytes >= 8)
2344 {
2345 if (first_time)
2346 {
2347 output_asm_insn ("ld\t%5, %p1", operands);
2348 output_asm_insn ("ld\t%6, %p1", operands);
2349 output_asm_insn ("st\t%5, @%0", operands);
2350 output_asm_insn ("st\t%6, %s0", operands);
2351 }
2352 else
2353 {
2354 output_asm_insn ("ld\t%5, %p1", operands);
2355 output_asm_insn ("ld\t%6, %p1", operands);
2356 output_asm_insn ("st\t%5, %s0", operands);
2357 output_asm_insn ("st\t%6, %s0", operands);
2358 }
2359
2360 bytes -= 8;
2361 }
2362 else if (bytes >= 4)
2363 {
2364 if (bytes > 4)
2365 got_extra = 1;
2366
2367 output_asm_insn ("ld\t%5, %p1", operands);
2368
2369 if (got_extra)
2370 output_asm_insn ("ld\t%6, %p1", operands);
2371
2372 if (first_time)
2373 output_asm_insn ("st\t%5, @%0", operands);
2374 else
2375 output_asm_insn ("st\t%5, %s0", operands);
2376
2377 bytes -= 4;
2378 }
2379 else
2380 {
2381 /* Get the entire next word, even though we do not want all of it.
2382 The saves us from doing several smaller loads, and we assume that
2383 we cannot cause a page fault when at least part of the word is in
2384 valid memory [since we don't get called if things aren't properly
2385 aligned]. */
2386 int dst_offset = first_time ? 0 : 4;
2387 /* The amount of increment we have to make to the
2388 destination pointer. */
2389 int dst_inc_amount = dst_offset + bytes - 4;
2390 /* The same for the source pointer. */
2391 int src_inc_amount = bytes;
2392 int last_shift;
2393 rtx my_operands[3];
2394
2395 /* If got_extra is true then we have already loaded
2396 the next word as part of loading and storing the previous word. */
2397 if (! got_extra)
2398 output_asm_insn ("ld\t%6, @%1", operands);
2399
2400 if (bytes >= 2)
2401 {
2402 bytes -= 2;
2403
2404 output_asm_insn ("sra3\t%5, %6, #16", operands);
2405 my_operands[0] = operands[5];
2406 my_operands[1] = GEN_INT (dst_offset);
2407 my_operands[2] = operands[0];
2408 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2409
2410 /* If there is a byte left to store then increment the
2411 destination address and shift the contents of the source
2412 register down by 8 bits. We could not do the address
2413 increment in the store half word instruction, because it does
2414 not have an auto increment mode. */
2415 if (bytes > 0) /* assert (bytes == 1) */
2416 {
2417 dst_offset += 2;
2418 last_shift = 8;
2419 }
2420 }
2421 else
2422 last_shift = 24;
2423
2424 if (bytes > 0)
2425 {
2426 my_operands[0] = operands[6];
2427 my_operands[1] = GEN_INT (last_shift);
2428 output_asm_insn ("srai\t%0, #%1", my_operands);
2429 my_operands[0] = operands[6];
2430 my_operands[1] = GEN_INT (dst_offset);
2431 my_operands[2] = operands[0];
2432 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2433 }
2434
2435 /* Update the destination pointer if needed. We have to do
2436 this so that the patterns matches what we output in this
2437 function. */
2438 if (dst_inc_amount
2439 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2440 {
2441 my_operands[0] = operands[0];
2442 my_operands[1] = GEN_INT (dst_inc_amount);
2443 output_asm_insn ("addi\t%0, #%1", my_operands);
2444 }
2445
2446 /* Update the source pointer if needed. We have to do this
2447 so that the patterns matches what we output in this
2448 function. */
2449 if (src_inc_amount
2450 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2451 {
2452 my_operands[0] = operands[1];
2453 my_operands[1] = GEN_INT (src_inc_amount);
2454 output_asm_insn ("addi\t%0, #%1", my_operands);
2455 }
2456
2457 bytes = 0;
2458 }
2459
2460 first_time = 0;
2461 }
2462 }
2463
2464 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2465
2466 int
2467 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2468 unsigned int new_reg)
2469 {
2470 /* Interrupt routines can't clobber any register that isn't already used. */
2471 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2472 && !regs_ever_live[new_reg])
2473 return 0;
2474
2475 /* We currently emit epilogues as text, not rtl, so the liveness
2476 of the return address register isn't visible. */
2477 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2478 return 0;
2479
2480 return 1;
2481 }
2482
2483 rtx
2484 m32r_return_addr (int count)
2485 {
2486 if (count != 0)
2487 return const0_rtx;
2488
2489 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2490 }
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