1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
25 #include "stor-layout.h"
27 #include "stringpool.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "diagnostic-core.h"
48 #include "dominance.h"
54 #include "cfgcleanup.h"
56 #include "basic-block.h"
60 #include "target-def.h"
61 #include "tm-constrs.h"
65 /* Array of valid operand punctuation characters. */
66 static char m32r_punct_chars
[256];
68 /* Machine-specific symbol_ref flags. */
69 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
70 #define SYMBOL_REF_MODEL(X) \
71 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
73 /* For string literals, etc. */
74 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
76 /* Forward declaration. */
77 static void m32r_option_override (void);
78 static void init_reg_tables (void);
79 static void block_move_call (rtx
, rtx
, rtx
);
80 static int m32r_is_insn (rtx
);
81 static bool m32r_legitimate_address_p (machine_mode
, rtx
, bool);
82 static rtx
m32r_legitimize_address (rtx
, rtx
, machine_mode
);
83 static bool m32r_mode_dependent_address_p (const_rtx
, addr_space_t
);
84 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
85 static void m32r_print_operand (FILE *, rtx
, int);
86 static void m32r_print_operand_address (FILE *, rtx
);
87 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
88 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
89 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
91 static void m32r_file_start (void);
93 static int m32r_adjust_priority (rtx_insn
*, int);
94 static int m32r_issue_rate (void);
96 static void m32r_encode_section_info (tree
, rtx
, int);
97 static bool m32r_in_small_data_p (const_tree
);
98 static bool m32r_return_in_memory (const_tree
, const_tree
);
99 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
100 static rtx
m32r_libcall_value (machine_mode
, const_rtx
);
101 static bool m32r_function_value_regno_p (const unsigned int);
102 static void m32r_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
104 static void init_idents (void);
105 static bool m32r_rtx_costs (rtx
, int, int, int, int *, bool speed
);
106 static int m32r_memory_move_cost (machine_mode
, reg_class_t
, bool);
107 static bool m32r_pass_by_reference (cumulative_args_t
, machine_mode
,
109 static int m32r_arg_partial_bytes (cumulative_args_t
, machine_mode
,
111 static rtx
m32r_function_arg (cumulative_args_t
, machine_mode
,
113 static void m32r_function_arg_advance (cumulative_args_t
, machine_mode
,
115 static bool m32r_can_eliminate (const int, const int);
116 static void m32r_conditional_register_usage (void);
117 static void m32r_trampoline_init (rtx
, tree
, rtx
);
118 static bool m32r_legitimate_constant_p (machine_mode
, rtx
);
120 /* M32R specific attributes. */
122 static const struct attribute_spec m32r_attribute_table
[] =
124 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
125 affects_type_identity } */
126 { "interrupt", 0, 0, true, false, false, NULL
, false },
127 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
,
129 { NULL
, 0, 0, false, false, false, NULL
, false }
132 /* Initialize the GCC target structure. */
133 #undef TARGET_ATTRIBUTE_TABLE
134 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
136 #undef TARGET_LEGITIMATE_ADDRESS_P
137 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
138 #undef TARGET_LEGITIMIZE_ADDRESS
139 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
140 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
141 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
143 #undef TARGET_ASM_ALIGNED_HI_OP
144 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
145 #undef TARGET_ASM_ALIGNED_SI_OP
146 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
148 #undef TARGET_PRINT_OPERAND
149 #define TARGET_PRINT_OPERAND m32r_print_operand
150 #undef TARGET_PRINT_OPERAND_ADDRESS
151 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
152 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
153 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
155 #undef TARGET_ASM_FUNCTION_PROLOGUE
156 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
157 #undef TARGET_ASM_FUNCTION_EPILOGUE
158 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
160 #undef TARGET_ASM_FILE_START
161 #define TARGET_ASM_FILE_START m32r_file_start
163 #undef TARGET_SCHED_ADJUST_PRIORITY
164 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
165 #undef TARGET_SCHED_ISSUE_RATE
166 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
168 #undef TARGET_OPTION_OVERRIDE
169 #define TARGET_OPTION_OVERRIDE m32r_option_override
171 #undef TARGET_ENCODE_SECTION_INFO
172 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
173 #undef TARGET_IN_SMALL_DATA_P
174 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
177 #undef TARGET_MEMORY_MOVE_COST
178 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
179 #undef TARGET_RTX_COSTS
180 #define TARGET_RTX_COSTS m32r_rtx_costs
181 #undef TARGET_ADDRESS_COST
182 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
184 #undef TARGET_PROMOTE_PROTOTYPES
185 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
186 #undef TARGET_RETURN_IN_MEMORY
187 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
189 #undef TARGET_FUNCTION_VALUE
190 #define TARGET_FUNCTION_VALUE m32r_function_value
191 #undef TARGET_LIBCALL_VALUE
192 #define TARGET_LIBCALL_VALUE m32r_libcall_value
193 #undef TARGET_FUNCTION_VALUE_REGNO_P
194 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
196 #undef TARGET_SETUP_INCOMING_VARARGS
197 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
198 #undef TARGET_MUST_PASS_IN_STACK
199 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
200 #undef TARGET_PASS_BY_REFERENCE
201 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
202 #undef TARGET_ARG_PARTIAL_BYTES
203 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
204 #undef TARGET_FUNCTION_ARG
205 #define TARGET_FUNCTION_ARG m32r_function_arg
206 #undef TARGET_FUNCTION_ARG_ADVANCE
207 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
209 #undef TARGET_CAN_ELIMINATE
210 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
212 #undef TARGET_CONDITIONAL_REGISTER_USAGE
213 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
215 #undef TARGET_TRAMPOLINE_INIT
216 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
218 #undef TARGET_LEGITIMATE_CONSTANT_P
219 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
221 struct gcc_target targetm
= TARGET_INITIALIZER
;
223 /* Called by m32r_option_override to initialize various things. */
230 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
231 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
232 m32r_punct_chars
['#'] = 1;
233 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
235 /* Provide default value if not specified. */
236 if (!global_options_set
.x_g_switch_value
)
237 g_switch_value
= SDATA_DEFAULT_SIZE
;
241 m32r_option_override (void)
243 /* These need to be done at start up.
244 It's convenient to do them here. */
246 SUBTARGET_OVERRIDE_OPTIONS
;
249 /* Vectors to keep interesting information about registers where it can easily
250 be got. We use to use the actual mode value as the bit number, but there
251 is (or may be) more than 32 modes now. Instead we use two tables: one
252 indexed by hard register number, and one indexed by mode. */
254 /* The purpose of m32r_mode_class is to shrink the range of modes so that
255 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
256 mapped into one m32r_mode_class mode. */
261 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
262 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
265 /* Modes for condition codes. */
266 #define C_MODES (1 << (int) C_MODE)
268 /* Modes for single-word and smaller quantities. */
269 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
271 /* Modes for double-word and smaller quantities. */
272 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
274 /* Modes for quad-word and smaller quantities. */
275 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
277 /* Modes for accumulators. */
278 #define A_MODES (1 << (int) A_MODE)
280 /* Value is 1 if register/mode pair is acceptable on arc. */
282 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
284 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
285 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
286 S_MODES
, C_MODES
, A_MODES
, A_MODES
289 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
291 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
294 init_reg_tables (void)
298 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
300 machine_mode m
= (machine_mode
) i
;
302 switch (GET_MODE_CLASS (m
))
305 case MODE_PARTIAL_INT
:
306 case MODE_COMPLEX_INT
:
307 if (GET_MODE_SIZE (m
) <= 4)
308 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
309 else if (GET_MODE_SIZE (m
) == 8)
310 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
311 else if (GET_MODE_SIZE (m
) == 16)
312 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
313 else if (GET_MODE_SIZE (m
) == 32)
314 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
316 m32r_mode_class
[i
] = 0;
319 case MODE_COMPLEX_FLOAT
:
320 if (GET_MODE_SIZE (m
) <= 4)
321 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
322 else if (GET_MODE_SIZE (m
) == 8)
323 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
324 else if (GET_MODE_SIZE (m
) == 16)
325 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
326 else if (GET_MODE_SIZE (m
) == 32)
327 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
329 m32r_mode_class
[i
] = 0;
332 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
335 m32r_mode_class
[i
] = 0;
340 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
343 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
344 else if (i
== ARG_POINTER_REGNUM
)
345 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
347 m32r_regno_reg_class
[i
] = NO_REGS
;
351 /* M32R specific attribute support.
353 interrupt - for interrupt functions
355 model - select code model used to access object
357 small: addresses use 24 bits, use bl to make calls
358 medium: addresses use 32 bits, use bl to make calls
359 large: addresses use 32 bits, use seth/add3/jl to make calls
361 Grep for MODEL in m32r.h for more info. */
363 static tree small_ident1
;
364 static tree small_ident2
;
365 static tree medium_ident1
;
366 static tree medium_ident2
;
367 static tree large_ident1
;
368 static tree large_ident2
;
373 if (small_ident1
== 0)
375 small_ident1
= get_identifier ("small");
376 small_ident2
= get_identifier ("__small__");
377 medium_ident1
= get_identifier ("medium");
378 medium_ident2
= get_identifier ("__medium__");
379 large_ident1
= get_identifier ("large");
380 large_ident2
= get_identifier ("__large__");
384 /* Handle an "model" attribute; arguments as in
385 struct attribute_spec.handler. */
387 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
388 tree args
, int flags ATTRIBUTE_UNUSED
,
394 arg
= TREE_VALUE (args
);
396 if (arg
!= small_ident1
397 && arg
!= small_ident2
398 && arg
!= medium_ident1
399 && arg
!= medium_ident2
400 && arg
!= large_ident1
401 && arg
!= large_ident2
)
403 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
404 IDENTIFIER_POINTER (name
));
405 *no_add_attrs
= true;
411 /* Encode section information of DECL, which is either a VAR_DECL,
412 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
414 For the M32R we want to record:
416 - whether the object lives in .sdata/.sbss.
417 - what code model should be used to access the object
421 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
425 enum m32r_model model
;
427 default_encode_section_info (decl
, rtl
, first
);
432 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
439 id
= TREE_VALUE (TREE_VALUE (model_attr
));
441 if (id
== small_ident1
|| id
== small_ident2
)
442 model
= M32R_MODEL_SMALL
;
443 else if (id
== medium_ident1
|| id
== medium_ident2
)
444 model
= M32R_MODEL_MEDIUM
;
445 else if (id
== large_ident1
|| id
== large_ident2
)
446 model
= M32R_MODEL_LARGE
;
448 gcc_unreachable (); /* shouldn't happen */
452 if (TARGET_MODEL_SMALL
)
453 model
= M32R_MODEL_SMALL
;
454 else if (TARGET_MODEL_MEDIUM
)
455 model
= M32R_MODEL_MEDIUM
;
456 else if (TARGET_MODEL_LARGE
)
457 model
= M32R_MODEL_LARGE
;
459 gcc_unreachable (); /* shouldn't happen */
461 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
464 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
467 /* Only mark the object as being small data area addressable if
468 it hasn't been explicitly marked with a code model.
470 The user can explicitly put an object in the small data area with the
471 section attribute. If the object is in sdata/sbss and marked with a
472 code model do both [put the object in .sdata and mark it as being
473 addressed with a specific code model - don't mark it as being addressed
474 with an SDA reloc though]. This is ok and might be useful at times. If
475 the object doesn't fit the linker will give an error. */
478 m32r_in_small_data_p (const_tree decl
)
482 if (TREE_CODE (decl
) != VAR_DECL
)
485 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
488 section
= DECL_SECTION_NAME (decl
);
491 if (strcmp (section
, ".sdata") == 0 || strcmp (section
, ".sbss") == 0)
496 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
498 int size
= int_size_in_bytes (TREE_TYPE (decl
));
500 if (size
> 0 && size
<= g_switch_value
)
508 /* Do anything needed before RTL is emitted for each function. */
511 m32r_init_expanders (void)
513 /* ??? At one point there was code here. The function is left in
514 to make it easy to experiment. */
518 call_operand (rtx op
, machine_mode mode
)
523 return call_address_operand (op
, mode
);
526 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
529 small_data_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
531 if (! TARGET_SDATA_USE
)
534 if (GET_CODE (op
) == SYMBOL_REF
)
535 return SYMBOL_REF_SMALL_P (op
);
537 if (GET_CODE (op
) == CONST
538 && GET_CODE (XEXP (op
, 0)) == PLUS
539 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
540 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
541 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
546 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
549 addr24_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
556 if (GET_CODE (op
) == LABEL_REF
)
557 return TARGET_ADDR24
;
559 if (GET_CODE (op
) == SYMBOL_REF
)
561 else if (GET_CODE (op
) == CONST
562 && GET_CODE (XEXP (op
, 0)) == PLUS
563 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
564 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
565 sym
= XEXP (XEXP (op
, 0), 0);
569 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
573 && (CONSTANT_POOL_ADDRESS_P (sym
)
574 || LIT_NAME_P (XSTR (sym
, 0))))
580 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
583 addr32_operand (rtx op
, machine_mode mode
)
587 if (GET_CODE (op
) == LABEL_REF
)
588 return TARGET_ADDR32
;
590 if (GET_CODE (op
) == SYMBOL_REF
)
592 else if (GET_CODE (op
) == CONST
593 && GET_CODE (XEXP (op
, 0)) == PLUS
594 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
595 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
597 sym
= XEXP (XEXP (op
, 0), 0);
601 return (! addr24_operand (sym
, mode
)
602 && ! small_data_operand (sym
, mode
));
605 /* Return 1 if OP is a function that can be called with the `bl' insn. */
608 call26_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
613 if (GET_CODE (op
) == SYMBOL_REF
)
614 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
616 return TARGET_CALL26
;
619 /* Return 1 if OP is a DImode const we want to handle inline.
620 This must match the code in the movdi pattern.
621 It is used by the 'G' constraint. */
624 easy_di_const (rtx op
)
626 rtx high_rtx
, low_rtx
;
627 HOST_WIDE_INT high
, low
;
629 split_double (op
, &high_rtx
, &low_rtx
);
630 high
= INTVAL (high_rtx
);
631 low
= INTVAL (low_rtx
);
632 /* Pick constants loadable with 2 16-bit `ldi' insns. */
633 if (high
>= -128 && high
<= 127
634 && low
>= -128 && low
<= 127)
639 /* Return 1 if OP is a DFmode const we want to handle inline.
640 This must match the code in the movdf pattern.
641 It is used by the 'H' constraint. */
644 easy_df_const (rtx op
)
649 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
650 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
651 if (l
[0] == 0 && l
[1] == 0)
653 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
658 /* Return 1 if OP is (mem (reg ...)).
659 This is used in insn length calcs. */
662 memreg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
664 return MEM_P (op
) && REG_P (XEXP (op
, 0));
667 /* Return nonzero if TYPE must be passed by indirect reference. */
670 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
671 machine_mode mode
, const_tree type
,
672 bool named ATTRIBUTE_UNUSED
)
677 size
= int_size_in_bytes (type
);
679 size
= GET_MODE_SIZE (mode
);
681 return (size
< 0 || size
> 8);
686 /* X and Y are two things to compare using CODE. Emit the compare insn and
687 return the rtx for compare [arg0 of the if_then_else].
688 If need_compare is true then the comparison insn must be generated, rather
689 than being subsumed into the following branch instruction. */
692 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
694 enum rtx_code compare_code
;
695 enum rtx_code branch_code
;
696 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
701 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
702 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
703 case LT
: compare_code
= LT
; branch_code
= NE
; break;
704 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
705 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
706 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
707 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
708 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
709 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
710 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
718 switch (compare_code
)
721 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
724 rtx tmp
= gen_reg_rtx (SImode
);
726 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
730 else if (CONSTANT_P (y
)) /* Reg equal to const. */
732 rtx tmp
= force_reg (GET_MODE (x
), y
);
736 if (register_operand (y
, SImode
) /* Reg equal to reg. */
737 || y
== const0_rtx
) /* Reg equal to zero. */
739 emit_insn (gen_cmp_eqsi_insn (x
, y
));
741 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
746 if (register_operand (y
, SImode
)
747 || satisfies_constraint_P (y
))
749 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
754 emit_insn (gen_cmp_ltsi_insn (x
, y
));
761 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
762 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
767 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
769 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
770 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
774 emit_insn (gen_cmp_ltsi_insn (x
, y
));
781 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
786 if (register_operand (y
, SImode
)
787 || satisfies_constraint_P (y
))
789 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
794 emit_insn (gen_cmp_ltusi_insn (x
, y
));
801 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
802 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
807 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
809 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
810 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
814 emit_insn (gen_cmp_ltusi_insn (x
, y
));
821 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
831 /* Reg/reg equal comparison. */
832 if (compare_code
== EQ
833 && register_operand (y
, SImode
))
834 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
836 /* Reg/zero signed comparison. */
837 if ((compare_code
== EQ
|| compare_code
== LT
)
839 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
841 /* Reg/smallconst equal comparison. */
842 if (compare_code
== EQ
843 && satisfies_constraint_P (y
))
845 rtx tmp
= gen_reg_rtx (SImode
);
847 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
848 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
851 /* Reg/const equal comparison. */
852 if (compare_code
== EQ
855 rtx tmp
= force_reg (GET_MODE (x
), y
);
857 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
864 y
= force_reg (GET_MODE (x
), y
);
867 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
870 y
= force_reg (GET_MODE (x
), y
);
874 switch (compare_code
)
877 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
880 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
883 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
890 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
894 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
896 machine_mode mode
= GET_MODE (op0
);
898 gcc_assert (mode
== SImode
);
902 if (!register_operand (op1
, mode
))
903 op1
= force_reg (mode
, op1
);
905 if (TARGET_M32RX
|| TARGET_M32R2
)
907 if (!reg_or_zero_operand (op2
, mode
))
908 op2
= force_reg (mode
, op2
);
910 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
913 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
915 emit_insn (gen_seq_zero_insn (op0
, op1
));
919 if (!reg_or_eq_int16_operand (op2
, mode
))
920 op2
= force_reg (mode
, op2
);
922 emit_insn (gen_seq_insn (op0
, op1
, op2
));
926 if (!CONST_INT_P (op2
)
927 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
931 if (reload_completed
|| reload_in_progress
)
934 reg
= gen_reg_rtx (SImode
);
935 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
938 if (!register_operand (op1
, mode
))
939 op1
= force_reg (mode
, op1
);
941 emit_insn (gen_sne_zero_insn (op0
, op1
));
956 if (!register_operand (op1
, mode
))
957 op1
= force_reg (mode
, op1
);
959 if (!reg_or_int16_operand (op2
, mode
))
960 op2
= force_reg (mode
, op2
);
962 emit_insn (gen_slt_insn (op0
, op1
, op2
));
975 if (!register_operand (op1
, mode
))
976 op1
= force_reg (mode
, op1
);
978 if (!reg_or_int16_operand (op2
, mode
))
979 op2
= force_reg (mode
, op2
);
981 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
986 if (!register_operand (op1
, mode
))
987 op1
= force_reg (mode
, op1
);
989 if (!reg_or_int16_operand (op2
, mode
))
990 op2
= force_reg (mode
, op2
);
993 emit_insn (gen_sge_insn (op0
, op1
, op2
));
995 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
1000 if (!register_operand (op1
, mode
))
1001 op1
= force_reg (mode
, op1
);
1003 if (CONST_INT_P (op2
))
1005 HOST_WIDE_INT value
= INTVAL (op2
);
1006 if (value
>= 2147483647)
1008 emit_move_insn (op0
, const1_rtx
);
1012 op2
= GEN_INT (value
+ 1);
1013 if (value
< -32768 || value
>= 32767)
1014 op2
= force_reg (mode
, op2
);
1017 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1019 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1023 if (!register_operand (op2
, mode
))
1024 op2
= force_reg (mode
, op2
);
1027 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1029 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1038 /* Split a 2 word move (DI or DF) into component parts. */
1041 gen_split_move_double (rtx operands
[])
1043 machine_mode mode
= GET_MODE (operands
[0]);
1044 rtx dest
= operands
[0];
1045 rtx src
= operands
[1];
1048 /* We might have (SUBREG (MEM)) here, so just get rid of the
1049 subregs to make this code simpler. It is safe to call
1050 alter_subreg any time after reload. */
1051 if (GET_CODE (dest
) == SUBREG
)
1052 alter_subreg (&dest
, true);
1053 if (GET_CODE (src
) == SUBREG
)
1054 alter_subreg (&src
, true);
1059 int dregno
= REGNO (dest
);
1064 int sregno
= REGNO (src
);
1066 int reverse
= (dregno
== sregno
+ 1);
1068 /* We normally copy the low-numbered register first. However, if
1069 the first register operand 0 is the same as the second register of
1070 operand 1, we must copy in the opposite order. */
1071 emit_insn (gen_rtx_SET (VOIDmode
,
1072 operand_subword (dest
, reverse
, TRUE
, mode
),
1073 operand_subword (src
, reverse
, TRUE
, mode
)));
1075 emit_insn (gen_rtx_SET (VOIDmode
,
1076 operand_subword (dest
, !reverse
, TRUE
, mode
),
1077 operand_subword (src
, !reverse
, TRUE
, mode
)));
1080 /* Reg = constant. */
1081 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1084 split_double (src
, &words
[0], &words
[1]);
1085 emit_insn (gen_rtx_SET (VOIDmode
,
1086 operand_subword (dest
, 0, TRUE
, mode
),
1089 emit_insn (gen_rtx_SET (VOIDmode
,
1090 operand_subword (dest
, 1, TRUE
, mode
),
1095 else if (MEM_P (src
))
1097 /* If the high-address word is used in the address, we must load it
1098 last. Otherwise, load it first. */
1099 int reverse
= refers_to_regno_p (dregno
, XEXP (src
, 0));
1101 /* We used to optimize loads from single registers as
1105 if r3 were not used subsequently. However, the REG_NOTES aren't
1106 propagated correctly by the reload phase, and it can cause bad
1107 code to be generated. We could still try:
1109 ld r1,r3+; ld r2,r3; addi r3,-4
1111 which saves 2 bytes and doesn't force longword alignment. */
1112 emit_insn (gen_rtx_SET (VOIDmode
,
1113 operand_subword (dest
, reverse
, TRUE
, mode
),
1114 adjust_address (src
, SImode
,
1115 reverse
* UNITS_PER_WORD
)));
1117 emit_insn (gen_rtx_SET (VOIDmode
,
1118 operand_subword (dest
, !reverse
, TRUE
, mode
),
1119 adjust_address (src
, SImode
,
1120 !reverse
* UNITS_PER_WORD
)));
1127 /* We used to optimize loads from single registers as
1131 if r3 were not used subsequently. However, the REG_NOTES aren't
1132 propagated correctly by the reload phase, and it can cause bad
1133 code to be generated. We could still try:
1135 st r1,r3; st r2,+r3; addi r3,-4
1137 which saves 2 bytes and doesn't force longword alignment. */
1138 else if (MEM_P (dest
) && REG_P (src
))
1140 emit_insn (gen_rtx_SET (VOIDmode
,
1141 adjust_address (dest
, SImode
, 0),
1142 operand_subword (src
, 0, TRUE
, mode
)));
1144 emit_insn (gen_rtx_SET (VOIDmode
,
1145 adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1146 operand_subword (src
, 1, TRUE
, mode
)));
1159 m32r_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1160 tree type
, bool named ATTRIBUTE_UNUSED
)
1162 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1166 (((mode
== BLKmode
&& type
)
1167 ? (unsigned int) int_size_in_bytes (type
)
1168 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1171 if (*cum
>= M32R_MAX_PARM_REGS
)
1173 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1174 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1178 return words
* UNITS_PER_WORD
;
1181 /* The ROUND_ADVANCE* macros are local to this file. */
1182 /* Round SIZE up to a word boundary. */
1183 #define ROUND_ADVANCE(SIZE) \
1184 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1186 /* Round arg MODE/TYPE up to the next word boundary. */
1187 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1188 ((MODE) == BLKmode \
1189 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1190 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1192 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1193 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1195 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1196 a reg. This includes arguments that have to be passed by reference as the
1197 pointer to them is passed in a reg if one is available (and that is what
1199 This macro is only used in this file. */
1200 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1201 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1203 /* Determine where to put an argument to a function.
1204 Value is zero to push the argument on the stack,
1205 or a hard register in which to store the argument.
1207 MODE is the argument's machine mode.
1208 TYPE is the data type of the argument (as a tree).
1209 This is null for libcalls where that information may
1211 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1212 the preceding args and about the function being called.
1213 NAMED is nonzero if this argument is a named parameter
1214 (otherwise it is an extra parameter matching an ellipsis). */
1215 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1216 and the rest are pushed. */
1219 m32r_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1220 const_tree type ATTRIBUTE_UNUSED
,
1221 bool named ATTRIBUTE_UNUSED
)
1223 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1225 return (PASS_IN_REG_P (*cum
, mode
, type
)
1226 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1230 /* Update the data in CUM to advance over an argument
1231 of mode MODE and data type TYPE.
1232 (TYPE is null for libcalls where that information may not be available.) */
1235 m32r_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1236 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1238 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1240 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1241 + ROUND_ADVANCE_ARG (mode
, type
));
1244 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1247 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1249 cumulative_args_t dummy
= pack_cumulative_args (NULL
);
1251 return m32r_pass_by_reference (dummy
, TYPE_MODE (type
), type
, false);
1254 /* Worker function for TARGET_FUNCTION_VALUE. */
1257 m32r_function_value (const_tree valtype
,
1258 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1259 bool outgoing ATTRIBUTE_UNUSED
)
1261 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1264 /* Worker function for TARGET_LIBCALL_VALUE. */
1267 m32r_libcall_value (machine_mode mode
,
1268 const_rtx fun ATTRIBUTE_UNUSED
)
1270 return gen_rtx_REG (mode
, 0);
1273 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1275 ??? What about r1 in DI/DF values. */
1278 m32r_function_value_regno_p (const unsigned int regno
)
1280 return (regno
== 0);
1283 /* Do any needed setup for a variadic function. For the M32R, we must
1284 create a register parameter block, and then copy any anonymous arguments
1285 in registers to memory.
1287 CUM has not been updated for the last named argument which has type TYPE
1288 and mode MODE, and we rely on this fact. */
1291 m32r_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
1292 tree type
, int *pretend_size
, int no_rtl
)
1299 /* All BLKmode values are passed by reference. */
1300 gcc_assert (mode
!= BLKmode
);
1302 first_anon_arg
= (ROUND_ADVANCE_CUM (*get_cumulative_args (cum
), mode
, type
)
1303 + ROUND_ADVANCE_ARG (mode
, type
));
1305 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1307 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1308 int first_reg_offset
= first_anon_arg
;
1309 /* Size in words to "pretend" allocate. */
1310 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1313 regblock
= gen_frame_mem (BLKmode
,
1314 plus_constant (Pmode
, arg_pointer_rtx
,
1315 FIRST_PARM_OFFSET (0)));
1316 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1317 move_block_from_reg (first_reg_offset
, regblock
, size
);
1319 *pretend_size
= (size
* UNITS_PER_WORD
);
1324 /* Return true if INSN is real instruction bearing insn. */
1327 m32r_is_insn (rtx insn
)
1329 return (NONDEBUG_INSN_P (insn
)
1330 && GET_CODE (PATTERN (insn
)) != USE
1331 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
1334 /* Increase the priority of long instructions so that the
1335 short instructions are scheduled ahead of the long ones. */
1338 m32r_adjust_priority (rtx_insn
*insn
, int priority
)
1340 if (m32r_is_insn (insn
)
1341 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1348 /* Indicate how many instructions can be issued at the same time.
1349 This is sort of a lie. The m32r can issue only 1 long insn at
1350 once, but it can issue 2 short insns. The default therefore is
1351 set at 2, but this can be overridden by the command line option
1355 m32r_issue_rate (void)
1357 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1360 /* Cost functions. */
1361 /* Memory is 3 times as expensive as registers.
1362 ??? Is that the right way to look at it? */
1365 m32r_memory_move_cost (machine_mode mode
,
1366 reg_class_t rclass ATTRIBUTE_UNUSED
,
1367 bool in ATTRIBUTE_UNUSED
)
1369 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1376 m32r_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
1377 int opno ATTRIBUTE_UNUSED
, int *total
,
1378 bool speed ATTRIBUTE_UNUSED
)
1382 /* Small integers are as cheap as registers. 4 byte values can be
1383 fetched as immediate constants - let's give that the cost of an
1386 if (INT16_P (INTVAL (x
)))
1396 *total
= COSTS_N_INSNS (1);
1403 split_double (x
, &high
, &low
);
1404 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1405 + !INT16_P (INTVAL (low
)));
1410 *total
= COSTS_N_INSNS (3);
1417 *total
= COSTS_N_INSNS (10);
1425 /* Type of function DECL.
1427 The result is cached. To reset the cache at the end of a function,
1428 call with DECL = NULL_TREE. */
1430 enum m32r_function_type
1431 m32r_compute_function_type (tree decl
)
1434 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1435 /* Last function we were called for. */
1436 static tree last_fn
= NULL_TREE
;
1438 /* Resetting the cached value? */
1439 if (decl
== NULL_TREE
)
1441 fn_type
= M32R_FUNCTION_UNKNOWN
;
1442 last_fn
= NULL_TREE
;
1446 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1449 /* Compute function type. */
1450 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1451 ? M32R_FUNCTION_INTERRUPT
1452 : M32R_FUNCTION_NORMAL
);
1457 \f/* Function prologue/epilogue handlers. */
1459 /* M32R stack frames look like:
1461 Before call After call
1462 +-----------------------+ +-----------------------+
1464 high | local variables, | | local variables, |
1465 mem | reg save area, etc. | | reg save area, etc. |
1467 +-----------------------+ +-----------------------+
1469 | arguments on stack. | | arguments on stack. |
1471 SP+0->+-----------------------+ +-----------------------+
1472 | reg parm save area, |
1473 | only created for |
1474 | variable argument |
1476 +-----------------------+
1477 | previous frame ptr |
1478 +-----------------------+
1480 | register save area |
1482 +-----------------------+
1484 +-----------------------+
1488 +-----------------------+
1490 | alloca allocations |
1492 +-----------------------+
1494 low | arguments on stack |
1496 SP+0->+-----------------------+
1499 1) The "reg parm save area" does not exist for non variable argument fns.
1500 2) The "reg parm save area" can be eliminated completely if we saved regs
1501 containing anonymous args separately but that complicates things too
1502 much (so it's not done).
1503 3) The return address is saved after the register save area so as to have as
1504 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1506 /* Structure to be filled in by m32r_compute_frame_size with register
1507 save masks, and offsets for the current function. */
1508 struct m32r_frame_info
1510 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1511 unsigned int extra_size
; /* # bytes of extra stuff. */
1512 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1513 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1514 unsigned int reg_size
; /* # bytes needed to store regs. */
1515 unsigned int var_size
; /* # bytes that variables take up. */
1516 unsigned int gmask
; /* Mask of saved gp registers. */
1517 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1518 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1519 int initialized
; /* Nonzero if frame size already calculated. */
1522 /* Current frame information calculated by m32r_compute_frame_size. */
1523 static struct m32r_frame_info current_frame_info
;
1525 /* Zero structure to initialize current_frame_info. */
1526 static struct m32r_frame_info zero_frame_info
;
1528 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1529 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1531 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1532 The return address and frame pointer are treated separately.
1533 Don't consider them here. */
1534 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1535 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1536 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1538 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1539 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1541 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1542 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1544 /* Return the bytes needed to compute the frame pointer from the current
1547 SIZE is the size needed for local variables. */
1550 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1553 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1554 unsigned int reg_size
;
1556 enum m32r_function_type fn_type
;
1558 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1561 var_size
= M32R_STACK_ALIGN (size
);
1562 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1563 pretend_size
= crtl
->args
.pretend_args_size
;
1564 extra_size
= FIRST_PARM_OFFSET (0);
1565 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1569 /* See if this is an interrupt handler. Call used registers must be saved
1571 fn_type
= m32r_compute_function_type (current_function_decl
);
1572 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1574 /* Calculate space needed for registers. */
1575 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1577 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1578 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1580 reg_size
+= UNITS_PER_WORD
;
1581 gmask
|= 1 << regno
;
1585 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1586 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1588 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1590 total_size
+= reg_size
;
1592 /* ??? Not sure this is necessary, and I don't think the epilogue
1593 handler will do the right thing if this changes total_size. */
1594 total_size
= M32R_STACK_ALIGN (total_size
);
1596 /* frame_size = total_size - (pretend_size + reg_size); */
1598 /* Save computed information. */
1599 current_frame_info
.total_size
= total_size
;
1600 current_frame_info
.extra_size
= extra_size
;
1601 current_frame_info
.pretend_size
= pretend_size
;
1602 current_frame_info
.var_size
= var_size
;
1603 current_frame_info
.args_size
= args_size
;
1604 current_frame_info
.reg_size
= reg_size
;
1605 current_frame_info
.gmask
= gmask
;
1606 current_frame_info
.initialized
= reload_completed
;
1608 /* Ok, we're done. */
1612 /* Worker function for TARGET_CAN_ELIMINATE. */
1615 m32r_can_eliminate (const int from
, const int to
)
1617 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1618 ? ! frame_pointer_needed
1623 /* The table we use to reference PIC data. */
1624 static rtx global_offset_table
;
1627 m32r_reload_lr (rtx sp
, int size
)
1629 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1632 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1633 else if (size
< 32768)
1634 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1635 gen_rtx_PLUS (Pmode
, sp
,
1639 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1641 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1642 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1643 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1650 m32r_load_pic_register (void)
1652 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1653 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1654 GEN_INT (TARGET_MODEL_SMALL
)));
1656 /* Need to emit this whether or not we obey regdecls,
1657 since setjmp/longjmp can cause life info to screw up. */
1658 emit_use (pic_offset_table_rtx
);
1661 /* Expand the m32r prologue as a series of insns. */
1664 m32r_expand_prologue (void)
1669 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1672 if (! current_frame_info
.initialized
)
1673 m32r_compute_frame_size (get_frame_size ());
1675 gmask
= current_frame_info
.gmask
;
1677 /* These cases shouldn't happen. Catch them now. */
1678 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1680 /* Allocate space for register arguments if this is a variadic function. */
1681 if (current_frame_info
.pretend_size
!= 0)
1683 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1684 the wrong result on a 64-bit host. */
1685 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1686 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1688 GEN_INT (-pretend_size
)));
1691 /* Save any registers we need to and set up fp. */
1692 if (current_frame_info
.save_fp
)
1693 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1695 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1697 /* Save any needed call-saved regs (and call-used if this is an
1698 interrupt handler). */
1699 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1701 if ((gmask
& (1 << regno
)) != 0)
1702 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1703 gen_rtx_REG (Pmode
, regno
)));
1706 if (current_frame_info
.save_lr
)
1707 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1708 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1710 /* Allocate the stack frame. */
1711 frame_size
= (current_frame_info
.total_size
1712 - (current_frame_info
.pretend_size
1713 + current_frame_info
.reg_size
));
1715 if (frame_size
== 0)
1716 ; /* Nothing to do. */
1717 else if (frame_size
<= 32768)
1718 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1719 GEN_INT (-frame_size
)));
1722 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1724 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1725 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1728 if (frame_pointer_needed
)
1729 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1732 /* Push lr for mcount (form_pc, x). */
1733 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1734 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1738 m32r_load_pic_register ();
1739 m32r_reload_lr (stack_pointer_rtx
,
1740 (crtl
->profile
? 0 : frame_size
));
1743 if (crtl
->profile
&& !pic_reg_used
)
1744 emit_insn (gen_blockage ());
1748 /* Set up the stack and frame pointer (if desired) for the function.
1749 Note, if this is changed, you need to mirror the changes in
1750 m32r_compute_frame_size which calculates the prolog size. */
1753 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1755 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1757 /* If this is an interrupt handler, mark it as such. */
1758 if (M32R_INTERRUPT_P (fn_type
))
1759 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1761 if (! current_frame_info
.initialized
)
1762 m32r_compute_frame_size (size
);
1764 /* This is only for the human reader. */
1766 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1768 current_frame_info
.var_size
,
1769 current_frame_info
.reg_size
/ 4,
1770 current_frame_info
.args_size
,
1771 current_frame_info
.extra_size
);
1774 /* Output RTL to pop register REGNO from the stack. */
1781 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1782 stack_pointer_rtx
));
1783 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1786 /* Expand the m32r epilogue as a series of insns. */
1789 m32r_expand_epilogue (void)
1792 int noepilogue
= FALSE
;
1795 gcc_assert (current_frame_info
.initialized
);
1796 total_size
= current_frame_info
.total_size
;
1798 if (total_size
== 0)
1800 rtx insn
= get_last_insn ();
1802 /* If the last insn was a BARRIER, we don't have to write any code
1803 because a jump (aka return) was put there. */
1804 if (insn
&& NOTE_P (insn
))
1805 insn
= prev_nonnote_insn (insn
);
1806 if (insn
&& BARRIER_P (insn
))
1812 unsigned int var_size
= current_frame_info
.var_size
;
1813 unsigned int args_size
= current_frame_info
.args_size
;
1814 unsigned int gmask
= current_frame_info
.gmask
;
1815 int can_trust_sp_p
= !cfun
->calls_alloca
;
1817 if (flag_exceptions
)
1818 emit_insn (gen_blockage ());
1820 /* The first thing to do is point the sp at the bottom of the register
1824 unsigned int reg_offset
= var_size
+ args_size
;
1826 if (reg_offset
== 0)
1827 ; /* Nothing to do. */
1828 else if (reg_offset
< 32768)
1829 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1830 GEN_INT (reg_offset
)));
1833 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1835 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1836 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1840 else if (frame_pointer_needed
)
1842 unsigned int reg_offset
= var_size
+ args_size
;
1844 if (reg_offset
== 0)
1845 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1846 else if (reg_offset
< 32768)
1847 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1848 GEN_INT (reg_offset
)));
1851 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1853 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1854 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1855 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1862 if (current_frame_info
.save_lr
)
1863 pop (RETURN_ADDR_REGNUM
);
1865 /* Restore any saved registers, in reverse order of course. */
1866 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1867 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1869 if ((gmask
& (1L << regno
)) != 0)
1873 if (current_frame_info
.save_fp
)
1874 pop (FRAME_POINTER_REGNUM
);
1876 /* Remove varargs area if present. */
1877 if (current_frame_info
.pretend_size
!= 0)
1878 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1879 GEN_INT (current_frame_info
.pretend_size
)));
1881 emit_insn (gen_blockage ());
1885 /* Do any necessary cleanup after a function to restore stack, frame,
1889 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED
,
1890 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1892 /* Reset state info for each function. */
1893 current_frame_info
= zero_frame_info
;
1894 m32r_compute_function_type (NULL_TREE
);
1897 /* Return nonzero if this function is known to have a null or 1 instruction
1901 direct_return (void)
1903 if (!reload_completed
)
1906 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1909 if (! current_frame_info
.initialized
)
1910 m32r_compute_frame_size (get_frame_size ());
1912 return current_frame_info
.total_size
== 0;
1919 m32r_legitimate_pic_operand_p (rtx x
)
1921 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1924 if (GET_CODE (x
) == CONST
1925 && GET_CODE (XEXP (x
, 0)) == PLUS
1926 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1927 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1928 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1935 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1938 printf("m32r_legitimize_pic_address()\n");
1941 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1943 rtx pic_ref
, address
;
1948 gcc_assert (!reload_in_progress
&& !reload_completed
);
1949 reg
= gen_reg_rtx (Pmode
);
1955 address
= gen_reg_rtx (Pmode
);
1959 crtl
->uses_pic_offset_table
= 1;
1961 if (GET_CODE (orig
) == LABEL_REF
1962 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1964 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1965 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1969 emit_insn (gen_pic_load_addr (address
, orig
));
1971 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1972 pic_ref
= gen_const_mem (Pmode
, address
);
1973 emit_move_insn (reg
, pic_ref
);
1976 else if (GET_CODE (orig
) == CONST
)
1980 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1981 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1986 gcc_assert (!reload_in_progress
&& !reload_completed
);
1987 reg
= gen_reg_rtx (Pmode
);
1990 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1992 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
1994 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
1996 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
2001 if (CONST_INT_P (offset
))
2003 if (INT16_P (INTVAL (offset
)))
2004 return plus_constant (Pmode
, base
, INTVAL (offset
));
2007 gcc_assert (! reload_in_progress
&& ! reload_completed
);
2008 offset
= force_reg (Pmode
, offset
);
2012 return gen_rtx_PLUS (Pmode
, base
, offset
);
2019 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2020 machine_mode mode ATTRIBUTE_UNUSED
)
2023 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2028 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2031 m32r_mode_dependent_address_p (const_rtx addr
, addr_space_t as ATTRIBUTE_UNUSED
)
2033 if (GET_CODE (addr
) == LO_SUM
)
2039 /* Nested function support. */
2041 /* Emit RTL insns to initialize the variable parts of a trampoline.
2042 FNADDR is an RTX for the address of the function's pure code.
2043 CXT is an RTX for the static chain value for the function. */
2046 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2047 rtx fnaddr ATTRIBUTE_UNUSED
,
2048 rtx cxt ATTRIBUTE_UNUSED
)
2053 m32r_file_start (void)
2055 default_file_start ();
2057 if (flag_verbose_asm
)
2058 fprintf (asm_out_file
,
2059 "%s M32R/D special options: -G %d\n",
2060 ASM_COMMENT_START
, g_switch_value
);
2062 if (TARGET_LITTLE_ENDIAN
)
2063 fprintf (asm_out_file
, "\t.little\n");
2066 /* Print operand X (an rtx) in assembler syntax to file FILE.
2067 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2068 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2071 m32r_print_operand (FILE * file
, rtx x
, int code
)
2077 /* The 's' and 'p' codes are used by output_block_move() to
2078 indicate post-increment 's'tores and 'p're-increment loads. */
2081 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2083 output_operand_lossage ("invalid operand to %%s code");
2088 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2090 output_operand_lossage ("invalid operand to %%p code");
2094 /* Write second word of DImode or DFmode reference,
2095 register or memory. */
2097 fputs (reg_names
[REGNO (x
)+1], file
);
2100 fprintf (file
, "@(");
2101 /* Handle possible auto-increment. Since it is pre-increment and
2102 we have already done it, we can just use an offset of four. */
2103 /* ??? This is taken from rs6000.c I think. I don't think it is
2104 currently necessary, but keep it around. */
2105 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2106 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2107 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 4));
2109 output_address (plus_constant (Pmode
, XEXP (x
, 0), 4));
2113 output_operand_lossage ("invalid operand to %%R code");
2116 case 'H' : /* High word. */
2117 case 'L' : /* Low word. */
2120 /* L = least significant word, H = most significant word. */
2121 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2122 fputs (reg_names
[REGNO (x
)], file
);
2124 fputs (reg_names
[REGNO (x
)+1], file
);
2126 else if (CONST_INT_P (x
)
2127 || GET_CODE (x
) == CONST_DOUBLE
)
2131 split_double (x
, &first
, &second
);
2132 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2133 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2136 output_operand_lossage ("invalid operand to %%H/%%L code");
2143 if (GET_CODE (x
) != CONST_DOUBLE
2144 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2145 fatal_insn ("bad insn for 'A'", x
);
2147 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2148 fprintf (file
, "%s", str
);
2152 case 'B' : /* Bottom half. */
2153 case 'T' : /* Top half. */
2154 /* Output the argument to a `seth' insn (sets the Top half-word).
2155 For constants output arguments to a seth/or3 pair to set Top and
2156 Bottom halves. For symbols output arguments to a seth/add3 pair to
2157 set Top and Bottom halves. The difference exists because for
2158 constants seth/or3 is more readable but for symbols we need to use
2159 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2160 switch (GET_CODE (x
))
2167 split_double (x
, &first
, &second
);
2168 x
= WORDS_BIG_ENDIAN
? second
: first
;
2169 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2171 ? INTVAL (x
) & 0xffff
2172 : (INTVAL (x
) >> 16) & 0xffff));
2178 && small_data_operand (x
, VOIDmode
))
2180 fputs ("sda(", file
);
2181 output_addr_const (file
, x
);
2187 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2188 output_addr_const (file
, x
);
2192 output_operand_lossage ("invalid operand to %%T/%%B code");
2199 /* Output a load/store with update indicator if appropriate. */
2202 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2203 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2207 output_operand_lossage ("invalid operand to %%U code");
2211 /* Print a constant value negated. */
2212 if (CONST_INT_P (x
))
2213 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2215 output_operand_lossage ("invalid operand to %%N code");
2219 /* Print a const_int in hex. Used in comments. */
2220 if (CONST_INT_P (x
))
2221 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2225 fputs (IMMEDIATE_PREFIX
, file
);
2229 /* Do nothing special. */
2234 output_operand_lossage ("invalid operand output code");
2237 switch (GET_CODE (x
))
2240 fputs (reg_names
[REGNO (x
)], file
);
2245 if (GET_CODE (addr
) == PRE_INC
)
2247 if (!REG_P (XEXP (addr
, 0)))
2248 fatal_insn ("pre-increment address is not a register", x
);
2250 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2252 else if (GET_CODE (addr
) == PRE_DEC
)
2254 if (!REG_P (XEXP (addr
, 0)))
2255 fatal_insn ("pre-decrement address is not a register", x
);
2257 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2259 else if (GET_CODE (addr
) == POST_INC
)
2261 if (!REG_P (XEXP (addr
, 0)))
2262 fatal_insn ("post-increment address is not a register", x
);
2264 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2269 output_address (XEXP (x
, 0));
2275 /* We handle SFmode constants here as output_addr_const doesn't. */
2276 if (GET_MODE (x
) == SFmode
)
2281 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
2282 REAL_VALUE_TO_TARGET_SINGLE (d
, l
);
2283 fprintf (file
, "0x%08lx", l
);
2287 /* Fall through. Let output_addr_const deal with it. */
2290 output_addr_const (file
, x
);
2295 /* Print a memory address as an operand to reference that memory location. */
2298 m32r_print_operand_address (FILE * file
, rtx addr
)
2304 switch (GET_CODE (addr
))
2307 fputs (reg_names
[REGNO (addr
)], file
);
2311 if (CONST_INT_P (XEXP (addr
, 0)))
2312 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2313 else if (CONST_INT_P (XEXP (addr
, 1)))
2314 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2316 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2319 /* Print the offset first (if present) to conform to the manual. */
2323 fprintf (file
, "%d,", offset
);
2324 fputs (reg_names
[REGNO (base
)], file
);
2326 /* The chip doesn't support this, but left in for generality. */
2327 else if (REG_P (index
))
2328 fprintf (file
, "%s,%s",
2329 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2330 /* Not sure this can happen, but leave in for now. */
2331 else if (GET_CODE (index
) == SYMBOL_REF
)
2333 output_addr_const (file
, index
);
2335 fputs (reg_names
[REGNO (base
)], file
);
2338 fatal_insn ("bad address", addr
);
2340 else if (GET_CODE (base
) == LO_SUM
)
2342 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2343 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2344 fputs ("sda(", file
);
2346 fputs ("low(", file
);
2347 output_addr_const (file
, plus_constant (Pmode
, XEXP (base
, 1),
2350 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2353 fatal_insn ("bad address", addr
);
2357 if (!REG_P (XEXP (addr
, 0)))
2358 fatal_insn ("lo_sum not of register", addr
);
2359 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2360 fputs ("sda(", file
);
2362 fputs ("low(", file
);
2363 output_addr_const (file
, XEXP (addr
, 1));
2365 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2368 case PRE_INC
: /* Assume SImode. */
2369 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2372 case PRE_DEC
: /* Assume SImode. */
2373 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2376 case POST_INC
: /* Assume SImode. */
2377 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2381 output_addr_const (file
, addr
);
2387 m32r_print_operand_punct_valid_p (unsigned char code
)
2389 return m32r_punct_chars
[code
];
2392 /* Return true if the operands are the constants 0 and 1. */
2395 zero_and_one (rtx operand1
, rtx operand2
)
2398 CONST_INT_P (operand1
)
2399 && CONST_INT_P (operand2
)
2400 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2401 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2404 /* Generate the correct assembler code to handle the conditional loading of a
2405 value into a register. It is known that the operands satisfy the
2406 conditional_move_operand() function above. The destination is operand[0].
2407 The condition is operand [1]. The 'true' value is operand [2] and the
2408 'false' value is operand [3]. */
2411 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2413 static char buffer
[100];
2414 const char * dest
= reg_names
[REGNO (operands
[0])];
2418 /* Destination must be a register. */
2419 gcc_assert (REG_P (operands
[0]));
2420 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2421 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2423 /* Check to see if the test is reversed. */
2424 if (GET_CODE (operands
[1]) == NE
)
2426 rtx tmp
= operands
[2];
2427 operands
[2] = operands
[3];
2431 sprintf (buffer
, "mvfc %s, cbr", dest
);
2433 /* If the true value was '0' then we need to invert the results of the move. */
2434 if (INTVAL (operands
[2]) == 0)
2435 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2441 /* Returns true if the registers contained in the two
2442 rtl expressions are different. */
2445 m32r_not_same_reg (rtx a
, rtx b
)
2450 while (GET_CODE (a
) == SUBREG
)
2456 while (GET_CODE (b
) == SUBREG
)
2462 return reg_a
!= reg_b
;
2467 m32r_function_symbol (const char *name
)
2469 int extra_flags
= 0;
2470 enum m32r_model model
;
2471 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2473 if (TARGET_MODEL_SMALL
)
2474 model
= M32R_MODEL_SMALL
;
2475 else if (TARGET_MODEL_MEDIUM
)
2476 model
= M32R_MODEL_MEDIUM
;
2477 else if (TARGET_MODEL_LARGE
)
2478 model
= M32R_MODEL_LARGE
;
2480 gcc_unreachable (); /* Shouldn't happen. */
2481 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2484 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2489 /* Use a library function to move some bytes. */
2492 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2494 /* We want to pass the size as Pmode, which will normally be SImode
2495 but will be DImode if we are using 64-bit longs and pointers. */
2496 if (GET_MODE (bytes_rtx
) != VOIDmode
2497 && GET_MODE (bytes_rtx
) != Pmode
)
2498 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2500 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2501 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2502 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2503 TYPE_UNSIGNED (sizetype
)),
2504 TYPE_MODE (sizetype
));
2507 /* Expand string/block move operations.
2509 operands[0] is the pointer to the destination.
2510 operands[1] is the pointer to the source.
2511 operands[2] is the number of bytes to move.
2512 operands[3] is the alignment.
2514 Returns 1 upon success, 0 otherwise. */
2517 m32r_expand_block_move (rtx operands
[])
2519 rtx orig_dst
= operands
[0];
2520 rtx orig_src
= operands
[1];
2521 rtx bytes_rtx
= operands
[2];
2522 rtx align_rtx
= operands
[3];
2523 int constp
= CONST_INT_P (bytes_rtx
);
2524 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2525 int align
= INTVAL (align_rtx
);
2530 if (constp
&& bytes
<= 0)
2533 /* Move the address into scratch registers. */
2534 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2535 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2537 if (align
> UNITS_PER_WORD
)
2538 align
= UNITS_PER_WORD
;
2540 /* If we prefer size over speed, always use a function call.
2541 If we do not know the size, use a function call.
2542 If the blocks are not word aligned, use a function call. */
2543 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2545 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2549 leftover
= bytes
% MAX_MOVE_BYTES
;
2552 /* If necessary, generate a loop to handle the bulk of the copy. */
2555 rtx_code_label
*label
= NULL
;
2556 rtx final_src
= NULL_RTX
;
2557 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2558 rtx rounded_total
= GEN_INT (bytes
);
2559 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2560 rtx new_src_reg
= gen_reg_rtx (SImode
);
2562 /* If we are going to have to perform this loop more than
2563 once, then generate a label and compute the address the
2564 source register will contain upon completion of the final
2566 if (bytes
> MAX_MOVE_BYTES
)
2568 final_src
= gen_reg_rtx (Pmode
);
2571 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2574 emit_insn (gen_movsi (final_src
, rounded_total
));
2575 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2578 label
= gen_label_rtx ();
2582 /* It is known that output_block_move() will update src_reg to point
2583 to the word after the end of the source block, and dst_reg to point
2584 to the last word of the destination block, provided that the block
2585 is MAX_MOVE_BYTES long. */
2586 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2587 new_dst_reg
, new_src_reg
));
2588 emit_move_insn (dst_reg
, new_dst_reg
);
2589 emit_move_insn (src_reg
, new_src_reg
);
2590 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2592 if (bytes
> MAX_MOVE_BYTES
)
2594 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2595 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2600 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2601 gen_reg_rtx (SImode
),
2602 gen_reg_rtx (SImode
)));
2607 /* Emit load/stores for a small constant word aligned block_move.
2609 operands[0] is the memory address of the destination.
2610 operands[1] is the memory address of the source.
2611 operands[2] is the number of bytes to move.
2612 operands[3] is a temp register.
2613 operands[4] is a temp register. */
2616 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2618 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2622 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2624 /* We do not have a post-increment store available, so the first set of
2625 stores are done without any increment, then the remaining ones can use
2626 the pre-increment addressing mode.
2628 Note: expand_block_move() also relies upon this behavior when building
2629 loops to copy large blocks. */
2638 output_asm_insn ("ld\t%5, %p1", operands
);
2639 output_asm_insn ("ld\t%6, %p1", operands
);
2640 output_asm_insn ("st\t%5, @%0", operands
);
2641 output_asm_insn ("st\t%6, %s0", operands
);
2645 output_asm_insn ("ld\t%5, %p1", operands
);
2646 output_asm_insn ("ld\t%6, %p1", operands
);
2647 output_asm_insn ("st\t%5, %s0", operands
);
2648 output_asm_insn ("st\t%6, %s0", operands
);
2653 else if (bytes
>= 4)
2658 output_asm_insn ("ld\t%5, %p1", operands
);
2661 output_asm_insn ("ld\t%6, %p1", operands
);
2664 output_asm_insn ("st\t%5, @%0", operands
);
2666 output_asm_insn ("st\t%5, %s0", operands
);
2672 /* Get the entire next word, even though we do not want all of it.
2673 The saves us from doing several smaller loads, and we assume that
2674 we cannot cause a page fault when at least part of the word is in
2675 valid memory [since we don't get called if things aren't properly
2677 int dst_offset
= first_time
? 0 : 4;
2678 /* The amount of increment we have to make to the
2679 destination pointer. */
2680 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2681 /* The same for the source pointer. */
2682 int src_inc_amount
= bytes
;
2686 /* If got_extra is true then we have already loaded
2687 the next word as part of loading and storing the previous word. */
2689 output_asm_insn ("ld\t%6, @%1", operands
);
2695 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2696 my_operands
[0] = operands
[5];
2697 my_operands
[1] = GEN_INT (dst_offset
);
2698 my_operands
[2] = operands
[0];
2699 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2701 /* If there is a byte left to store then increment the
2702 destination address and shift the contents of the source
2703 register down by 8 bits. We could not do the address
2704 increment in the store half word instruction, because it does
2705 not have an auto increment mode. */
2706 if (bytes
> 0) /* assert (bytes == 1) */
2717 my_operands
[0] = operands
[6];
2718 my_operands
[1] = GEN_INT (last_shift
);
2719 output_asm_insn ("srai\t%0, #%1", my_operands
);
2720 my_operands
[0] = operands
[6];
2721 my_operands
[1] = GEN_INT (dst_offset
);
2722 my_operands
[2] = operands
[0];
2723 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2726 /* Update the destination pointer if needed. We have to do
2727 this so that the patterns matches what we output in this
2730 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2732 my_operands
[0] = operands
[0];
2733 my_operands
[1] = GEN_INT (dst_inc_amount
);
2734 output_asm_insn ("addi\t%0, #%1", my_operands
);
2737 /* Update the source pointer if needed. We have to do this
2738 so that the patterns matches what we output in this
2741 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2743 my_operands
[0] = operands
[1];
2744 my_operands
[1] = GEN_INT (src_inc_amount
);
2745 output_asm_insn ("addi\t%0, #%1", my_operands
);
2755 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2758 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2759 unsigned int new_reg
)
2761 /* Interrupt routines can't clobber any register that isn't already used. */
2762 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2763 && !df_regs_ever_live_p (new_reg
))
2770 m32r_return_addr (int count
)
2775 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2779 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2781 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2782 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2783 0x017e8e17 : 0x178e7e01, SImode
));
2784 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2785 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2786 0x0c00ae86 : 0x86ae000c, SImode
));
2787 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2788 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2789 0xe627871e : 0x1e8727e6, SImode
));
2790 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2791 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2792 0xc616c626 : 0x26c61fc6, SImode
));
2793 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2795 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2796 XEXP (DECL_RTL (fndecl
), 0));
2798 if (m32r_cache_flush_trap
>= 0)
2799 emit_insn (gen_flush_icache
2800 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2801 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2802 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2803 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2804 LCT_NORMAL
, VOIDmode
, 3, XEXP (m_tramp
, 0), Pmode
,
2805 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2806 GEN_INT (3), SImode
);
2809 /* True if X is a reg that can be used as a base reg. */
2812 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2819 if (GPR_P (REGNO (x
)))
2824 if (GPR_P (REGNO (x
))
2825 || REGNO (x
) == ARG_POINTER_REGNUM
2826 || ! HARD_REGISTER_P (x
))
2834 m32r_rtx_ok_for_offset_p (const_rtx x
)
2836 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2840 m32r_legitimate_offset_addres_p (machine_mode mode ATTRIBUTE_UNUSED
,
2841 const_rtx x
, bool strict
)
2843 if (GET_CODE (x
) == PLUS
2844 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2845 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2851 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2852 since more than one instruction will be required. */
2855 m32r_legitimate_lo_sum_addres_p (machine_mode mode
, const_rtx x
,
2858 if (GET_CODE (x
) == LO_SUM
2859 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2860 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2861 && CONSTANT_P (XEXP (x
, 1)))
2867 /* Is this a load and increment operation. */
2870 m32r_load_postinc_p (machine_mode mode
, const_rtx x
, bool strict
)
2872 if ((mode
== SImode
|| mode
== SFmode
)
2873 && GET_CODE (x
) == POST_INC
2874 && REG_P (XEXP (x
, 0))
2875 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2881 /* Is this an increment/decrement and store operation. */
2884 m32r_store_preinc_predec_p (machine_mode mode
, const_rtx x
, bool strict
)
2886 if ((mode
== SImode
|| mode
== SFmode
)
2887 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2888 && REG_P (XEXP (x
, 0)) \
2889 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2895 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2898 m32r_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2900 if (m32r_rtx_ok_for_base_p (x
, strict
)
2901 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2902 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2903 || m32r_load_postinc_p (mode
, x
, strict
)
2904 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2911 m32r_conditional_register_usage (void)
2915 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2916 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2920 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2922 We don't allow (plus symbol large-constant) as the relocations can't
2923 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2924 We allow all CONST_DOUBLE's as the md file patterns will force the
2925 constant to memory if they can't handle them. */
2928 m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2930 return !(GET_CODE (x
) == CONST
2931 && GET_CODE (XEXP (x
, 0)) == PLUS
2932 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2933 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
2934 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
2935 && UINTVAL (XEXP (XEXP (x
, 0), 1)) > 32767);