1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
28 #undef WCHAR_TYPE_SIZE
39 /* M32R/X overrides. */
41 /* Additional flags for the preprocessor. */
42 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \
43 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \
44 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \
47 /* Assembler switches. */
48 #define ASM_CPU_SPEC \
49 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
51 /* Use m32rx specific crt0/crtinit/crtfini files. */
52 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
53 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
55 /* Define this macro as a C expression for the initializer of an array of
56 strings to tell the driver program which options are defaults for this
57 target and thus do not need to be handled specially when using
58 `MULTILIB_OPTIONS'. */
59 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
61 /* Number of additional registers the subtarget defines. */
62 #define SUBTARGET_NUM_REGISTERS 1
64 /* 1 for registers that cannot be allocated. */
65 #define SUBTARGET_FIXED_REGISTERS , 1
67 /* 1 for registers that are not available across function calls. */
68 #define SUBTARGET_CALL_USED_REGISTERS , 1
70 /* Order to allocate model specific registers. */
71 #define SUBTARGET_REG_ALLOC_ORDER , 19
73 /* Registers which are accumulators. */
74 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
76 /* All registers added. */
77 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
79 /* Additional accumulator registers. */
80 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
82 /* Define additional register names. */
83 #define SUBTARGET_REGISTER_NAMES , "a1"
84 /* end M32R/X overrides. */
86 /* Names to predefine in the preprocessor for this target machine. */
87 /* __M32R__ is defined by the existing compiler so we use that. */
88 #define TARGET_CPU_CPP_BUILTINS() \
91 builtin_define ("__M32R__"); \
92 builtin_define ("__m32r__"); \
93 builtin_assert ("cpu=m32r"); \
94 builtin_assert ("machine=m32r"); \
95 builtin_define (TARGET_BIG_ENDIAN \
96 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \
100 /* This macro defines names of additional specifications to put in the specs
101 that can be used in various specifications like CC1_SPEC. Its definition
102 is an initializer with a subgrouping for each command option.
104 Each subgrouping contains a string constant, that defines the
105 specification name, and a string constant that used by the GCC driver
108 Do not define this macro if it does not need to do anything. */
110 #ifndef SUBTARGET_EXTRA_SPECS
111 #define SUBTARGET_EXTRA_SPECS
115 #define ASM_CPU_SPEC ""
119 #define CPP_CPU_SPEC ""
123 #define CC1_CPU_SPEC ""
126 #ifndef LINK_CPU_SPEC
127 #define LINK_CPU_SPEC ""
130 #ifndef STARTFILE_CPU_SPEC
131 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
134 #ifndef ENDFILE_CPU_SPEC
135 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
139 #if 0 /* Not supported yet. */
140 #define RELAX_SPEC "%{mrelax:-relax}"
142 #define RELAX_SPEC ""
146 #define EXTRA_SPECS \
147 { "asm_cpu", ASM_CPU_SPEC }, \
148 { "cpp_cpu", CPP_CPU_SPEC }, \
149 { "cc1_cpu", CC1_CPU_SPEC }, \
150 { "link_cpu", LINK_CPU_SPEC }, \
151 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
152 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
153 { "relax", RELAX_SPEC }, \
154 SUBTARGET_EXTRA_SPECS
156 #define CPP_SPEC "%(cpp_cpu)"
159 #define CC1_SPEC "%{G*} %(cc1_cpu)"
161 /* Options to pass on to the assembler. */
163 #define ASM_SPEC "%(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}"
165 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
167 #undef STARTFILE_SPEC
168 #define STARTFILE_SPEC "%(startfile_cpu)"
171 #define ENDFILE_SPEC "%(endfile_cpu)"
175 /* Run-time compilation parameters selecting different hardware subsets. */
177 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2)
179 #ifndef TARGET_LITTLE_ENDIAN
180 #define TARGET_LITTLE_ENDIAN 0
182 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN)
184 /* This defaults us to m32r. */
185 #ifndef TARGET_CPU_DEFAULT
186 #define TARGET_CPU_DEFAULT 0
190 #include "config/m32r/m32r-opts.h"
193 /* Define this macro as a C expression for the initializer of an array of
194 strings to tell the driver program which options are defaults for this
195 target and thus do not need to be handled specially when using
196 `MULTILIB_OPTIONS'. */
197 #ifndef SUBTARGET_MULTILIB_DEFAULTS
198 #define SUBTARGET_MULTILIB_DEFAULTS
201 #ifndef MULTILIB_DEFAULTS
202 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
205 #ifndef SUBTARGET_OVERRIDE_OPTIONS
206 #define SUBTARGET_OVERRIDE_OPTIONS
209 /* Target machine storage layout. */
211 /* Define this if most significant bit is lowest numbered
212 in instructions that operate on numbered bit-fields. */
213 #define BITS_BIG_ENDIAN 1
215 /* Define this if most significant byte of a word is the lowest numbered. */
216 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
218 /* Define this if most significant word of a multiword number is the lowest
220 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
222 /* Width of a word, in units (bytes). */
223 #define UNITS_PER_WORD 4
225 /* Define this macro if it is advisable to hold scalars in registers
226 in a wider mode than that declared by the program. In such cases,
227 the value is constrained to be within the bounds of the declared
228 type, but kept valid in the wider mode. The signedness of the
229 extension may differ from that of the type. */
230 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
231 if (GET_MODE_CLASS (MODE) == MODE_INT \
232 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
237 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
238 #define PARM_BOUNDARY 32
240 /* Boundary (in *bits*) on which stack pointer should be aligned. */
241 #define STACK_BOUNDARY 32
243 /* ALIGN FRAMES on word boundaries */
244 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3)
246 /* Allocation boundary (in *bits*) for the code of a function. */
247 #define FUNCTION_BOUNDARY 32
249 /* Alignment of field after `int : 0' in a structure. */
250 #define EMPTY_FIELD_BOUNDARY 32
252 /* Every structure's size must be a multiple of this. */
253 #define STRUCTURE_SIZE_BOUNDARY 8
255 /* A bit-field declared as `int' forces `int' alignment for the struct. */
256 #define PCC_BITFIELD_TYPE_MATTERS 1
258 /* No data type wants to be aligned rounder than this. */
259 #define BIGGEST_ALIGNMENT 32
261 /* The best alignment to use in cases where we have a choice. */
262 #define FASTEST_ALIGNMENT 32
264 /* Make strings word-aligned so strcpy from constants will be faster. */
265 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
266 ((TREE_CODE (EXP) == STRING_CST \
267 && (ALIGN) < FASTEST_ALIGNMENT) \
268 ? FASTEST_ALIGNMENT : (ALIGN))
270 /* Make arrays of chars word-aligned for the same reasons. */
271 #define DATA_ALIGNMENT(TYPE, ALIGN) \
272 (TREE_CODE (TYPE) == ARRAY_TYPE \
273 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
274 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
276 /* Set this nonzero if move instructions will actually fail to work
277 when given unaligned data. */
278 #define STRICT_ALIGNMENT 1
280 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */
281 #define LABEL_ALIGN(insn) 2
283 /* Layout of source language data types. */
285 #define SHORT_TYPE_SIZE 16
286 #define INT_TYPE_SIZE 32
287 #define LONG_TYPE_SIZE 32
288 #define LONG_LONG_TYPE_SIZE 64
289 #define FLOAT_TYPE_SIZE 32
290 #define DOUBLE_TYPE_SIZE 64
291 #define LONG_DOUBLE_TYPE_SIZE 64
293 /* Define this as 1 if `char' should by default be signed; else as 0. */
294 #define DEFAULT_SIGNED_CHAR 1
296 #define SIZE_TYPE "long unsigned int"
297 #define PTRDIFF_TYPE "long int"
298 #define WCHAR_TYPE "short unsigned int"
299 #define WCHAR_TYPE_SIZE 16
301 /* Standard register usage. */
303 /* Number of actual hardware registers.
304 The hardware registers are assigned numbers for the compiler
305 from 0 to just below FIRST_PSEUDO_REGISTER.
306 All registers that the compiler knows about must be given numbers,
307 even those that are not normally considered general registers. */
309 #define M32R_NUM_REGISTERS 19
311 #ifndef SUBTARGET_NUM_REGISTERS
312 #define SUBTARGET_NUM_REGISTERS 0
315 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
317 /* 1 for registers that have pervasive standard uses
318 and are not available for the register allocator.
320 0-3 - arguments/results
321 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
323 7 - call used, static chain pointer
325 12 - call saved [reserved for global pointer]
327 14 - subroutine link register
332 19 - accumulator 1 in the m32r/x
333 By default, the extension registers are not available. */
335 #ifndef SUBTARGET_FIXED_REGISTERS
336 #define SUBTARGET_FIXED_REGISTERS
339 #define FIXED_REGISTERS \
341 0, 0, 0, 0, 0, 0, 0, 0, \
342 0, 0, 0, 0, 0, 0, 0, 1, \
344 SUBTARGET_FIXED_REGISTERS \
347 /* 1 for registers not available across function calls.
348 These must include the FIXED_REGISTERS and also any
349 registers that can be used without being saved.
350 The latter must include the registers where values are returned
351 and the register where structure-value addresses are passed.
352 Aside from that, you can include as many other registers as you like. */
354 #ifndef SUBTARGET_CALL_USED_REGISTERS
355 #define SUBTARGET_CALL_USED_REGISTERS
358 #define CALL_USED_REGISTERS \
360 1, 1, 1, 1, 1, 1, 1, 1, \
361 0, 0, 0, 0, 0, 0, 1, 1, \
363 SUBTARGET_CALL_USED_REGISTERS \
366 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
368 /* If defined, an initializer for a vector of integers, containing the
369 numbers of hard registers in the order in which GCC should
370 prefer to use them (from most preferred to least). */
372 #ifndef SUBTARGET_REG_ALLOC_ORDER
373 #define SUBTARGET_REG_ALLOC_ORDER
376 #if 1 /* Better for int code. */
377 #define REG_ALLOC_ORDER \
379 4, 5, 6, 7, 2, 3, 8, 9, 10, \
380 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
381 SUBTARGET_REG_ALLOC_ORDER \
384 #else /* Better for fp code at expense of int code. */
385 #define REG_ALLOC_ORDER \
387 0, 1, 2, 3, 4, 5, 6, 7, 8, \
388 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
389 SUBTARGET_REG_ALLOC_ORDER \
393 /* Return number of consecutive hard regs needed starting at reg REGNO
394 to hold something of mode MODE.
395 This is ordinarily the length in words of a value of mode MODE
396 but can be less for certain modes in special long registers. */
397 #define HARD_REGNO_NREGS(REGNO, MODE) \
398 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
400 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
401 extern const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
402 extern unsigned int m32r_mode_class
[];
403 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
404 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
406 /* A C expression that is nonzero if it is desirable to choose
407 register allocation so as to avoid move instructions between a
408 value of mode MODE1 and a value of mode MODE2.
410 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
411 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
412 MODE2)' must be zero. */
414 /* Tie QI/HI/SI modes together. */
415 #define MODES_TIEABLE_P(MODE1, MODE2) \
416 ( GET_MODE_CLASS (MODE1) == MODE_INT \
417 && GET_MODE_CLASS (MODE2) == MODE_INT \
418 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
419 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
421 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
422 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
424 /* Register classes and constants. */
426 /* Define the classes of registers for register constraints in the
427 machine description. Also define ranges of constants.
429 One of the classes must always be named ALL_REGS and include all hard regs.
430 If there is more than one class, another class must be named NO_REGS
431 and contain no registers.
433 The name GENERAL_REGS must be the name of a class (or an alias for
434 another name such as ALL_REGS). This is the class of registers
435 that is allowed by "g" or "r" in a register constraint.
436 Also, registers outside this class are allocated only when
437 instructions express preferences for them.
439 The classes must be numbered in nondecreasing order; that is,
440 a larger-numbered class must never be contained completely
441 in a smaller-numbered class.
443 For any two classes, it is very desirable that there be another
444 class that represents their union.
446 It is important that any condition codes have class NO_REGS.
447 See `register_operand'. */
451 NO_REGS
, CARRY_REG
, ACCUM_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
454 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
456 /* Give names of register classes as strings for dump file. */
457 #define REG_CLASS_NAMES \
458 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
460 /* Define which registers fit in which classes.
461 This is an initializer for a vector of HARD_REG_SET
462 of length N_REG_CLASSES. */
464 #ifndef SUBTARGET_REG_CLASS_CARRY
465 #define SUBTARGET_REG_CLASS_CARRY 0
468 #ifndef SUBTARGET_REG_CLASS_ACCUM
469 #define SUBTARGET_REG_CLASS_ACCUM 0
472 #ifndef SUBTARGET_REG_CLASS_GENERAL
473 #define SUBTARGET_REG_CLASS_GENERAL 0
476 #ifndef SUBTARGET_REG_CLASS_ALL
477 #define SUBTARGET_REG_CLASS_ALL 0
480 #define REG_CLASS_CONTENTS \
483 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
484 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
485 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
486 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
489 /* The same information, inverted:
490 Return the class number of the smallest class containing
491 reg number REGNO. This could be a conditional expression
492 or could index an array. */
493 extern enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
494 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
496 /* The class value for index registers, and the one for base regs. */
497 #define INDEX_REG_CLASS GENERAL_REGS
498 #define BASE_REG_CLASS GENERAL_REGS
500 /* These assume that REGNO is a hard or pseudo reg number.
501 They give nonzero only if REGNO is a hard reg of the suitable class
502 or a pseudo reg currently allocated to a suitable hard reg.
503 Since they use reg_renumber, they are safe only once reg_renumber
504 has been allocated, which happens in local-alloc.c. */
505 #define REGNO_OK_FOR_BASE_P(REGNO) \
506 ((REGNO) < FIRST_PSEUDO_REGISTER \
507 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
508 : GPR_P (reg_renumber[REGNO]))
510 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
512 /* Return the maximum number of consecutive registers
513 needed to represent mode MODE in a register of class CLASS. */
514 #define CLASS_MAX_NREGS(CLASS, MODE) \
515 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
517 /* Return true if a value is inside a range. */
518 #define IN_RANGE_P(VALUE, LOW, HIGH) \
519 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
520 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
522 /* Some range macros. */
523 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff)
524 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000)
525 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
526 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
528 /* Stack layout and stack pointer usage. */
530 /* Define this macro if pushing a word onto the stack moves the stack
531 pointer to a smaller address. */
532 #define STACK_GROWS_DOWNWARD
534 /* Offset from frame pointer to start allocating local variables at.
535 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
536 first local allocated. Otherwise, it is the offset to the BEGINNING
537 of the first local allocated. */
538 /* The frame pointer points at the same place as the stack pointer, except if
539 alloca has been called. */
540 #define STARTING_FRAME_OFFSET \
541 M32R_STACK_ALIGN (crtl->outgoing_args_size)
543 /* Offset from the stack pointer register to the first location at which
544 outgoing arguments are placed. */
545 #define STACK_POINTER_OFFSET 0
547 /* Offset of first parameter from the argument pointer register value. */
548 #define FIRST_PARM_OFFSET(FNDECL) 0
550 /* Register to use for pushing function arguments. */
551 #define STACK_POINTER_REGNUM 15
553 /* Base register for access to local variables of the function. */
554 #define FRAME_POINTER_REGNUM 13
556 /* Base register for access to arguments of the function. */
557 #define ARG_POINTER_REGNUM 16
559 /* Register in which static-chain is passed to a function.
560 This must not be a register used by the prologue. */
561 #define STATIC_CHAIN_REGNUM 7
563 /* These aren't official macros. */
564 #define PROLOGUE_TMP_REGNUM 4
565 #define RETURN_ADDR_REGNUM 14
566 /* #define GP_REGNUM 12 */
567 #define CARRY_REGNUM 17
568 #define ACCUM_REGNUM 18
569 #define M32R_MAX_INT_REGS 16
571 #ifndef SUBTARGET_GPR_P
572 #define SUBTARGET_GPR_P(REGNO) 0
575 #ifndef SUBTARGET_ACCUM_P
576 #define SUBTARGET_ACCUM_P(REGNO) 0
579 #ifndef SUBTARGET_CARRY_P
580 #define SUBTARGET_CARRY_P(REGNO) 0
583 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
584 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
585 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
587 /* Eliminating the frame and arg pointers. */
590 /* C statement to store the difference between the frame pointer
591 and the stack pointer values immediately after the function prologue.
592 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
593 need not be defined. */
594 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
595 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
598 /* If defined, this macro specifies a table of register pairs used to
599 eliminate unneeded registers that point into the stack frame. If
600 it is not defined, the only elimination attempted by the compiler
601 is to replace references to the frame pointer with references to
604 Note that the elimination of the argument pointer with the stack
605 pointer is specified first since that is the preferred elimination. */
607 #define ELIMINABLE_REGS \
608 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
609 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
610 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
612 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
613 specifies the initial difference between the specified pair of
614 registers. This macro must be defined if `ELIMINABLE_REGS' is
617 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
620 int size = m32r_compute_frame_size (get_frame_size ()); \
622 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
624 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
625 (OFFSET) = size - crtl->args.pretend_args_size; \
626 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
627 (OFFSET) = size - crtl->args.pretend_args_size; \
629 gcc_unreachable (); \
633 /* Function argument passing. */
635 /* If defined, the maximum amount of space required for outgoing
636 arguments will be computed and placed into the variable
637 `crtl->outgoing_args_size'. No space will be pushed
638 onto the stack for each call; instead, the function prologue should
639 increase the stack frame size by this amount. */
640 #define ACCUMULATE_OUTGOING_ARGS 1
642 /* Define a data type for recording info about an argument list
643 during the scan of that argument list. This data type should
644 hold all necessary information about the function itself
645 and about the args processed so far, enough to enable macros
646 such as FUNCTION_ARG to determine where the next arg should go. */
647 #define CUMULATIVE_ARGS int
649 /* Initialize a variable CUM of type CUMULATIVE_ARGS
650 for a call to a function whose data type is FNTYPE.
651 For a library call, FNTYPE is 0. */
652 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
655 /* The number of registers used for parameter passing. Local to this file. */
656 #define M32R_MAX_PARM_REGS 4
658 /* 1 if N is a possible register number for function argument passing. */
659 #define FUNCTION_ARG_REGNO_P(N) \
660 ((unsigned) (N) < M32R_MAX_PARM_REGS)
663 /* Function results. */
665 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
666 #define DEFAULT_PCC_STRUCT_RETURN 0
668 /* Function entry and exit. */
670 /* Initialize data used by insn expanders. This is called from
671 init_emit, once for each function, before code is generated. */
672 #define INIT_EXPANDERS m32r_init_expanders ()
674 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
675 the stack pointer does not matter. The value is tested only in
676 functions that have frame pointers.
677 No definition is equivalent to always zero. */
678 #define EXIT_IGNORE_STACK 1
680 /* Output assembler code to FILE to increment profiler label # LABELNO
681 for profiling a function entry. */
682 #undef FUNCTION_PROFILER
683 #define FUNCTION_PROFILER(FILE, LABELNO) \
688 fprintf (FILE, "\tld24 r14,#mcount\n"); \
689 fprintf (FILE, "\tadd r14,r12\n"); \
690 fprintf (FILE, "\tld r14,@r14\n"); \
691 fprintf (FILE, "\tjl r14\n"); \
696 fprintf (FILE, "\tbl mcount\n"); \
699 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \
700 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \
701 fprintf (FILE, "\tjl r14\n"); \
704 fprintf (FILE, "\taddi sp,#4\n"); \
710 /* On the M32R, the trampoline is:
712 mv r7, lr -> bl L1 ; 178e 7e01
713 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12)
714 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6
715 ld r6, @r6 -> jmp r6 ; 26c6 1fc6
719 #ifndef CACHE_FLUSH_FUNC
720 #define CACHE_FLUSH_FUNC "_flush_cache"
722 #ifndef CACHE_FLUSH_TRAP
723 #define CACHE_FLUSH_TRAP 12
726 /* Length in bytes of the trampoline for entering a nested function. */
727 #define TRAMPOLINE_SIZE 24
730 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT)
732 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
734 /* Addressing modes, and classification of registers for them. */
736 /* Maximum number of registers that can appear in a valid memory address. */
737 #define MAX_REGS_PER_ADDRESS 1
739 /* We have post-inc load and pre-dec,pre-inc store,
740 but only for 4 byte vals. */
741 #define HAVE_PRE_DECREMENT 1
742 #define HAVE_PRE_INCREMENT 1
743 #define HAVE_POST_INCREMENT 1
745 /* Recognize any constant value that is a valid address. */
746 #define CONSTANT_ADDRESS_P(X) \
747 ( GET_CODE (X) == LABEL_REF \
748 || GET_CODE (X) == SYMBOL_REF \
750 || (GET_CODE (X) == CONST \
751 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
753 /* Condition code usage. */
755 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
756 floating point inequality comparison. */
757 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
761 /* The cost of a branch insn. */
762 /* A value of 2 here causes GCC to avoid using branches in comparisons like
763 while (a < N && a). Branches aren't that expensive on the M32R so
764 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
765 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1)
767 /* Nonzero if access to memory by bytes is slow and undesirable.
768 For RISC chips, it means that access to memory by bytes is no
769 better than access by words when possible, so grab a whole word
770 and maybe make use of that. */
771 #define SLOW_BYTE_ACCESS 1
773 /* Define this macro if it is as good or better to call a constant
774 function address than to call an address kept in a register. */
775 #define NO_FUNCTION_CSE
777 /* Section selection. */
779 #define TEXT_SECTION_ASM_OP "\t.section .text"
780 #define DATA_SECTION_ASM_OP "\t.section .data"
781 #define BSS_SECTION_ASM_OP "\t.section .bss"
783 /* Define this macro if jump tables (for tablejump insns) should be
784 output in the text section, along with the assembler instructions.
785 Otherwise, the readonly data section is used.
786 This macro is irrelevant if there is no separate readonly data section. */
787 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
789 /* Position Independent Code. */
791 /* The register number of the register used to address a table of static
792 data addresses in memory. In some cases this register is defined by a
793 processor's ``application binary interface'' (ABI). When this macro
794 is defined, RTL is generated for this register once, as with the stack
795 pointer and frame pointer registers. If this macro is not defined, it
796 is up to the machine-dependent files to allocate such a register (if
798 #define PIC_OFFSET_TABLE_REGNUM 12
800 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
801 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
803 /* This register is call-saved on the M32R. */
804 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
806 /* A C expression that is nonzero if X is a legitimate immediate
807 operand on the target machine when generating position independent code.
808 You can assume that X satisfies CONSTANT_P, so you need not
809 check this. You can also assume `flag_pic' is true, so you need not
810 check it either. You need not define this macro if all constants
811 (including SYMBOL_REF) can be immediate operands when generating
812 position independent code. */
813 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X)
815 /* Control the assembler format that we output. */
817 /* A C string constant describing how to begin a comment in the target
818 assembler language. The compiler assumes that the comment will
819 end at the end of the line. */
820 #define ASM_COMMENT_START ";"
822 /* Output to assembler file text saying following lines
823 may contain character constants, extra white space, comments, etc. */
824 #define ASM_APP_ON ""
826 /* Output to assembler file text saying following lines
827 no longer contain unusual constructs. */
828 #define ASM_APP_OFF ""
830 /* Globalizing directive for a label. */
831 #define GLOBAL_ASM_OP "\t.global\t"
833 /* We do not use DBX_LINES_FUNCTION_RELATIVE or
834 dbxout_stab_value_internal_label_diff here because
835 we need to use .debugsym for the line label. */
837 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \
840 const char * begin_label = \
841 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \
843 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \
845 dbxout_begin_stabn_sline (line); \
846 assemble_name (file, label); \
848 assemble_name (file, begin_label); \
849 fputs ("\n\t.debugsym ", file); \
850 assemble_name (file, label); \
856 /* How to refer to registers in assembler output.
857 This sequence is indexed by compiler's hard-register-number (see above). */
858 #ifndef SUBTARGET_REGISTER_NAMES
859 #define SUBTARGET_REGISTER_NAMES
862 #define REGISTER_NAMES \
864 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
865 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
867 SUBTARGET_REGISTER_NAMES \
870 /* If defined, a C initializer for an array of structures containing
871 a name and a register number. This macro defines additional names
872 for hard registers, thus allowing the `asm' option in declarations
873 to refer to registers using alternate names. */
874 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
875 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
878 #define ADDITIONAL_REGISTER_NAMES \
880 /*{ "gp", GP_REGNUM },*/ \
881 { "r13", FRAME_POINTER_REGNUM }, \
882 { "r14", RETURN_ADDR_REGNUM }, \
883 { "r15", STACK_POINTER_REGNUM }, \
884 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
887 /* If defined, C string expressions to be used for the `%R', `%L',
888 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
889 are useful when a single `md' file must support multiple assembler
890 formats. In that case, the various `tm.h' files can define these
891 macros differently. */
892 #define REGISTER_PREFIX ""
893 #define LOCAL_LABEL_PREFIX ".L"
894 #define USER_LABEL_PREFIX ""
895 #define IMMEDIATE_PREFIX "#"
897 /* This is how to output an element of a case-vector that is absolute. */
898 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
902 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
903 fprintf (FILE, "\t.word\t"); \
904 assemble_name (FILE, label); \
905 fprintf (FILE, "\n"); \
909 /* This is how to output an element of a case-vector that is relative. */
910 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
914 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
915 fprintf (FILE, "\t.word\t"); \
916 assemble_name (FILE, label); \
917 fprintf (FILE, "-"); \
918 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
919 assemble_name (FILE, label); \
920 fprintf (FILE, "\n"); \
924 /* The desired alignment for the location counter at the beginning
926 /* On the M32R, align loops to 32 byte boundaries (cache line size)
928 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
930 /* Define this to be the maximum number of insns to move around when moving
931 a loop test from the top of a loop to the bottom
932 and seeing whether to duplicate it. The default is thirty.
934 Loop unrolling currently doesn't like this optimization, so
935 disable doing if we are unrolling loops and saving space. */
936 #define LOOP_TEST_THRESHOLD (optimize_size \
937 && !flag_unroll_loops \
938 && !flag_unroll_all_loops ? 2 : 30)
940 /* This is how to output an assembler line
941 that says to advance the location counter
942 to a multiple of 2**LOG bytes. */
943 /* .balign is used to avoid confusion. */
944 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
948 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
952 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
953 separate, explicit argument. If you define this macro, it is used in
954 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
955 handling the required alignment of the variable. The alignment is
956 specified as the number of bits. */
958 #define SCOMMON_ASM_OP "\t.scomm\t"
960 #undef ASM_OUTPUT_ALIGNED_COMMON
961 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
964 if (! TARGET_SDATA_NONE \
966 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
967 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
969 fprintf ((FILE), "%s", COMMON_ASM_OP); \
970 assemble_name ((FILE), (NAME)); \
971 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
975 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
978 if (! TARGET_SDATA_NONE \
980 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \
981 switch_to_section (get_named_section (NULL, ".sbss", 0)); \
983 switch_to_section (bss_section); \
984 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \
985 last_assemble_variable_decl = DECL; \
986 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
987 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
991 /* Debugging information. */
993 /* Generate DBX and DWARF debugging information. */
994 #define DBX_DEBUGGING_INFO 1
995 #define DWARF2_DEBUGGING_INFO 1
997 /* Use DWARF2 debugging info by default. */
998 #undef PREFERRED_DEBUGGING_TYPE
999 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1001 /* Turn off splitting of long stabs. */
1002 #define DBX_CONTIN_LENGTH 0
1004 /* Miscellaneous. */
1006 /* Specify the machine mode that this machine uses
1007 for the index in the tablejump instruction. */
1008 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode)
1010 /* Define if operations between registers always perform the operation
1011 on the full register even if a narrower mode is specified. */
1012 #define WORD_REGISTER_OPERATIONS
1014 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1015 will either zero-extend or sign-extend. The value of this macro should
1016 be the code that says which one of the two operations is implicitly
1017 done, UNKNOWN if none. */
1018 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1020 /* Max number of bytes we can move from memory
1021 to memory in one reasonably fast instruction. */
1024 /* Define this to be nonzero if shift instructions ignore all but the low-order
1026 #define SHIFT_COUNT_TRUNCATED 1
1028 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1029 is done just by pretending it is already truncated. */
1030 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1032 /* Specify the machine mode that pointers have.
1033 After generation of rtl, the compiler makes no further distinction
1034 between pointers and any other objects of this machine mode. */
1035 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has
1036 its own problems (you have to add extendpsisi2 and truncsipsi2).
1038 #define Pmode SImode
1040 /* A function address in a call instruction. */
1041 #define FUNCTION_MODE SImode
1043 /* M32R function types. */
1044 enum m32r_function_type
1046 M32R_FUNCTION_UNKNOWN
, M32R_FUNCTION_NORMAL
, M32R_FUNCTION_INTERRUPT
1049 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1051 /* The maximum number of bytes to copy using pairs of load/store instructions.
1052 If a block is larger than this then a loop will be generated to copy
1053 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice.
1054 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
1055 string copy in it. */
1056 #define MAX_MOVE_BYTES 32