1 ;; Machine description of the Renesas M32R cpu for GNU C compiler
2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2001, 2003, 2004, 2005,
3 ; 2007, 2008, 2009, 2011 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; UNSPEC_VOLATILE usage
26 (UNSPECV_FLUSH_ICACHE 1)])
30 [(UNSPEC_LOAD_SDA_BASE 2)
32 (UNSPEC_PIC_LOAD_ADDR 4)
37 ;; Insn type. Used to default other attribute values.
39 "int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
40 (const_string "misc"))
43 (define_attr "length" ""
44 (cond [(eq_attr "type" "int2,load2,store2,shift2,mul2")
47 (eq_attr "type" "int4,load4,store4,shift4,div4")
50 (eq_attr "type" "multi")
53 (eq_attr "type" "uncond_branch,branch,call")
58 ;; The length here is the length of a single asm. Unfortunately it might be
59 ;; 2 or 4 so we must allow for 4. That's ok though.
60 (define_asm_attributes
61 [(set_attr "length" "4")
62 (set_attr "type" "multi")])
64 ;; Whether an instruction is short (16-bit) or long (32-bit).
65 (define_attr "insn_size" "short,long"
66 (if_then_else (eq_attr "type" "int2,load2,store2,shift2,mul2")
67 (const_string "short")
68 (const_string "long")))
70 ;; The target CPU we're compiling for.
71 (define_attr "cpu" "m32r,m32r2,m32rx"
72 (cond [(match_test "TARGET_M32RX")
73 (const_string "m32rx")
74 (match_test "TARGET_M32R2")
75 (const_string "m32r2")]
76 (const_string "m32r")))
78 ;; Defines the pipeline where an instruction can be executed on.
79 ;; For the M32R, a short instruction can execute one of the two pipes.
80 ;; For the M32Rx, the restrictions are modelled in the second
81 ;; condition of this attribute definition.
82 (define_attr "m32r_pipeline" "either,s,o,long"
83 (cond [(and (eq_attr "cpu" "m32r")
84 (eq_attr "insn_size" "short"))
85 (const_string "either")
86 (eq_attr "insn_size" "!short")
87 (const_string "long")]
88 (cond [(eq_attr "type" "int2")
89 (const_string "either")
90 (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
92 (eq_attr "type" "mul2")
94 (const_string "long"))))
96 ;; ::::::::::::::::::::
98 ;; :: Pipeline description
100 ;; ::::::::::::::::::::
102 ;; This model is based on Chapter 2, Appendix 3 and Appendix 4 of the
103 ;; "M32R-FPU Software Manual", Revision 1.01, plus additional information
104 ;; obtained by our best friend and mine, Google.
106 ;; The pipeline is modelled as a fetch unit, and a core with a memory unit,
107 ;; two execution units, where "fetch" models IF and D, "memory" for MEM1
108 ;; and MEM2, and "EXEC" for E, E1, E2, EM, and EA. Writeback and
109 ;; bypasses are not modelled.
110 (define_automaton "m32r")
112 ;; We pretend there are two short (16 bits) instruction fetchers. The
113 ;; "s" short fetcher cannot be reserved until the "o" short fetcher is
114 ;; reserved. Some instructions reserve both the left and right fetchers.
115 ;; These fetch units are a hack to get GCC to better pack the instructions
116 ;; for the M32Rx processor, which has two execution pipes.
118 ;; In reality there is only one decoder, which can decode either two 16-bit
119 ;; instructions, or a single 32-bit instruction.
121 ;; Note, "fetch" models both the IF and the D pipeline stages.
123 ;; The m32rx core has two execution pipes. We name them o_E and s_E.
124 ;; In addition, there's a memory unit.
126 (define_cpu_unit "o_IF,s_IF,o_E,s_E,memory" "m32r")
128 ;; Prevent the s pipe from being reserved before the o pipe.
129 (absence_set "s_IF" "o_IF")
130 (absence_set "s_E" "o_E")
132 ;; On the M32Rx, long instructions execute on both pipes, so reserve
133 ;; both fetch slots and both pipes.
134 (define_reservation "long_IF" "o_IF+s_IF")
135 (define_reservation "long_E" "o_E+s_E")
137 ;; ::::::::::::::::::::
139 ;; Simple instructions do 4 stages: IF D E WB. WB is not modelled.
140 ;; Hence, ready latency is 1.
141 (define_insn_reservation "short_left" 1
142 (and (eq_attr "m32r_pipeline" "o")
143 (and (eq_attr "insn_size" "short")
144 (eq_attr "type" "!load2")))
147 (define_insn_reservation "short_right" 1
148 (and (eq_attr "m32r_pipeline" "s")
149 (and (eq_attr "insn_size" "short")
150 (eq_attr "type" "!load2")))
153 (define_insn_reservation "short_either" 1
154 (and (eq_attr "m32r_pipeline" "either")
155 (and (eq_attr "insn_size" "short")
156 (eq_attr "type" "!load2")))
159 (define_insn_reservation "long_m32r" 1
160 (and (eq_attr "cpu" "m32r")
161 (and (eq_attr "insn_size" "long")
162 (eq_attr "type" "!load4,load8")))
165 (define_insn_reservation "long_m32rx" 2
166 (and (eq_attr "m32r_pipeline" "long")
167 (and (eq_attr "insn_size" "long")
168 (eq_attr "type" "!load4,load8")))
171 ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB.
172 ;; MEM1 may require more than one cycle depending on locality. We
173 ;; optimistically assume all memory is nearby, i.e. MEM1 takes only
174 ;; one cycle. Hence, ready latency is 3.
176 ;; The M32Rx can do short load/store only on the left pipe.
177 (define_insn_reservation "short_load_left" 3
178 (and (eq_attr "m32r_pipeline" "o")
179 (and (eq_attr "insn_size" "short")
180 (eq_attr "type" "load2")))
183 (define_insn_reservation "short_load" 3
184 (and (eq_attr "m32r_pipeline" "either")
185 (and (eq_attr "insn_size" "short")
186 (eq_attr "type" "load2")))
187 "s_IF|o_IF,s_E|o_E,memory*2")
189 (define_insn_reservation "long_load" 3
190 (and (eq_attr "cpu" "m32r")
191 (and (eq_attr "insn_size" "long")
192 (eq_attr "type" "load4,load8")))
193 "long_IF,long_E,memory*2")
195 (define_insn_reservation "long_load_m32rx" 3
196 (and (eq_attr "m32r_pipeline" "long")
197 (eq_attr "type" "load4,load8"))
198 "long_IF,long_E,memory*2")
201 (include "predicates.md")
202 (include "constraints.md")
204 ;; Expand prologue as RTL
205 (define_expand "prologue"
210 m32r_expand_prologue ();
214 ;; Expand epilogue as RTL
215 (define_expand "epilogue"
220 m32r_expand_epilogue ();
221 emit_jump_insn (gen_return_normal ());
225 ;; Move instructions.
227 ;; For QI and HI moves, the register must contain the full properly
228 ;; sign-extended value. nonzero_bits assumes this [otherwise
229 ;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
230 ;; says it's a kludge and the .md files should be fixed instead].
232 (define_expand "movqi"
233 [(set (match_operand:QI 0 "general_operand" "")
234 (match_operand:QI 1 "general_operand" ""))]
238 /* Fixup PIC cases. */
241 if (symbolic_operand (operands[1], QImode))
243 if (reload_in_progress || reload_completed)
244 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
246 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
250 /* Everything except mem = const or mem = mem can be done easily.
251 Objects in the small data area are handled too. */
253 if (MEM_P (operands[0]))
254 operands[1] = force_reg (QImode, operands[1]);
257 (define_insn "*movqi_insn"
258 [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,r,T,m")
259 (match_operand:QI 1 "move_src_operand" "r,I,JQR,T,m,r,r"))]
260 "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
269 [(set_attr "type" "int2,int2,int4,load2,load4,store2,store4")
270 (set_attr "length" "2,2,4,2,4,2,4")])
272 (define_expand "movhi"
273 [(set (match_operand:HI 0 "general_operand" "")
274 (match_operand:HI 1 "general_operand" ""))]
278 /* Fixup PIC cases. */
281 if (symbolic_operand (operands[1], HImode))
283 if (reload_in_progress || reload_completed)
284 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
286 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
290 /* Everything except mem = const or mem = mem can be done easily. */
292 if (MEM_P (operands[0]))
293 operands[1] = force_reg (HImode, operands[1]);
296 (define_insn "*movhi_insn"
297 [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,r,T,m")
298 (match_operand:HI 1 "move_src_operand" "r,I,JQR,K,T,m,r,r"))]
299 "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
309 [(set_attr "type" "int2,int2,int4,int4,load2,load4,store2,store4")
310 (set_attr "length" "2,2,4,4,2,4,2,4")])
312 (define_expand "movsi_push"
313 [(set (mem:SI (pre_dec:SI (match_operand:SI 0 "register_operand" "")))
314 (match_operand:SI 1 "register_operand" ""))]
318 (define_expand "movsi_pop"
319 [(set (match_operand:SI 0 "register_operand" "")
320 (mem:SI (post_inc:SI (match_operand:SI 1 "register_operand" ""))))]
324 (define_expand "movsi"
325 [(set (match_operand:SI 0 "general_operand" "")
326 (match_operand:SI 1 "general_operand" ""))]
330 /* Fixup PIC cases. */
333 if (symbolic_operand (operands[1], SImode))
335 if (reload_in_progress || reload_completed)
336 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
338 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
342 /* Everything except mem = const or mem = mem can be done easily. */
344 if (MEM_P (operands[0]))
345 operands[1] = force_reg (SImode, operands[1]);
347 /* Small Data Area reference? */
348 if (small_data_operand (operands[1], SImode))
350 emit_insn (gen_movsi_sda (operands[0], operands[1]));
354 /* If medium or large code model, symbols have to be loaded with
356 if (addr32_operand (operands[1], SImode))
358 emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
363 ;; ??? Do we need a const_double constraint here for large unsigned values?
364 (define_insn "*movsi_insn"
365 [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
366 (match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
367 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
370 if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
372 switch (GET_CODE (operands[1]))
382 if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
383 && XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
389 if (satisfies_constraint_J (operands[1]))
390 return \"ldi %0,%#%1\\t; %X1\";
392 if (satisfies_constraint_M (operands[1]))
393 return \"ld24 %0,%#%1\\t; %X1\";
395 if (satisfies_constraint_L (operands[1]))
396 return \"seth %0,%#%T1\\t; %X1\";
404 return \"ld24 %0,%#%1\";
410 else if (MEM_P (operands[0])
411 && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
413 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
414 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
422 [(set_attr "type" "int2,int2,int4,int4,int4,multi,load2,load2,load4,store2,store2,store4")
423 (set_attr "length" "2,2,4,4,4,8,2,2,4,2,2,4")])
425 ; Try to use a four byte / two byte pair for constants not loadable with
429 [(set (match_operand:SI 0 "register_operand" "")
430 (match_operand:SI 1 "two_insn_const_operand" ""))]
432 [(set (match_dup 0) (match_dup 2))
433 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
436 unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
437 unsigned HOST_WIDE_INT tmp;
440 /* In all cases we will emit two instructions. However we try to
441 use 2 byte instructions wherever possible. We can assume the
442 constant isn't loadable with any of ldi, ld24, or seth. */
444 /* See if we can load a 24-bit unsigned value and invert it. */
445 if (UINT24_P (~ val))
447 emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
448 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
452 /* See if we can load a 24-bit unsigned value and shift it into place.
453 0x01fffffe is just beyond ld24's range. */
454 for (shift = 1, tmp = 0x01fffffe;
458 if ((val & ~tmp) == 0)
460 emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
461 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
466 /* Can't use any two byte insn, fall back to seth/or3. Use ~0xffff instead
467 of 0xffff0000, since the later fails on a 64-bit host. */
468 operands[2] = GEN_INT ((val) & ~0xffff);
469 operands[3] = GEN_INT ((val) & 0xffff);
473 [(set (match_operand:SI 0 "register_operand" "")
474 (match_operand:SI 1 "seth_add3_operand" ""))]
477 (high:SI (match_dup 1)))
479 (lo_sum:SI (match_dup 0)
483 ;; Small data area support.
484 ;; The address of _SDA_BASE_ is loaded into a register and all objects in
485 ;; the small data area are indexed off that. This is done for each reference
486 ;; but cse will clean things up for us. We let the compiler choose the
487 ;; register to use so we needn't allocate (and maybe even fix) a special
488 ;; register to use. Since the load and store insns have a 16-bit offset the
489 ;; total size of the data area can be 64K. However, if the data area lives
490 ;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
491 ;; would then yield 3 instructions to reference an object [though there would
492 ;; be no net loss if two or more objects were referenced]. The 3 insns can be
493 ;; reduced back to 2 if the size of the small data area were reduced to 32K
494 ;; [then seth + ld/st would work for any object in the area]. Doing this
495 ;; would require special handling of _SDA_BASE_ (its value would be
496 ;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
497 ;; [I think]. What to do about this is deferred until later and for now we
498 ;; require .sdata to be in the first 16M.
500 (define_expand "movsi_sda"
502 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
503 (set (match_operand:SI 0 "register_operand" "")
504 (lo_sum:SI (match_dup 2)
505 (match_operand:SI 1 "small_data_operand" "")))]
509 if (reload_in_progress || reload_completed)
510 operands[2] = operands[0];
512 operands[2] = gen_reg_rtx (SImode);
515 (define_insn "*load_sda_base_32"
516 [(set (match_operand:SI 0 "register_operand" "=r")
517 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
519 "seth %0,%#shigh(_SDA_BASE_)\;add3 %0,%0,%#low(_SDA_BASE_)"
520 [(set_attr "type" "multi")
521 (set_attr "length" "8")])
523 (define_insn "*load_sda_base"
524 [(set (match_operand:SI 0 "register_operand" "=r")
525 (unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
527 "ld24 %0,#_SDA_BASE_"
528 [(set_attr "type" "int4")
529 (set_attr "length" "4")])
531 ;; 32-bit address support.
533 (define_expand "movsi_addr32"
535 ; addr32_operand isn't used because it's too restrictive,
536 ; seth_add3_operand is more general and thus safer.
537 (high:SI (match_operand:SI 1 "seth_add3_operand" "")))
538 (set (match_operand:SI 0 "register_operand" "")
539 (lo_sum:SI (match_dup 2) (match_dup 1)))]
543 if (reload_in_progress || reload_completed)
544 operands[2] = operands[0];
546 operands[2] = gen_reg_rtx (SImode);
549 (define_insn "set_hi_si"
550 [(set (match_operand:SI 0 "register_operand" "=r")
551 (high:SI (match_operand 1 "symbolic_operand" "")))]
553 "seth %0,%#shigh(%1)"
554 [(set_attr "type" "int4")
555 (set_attr "length" "4")])
557 (define_insn "lo_sum_si"
558 [(set (match_operand:SI 0 "register_operand" "=r")
559 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
560 (match_operand:SI 2 "immediate_operand" "in")))]
563 [(set_attr "type" "int4")
564 (set_attr "length" "4")])
566 (define_expand "movdi"
567 [(set (match_operand:DI 0 "general_operand" "")
568 (match_operand:DI 1 "general_operand" ""))]
572 /* Fixup PIC cases. */
575 if (symbolic_operand (operands[1], DImode))
577 if (reload_in_progress || reload_completed)
578 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
580 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
584 /* Everything except mem = const or mem = mem can be done easily. */
586 if (MEM_P (operands[0]))
587 operands[1] = force_reg (DImode, operands[1]);
590 (define_insn "*movdi_insn"
591 [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,r,m")
592 (match_operand:DI 1 "move_double_src_operand" "r,nG,F,m,r"))]
593 "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
595 [(set_attr "type" "multi,multi,multi,load8,store8")
596 (set_attr "length" "4,4,16,6,6")])
599 [(set (match_operand:DI 0 "move_dest_operand" "")
600 (match_operand:DI 1 "move_double_src_operand" ""))]
603 "operands[2] = gen_split_move_double (operands);")
605 ;; Floating point move insns.
607 (define_expand "movsf"
608 [(set (match_operand:SF 0 "general_operand" "")
609 (match_operand:SF 1 "general_operand" ""))]
613 /* Fixup PIC cases. */
616 if (symbolic_operand (operands[1], SFmode))
618 if (reload_in_progress || reload_completed)
619 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
621 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
625 /* Everything except mem = const or mem = mem can be done easily. */
627 if (MEM_P (operands[0]))
628 operands[1] = force_reg (SFmode, operands[1]);
631 (define_insn "*movsf_insn"
632 [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
633 (match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
634 "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
644 ;; ??? Length of alternative 1 is either 2, 4 or 8.
645 [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
646 (set_attr "length" "2,8,2,2,4,2,2,4")])
649 [(set (match_operand:SF 0 "register_operand" "")
650 (match_operand:SF 1 "const_double_operand" ""))]
652 [(set (match_dup 2) (match_dup 3))]
655 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
656 operands[3] = operand_subword (operands[1], 0, 0, SFmode);
659 (define_expand "movdf"
660 [(set (match_operand:DF 0 "general_operand" "")
661 (match_operand:DF 1 "general_operand" ""))]
665 /* Fixup PIC cases. */
668 if (symbolic_operand (operands[1], DFmode))
670 if (reload_in_progress || reload_completed)
671 operands[1] = m32r_legitimize_pic_address (operands[1], operands[0]);
673 operands[1] = m32r_legitimize_pic_address (operands[1], NULL_RTX);
677 /* Everything except mem = const or mem = mem can be done easily. */
679 if (MEM_P (operands[0]))
680 operands[1] = force_reg (DFmode, operands[1]);
683 (define_insn "*movdf_insn"
684 [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
685 (match_operand:DF 1 "move_double_src_operand" "r,F,m,r"))]
686 "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
688 [(set_attr "type" "multi,multi,load8,store8")
689 (set_attr "length" "4,16,6,6")])
692 [(set (match_operand:DF 0 "move_dest_operand" "")
693 (match_operand:DF 1 "move_double_src_operand" ""))]
696 "operands[2] = gen_split_move_double (operands);")
698 ;; Zero extension instructions.
700 (define_insn "zero_extendqihi2"
701 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
702 (zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
708 [(set_attr "type" "int4,load2,load4")
709 (set_attr "length" "4,2,4")])
711 (define_insn "zero_extendqisi2"
712 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
713 (zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
719 [(set_attr "type" "int4,load2,load4")
720 (set_attr "length" "4,2,4")])
722 (define_insn "zero_extendhisi2"
723 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
724 (zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
730 [(set_attr "type" "int4,load2,load4")
731 (set_attr "length" "4,2,4")])
733 ;; Signed conversions from a smaller integer to a larger integer
734 (define_insn "extendqihi2"
735 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
736 (sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
742 [(set_attr "type" "multi,load2,load4")
743 (set_attr "length" "2,2,4")])
746 [(set (match_operand:HI 0 "register_operand" "")
747 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
753 rtx op0 = gen_lowpart (SImode, operands[0]);
754 rtx shift = GEN_INT (24);
756 operands[2] = gen_ashlsi3 (op0, op0, shift);
757 operands[3] = gen_ashrsi3 (op0, op0, shift);
760 (define_insn "extendqisi2"
761 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
762 (sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
768 [(set_attr "type" "multi,load2,load4")
769 (set_attr "length" "4,2,4")])
772 [(set (match_operand:SI 0 "register_operand" "")
773 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
779 rtx shift = GEN_INT (24);
781 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
782 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
785 (define_insn "extendhisi2"
786 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
787 (sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
793 [(set_attr "type" "multi,load2,load4")
794 (set_attr "length" "4,2,4")])
797 [(set (match_operand:SI 0 "register_operand" "")
798 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
804 rtx shift = GEN_INT (16);
806 operands[2] = gen_ashlsi3 (operands[0], operands[0], shift);
807 operands[3] = gen_ashrsi3 (operands[0], operands[0], shift);
810 ;; Arithmetic instructions.
812 ; ??? Adding an alternative to split add3 of small constants into two
813 ; insns yields better instruction packing but slower code. Adds of small
814 ; values is done a lot.
816 (define_insn "addsi3"
817 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
818 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
819 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
825 [(set_attr "type" "int2,int2,int4")
826 (set_attr "length" "2,2,4")])
829 ; [(set (match_operand:SI 0 "register_operand" "")
830 ; (plus:SI (match_operand:SI 1 "register_operand" "")
831 ; (match_operand:SI 2 "int8_operand" "")))]
833 ; && REGNO (operands[0]) != REGNO (operands[1])
834 ; && satisfies_constraint_I (operands[2])
835 ; && INTVAL (operands[2]) != 0"
836 ; [(set (match_dup 0) (match_dup 1))
837 ; (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
840 (define_insn "adddi3"
841 [(set (match_operand:DI 0 "register_operand" "=r")
842 (plus:DI (match_operand:DI 1 "register_operand" "%0")
843 (match_operand:DI 2 "register_operand" "r")))
844 (clobber (reg:CC 17))]
847 [(set_attr "type" "multi")
848 (set_attr "length" "6")])
850 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
852 [(set (match_operand:DI 0 "register_operand" "")
853 (plus:DI (match_operand:DI 1 "register_operand" "")
854 (match_operand:DI 2 "register_operand" "")))
855 (clobber (reg:CC 17))]
857 [(parallel [(set (reg:CC 17)
859 (use (match_dup 4))])
860 (parallel [(set (match_dup 4)
861 (plus:SI (match_dup 4)
862 (plus:SI (match_dup 5)
863 (ne:SI (reg:CC 17) (const_int 0)))))
865 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
866 (parallel [(set (match_dup 6)
867 (plus:SI (match_dup 6)
868 (plus:SI (match_dup 7)
869 (ne:SI (reg:CC 17) (const_int 0)))))
871 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
874 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
875 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
876 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
877 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
880 (define_insn "*clear_c"
883 (use (match_operand:SI 0 "register_operand" "r"))]
886 [(set_attr "type" "int2")
887 (set_attr "length" "2")])
889 (define_insn "*add_carry"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (plus:SI (match_operand:SI 1 "register_operand" "%0")
892 (plus:SI (match_operand:SI 2 "register_operand" "r")
893 (ne:SI (reg:CC 17) (const_int 0)))))
895 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
898 [(set_attr "type" "int2")
899 (set_attr "length" "2")])
901 (define_insn "subsi3"
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (minus:SI (match_operand:SI 1 "register_operand" "0")
904 (match_operand:SI 2 "register_operand" "r")))]
907 [(set_attr "type" "int2")
908 (set_attr "length" "2")])
910 (define_insn "subdi3"
911 [(set (match_operand:DI 0 "register_operand" "=r")
912 (minus:DI (match_operand:DI 1 "register_operand" "0")
913 (match_operand:DI 2 "register_operand" "r")))
914 (clobber (reg:CC 17))]
917 [(set_attr "type" "multi")
918 (set_attr "length" "6")])
920 ;; ??? The cmp clears the condition bit. Can we speed up somehow?
922 [(set (match_operand:DI 0 "register_operand" "")
923 (minus:DI (match_operand:DI 1 "register_operand" "")
924 (match_operand:DI 2 "register_operand" "")))
925 (clobber (reg:CC 17))]
927 [(parallel [(set (reg:CC 17)
929 (use (match_dup 4))])
930 (parallel [(set (match_dup 4)
931 (minus:SI (match_dup 4)
932 (minus:SI (match_dup 5)
933 (ne:SI (reg:CC 17) (const_int 0)))))
935 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
936 (parallel [(set (match_dup 6)
937 (minus:SI (match_dup 6)
938 (minus:SI (match_dup 7)
939 (ne:SI (reg:CC 17) (const_int 0)))))
941 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
944 operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
945 operands[5] = operand_subword (operands[2], (WORDS_BIG_ENDIAN != 0), 0, DImode);
946 operands[6] = operand_subword (operands[0], (WORDS_BIG_ENDIAN == 0), 0, DImode);
947 operands[7] = operand_subword (operands[2], (WORDS_BIG_ENDIAN == 0), 0, DImode);
950 (define_insn "*sub_carry"
951 [(set (match_operand:SI 0 "register_operand" "=r")
952 (minus:SI (match_operand:SI 1 "register_operand" "%0")
953 (minus:SI (match_operand:SI 2 "register_operand" "r")
954 (ne:SI (reg:CC 17) (const_int 0)))))
956 (unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
959 [(set_attr "type" "int2")
960 (set_attr "length" "2")])
962 ; Multiply/Divide instructions.
964 (define_insn "mulhisi3"
965 [(set (match_operand:SI 0 "register_operand" "=r")
966 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
967 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
969 "mullo %1,%2\;mvfacmi %0"
970 [(set_attr "type" "multi")
971 (set_attr "length" "4")])
973 (define_insn "mulsi3"
974 [(set (match_operand:SI 0 "register_operand" "=r")
975 (mult:SI (match_operand:SI 1 "register_operand" "%0")
976 (match_operand:SI 2 "register_operand" "r")))]
979 [(set_attr "type" "mul2")
980 (set_attr "length" "2")])
982 (define_insn "divsi3"
983 [(set (match_operand:SI 0 "register_operand" "=r")
984 (div:SI (match_operand:SI 1 "register_operand" "0")
985 (match_operand:SI 2 "register_operand" "r")))]
988 [(set_attr "type" "div4")
989 (set_attr "length" "4")])
991 (define_insn "udivsi3"
992 [(set (match_operand:SI 0 "register_operand" "=r")
993 (udiv:SI (match_operand:SI 1 "register_operand" "0")
994 (match_operand:SI 2 "register_operand" "r")))]
997 [(set_attr "type" "div4")
998 (set_attr "length" "4")])
1000 (define_insn "modsi3"
1001 [(set (match_operand:SI 0 "register_operand" "=r")
1002 (mod:SI (match_operand:SI 1 "register_operand" "0")
1003 (match_operand:SI 2 "register_operand" "r")))]
1006 [(set_attr "type" "div4")
1007 (set_attr "length" "4")])
1009 (define_insn "umodsi3"
1010 [(set (match_operand:SI 0 "register_operand" "=r")
1011 (umod:SI (match_operand:SI 1 "register_operand" "0")
1012 (match_operand:SI 2 "register_operand" "r")))]
1015 [(set_attr "type" "div4")
1016 (set_attr "length" "4")])
1018 ;; Boolean instructions.
1020 ;; We don't define the DImode versions as expand_binop does a good enough job.
1021 ;; And if it doesn't it should be fixed.
1023 (define_insn "andsi3"
1024 [(set (match_operand:SI 0 "register_operand" "=r,r")
1025 (and:SI (match_operand:SI 1 "register_operand" "%0,r")
1026 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1030 /* If we are worried about space, see if we can break this up into two
1031 short instructions, which might eliminate a NOP being inserted. */
1033 && m32r_not_same_reg (operands[0], operands[1])
1034 && satisfies_constraint_I (operands[2]))
1037 else if (CONST_INT_P (operands[2]))
1038 return \"and3 %0,%1,%#%X2\";
1040 return \"and %0,%2\";
1042 [(set_attr "type" "int2,int4")
1043 (set_attr "length" "2,4")])
1046 [(set (match_operand:SI 0 "register_operand" "")
1047 (and:SI (match_operand:SI 1 "register_operand" "")
1048 (match_operand:SI 2 "int8_operand" "")))]
1049 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1050 [(set (match_dup 0) (match_dup 2))
1051 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))]
1054 (define_insn "iorsi3"
1055 [(set (match_operand:SI 0 "register_operand" "=r,r")
1056 (ior:SI (match_operand:SI 1 "register_operand" "%0,r")
1057 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1061 /* If we are worried about space, see if we can break this up into two
1062 short instructions, which might eliminate a NOP being inserted. */
1064 && m32r_not_same_reg (operands[0], operands[1])
1065 && satisfies_constraint_I (operands[2]))
1068 else if (CONST_INT_P (operands[2]))
1069 return \"or3 %0,%1,%#%X2\";
1071 return \"or %0,%2\";
1073 [(set_attr "type" "int2,int4")
1074 (set_attr "length" "2,4")])
1077 [(set (match_operand:SI 0 "register_operand" "")
1078 (ior:SI (match_operand:SI 1 "register_operand" "")
1079 (match_operand:SI 2 "int8_operand" "")))]
1080 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1081 [(set (match_dup 0) (match_dup 2))
1082 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 1)))]
1085 (define_insn "xorsi3"
1086 [(set (match_operand:SI 0 "register_operand" "=r,r")
1087 (xor:SI (match_operand:SI 1 "register_operand" "%0,r")
1088 (match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
1092 /* If we are worried about space, see if we can break this up into two
1093 short instructions, which might eliminate a NOP being inserted. */
1095 && m32r_not_same_reg (operands[0], operands[1])
1096 && satisfies_constraint_I (operands[2]))
1099 else if (CONST_INT_P (operands[2]))
1100 return \"xor3 %0,%1,%#%X2\";
1102 return \"xor %0,%2\";
1104 [(set_attr "type" "int2,int4")
1105 (set_attr "length" "2,4")])
1108 [(set (match_operand:SI 0 "register_operand" "")
1109 (xor:SI (match_operand:SI 1 "register_operand" "")
1110 (match_operand:SI 2 "int8_operand" "")))]
1111 "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
1112 [(set (match_dup 0) (match_dup 2))
1113 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))]
1116 (define_insn "negsi2"
1117 [(set (match_operand:SI 0 "register_operand" "=r")
1118 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1121 [(set_attr "type" "int2")
1122 (set_attr "length" "2")])
1124 (define_insn "one_cmplsi2"
1125 [(set (match_operand:SI 0 "register_operand" "=r")
1126 (not:SI (match_operand:SI 1 "register_operand" "r")))]
1129 [(set_attr "type" "int2")
1130 (set_attr "length" "2")])
1132 ;; Shift instructions.
1134 (define_insn "ashlsi3"
1135 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1136 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1137 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1143 [(set_attr "type" "shift2,shift2,shift4")
1144 (set_attr "length" "2,2,4")])
1146 (define_insn "ashrsi3"
1147 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1148 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1149 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1155 [(set_attr "type" "shift2,shift2,shift4")
1156 (set_attr "length" "2,2,4")])
1158 (define_insn "lshrsi3"
1159 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1160 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1161 (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
1167 [(set_attr "type" "shift2,shift2,shift4")
1168 (set_attr "length" "2,2,4")])
1170 ;; Compare instructions.
1171 ;; This controls RTL generation and register allocation.
1173 ;; We generate RTL for comparisons and branches by having the cmpxx
1174 ;; patterns store away the operands. Then the bcc patterns
1175 ;; emit RTL for both the compare and the branch.
1177 ;; On the m32r it is more efficient to use the bxxz instructions and
1178 ;; thus merge the compare and branch into one instruction, so they are
1181 (define_insn "cmp_eqsi_zero_insn"
1183 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1184 (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
1185 "TARGET_M32RX || TARGET_M32R2"
1189 [(set_attr "type" "int4")
1190 (set_attr "length" "4")])
1192 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
1193 ;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
1194 ;; is quite inefficient. However, it is rarely used.
1196 (define_insn "cmp_eqsi_insn"
1198 (eq:CC (match_operand:SI 0 "register_operand" "r,r")
1199 (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
1200 (clobber (match_scratch:SI 2 "=&r,&r"))]
1204 if (which_alternative == 0)
1206 return \"mv %2,%0\;sub %2,%1\;cmpui %2,#1\";
1210 if (INTVAL (operands [1]) == 0)
1211 return \"cmpui %0, #1\";
1212 else if (REGNO (operands [2]) == REGNO (operands [0]))
1213 return \"addi %0,%#%N1\;cmpui %2,#1\";
1215 return \"add3 %2,%0,%#%N1\;cmpui %2,#1\";
1218 [(set_attr "type" "multi,multi")
1219 (set_attr "length" "8,8")])
1221 (define_insn "cmp_ltsi_insn"
1223 (lt:CC (match_operand:SI 0 "register_operand" "r,r")
1224 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1229 [(set_attr "type" "int2,int4")
1230 (set_attr "length" "2,4")])
1232 (define_insn "cmp_ltusi_insn"
1234 (ltu:CC (match_operand:SI 0 "register_operand" "r,r")
1235 (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
1240 [(set_attr "type" "int2,int4")
1241 (set_attr "length" "2,4")])
1243 ;; These control RTL generation for conditional jump insns.
1245 (define_expand "cbranchsi4"
1246 ; the comparison is emitted by gen_compare if needed.
1248 (if_then_else (match_operator 0 "ordered_comparison_operator"
1249 [(match_operand:SI 1 "register_operand" "")
1250 (match_operand:SI 2 "reg_or_cmp_int16_operand" "")])
1251 (label_ref (match_operand 3 "" ""))
1256 operands[0] = gen_compare (GET_CODE (operands[0]), operands[1], operands[2], FALSE);
1257 operands[1] = XEXP (operands[0], 0);
1258 operands[2] = XEXP (operands[0], 1);
1261 ;; Now match both normal and inverted jump.
1263 (define_insn "*branch_insn"
1265 (if_then_else (match_operator 1 "eqne_comparison_operator"
1266 [(reg 17) (const_int 0)])
1267 (label_ref (match_operand 0 "" ""))
1272 static char instruction[40];
1273 sprintf (instruction, \"%s%s %%l0\",
1274 (GET_CODE (operands[1]) == NE) ? \"bc\" : \"bnc\",
1275 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1278 [(set_attr "type" "branch")
1280 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1281 ; lengths and insn alignments that are complex to track.
1282 ; It's not important that we be hyper-precise here. It may be more
1283 ; important blah blah blah when the chip supports parallel execution
1284 ; blah blah blah but until then blah blah blah this is simple and
1286 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1292 (define_insn "*rev_branch_insn"
1294 (if_then_else (match_operator 1 "eqne_comparison_operator"
1295 [(reg 17) (const_int 0)])
1297 (label_ref (match_operand 0 "" ""))))]
1298 ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
1302 static char instruction[40];
1303 sprintf (instruction, \"%s%s %%l0\",
1304 (GET_CODE (operands[1]) == EQ) ? \"bc\" : \"bnc\",
1305 (get_attr_length (insn) == 2) ? \".s\" : \"\");
1308 [(set_attr "type" "branch")
1310 ; We use 300/600 instead of 512,1024 to account for inaccurate insn
1311 ; lengths and insn alignments that are complex to track.
1312 ; It's not important that we be hyper-precise here. It may be more
1313 ; important blah blah blah when the chip supports parallel execution
1314 ; blah blah blah but until then blah blah blah this is simple and
1316 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1322 ; reg/reg compare and branch insns
1324 (define_insn "*reg_branch_insn"
1326 (if_then_else (match_operator 1 "eqne_comparison_operator"
1327 [(match_operand:SI 2 "register_operand" "r")
1328 (match_operand:SI 3 "register_operand" "r")])
1329 (label_ref (match_operand 0 "" ""))
1334 /* Is branch target reachable with beq/bne? */
1335 if (get_attr_length (insn) == 4)
1337 if (GET_CODE (operands[1]) == EQ)
1338 return \"beq %2,%3,%l0\";
1340 return \"bne %2,%3,%l0\";
1344 if (GET_CODE (operands[1]) == EQ)
1345 return \"bne %2,%3,1f\;bra %l0\;1:\";
1347 return \"beq %2,%3,1f\;bra %l0\;1:\";
1350 [(set_attr "type" "branch")
1351 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1352 ; which is complex to track and inaccurate length specs.
1353 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1359 (define_insn "*rev_reg_branch_insn"
1361 (if_then_else (match_operator 1 "eqne_comparison_operator"
1362 [(match_operand:SI 2 "register_operand" "r")
1363 (match_operand:SI 3 "register_operand" "r")])
1365 (label_ref (match_operand 0 "" ""))))]
1369 /* Is branch target reachable with beq/bne? */
1370 if (get_attr_length (insn) == 4)
1372 if (GET_CODE (operands[1]) == NE)
1373 return \"beq %2,%3,%l0\";
1375 return \"bne %2,%3,%l0\";
1379 if (GET_CODE (operands[1]) == NE)
1380 return \"bne %2,%3,1f\;bra %l0\;1:\";
1382 return \"beq %2,%3,1f\;bra %l0\;1:\";
1385 [(set_attr "type" "branch")
1386 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1387 ; which is complex to track and inaccurate length specs.
1388 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1394 ; reg/zero compare and branch insns
1396 (define_insn "*zero_branch_insn"
1398 (if_then_else (match_operator 1 "signed_comparison_operator"
1399 [(match_operand:SI 2 "register_operand" "r")
1401 (label_ref (match_operand 0 "" ""))
1406 const char *br,*invbr;
1409 switch (GET_CODE (operands[1]))
1411 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1412 case NE : br = \"ne\"; invbr = \"eq\"; break;
1413 case LE : br = \"le\"; invbr = \"gt\"; break;
1414 case GT : br = \"gt\"; invbr = \"le\"; break;
1415 case LT : br = \"lt\"; invbr = \"ge\"; break;
1416 case GE : br = \"ge\"; invbr = \"lt\"; break;
1418 default: gcc_unreachable ();
1421 /* Is branch target reachable with bxxz? */
1422 if (get_attr_length (insn) == 4)
1424 sprintf (asmtext, \"b%sz %%2,%%l0\", br);
1425 output_asm_insn (asmtext, operands);
1429 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
1430 output_asm_insn (asmtext, operands);
1434 [(set_attr "type" "branch")
1435 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1436 ; which is complex to track and inaccurate length specs.
1437 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1443 (define_insn "*rev_zero_branch_insn"
1445 (if_then_else (match_operator 1 "eqne_comparison_operator"
1446 [(match_operand:SI 2 "register_operand" "r")
1449 (label_ref (match_operand 0 "" ""))))]
1453 const char *br,*invbr;
1456 switch (GET_CODE (operands[1]))
1458 case EQ : br = \"eq\"; invbr = \"ne\"; break;
1459 case NE : br = \"ne\"; invbr = \"eq\"; break;
1460 case LE : br = \"le\"; invbr = \"gt\"; break;
1461 case GT : br = \"gt\"; invbr = \"le\"; break;
1462 case LT : br = \"lt\"; invbr = \"ge\"; break;
1463 case GE : br = \"ge\"; invbr = \"lt\"; break;
1465 default: gcc_unreachable ();
1468 /* Is branch target reachable with bxxz? */
1469 if (get_attr_length (insn) == 4)
1471 sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
1472 output_asm_insn (asmtext, operands);
1476 sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
1477 output_asm_insn (asmtext, operands);
1481 [(set_attr "type" "branch")
1482 ; We use 25000/50000 instead of 32768/65536 to account for slot filling
1483 ; which is complex to track and inaccurate length specs.
1484 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1490 ;; S<cc> operations to set a register to 1/0 based on a comparison
1492 (define_expand "cstoresi4"
1493 [(match_operand:SI 0 "register_operand" "")
1494 (match_operator:SI 1 "ordered_comparison_operator"
1495 [(match_operand:SI 2 "register_operand" "")
1496 (match_operand:SI 3 "reg_or_cmp_int16_operand" "")])]
1500 if (GET_MODE (operands[0]) != SImode)
1503 if (!gen_cond_store (GET_CODE (operands[1]),
1504 operands[0], operands[2], operands[3]))
1510 (define_insn "seq_insn_m32rx"
1511 [(set (match_operand:SI 0 "register_operand" "=r")
1512 (eq:SI (match_operand:SI 1 "register_operand" "%r")
1513 (match_operand:SI 2 "reg_or_zero_operand" "rP")))
1514 (clobber (reg:CC 17))]
1515 "TARGET_M32RX || TARGET_M32R2"
1517 [(set_attr "type" "multi")
1518 (set_attr "length" "6")])
1521 [(set (match_operand:SI 0 "register_operand" "")
1522 (eq:SI (match_operand:SI 1 "register_operand" "")
1523 (match_operand:SI 2 "reg_or_zero_operand" "")))
1524 (clobber (reg:CC 17))]
1525 "TARGET_M32RX || TARGET_M32R2"
1527 (eq:CC (match_dup 1)
1530 (ne:SI (reg:CC 17) (const_int 0)))]
1533 (define_insn "seq_zero_insn"
1534 [(set (match_operand:SI 0 "register_operand" "=r")
1535 (eq:SI (match_operand:SI 1 "register_operand" "r")
1537 (clobber (reg:CC 17))]
1540 [(set_attr "type" "multi")
1541 (set_attr "length" "6")])
1544 [(set (match_operand:SI 0 "register_operand" "")
1545 (eq:SI (match_operand:SI 1 "register_operand" "")
1547 (clobber (reg:CC 17))]
1552 rtx op0 = operands[0];
1553 rtx op1 = operands[1];
1556 emit_insn (gen_cmp_ltusi_insn (op1, const1_rtx));
1557 emit_insn (gen_movcc_insn (op0));
1558 operands[3] = get_insns ();
1562 (define_insn "seq_insn"
1563 [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
1564 (eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
1565 (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
1566 (clobber (reg:CC 17))
1567 (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
1570 [(set_attr "type" "multi")
1571 (set_attr "length" "8,8,10,10")])
1574 [(set (match_operand:SI 0 "register_operand" "")
1575 (eq:SI (match_operand:SI 1 "register_operand" "")
1576 (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
1577 (clobber (reg:CC 17))
1578 (clobber (match_scratch:SI 3 ""))]
1579 "TARGET_M32R && reload_completed"
1583 rtx op0 = operands[0];
1584 rtx op1 = operands[1];
1585 rtx op2 = operands[2];
1586 rtx op3 = operands[3];
1587 HOST_WIDE_INT value;
1589 if (REG_P (op2) && REG_P (op3)
1590 && REGNO (op2) == REGNO (op3))
1597 if (REG_P (op1) && REG_P (op3)
1598 && REGNO (op1) != REGNO (op3))
1600 emit_move_insn (op3, op1);
1604 if (satisfies_constraint_P (op2) && (value = INTVAL (op2)) != 0)
1605 emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
1607 emit_insn (gen_xorsi3 (op3, op1, op2));
1609 emit_insn (gen_cmp_ltusi_insn (op3, const1_rtx));
1610 emit_insn (gen_movcc_insn (op0));
1611 operands[4] = get_insns ();
1615 (define_insn "sne_zero_insn"
1616 [(set (match_operand:SI 0 "register_operand" "=r")
1617 (ne:SI (match_operand:SI 1 "register_operand" "r")
1619 (clobber (reg:CC 17))
1620 (clobber (match_scratch:SI 2 "=&r"))]
1623 [(set_attr "type" "multi")
1624 (set_attr "length" "6")])
1627 [(set (match_operand:SI 0 "register_operand" "")
1628 (ne:SI (match_operand:SI 1 "register_operand" "")
1630 (clobber (reg:CC 17))
1631 (clobber (match_scratch:SI 2 ""))]
1636 (ltu:CC (match_dup 2)
1639 (ne:SI (reg:CC 17) (const_int 0)))]
1642 (define_insn "slt_insn"
1643 [(set (match_operand:SI 0 "register_operand" "=r,r")
1644 (lt:SI (match_operand:SI 1 "register_operand" "r,r")
1645 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1646 (clobber (reg:CC 17))]
1649 [(set_attr "type" "multi")
1650 (set_attr "length" "4,6")])
1653 [(set (match_operand:SI 0 "register_operand" "")
1654 (lt:SI (match_operand:SI 1 "register_operand" "")
1655 (match_operand:SI 2 "reg_or_int16_operand" "")))
1656 (clobber (reg:CC 17))]
1659 (lt:CC (match_dup 1)
1662 (ne:SI (reg:CC 17) (const_int 0)))]
1665 (define_insn "sle_insn"
1666 [(set (match_operand:SI 0 "register_operand" "=r")
1667 (le:SI (match_operand:SI 1 "register_operand" "r")
1668 (match_operand:SI 2 "register_operand" "r")))
1669 (clobber (reg:CC 17))]
1672 [(set_attr "type" "multi")
1673 (set_attr "length" "8")])
1676 [(set (match_operand:SI 0 "register_operand" "")
1677 (le:SI (match_operand:SI 1 "register_operand" "")
1678 (match_operand:SI 2 "register_operand" "")))
1679 (clobber (reg:CC 17))]
1682 (lt:CC (match_dup 2)
1685 (ne:SI (reg:CC 17) (const_int 0)))
1687 (xor:SI (match_dup 0)
1691 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1692 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1694 [(set (match_operand:SI 0 "register_operand" "")
1695 (le:SI (match_operand:SI 1 "register_operand" "")
1696 (match_operand:SI 2 "register_operand" "")))
1697 (clobber (reg:CC 17))]
1700 (lt:CC (match_dup 2)
1703 (ne:SI (reg:CC 17) (const_int 0)))
1705 (plus:SI (match_dup 0)
1708 (neg:SI (match_dup 0)))]
1711 (define_insn "sge_insn"
1712 [(set (match_operand:SI 0 "register_operand" "=r,r")
1713 (ge:SI (match_operand:SI 1 "register_operand" "r,r")
1714 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1715 (clobber (reg:CC 17))]
1718 [(set_attr "type" "multi")
1719 (set_attr "length" "8,10")])
1722 [(set (match_operand:SI 0 "register_operand" "")
1723 (ge:SI (match_operand:SI 1 "register_operand" "")
1724 (match_operand:SI 2 "reg_or_int16_operand" "")))
1725 (clobber (reg:CC 17))]
1728 (lt:CC (match_dup 1)
1731 (ne:SI (reg:CC 17) (const_int 0)))
1733 (xor:SI (match_dup 0)
1737 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1738 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1740 [(set (match_operand:SI 0 "register_operand" "")
1741 (ge:SI (match_operand:SI 1 "register_operand" "")
1742 (match_operand:SI 2 "reg_or_int16_operand" "")))
1743 (clobber (reg:CC 17))]
1746 (lt:CC (match_dup 1)
1749 (ne:SI (reg:CC 17) (const_int 0)))
1751 (plus:SI (match_dup 0)
1754 (neg:SI (match_dup 0)))]
1757 (define_insn "sltu_insn"
1758 [(set (match_operand:SI 0 "register_operand" "=r,r")
1759 (ltu:SI (match_operand:SI 1 "register_operand" "r,r")
1760 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1761 (clobber (reg:CC 17))]
1764 [(set_attr "type" "multi")
1765 (set_attr "length" "6,8")])
1768 [(set (match_operand:SI 0 "register_operand" "")
1769 (ltu:SI (match_operand:SI 1 "register_operand" "")
1770 (match_operand:SI 2 "reg_or_int16_operand" "")))
1771 (clobber (reg:CC 17))]
1774 (ltu:CC (match_dup 1)
1777 (ne:SI (reg:CC 17) (const_int 0)))]
1780 (define_insn "sleu_insn"
1781 [(set (match_operand:SI 0 "register_operand" "=r")
1782 (leu:SI (match_operand:SI 1 "register_operand" "r")
1783 (match_operand:SI 2 "register_operand" "r")))
1784 (clobber (reg:CC 17))]
1787 [(set_attr "type" "multi")
1788 (set_attr "length" "8")])
1791 [(set (match_operand:SI 0 "register_operand" "")
1792 (leu:SI (match_operand:SI 1 "register_operand" "")
1793 (match_operand:SI 2 "register_operand" "")))
1794 (clobber (reg:CC 17))]
1797 (ltu:CC (match_dup 2)
1800 (ne:SI (reg:CC 17) (const_int 0)))
1802 (xor:SI (match_dup 0)
1806 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1807 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1809 [(set (match_operand:SI 0 "register_operand" "")
1810 (leu:SI (match_operand:SI 1 "register_operand" "")
1811 (match_operand:SI 2 "register_operand" "")))
1812 (clobber (reg:CC 17))]
1815 (ltu:CC (match_dup 2)
1818 (ne:SI (reg:CC 17) (const_int 0)))
1820 (plus:SI (match_dup 0)
1823 (neg:SI (match_dup 0)))]
1826 (define_insn "sgeu_insn"
1827 [(set (match_operand:SI 0 "register_operand" "=r,r")
1828 (geu:SI (match_operand:SI 1 "register_operand" "r,r")
1829 (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
1830 (clobber (reg:CC 17))]
1833 [(set_attr "type" "multi")
1834 (set_attr "length" "8,10")])
1837 [(set (match_operand:SI 0 "register_operand" "")
1838 (geu:SI (match_operand:SI 1 "register_operand" "")
1839 (match_operand:SI 2 "reg_or_int16_operand" "")))
1840 (clobber (reg:CC 17))]
1843 (ltu:CC (match_dup 1)
1846 (ne:SI (reg:CC 17) (const_int 0)))
1848 (xor:SI (match_dup 0)
1852 ;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
1853 ;; xor reg,reg,1 which might eliminate a NOP being inserted.
1855 [(set (match_operand:SI 0 "register_operand" "")
1856 (geu:SI (match_operand:SI 1 "register_operand" "")
1857 (match_operand:SI 2 "reg_or_int16_operand" "")))
1858 (clobber (reg:CC 17))]
1861 (ltu:CC (match_dup 1)
1864 (ne:SI (reg:CC 17) (const_int 0)))
1866 (plus:SI (match_dup 0)
1869 (neg:SI (match_dup 0)))]
1872 (define_insn "movcc_insn"
1873 [(set (match_operand:SI 0 "register_operand" "=r")
1874 (ne:SI (reg:CC 17) (const_int 0)))]
1877 [(set_attr "type" "misc")
1878 (set_attr "length" "2")])
1881 ;; Unconditional and other jump instructions.
1884 [(set (pc) (label_ref (match_operand 0 "" "")))]
1887 [(set_attr "type" "uncond_branch")
1888 (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
1894 (define_insn "indirect_jump"
1895 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1898 [(set_attr "type" "uncond_branch")
1899 (set_attr "length" "2")])
1901 (define_insn "return_lr"
1902 [(parallel [(return) (use (reg:SI 14))])]
1905 [(set_attr "type" "uncond_branch")
1906 (set_attr "length" "2")])
1908 (define_insn "return_rte"
1912 [(set_attr "type" "uncond_branch")
1913 (set_attr "length" "2")])
1915 (define_expand "return"
1920 emit_jump_insn (gen_return_lr ());
1924 (define_expand "return_normal"
1929 enum m32r_function_type fn_type;
1931 fn_type = m32r_compute_function_type (current_function_decl);
1932 if (M32R_INTERRUPT_P (fn_type))
1934 emit_jump_insn (gen_return_rte ());
1938 emit_jump_insn (gen_return_lr ());
1942 (define_expand "tablejump"
1943 [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
1944 (use (label_ref (match_operand 1 "" "")))])]
1948 /* In pic mode, our address differences are against the base of the
1949 table. Add that base value back in; CSE ought to be able to combine
1950 the two address loads. */
1955 tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
1957 tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
1958 operands[0] = memory_address (Pmode, tmp);
1962 (define_insn "*tablejump_insn"
1963 [(set (pc) (match_operand:SI 0 "address_operand" "p"))
1964 (use (label_ref (match_operand 1 "" "")))]
1967 [(set_attr "type" "uncond_branch")
1968 (set_attr "length" "2")])
1970 (define_expand "call"
1971 ;; operands[1] is stack_size_rtx
1972 ;; operands[2] is next_arg_register
1973 [(parallel [(call (match_operand:SI 0 "call_operand" "")
1974 (match_operand 1 "" ""))
1975 (clobber (reg:SI 14))])]
1980 crtl->uses_pic_offset_table = 1;
1983 (define_insn "*call_via_reg"
1984 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
1985 (match_operand 1 "" ""))
1986 (clobber (reg:SI 14))]
1989 [(set_attr "type" "call")
1990 (set_attr "length" "2")])
1992 (define_insn "*call_via_label"
1993 [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
1994 (match_operand 1 "" ""))
1995 (clobber (reg:SI 14))]
1999 int call26_p = call26_operand (operands[0], FUNCTION_MODE);
2003 /* We may not be able to reach with a `bl' insn so punt and leave it to
2005 We do this here, rather than doing a force_reg in the define_expand
2006 so these insns won't be separated, say by scheduling, thus simplifying
2008 return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
2013 [(set_attr "type" "call")
2014 (set (attr "length")
2015 (if_then_else (not (match_test "call26_operand (operands[0], FUNCTION_MODE)"))
2016 (const_int 12) ; 10 + 2 for nop filler
2017 ; The return address must be on a 4 byte boundary so
2018 ; there's no point in using a value of 2 here. A 2 byte
2019 ; insn may go in the left slot but we currently can't
2020 ; use such knowledge.
2023 (define_expand "call_value"
2024 ;; operand 2 is stack_size_rtx
2025 ;; operand 3 is next_arg_register
2026 [(parallel [(set (match_operand 0 "register_operand" "=r")
2027 (call (match_operand:SI 1 "call_operand" "")
2028 (match_operand 2 "" "")))
2029 (clobber (reg:SI 14))])]
2034 crtl->uses_pic_offset_table = 1;
2037 (define_insn "*call_value_via_reg"
2038 [(set (match_operand 0 "register_operand" "=r")
2039 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
2040 (match_operand 2 "" "")))
2041 (clobber (reg:SI 14))]
2044 [(set_attr "type" "call")
2045 (set_attr "length" "2")])
2047 (define_insn "*call_value_via_label"
2048 [(set (match_operand 0 "register_operand" "=r")
2049 (call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
2050 (match_operand 2 "" "")))
2051 (clobber (reg:SI 14))]
2055 int call26_p = call26_operand (operands[1], FUNCTION_MODE);
2058 crtl->uses_pic_offset_table = 1;
2062 /* We may not be able to reach with a `bl' insn so punt and leave it to
2064 We do this here, rather than doing a force_reg in the define_expand
2065 so these insns won't be separated, say by scheduling, thus simplifying
2067 return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
2072 [(set_attr "type" "call")
2073 (set (attr "length")
2074 (if_then_else (not (match_test "call26_operand (operands[1], FUNCTION_MODE)"))
2075 (const_int 12) ; 10 + 2 for nop filler
2076 ; The return address must be on a 4 byte boundary so
2077 ; there's no point in using a value of 2 here. A 2 byte
2078 ; insn may go in the left slot but we currently can't
2079 ; use such knowledge.
2086 [(set_attr "type" "int2")
2087 (set_attr "length" "2")])
2089 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2090 ;; all of memory. This blocks insns from being moved across this point.
2092 (define_insn "blockage"
2093 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
2097 ;; Special pattern to flush the icache.
2099 (define_insn "flush_icache"
2100 [(unspec_volatile [(match_operand 0 "memory_operand" "m")]
2101 UNSPECV_FLUSH_ICACHE)
2102 (match_operand 1 "" "")
2103 (clobber (reg:SI 17))]
2105 "* return \"trap %#%1 ; flush-icache\";"
2106 [(set_attr "type" "int4")
2107 (set_attr "length" "4")])
2109 ;; Speed up fabs and provide correct sign handling for -0
2111 (define_insn "absdf2"
2112 [(set (match_operand:DF 0 "register_operand" "=r")
2113 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
2116 [(set_attr "type" "multi")
2117 (set_attr "length" "4")])
2120 [(set (match_operand:DF 0 "register_operand" "")
2121 (abs:DF (match_operand:DF 1 "register_operand" "")))]
2124 (ashift:SI (match_dup 2)
2127 (lshiftrt:SI (match_dup 2)
2129 "operands[2] = gen_highpart (SImode, operands[0]);")
2131 (define_insn "abssf2"
2132 [(set (match_operand:SF 0 "register_operand" "=r")
2133 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
2136 [(set_attr "type" "multi")
2137 (set_attr "length" "4")])
2140 [(set (match_operand:SF 0 "register_operand" "")
2141 (abs:SF (match_operand:SF 1 "register_operand" "")))]
2144 (ashift:SI (match_dup 2)
2147 (lshiftrt:SI (match_dup 2)
2149 "operands[2] = gen_highpart (SImode, operands[0]);")
2151 ;; Conditional move instructions
2152 ;; Based on those done for the d10v
2154 (define_expand "movsicc"
2156 (set (match_operand:SI 0 "register_operand" "r")
2157 (if_then_else:SI (match_operand 1 "" "")
2158 (match_operand:SI 2 "conditional_move_operand" "O")
2159 (match_operand:SI 3 "conditional_move_operand" "O")
2166 if (! zero_and_one (operands [2], operands [3]))
2169 /* Generate the comparison that will set the carry flag. */
2170 operands[1] = gen_compare (GET_CODE (operands[1]), XEXP (operands[1], 0),
2171 XEXP (operands[1], 1), TRUE);
2173 /* See other movsicc pattern below for reason why. */
2174 emit_insn (gen_blockage ());
2177 ;; Generate the conditional instructions based on how the carry flag is examined.
2178 (define_insn "*movsicc_internal"
2179 [(set (match_operand:SI 0 "register_operand" "=r")
2180 (if_then_else:SI (match_operand 1 "carry_compare_operand" "")
2181 (match_operand:SI 2 "conditional_move_operand" "O")
2182 (match_operand:SI 3 "conditional_move_operand" "O")
2185 "zero_and_one (operands [2], operands[3])"
2186 "* return emit_cond_move (operands, insn);"
2187 [(set_attr "type" "multi")
2188 (set_attr "length" "8")
2193 ;; Block moves, see m32r.c for more details.
2194 ;; Argument 0 is the destination
2195 ;; Argument 1 is the source
2196 ;; Argument 2 is the length
2197 ;; Argument 3 is the alignment
2199 (define_expand "movmemsi"
2200 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
2201 (match_operand:BLK 1 "general_operand" ""))
2202 (use (match_operand:SI 2 "immediate_operand" ""))
2203 (use (match_operand:SI 3 "immediate_operand" ""))])]
2207 if (operands[0]) /* Avoid unused code messages. */
2209 if (m32r_expand_block_move (operands))
2216 ;; Insn generated by block moves
2218 (define_insn "movmemsi_internal"
2219 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination
2220 (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source
2221 (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move
2222 (set (match_operand:SI 3 "register_operand" "=0")
2223 (plus:SI (minus (match_dup 2) (const_int 4))
2225 (set (match_operand:SI 4 "register_operand" "=1")
2226 (plus:SI (match_dup 1)
2228 (clobber (match_scratch:SI 5 "=&r")) ;; temp1
2229 (clobber (match_scratch:SI 6 "=&r"))] ;; temp2
2231 "* m32r_output_block_move (insn, operands); return \"\"; "
2232 [(set_attr "type" "store8")
2233 (set_attr "length" "72")]) ;; Maximum
2237 /* When generating pic, we need to load the symbol offset into a register.
2238 So that the optimizer does not confuse this with a normal symbol load
2239 we use an unspec. The offset will be loaded from a constant pool entry,
2240 since that is the only type of relocation we can use. */
2242 (define_insn "pic_load_addr"
2243 [(set (match_operand:SI 0 "register_operand" "=r")
2244 (unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
2247 [(set_attr "type" "int4")])
2249 (define_insn "gotoff_load_addr"
2250 [(set (match_operand:SI 0 "register_operand" "=r")
2251 (unspec:SI [(match_operand 1 "" "")] UNSPEC_GOTOFF))]
2253 "seth %0, %#shigh(%1@GOTOFF)\;add3 %0, %0, low(%1@GOTOFF)"
2254 [(set_attr "type" "int4")
2255 (set_attr "length" "8")])
2257 ;; Load program counter insns.
2259 (define_insn "get_pc"
2260 [(clobber (reg:SI 14))
2261 (set (match_operand 0 "register_operand" "=r,r")
2262 (unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
2263 (use (match_operand:SI 2 "immediate_operand" "W,i"))]
2266 bl.s .+4\;seth %0,%#shigh(%1)\;add3 %0,%0,%#low(%1+4)\;add %0,lr
2267 bl.s .+4\;ld24 %0,%#%1\;add %0,lr"
2268 [(set_attr "length" "12,8")])
2270 (define_expand "builtin_setjmp_receiver"
2271 [(label_ref (match_operand 0 "" ""))]
2275 m32r_load_pic_register ();