gcc/config/m32r/predicates.md

   1 ;; Predicate definitions for Renesas M32R.
   2 ;; Copyright (C) 2005 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 2, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING.  If not, write to
  18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  19 ;; Boston, MA 02110-1301, USA.
  20
  21 ;; Return true if OP is a register or the constant 0.
  22
  23 (define_predicate "reg_or_zero_operand"
  24   (match_code "reg,subreg,const_int")
  25 {
  26   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
  27     return register_operand (op, mode);
  28
  29   if (GET_CODE (op) != CONST_INT)
  30     return 0;
  31
  32   return INTVAL (op) == 0;
  33 })
  34
  35 ;; Return nonzero if the operand is suitable for use in a conditional
  36 ;; move sequence.
  37
  38 (define_predicate "conditional_move_operand"
  39   (match_code "reg,subreg,const_int")
  40 {
  41   /* Only defined for simple integers so far...  */
  42   if (mode != SImode && mode != HImode && mode != QImode)
  43     return FALSE;
  44
  45   /* At the moment we can handle moving registers and loading constants.  */
  46   /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
  47
  48   switch (GET_CODE (op))
  49     {
  50     case REG:
  51       return 1;
  52
  53     case CONST_INT:
  54       return INT8_P (INTVAL (op));
  55
  56     default:
  57 #if 0
  58       fprintf (stderr, "Test for cond move op of type: %s\n",
  59                GET_RTX_NAME (GET_CODE (op)));
  60 #endif
  61       return 0;
  62     }
  63 })
  64
  65 ;; Return true if the code is a test of the carry bit.
  66
  67 (define_predicate "carry_compare_operand"
  68   (match_code "eq,ne")
  69 {
  70   rtx x;
  71
  72   if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
  73     return FALSE;
  74
  75   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
  76     return FALSE;
  77
  78   x = XEXP (op, 0);
  79   if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
  80     return FALSE;
  81
  82   x = XEXP (op, 1);
  83   if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
  84     return FALSE;
  85
  86   return TRUE;
  87 })
  88
  89 ;; Return 1 if OP is an EQ or NE comparison operator.
  90
  91 (define_predicate "eqne_comparison_operator"
  92   (match_code "eq,ne")
  93 {
  94   enum rtx_code code = GET_CODE (op);
  95
  96   return (code == EQ || code == NE);
  97 })
  98
  99 ;; Return 1 if OP is a signed comparison operator.
 100
 101 (define_predicate "signed_comparison_operator"
 102   (match_code "eq,ne,lt,le,gt,ge")
 103 {
 104   enum rtx_code code = GET_CODE (op);
 105
 106   return (COMPARISON_P (op)
 107           && (code == EQ || code == NE
 108               || code == LT || code == LE || code == GT || code == GE));
 109 })
 110
 111 ;; Return true if OP is an acceptable argument for a move destination.
 112
 113 (define_predicate "move_dest_operand"
 114   (match_code "reg,subreg,mem")
 115 {
 116   switch (GET_CODE (op))
 117     {
 118     case REG :
 119       return register_operand (op, mode);
 120     case SUBREG :
 121       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 122          pseudo-reg and is now a stack slot.  */
 123       if (GET_CODE (SUBREG_REG (op)) == MEM)
 124         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 125       else
 126         return register_operand (op, mode);
 127     case MEM :
 128       if (GET_CODE (XEXP (op, 0)) == POST_INC)
 129         return 0;               /* stores can't do post inc */
 130       return address_operand (XEXP (op, 0), mode);
 131     default :
 132       return 0;
 133     }
 134 })
 135
 136 ;; Return true if OP is an acceptable argument for a single word move
 137 ;; source.
 138
 139 (define_predicate "move_src_operand"
 140   (match_code "reg,subreg,mem,const_int,const_double,label_ref,const,symbol_ref")
 141 {
 142   switch (GET_CODE (op))
 143     {
 144     case LABEL_REF :
 145     case SYMBOL_REF :
 146     case CONST :
 147       return addr24_operand (op, mode);
 148     case CONST_INT :
 149       /* ??? We allow more cse opportunities if we only allow constants
 150          loadable with one insn, and split the rest into two.  The instances
 151          where this would help should be rare and the current way is
 152          simpler.  */
 153       if (HOST_BITS_PER_WIDE_INT > 32)
 154         {
 155           HOST_WIDE_INT rest = INTVAL (op) >> 31;
 156           return (rest == 0 || rest == -1);
 157         }
 158       else
 159         return 1;
 160     case CONST_DOUBLE :
 161       if (mode == SFmode)
 162         return 1;
 163       else if (mode == SImode)
 164         {
 165           /* Large unsigned constants are represented as const_double's.  */
 166           unsigned HOST_WIDE_INT low, high;
 167
 168           low = CONST_DOUBLE_LOW (op);
 169           high = CONST_DOUBLE_HIGH (op);
 170           return high == 0 && low <= (unsigned) 0xffffffff;
 171         }
 172       else
 173         return 0;
 174     case REG :
 175       return register_operand (op, mode);
 176     case SUBREG :
 177       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 178          pseudo-reg and is now a stack slot.  */
 179       if (GET_CODE (SUBREG_REG (op)) == MEM)
 180         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 181       else
 182         return register_operand (op, mode);
 183     case MEM :
 184       if (GET_CODE (XEXP (op, 0)) == PRE_INC
 185           || GET_CODE (XEXP (op, 0)) == PRE_DEC)
 186         return 0;               /* loads can't do pre-{inc,dec} */
 187       return address_operand (XEXP (op, 0), mode);
 188     default :
 189       return 0;
 190     }
 191 })
 192
 193 ;; Return true if OP is an acceptable argument for a double word move
 194 ;; source.
 195
 196 (define_predicate "move_double_src_operand"
 197   (match_code "reg,subreg,mem,const_int,const_double")
 198 {
 199   switch (GET_CODE (op))
 200     {
 201     case CONST_INT :
 202     case CONST_DOUBLE :
 203       return 1;
 204     case REG :
 205       return register_operand (op, mode);
 206     case SUBREG :
 207       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 208          pseudo-reg and is now a stack slot.  */
 209       if (GET_CODE (SUBREG_REG (op)) == MEM)
 210         return move_double_src_operand (SUBREG_REG (op), mode);
 211       else
 212         return register_operand (op, mode);
 213     case MEM :
 214       /* Disallow auto inc/dec for now.  */
 215       if (GET_CODE (XEXP (op, 0)) == PRE_DEC
 216           || GET_CODE (XEXP (op, 0)) == PRE_INC)
 217         return 0;
 218       return address_operand (XEXP (op, 0), mode);
 219     default :
 220       return 0;
 221     }
 222 })
 223
 224 ;; Return true if OP is a const_int requiring two instructions to
 225 ;; load.
 226
 227 (define_predicate "two_insn_const_operand"
 228   (match_code "const_int")
 229 {
 230   if (GET_CODE (op) != CONST_INT)
 231     return 0;
 232   if (INT16_P (INTVAL (op))
 233       || UINT24_P (INTVAL (op))
 234       || UPPER16_P (INTVAL (op)))
 235     return 0;
 236   return 1;
 237 })
 238
 239 ;; Returns 1 if OP is a symbol reference.
 240
 241 (define_predicate "symbolic_operand"
 242   (match_code "symbol_ref,label_ref,const")
 243 {
 244   switch (GET_CODE (op))
 245     {
 246     case SYMBOL_REF:
 247     case LABEL_REF:
 248     case CONST :
 249       return 1;
 250
 251     default:
 252       return 0;
 253     }
 254 })
 255
 256 ;; Return true if OP is a signed 8-bit immediate value.
 257
 258 (define_predicate "int8_operand"
 259   (match_code "const_int")
 260 {
 261   if (GET_CODE (op) != CONST_INT)
 262     return 0;
 263   return INT8_P (INTVAL (op));
 264 })
 265
 266 ;; Return true if OP is an unsigned 16-bit immediate value.
 267
 268 (define_predicate "uint16_operand"
 269   (match_code "const_int")
 270 {
 271   if (GET_CODE (op) != CONST_INT)
 272     return 0;
 273   return UINT16_P (INTVAL (op));
 274 })
 275
 276 ;; Return true if OP is a register or signed 16-bit value.
 277
 278 (define_predicate "reg_or_int16_operand"
 279   (match_code "reg,subreg,const_int")
 280 {
 281   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 282     return register_operand (op, mode);
 283   if (GET_CODE (op) != CONST_INT)
 284     return 0;
 285   return INT16_P (INTVAL (op));
 286 })
 287
 288 ;; Return true if OP is a register or an unsigned 16-bit value.
 289
 290 (define_predicate "reg_or_uint16_operand"
 291   (match_code "reg,subreg,const_int")
 292 {
 293   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 294     return register_operand (op, mode);
 295   if (GET_CODE (op) != CONST_INT)
 296     return 0;
 297   return UINT16_P (INTVAL (op));
 298 })
 299
 300 ;; Return true if OP is a register or signed 16-bit value for
 301 ;; compares.
 302
 303 (define_predicate "reg_or_cmp_int16_operand"
 304   (match_code "reg,subreg,const_int")
 305 {
 306   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 307     return register_operand (op, mode);
 308   if (GET_CODE (op) != CONST_INT)
 309     return 0;
 310   return CMP_INT16_P (INTVAL (op));
 311 })
 312
 313 ;; Return true if OP is a register or an integer value that can be
 314 ;; used is SEQ/SNE.  We can use either XOR of the value or ADD of the
 315 ;; negative of the value for the constant.  Don't allow 0, because
 316 ;; that is special cased.
 317
 318 (define_predicate "reg_or_eq_int16_operand"
 319   (match_code "reg,subreg,const_int")
 320 {
 321   HOST_WIDE_INT value;
 322
 323   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 324     return register_operand (op, mode);
 325
 326   if (GET_CODE (op) != CONST_INT)
 327     return 0;
 328
 329   value = INTVAL (op);
 330   return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
 331 })
 332
 333 ;; Return true if OP is a signed 16-bit immediate value useful in
 334 ;; comparisons.
 335
 336 (define_predicate "cmp_int16_operand"
 337   (match_code "const_int")
 338 {
 339   if (GET_CODE (op) != CONST_INT)
 340     return 0;
 341   return CMP_INT16_P (INTVAL (op));
 342 })
 343
 344 ;; Acceptable arguments to the call insn.
 345
 346 (define_predicate "call_address_operand"
 347   (match_code "symbol_ref,label_ref,const")
 348 {
 349   return symbolic_operand (op, mode);
 350
 351 /* Constants and values in registers are not OK, because
 352    the m32r BL instruction can only support PC relative branching.  */
 353 })
 354
 355 ;; Return true if OP is an acceptable input argument for a zero/sign
 356 ;; extend operation.
 357
 358 (define_predicate "extend_operand"
 359   (match_code "reg,subreg,mem")
 360 {
 361   rtx addr;
 362
 363   switch (GET_CODE (op))
 364     {
 365     case REG :
 366     case SUBREG :
 367       return register_operand (op, mode);
 368
 369     case MEM :
 370       addr = XEXP (op, 0);
 371       if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
 372         return 0;               /* loads can't do pre inc/pre dec */
 373
 374       return address_operand (addr, mode);
 375
 376     default :
 377       return 0;
 378     }
 379 })
 380
 381 ;; Return nonzero if the operand is an insn that is a small
 382 ;; insn. Allow const_int 0 as well, which is a placeholder for NOP
 383 ;; slots.
 384
 385 (define_predicate "small_insn_p"
 386   (match_code "insn,call_insn,jump_insn")
 387 {
 388   if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
 389     return 1;
 390
 391   if (! INSN_P (op))
 392     return 0;
 393
 394   return get_attr_length (op) == 2;
 395 })
 396
 397 ;; Return true if op is an integer constant, less than or equal to
 398 ;; MAX_MOVE_BYTES.
 399
 400 (define_predicate "m32r_block_immediate_operand"
 401   (match_code "const_int")
 402 {
 403   if (GET_CODE (op) != CONST_INT
 404       || INTVAL (op) > MAX_MOVE_BYTES
 405       || INTVAL (op) <= 0)
 406     return 0;
 407
 408   return 1;
 409 })
 410
 411 ;; Return nonzero if the operand is an insn that is a large insn.
 412
 413 (define_predicate "large_insn_p"
 414   (match_code "insn,call_insn,jump_insn")
 415 {
 416   if (! INSN_P (op))
 417     return 0;
 418
 419   return get_attr_length (op) != 2;
 420 })
 421
 422 ;; Returns 1 if OP is an acceptable operand for seth/add3.
 423
 424 (define_predicate "seth_add3_operand"
 425   (match_code "symbol_ref,label_ref,const")
 426 {
 427   if (flag_pic)
 428     return 0;
 429
 430   if (GET_CODE (op) == SYMBOL_REF
 431       || GET_CODE (op) == LABEL_REF)
 432     return 1;
 433
 434   if (GET_CODE (op) == CONST
 435       && GET_CODE (XEXP (op, 0)) == PLUS
 436       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 437       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 438       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 439     return 1;
 440
 441   return 0;
 442 })