1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
39 /* Needed for use_return_insn. */
42 #ifdef SUPPORT_SUN_FPA
44 /* Index into this array by (register number >> 3) to find the
45 smallest class which contains that register. */
46 enum reg_class regno_reg_class
[]
47 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
48 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
50 #endif /* defined SUPPORT_SUN_FPA */
52 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
53 if SGS_SWITCH_TABLE. */
54 int switch_table_difference_label_flag
;
56 static rtx
find_addr_reg ();
57 rtx
legitimize_pic_address ();
58 void print_operand_address ();
61 /* Alignment to use for loops and jumps */
62 /* Specify power of two alignment used for loops. */
63 const char *m68k_align_loops_string
;
64 /* Specify power of two alignment used for non-loop jumps. */
65 const char *m68k_align_jumps_string
;
66 /* Specify power of two alignment used for functions. */
67 const char *m68k_align_funcs_string
;
69 /* Specify power of two alignment used for loops. */
71 /* Specify power of two alignment used for non-loop jumps. */
73 /* Specify power of two alignment used for functions. */
76 /* Nonzero if the last compare/test insn had FP operands. The
77 sCC expanders peek at this to determine what to do for the
78 68060, which has no fsCC instructions. */
79 int m68k_last_compare_had_fp_operands
;
81 /* Sometimes certain combinations of command options do not make
82 sense on a particular target machine. You can define a macro
83 `OVERRIDE_OPTIONS' to take account of this. This macro, if
84 defined, is executed once just after all the command options have
87 Don't use this macro to turn on various extra optimizations for
88 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
97 /* Validate -malign-loops= value, or provide default */
98 if (m68k_align_loops_string
)
100 m68k_align_loops
= atoi (m68k_align_loops_string
);
101 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
102 fatal ("-malign-loops=%d is not between 1 and %d",
103 m68k_align_loops
, MAX_CODE_ALIGN
);
106 m68k_align_loops
= def_align
;
108 /* Validate -malign-jumps= value, or provide default */
109 if (m68k_align_jumps_string
)
111 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
112 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
113 fatal ("-malign-jumps=%d is not between 1 and %d",
114 m68k_align_jumps
, MAX_CODE_ALIGN
);
117 m68k_align_jumps
= def_align
;
119 /* Validate -malign-functions= value, or provide default */
120 if (m68k_align_funcs_string
)
122 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
123 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
124 fatal ("-malign-functions=%d is not between 1 and %d",
125 m68k_align_funcs
, MAX_CODE_ALIGN
);
128 m68k_align_funcs
= def_align
;
131 /* This function generates the assembly code for function entry.
132 STREAM is a stdio stream to output the code to.
133 SIZE is an int: how many units of temporary storage to allocate.
134 Refer to the array `regs_ever_live' to determine which registers
135 to save; `regs_ever_live[I]' is nonzero if register number I
136 is ever used in the function. This function is responsible for
137 knowing which registers should not be saved even if used. */
140 /* Note that the order of the bit mask for fmovem is the opposite
141 of the order for movem! */
145 output_function_prologue (stream
, size
)
150 register int mask
= 0;
151 int num_saved_regs
= 0;
152 extern char call_used_regs
[];
153 int fsize
= (size
+ 3) & -4;
154 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
157 if (frame_pointer_needed
)
159 if (fsize
== 0 && TARGET_68040
)
161 /* on the 68040, pea + move is faster than link.w 0 */
163 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
164 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
165 reg_names
[FRAME_POINTER_REGNUM
]);
167 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
168 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
169 reg_names
[FRAME_POINTER_REGNUM
]);
172 else if (fsize
< 0x8000)
175 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
176 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
178 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
179 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
182 else if (TARGET_68020
)
185 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
186 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
188 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
189 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
194 /* Adding negative number is faster on the 68040. */
196 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
197 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
199 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
200 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
203 if (dwarf2out_do_frame ())
206 l
= (char *) dwarf2out_cfi_label ();
207 cfa_store_offset
+= 4;
208 cfa_offset
= cfa_store_offset
;
209 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
210 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
211 cfa_store_offset
+= fsize
;
216 if (fsize
+ 4 < 0x8000)
223 /* asm_fprintf() cannot handle %. */
225 asm_fprintf (stream
, "\tsubq.w %0I%d,%Rsp\n", fsize
+ 4);
227 asm_fprintf (stream
, "\tsubqw %0I%d,%Rsp\n", fsize
+ 4);
232 /* asm_fprintf() cannot handle %. */
234 asm_fprintf (stream
, "\tsubq.l %0I%d,%Rsp\n", fsize
+ 4);
236 asm_fprintf (stream
, "\tsubql %0I%d,%Rsp\n", fsize
+ 4);
240 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
242 /* On the CPU32 it is faster to use two subqw instructions to
243 subtract a small integer (8 < N <= 16) to a register. */
244 /* asm_fprintf() cannot handle %. */
246 asm_fprintf (stream
, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
249 asm_fprintf (stream
, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
254 #endif /* not NO_ADDSUB_Q */
257 /* Adding negative number is faster on the 68040. */
258 /* asm_fprintf() cannot handle %. */
260 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
262 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
268 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
270 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
276 /* asm_fprintf() cannot handle %. */
278 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
280 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
283 if (dwarf2out_do_frame ())
285 cfa_store_offset
+= fsize
;
286 cfa_offset
= cfa_store_offset
;
287 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
290 #ifdef SUPPORT_SUN_FPA
291 for (regno
= 24; regno
< 56; regno
++)
292 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
295 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
298 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
301 if (dwarf2out_do_frame ())
303 char *l
= dwarf2out_cfi_label ();
305 cfa_store_offset
+= 8;
306 if (! frame_pointer_needed
)
308 cfa_offset
= cfa_store_offset
;
309 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
311 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
317 for (regno
= 16; regno
< 24; regno
++)
318 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
320 mask
|= 1 << (regno
- 16);
323 if ((mask
& 0xff) != 0)
326 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
328 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
330 if (dwarf2out_do_frame ())
332 char *l
= (char *) dwarf2out_cfi_label ();
335 cfa_store_offset
+= num_saved_regs
* 12;
336 if (! frame_pointer_needed
)
338 cfa_offset
= cfa_store_offset
;
339 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
341 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
342 if (mask
& (1 << (regno
- 16)))
343 dwarf2out_reg_save (l
, regno
,
344 -cfa_store_offset
+ n_regs
++ * 12);
350 for (regno
= 0; regno
< 16; regno
++)
351 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
353 mask
|= 1 << (15 - regno
);
356 if (frame_pointer_needed
)
358 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
361 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
363 mask
|= 1 << (15 - PIC_OFFSET_TABLE_REGNUM
);
370 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
372 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
375 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
379 if (num_saved_regs
<= 2)
381 /* Store each separately in the same order moveml uses.
382 Using two movel instructions instead of a single moveml
383 is about 15% faster for the 68020 and 68030 at no expense
388 /* Undo the work from above. */
389 for (i
= 0; i
< 16; i
++)
394 "\t%Omove.l %s,-(%Rsp)\n",
396 "\tmovel %s,%Rsp@-\n",
399 if (dwarf2out_do_frame ())
401 char *l
= (char *) dwarf2out_cfi_label ();
403 cfa_store_offset
+= 4;
404 if (! frame_pointer_needed
)
406 cfa_offset
= cfa_store_offset
;
407 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
409 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
417 /* The coldfire does not support the predecrement form of the
418 movml instruction, so we must adjust the stack pointer and
419 then use the plain address register indirect mode. We also
420 have to invert the register save mask to use the new mode.
422 FIXME: if num_saved_regs was calculated earlier, we could
423 combine the stack pointer adjustment with any adjustment
424 done when the initial stack frame is created. This would
425 save an instruction */
430 for (i
= 0; i
< 16; i
++)
432 newmask
|= (1 << (15-i
));
435 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
436 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
438 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
439 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
445 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
447 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
450 if (dwarf2out_do_frame ())
452 char *l
= (char *) dwarf2out_cfi_label ();
455 cfa_store_offset
+= num_saved_regs
* 4;
456 if (! frame_pointer_needed
)
458 cfa_offset
= cfa_store_offset
;
459 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
461 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
462 if (mask
& (1 << (15 - regno
)))
463 dwarf2out_reg_save (l
, regno
,
464 -cfa_store_offset
+ n_regs
++ * 4);
467 if (flag_pic
&& current_function_uses_pic_offset_table
)
470 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
471 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
473 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
474 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
475 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
476 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
477 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
482 /* Return true if this function's epilogue can be output as RTL. */
489 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
492 /* Copied from output_function_epilogue (). We should probably create a
493 separate layout routine to perform the common work. */
495 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
496 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
502 /* This function generates the assembly code for function exit,
503 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
505 The function epilogue should not depend on the current stack pointer!
506 It should use the frame pointer only, if there is a frame pointer.
507 This is mandatory because of alloca; we also take advantage of it to
508 omit stack adjustments before returning. */
511 output_function_epilogue (stream
, size
)
516 register int mask
, fmask
;
518 int offset
, foffset
, fpoffset
;
519 extern char call_used_regs
[];
520 int fsize
= (size
+ 3) & -4;
522 rtx insn
= get_last_insn ();
523 int restore_from_sp
= 0;
525 /* If the last insn was a BARRIER, we don't have to write any code. */
526 if (GET_CODE (insn
) == NOTE
)
527 insn
= prev_nonnote_insn (insn
);
528 if (insn
&& GET_CODE (insn
) == BARRIER
)
530 /* Output just a no-op so that debuggers don't get confused
531 about which function the pc is in at this address. */
532 asm_fprintf (stream
, "\tnop\n");
536 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
537 if (profile_block_flag
== 2)
539 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
543 #ifdef FUNCTION_EXTRA_EPILOGUE
544 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
546 nregs
= 0; fmask
= 0; fpoffset
= 0;
547 #ifdef SUPPORT_SUN_FPA
548 for (regno
= 24 ; regno
< 56 ; regno
++)
549 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
551 fpoffset
= nregs
* 8;
556 for (regno
= 16; regno
< 24; regno
++)
557 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
560 fmask
|= 1 << (23 - regno
);
563 foffset
= fpoffset
+ nregs
* 12;
565 if (frame_pointer_needed
)
566 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
567 for (regno
= 0; regno
< 16; regno
++)
568 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
573 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
576 mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
578 offset
= foffset
+ nregs
* 4;
579 /* FIXME : leaf_function_p below is too strong.
580 What we really need to know there is if there could be pending
581 stack adjustment needed at that point. */
582 restore_from_sp
= ! frame_pointer_needed
583 || (! current_function_calls_alloca
&& leaf_function_p ());
584 if (offset
+ fsize
>= 0x8000
586 && (mask
|| fmask
|| fpoffset
))
589 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
591 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
595 if (TARGET_5200
|| nregs
<= 2)
597 /* Restore each separately in the same order moveml does.
598 Using two movel instructions instead of a single moveml
599 is about 15% faster for the 68020 and 68030 at no expense
604 /* Undo the work from above. */
605 for (i
= 0; i
< 16; i
++)
611 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
613 reg_names
[FRAME_POINTER_REGNUM
],
616 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
617 reg_names
[FRAME_POINTER_REGNUM
],
618 offset
+ fsize
, reg_names
[i
]);
621 else if (restore_from_sp
)
624 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
627 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
634 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
636 reg_names
[FRAME_POINTER_REGNUM
],
639 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
640 reg_names
[FRAME_POINTER_REGNUM
],
641 offset
+ fsize
, reg_names
[i
]);
652 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
654 reg_names
[FRAME_POINTER_REGNUM
],
657 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
658 reg_names
[FRAME_POINTER_REGNUM
],
659 offset
+ fsize
, mask
);
662 else if (restore_from_sp
)
665 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
667 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
673 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
675 reg_names
[FRAME_POINTER_REGNUM
],
678 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
679 reg_names
[FRAME_POINTER_REGNUM
],
680 offset
+ fsize
, mask
);
689 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
691 reg_names
[FRAME_POINTER_REGNUM
],
694 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
695 reg_names
[FRAME_POINTER_REGNUM
],
696 foffset
+ fsize
, fmask
);
699 else if (restore_from_sp
)
702 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
704 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
710 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
712 reg_names
[FRAME_POINTER_REGNUM
],
715 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
716 reg_names
[FRAME_POINTER_REGNUM
],
717 foffset
+ fsize
, fmask
);
722 for (regno
= 55; regno
>= 24; regno
--)
723 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
728 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
730 reg_names
[FRAME_POINTER_REGNUM
],
733 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
734 reg_names
[FRAME_POINTER_REGNUM
],
735 fpoffset
+ fsize
, reg_names
[regno
]);
738 else if (restore_from_sp
)
741 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
744 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
751 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
753 reg_names
[FRAME_POINTER_REGNUM
],
756 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
757 reg_names
[FRAME_POINTER_REGNUM
],
758 fpoffset
+ fsize
, reg_names
[regno
]);
763 if (frame_pointer_needed
)
764 fprintf (stream
, "\tunlk %s\n",
765 reg_names
[FRAME_POINTER_REGNUM
]);
774 asm_fprintf (stream
, "\taddq.w %0I%d,%Rsp\n", fsize
+ 4);
776 asm_fprintf (stream
, "\taddqw %0I%d,%Rsp\n", fsize
+ 4);
782 asm_fprintf (stream
, "\taddq.l %0I%d,%Rsp\n", fsize
+ 4);
784 asm_fprintf (stream
, "\taddql %0I%d,%Rsp\n", fsize
+ 4);
788 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
790 /* On the CPU32 it is faster to use two addqw instructions to
791 add a small integer (8 < N <= 16) to a register. */
792 /* asm_fprintf() cannot handle %. */
794 asm_fprintf (stream
, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
797 asm_fprintf (stream
, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
802 #endif /* not NO_ADDSUB_Q */
803 if (fsize
+ 4 < 0x8000)
807 /* asm_fprintf() cannot handle %. */
809 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
811 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
817 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
819 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
825 /* asm_fprintf() cannot handle %. */
827 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
829 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
833 if (current_function_pops_args
)
834 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
836 fprintf (stream
, "\trts\n");
839 /* Similar to general_operand, but exclude stack_pointer_rtx. */
842 not_sp_operand (op
, mode
)
844 enum machine_mode mode
;
846 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
849 /* Return TRUE if X is a valid comparison operator for the dbcc
852 Note it rejects floating point comparison operators.
853 (In the future we could use Fdbcc).
855 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
858 valid_dbcc_comparison_p (x
, mode
)
860 enum machine_mode mode ATTRIBUTE_UNUSED
;
862 switch (GET_CODE (x
))
864 case EQ
: case NE
: case GTU
: case LTU
:
868 /* Reject some when CC_NO_OVERFLOW is set. This may be over
870 case GT
: case LT
: case GE
: case LE
:
871 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
877 /* Return non-zero if flags are currently in the 68881 flag register. */
881 /* We could add support for these in the future */
882 return cc_status
.flags
& CC_IN_68881
;
885 /* Output a dbCC; jCC sequence. Note we do not handle the
886 floating point version of this sequence (Fdbcc). We also
887 do not handle alternative conditions when CC_NO_OVERFLOW is
888 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
889 kick those out before we get here. */
892 output_dbcc_and_branch (operands
)
895 switch (GET_CODE (operands
[3]))
899 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
901 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
907 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
909 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
915 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
917 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
923 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
925 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
931 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
933 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
939 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
941 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
947 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
949 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
955 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
957 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
963 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
965 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
971 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
973 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
981 /* If the decrement is to be done in SImode, then we have
982 to compensate for the fact that dbcc decrements in HImode. */
983 switch (GET_MODE (operands
[0]))
987 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
989 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1002 output_scc_di(op
, operand1
, operand2
, dest
)
1009 enum rtx_code op_code
= GET_CODE (op
);
1011 /* This does not produce a usefull cc. */
1014 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1015 below. Swap the operands and change the op if these requirements
1016 are not fulfilled. */
1017 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1021 operand1
= operand2
;
1023 op_code
= swap_condition (op_code
);
1025 loperands
[0] = operand1
;
1026 if (GET_CODE (operand1
) == REG
)
1027 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1029 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1030 if (operand2
!= const0_rtx
)
1032 loperands
[2] = operand2
;
1033 if (GET_CODE (operand2
) == REG
)
1034 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1036 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1038 loperands
[4] = gen_label_rtx();
1039 if (operand2
!= const0_rtx
)
1042 #ifdef SGS_CMP_ORDER
1043 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1045 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1048 #ifdef SGS_CMP_ORDER
1049 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1051 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1057 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[0]))
1058 output_asm_insn ("tst%.l %0", loperands
);
1061 #ifdef SGS_CMP_ORDER
1062 output_asm_insn ("cmp%.w %0,%#0", loperands
);
1064 output_asm_insn ("cmp%.w %#0,%0", loperands
);
1069 output_asm_insn ("jbne %l4", loperands
);
1071 output_asm_insn ("jne %l4", loperands
);
1074 if (TARGET_68020
|| TARGET_5200
|| ! ADDRESS_REG_P (loperands
[1]))
1075 output_asm_insn ("tst%.l %1", loperands
);
1078 #ifdef SGS_CMP_ORDER
1079 output_asm_insn ("cmp%.w %1,%#0", loperands
);
1081 output_asm_insn ("cmp%.w %#0,%1", loperands
);
1086 loperands
[5] = dest
;
1091 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1092 CODE_LABEL_NUMBER (loperands
[4]));
1093 output_asm_insn ("seq %5", loperands
);
1097 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1098 CODE_LABEL_NUMBER (loperands
[4]));
1099 output_asm_insn ("sne %5", loperands
);
1103 loperands
[6] = gen_label_rtx();
1105 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1107 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1109 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1110 CODE_LABEL_NUMBER (loperands
[4]));
1111 output_asm_insn ("sgt %5", loperands
);
1112 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1113 CODE_LABEL_NUMBER (loperands
[6]));
1117 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1118 CODE_LABEL_NUMBER (loperands
[4]));
1119 output_asm_insn ("shi %5", loperands
);
1123 loperands
[6] = gen_label_rtx();
1125 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1127 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1129 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1130 CODE_LABEL_NUMBER (loperands
[4]));
1131 output_asm_insn ("slt %5", loperands
);
1132 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1133 CODE_LABEL_NUMBER (loperands
[6]));
1137 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1138 CODE_LABEL_NUMBER (loperands
[4]));
1139 output_asm_insn ("scs %5", loperands
);
1143 loperands
[6] = gen_label_rtx();
1145 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1147 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1149 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1150 CODE_LABEL_NUMBER (loperands
[4]));
1151 output_asm_insn ("sge %5", loperands
);
1152 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1153 CODE_LABEL_NUMBER (loperands
[6]));
1157 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1158 CODE_LABEL_NUMBER (loperands
[4]));
1159 output_asm_insn ("scc %5", loperands
);
1163 loperands
[6] = gen_label_rtx();
1165 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1167 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1169 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1170 CODE_LABEL_NUMBER (loperands
[4]));
1171 output_asm_insn ("sle %5", loperands
);
1172 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1173 CODE_LABEL_NUMBER (loperands
[6]));
1177 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1178 CODE_LABEL_NUMBER (loperands
[4]));
1179 output_asm_insn ("sls %5", loperands
);
1189 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1191 rtx countop
, dataop
;
1195 operands
[0] = countop
;
1196 operands
[1] = dataop
;
1198 if (GET_CODE (countop
) == CONST_INT
)
1200 register int count
= INTVAL (countop
);
1201 /* If COUNT is bigger than size of storage unit in use,
1202 advance to the containing unit of same size. */
1203 if (count
> signpos
)
1205 int offset
= (count
& ~signpos
) / 8;
1206 count
= count
& signpos
;
1207 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1209 if (count
== signpos
)
1210 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1212 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1214 /* These three statements used to use next_insns_test_no...
1215 but it appears that this should do the same job. */
1217 && next_insn_tests_no_inequality (insn
))
1220 && next_insn_tests_no_inequality (insn
))
1223 && next_insn_tests_no_inequality (insn
))
1226 cc_status
.flags
= CC_NOT_NEGATIVE
;
1228 return "btst %0,%1";
1231 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1232 reference and a constant. */
1235 symbolic_operand (op
, mode
)
1237 enum machine_mode mode ATTRIBUTE_UNUSED
;
1239 switch (GET_CODE (op
))
1247 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1248 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1249 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1251 #if 0 /* Deleted, with corresponding change in m68k.h,
1252 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1254 return GET_MODE (op
) == mode
;
1262 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1265 extend_operator(x
, mode
)
1267 enum machine_mode mode
;
1269 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1271 switch (GET_CODE(x
))
1282 /* Legitimize PIC addresses. If the address is already
1283 position-independent, we return ORIG. Newly generated
1284 position-independent addresses go to REG. If we need more
1285 than one register, we lose.
1287 An address is legitimized by making an indirect reference
1288 through the Global Offset Table with the name of the symbol
1291 The assembler and linker are responsible for placing the
1292 address of the symbol in the GOT. The function prologue
1293 is responsible for initializing a5 to the starting address
1296 The assembler is also responsible for translating a symbol name
1297 into a constant displacement from the start of the GOT.
1299 A quick example may make things a little clearer:
1301 When not generating PIC code to store the value 12345 into _foo
1302 we would generate the following code:
1306 When generating PIC two transformations are made. First, the compiler
1307 loads the address of foo into a register. So the first transformation makes:
1312 The code in movsi will intercept the lea instruction and call this
1313 routine which will transform the instructions into:
1315 movel a5@(_foo:w), a0
1319 That (in a nutshell) is how *all* symbol and label references are
1323 legitimize_pic_address (orig
, mode
, reg
)
1325 enum machine_mode mode ATTRIBUTE_UNUSED
;
1329 /* First handle a simple SYMBOL_REF or LABEL_REF */
1330 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1335 pic_ref
= gen_rtx_MEM (Pmode
,
1336 gen_rtx_PLUS (Pmode
,
1337 pic_offset_table_rtx
, orig
));
1338 current_function_uses_pic_offset_table
= 1;
1339 if (reload_in_progress
)
1340 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1341 RTX_UNCHANGING_P (pic_ref
) = 1;
1342 emit_move_insn (reg
, pic_ref
);
1345 else if (GET_CODE (orig
) == CONST
)
1349 /* Make sure this is CONST has not already been legitimized */
1350 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1351 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1357 /* legitimize both operands of the PLUS */
1358 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1360 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1361 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1362 base
== reg
? 0 : reg
);
1366 if (GET_CODE (orig
) == CONST_INT
)
1367 return plus_constant_for_output (base
, INTVAL (orig
));
1368 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
1369 /* Likewise, should we set special REG_NOTEs here? */
1375 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1377 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1380 const_method (constant
)
1386 i
= INTVAL (constant
);
1390 /* The Coldfire doesn't have byte or word operations. */
1391 /* FIXME: This may not be useful for the m68060 either */
1394 /* if -256 < N < 256 but N is not in range for a moveq
1395 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1396 if (USE_MOVQ (i
^ 0xff))
1398 /* Likewise, try with not.w */
1399 if (USE_MOVQ (i
^ 0xffff))
1401 /* This is the only value where neg.w is useful */
1404 /* Try also with swap */
1406 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1409 /* Otherwise, use move.l */
1414 const_int_cost (constant
)
1417 switch (const_method (constant
))
1420 /* Constants between -128 and 127 are cheap due to moveq */
1426 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1436 output_move_const_into_data_reg (operands
)
1441 i
= INTVAL (operands
[1]);
1442 switch (const_method (operands
[1]))
1445 #if defined (MOTOROLA) && !defined (CRDS)
1446 return "moveq%.l %1,%0";
1448 return "moveq %1,%0";
1451 operands
[1] = GEN_INT (i
^ 0xff);
1452 #if defined (MOTOROLA) && !defined (CRDS)
1453 return "moveq%.l %1,%0\n\tnot%.b %0";
1455 return "moveq %1,%0\n\tnot%.b %0";
1458 operands
[1] = GEN_INT (i
^ 0xffff);
1459 #if defined (MOTOROLA) && !defined (CRDS)
1460 return "moveq%.l %1,%0\n\tnot%.w %0";
1462 return "moveq %1,%0\n\tnot%.w %0";
1465 #if defined (MOTOROLA) && !defined (CRDS)
1466 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1468 return "moveq %#-128,%0\n\tneg%.w %0";
1474 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
1475 #if defined (MOTOROLA) && !defined (CRDS)
1476 return "moveq%.l %1,%0\n\tswap %0";
1478 return "moveq %1,%0\n\tswap %0";
1482 return "move%.l %1,%0";
1489 output_move_simode_const (operands
)
1492 if (operands
[1] == const0_rtx
1493 && (DATA_REG_P (operands
[0])
1494 || GET_CODE (operands
[0]) == MEM
)
1495 /* clr insns on 68000 read before writing.
1496 This isn't so on the 68010, but we have no TARGET_68010. */
1497 && ((TARGET_68020
|| TARGET_5200
)
1498 || !(GET_CODE (operands
[0]) == MEM
1499 && MEM_VOLATILE_P (operands
[0]))))
1501 else if (operands
[1] == const0_rtx
1502 && ADDRESS_REG_P (operands
[0]))
1503 return "sub%.l %0,%0";
1504 else if (DATA_REG_P (operands
[0]))
1505 return output_move_const_into_data_reg (operands
);
1506 else if (ADDRESS_REG_P (operands
[0])
1507 && INTVAL (operands
[1]) < 0x8000
1508 && INTVAL (operands
[1]) >= -0x8000)
1509 return "move%.w %1,%0";
1510 else if (GET_CODE (operands
[0]) == MEM
1511 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1512 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1513 && INTVAL (operands
[1]) < 0x8000
1514 && INTVAL (operands
[1]) >= -0x8000)
1516 return "move%.l %1,%0";
1520 output_move_simode (operands
)
1523 if (GET_CODE (operands
[1]) == CONST_INT
)
1524 return output_move_simode_const (operands
);
1525 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1526 || GET_CODE (operands
[1]) == CONST
)
1527 && push_operand (operands
[0], SImode
))
1529 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1530 || GET_CODE (operands
[1]) == CONST
)
1531 && ADDRESS_REG_P (operands
[0]))
1532 return "lea %a1,%0";
1533 return "move%.l %1,%0";
1537 output_move_himode (operands
)
1540 if (GET_CODE (operands
[1]) == CONST_INT
)
1542 if (operands
[1] == const0_rtx
1543 && (DATA_REG_P (operands
[0])
1544 || GET_CODE (operands
[0]) == MEM
)
1545 /* clr insns on 68000 read before writing.
1546 This isn't so on the 68010, but we have no TARGET_68010. */
1547 && ((TARGET_68020
|| TARGET_5200
)
1548 || !(GET_CODE (operands
[0]) == MEM
1549 && MEM_VOLATILE_P (operands
[0]))))
1551 else if (operands
[1] == const0_rtx
1552 && ADDRESS_REG_P (operands
[0]))
1553 return "sub%.l %0,%0";
1554 else if (DATA_REG_P (operands
[0])
1555 && INTVAL (operands
[1]) < 128
1556 && INTVAL (operands
[1]) >= -128)
1558 #if defined(MOTOROLA) && !defined(CRDS)
1559 return "moveq%.l %1,%0";
1561 return "moveq %1,%0";
1564 else if (INTVAL (operands
[1]) < 0x8000
1565 && INTVAL (operands
[1]) >= -0x8000)
1566 return "move%.w %1,%0";
1568 else if (CONSTANT_P (operands
[1]))
1569 return "move%.l %1,%0";
1571 /* Recognize the insn before a tablejump, one that refers
1572 to a table of offsets. Such an insn will need to refer
1573 to a label on the insn. So output one. Use the label-number
1574 of the table of offsets to generate this label. This code,
1575 and similar code below, assumes that there will be at most one
1576 reference to each table. */
1577 if (GET_CODE (operands
[1]) == MEM
1578 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1579 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1580 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1582 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1583 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1585 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1586 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1588 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1589 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1590 #endif /* not SGS */
1591 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1592 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1593 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1594 #ifdef SGS_SWITCH_TABLES
1595 /* Set flag saying we need to define the symbol
1596 LD%n (with value L%n-LI%n) at the end of the switch table. */
1597 switch_table_difference_label_flag
= 1;
1598 #endif /* SGS_SWITCH_TABLES */
1599 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1601 #endif /* SGS_NO_LI */
1602 return "move%.w %1,%0";
1606 output_move_qimode (operands
)
1611 /* This is probably useless, since it loses for pushing a struct
1612 of several bytes a byte at a time. */
1613 /* 68k family always modifies the stack pointer by at least 2, even for
1614 byte pushes. The 5200 (coldfire) does not do this. */
1615 if (GET_CODE (operands
[0]) == MEM
1616 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1617 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1618 && ! ADDRESS_REG_P (operands
[1])
1621 xoperands
[1] = operands
[1];
1623 = gen_rtx_MEM (QImode
,
1624 gen_rtx_PLUS (VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1625 /* Just pushing a byte puts it in the high byte of the halfword. */
1626 /* We must put it in the low-order, high-numbered byte. */
1627 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1629 xoperands
[3] = stack_pointer_rtx
;
1631 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1633 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1637 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1641 /* clr and st insns on 68000 read before writing.
1642 This isn't so on the 68010, but we have no TARGET_68010. */
1643 if (!ADDRESS_REG_P (operands
[0])
1644 && ((TARGET_68020
|| TARGET_5200
)
1645 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1647 if (operands
[1] == const0_rtx
)
1649 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1650 && GET_CODE (operands
[1]) == CONST_INT
1651 && (INTVAL (operands
[1]) & 255) == 255)
1657 if (GET_CODE (operands
[1]) == CONST_INT
1658 && DATA_REG_P (operands
[0])
1659 && INTVAL (operands
[1]) < 128
1660 && INTVAL (operands
[1]) >= -128)
1662 #if defined(MOTOROLA) && !defined(CRDS)
1663 return "moveq%.l %1,%0";
1665 return "moveq %1,%0";
1668 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
1669 return "sub%.l %0,%0";
1670 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1671 return "move%.l %1,%0";
1672 /* 68k family (including the 5200 coldfire) does not support byte moves to
1673 from address registers. */
1674 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1675 return "move%.w %1,%0";
1676 return "move%.b %1,%0";
1680 output_move_stricthi (operands
)
1683 if (operands
[1] == const0_rtx
1684 /* clr insns on 68000 read before writing.
1685 This isn't so on the 68010, but we have no TARGET_68010. */
1686 && ((TARGET_68020
|| TARGET_5200
)
1687 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1689 return "move%.w %1,%0";
1693 output_move_strictqi (operands
)
1696 if (operands
[1] == const0_rtx
1697 /* clr insns on 68000 read before writing.
1698 This isn't so on the 68010, but we have no TARGET_68010. */
1699 && ((TARGET_68020
|| TARGET_5200
)
1700 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1702 return "move%.b %1,%0";
1705 /* Return the best assembler insn template
1706 for moving operands[1] into operands[0] as a fullword. */
1709 singlemove_string (operands
)
1712 #ifdef SUPPORT_SUN_FPA
1713 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1714 return "fpmoves %1,%0";
1716 if (GET_CODE (operands
[1]) == CONST_INT
)
1717 return output_move_simode_const (operands
);
1718 return "move%.l %1,%0";
1722 /* Output assembler code to perform a doubleword move insn
1723 with operands OPERANDS. */
1726 output_move_double (operands
)
1731 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1736 rtx addreg0
= 0, addreg1
= 0;
1737 int dest_overlapped_low
= 0;
1738 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1743 /* First classify both operands. */
1745 if (REG_P (operands
[0]))
1747 else if (offsettable_memref_p (operands
[0]))
1749 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1751 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1753 else if (GET_CODE (operands
[0]) == MEM
)
1758 if (REG_P (operands
[1]))
1760 else if (CONSTANT_P (operands
[1]))
1762 else if (offsettable_memref_p (operands
[1]))
1764 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1766 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1768 else if (GET_CODE (operands
[1]) == MEM
)
1773 /* Check for the cases that the operand constraints are not
1774 supposed to allow to happen. Abort if we get one,
1775 because generating code for these cases is painful. */
1777 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1780 /* If one operand is decrementing and one is incrementing
1781 decrement the former register explicitly
1782 and change that operand into ordinary indexing. */
1784 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1786 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1788 output_asm_insn ("sub%.l %#12,%0", operands
);
1790 output_asm_insn ("subq%.l %#8,%0", operands
);
1791 if (GET_MODE (operands
[1]) == XFmode
)
1792 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
1793 else if (GET_MODE (operands
[0]) == DFmode
)
1794 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
1796 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
1799 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1801 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1803 output_asm_insn ("sub%.l %#12,%1", operands
);
1805 output_asm_insn ("subq%.l %#8,%1", operands
);
1806 if (GET_MODE (operands
[1]) == XFmode
)
1807 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
1808 else if (GET_MODE (operands
[1]) == DFmode
)
1809 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
1811 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
1815 /* If an operand is an unoffsettable memory ref, find a register
1816 we can increment temporarily to make it refer to the second word. */
1818 if (optype0
== MEMOP
)
1819 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1821 if (optype1
== MEMOP
)
1822 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1824 /* Ok, we can do one word at a time.
1825 Normally we do the low-numbered word first,
1826 but if either operand is autodecrementing then we
1827 do the high-numbered word first.
1829 In either case, set up in LATEHALF the operands to use
1830 for the high-numbered word and in some cases alter the
1831 operands in OPERANDS to be suitable for the low-numbered word. */
1835 if (optype0
== REGOP
)
1837 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
1838 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1840 else if (optype0
== OFFSOP
)
1842 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1843 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1847 middlehalf
[0] = operands
[0];
1848 latehalf
[0] = operands
[0];
1851 if (optype1
== REGOP
)
1853 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
1854 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1856 else if (optype1
== OFFSOP
)
1858 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1859 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1861 else if (optype1
== CNSTOP
)
1863 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1868 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1869 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1870 operands
[1] = GEN_INT (l
[0]);
1871 middlehalf
[1] = GEN_INT (l
[1]);
1872 latehalf
[1] = GEN_INT (l
[2]);
1874 else if (CONSTANT_P (operands
[1]))
1876 /* actually, no non-CONST_DOUBLE constant should ever
1879 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1880 latehalf
[1] = constm1_rtx
;
1882 latehalf
[1] = const0_rtx
;
1887 middlehalf
[1] = operands
[1];
1888 latehalf
[1] = operands
[1];
1892 /* size is not 12: */
1894 if (optype0
== REGOP
)
1895 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
1896 else if (optype0
== OFFSOP
)
1897 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1899 latehalf
[0] = operands
[0];
1901 if (optype1
== REGOP
)
1902 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
1903 else if (optype1
== OFFSOP
)
1904 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1905 else if (optype1
== CNSTOP
)
1906 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1908 latehalf
[1] = operands
[1];
1911 /* If insn is effectively movd N(sp),-(sp) then we will do the
1912 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1913 for the low word as well, to compensate for the first decrement of sp. */
1914 if (optype0
== PUSHOP
1915 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1916 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1917 operands
[1] = middlehalf
[1] = latehalf
[1];
1919 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1920 if the upper part of reg N does not appear in the MEM, arrange to
1921 emit the move late-half first. Otherwise, compute the MEM address
1922 into the upper part of N and use that as a pointer to the memory
1924 if (optype0
== REGOP
1925 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1927 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
1929 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1930 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1932 /* If both halves of dest are used in the src memory address,
1933 compute the address into latehalf of dest.
1934 Note that this can't happen if the dest is two data regs. */
1936 xops
[0] = latehalf
[0];
1937 xops
[1] = XEXP (operands
[1], 0);
1938 output_asm_insn ("lea %a1,%0", xops
);
1939 if( GET_MODE (operands
[1]) == XFmode
)
1941 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
1942 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1943 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1947 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
1948 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1952 && reg_overlap_mentioned_p (middlehalf
[0],
1953 XEXP (operands
[1], 0)))
1955 /* Check for two regs used by both source and dest.
1956 Note that this can't happen if the dest is all data regs.
1957 It can happen if the dest is d6, d7, a0.
1958 But in that case, latehalf is an addr reg, so
1959 the code at compadr does ok. */
1961 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1962 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1965 /* JRV says this can't happen: */
1966 if (addreg0
|| addreg1
)
1969 /* Only the middle reg conflicts; simply put it last. */
1970 output_asm_insn (singlemove_string (operands
), operands
);
1971 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1972 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1975 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1976 /* If the low half of dest is mentioned in the source memory
1977 address, the arrange to emit the move late half first. */
1978 dest_overlapped_low
= 1;
1981 /* If one or both operands autodecrementing,
1982 do the two words, high-numbered first. */
1984 /* Likewise, the first move would clobber the source of the second one,
1985 do them in the other order. This happens only for registers;
1986 such overlap can't happen in memory unless the user explicitly
1987 sets it up, and that is an undefined circumstance. */
1989 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1990 || (optype0
== REGOP
&& optype1
== REGOP
1991 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1992 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1993 || dest_overlapped_low
)
1995 /* Make any unoffsettable addresses point at high-numbered word. */
1999 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
2001 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2006 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
2008 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2012 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2014 /* Undo the adds we just did. */
2016 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2018 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2022 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2024 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2026 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2029 /* Do low-numbered word. */
2030 return singlemove_string (operands
);
2033 /* Normal case: do the two words, low-numbered first. */
2035 output_asm_insn (singlemove_string (operands
), operands
);
2037 /* Do the middle one of the three words for long double */
2041 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2043 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2045 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2048 /* Make any unoffsettable addresses point at high-numbered word. */
2050 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2052 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2055 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2057 /* Undo the adds we just did. */
2061 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2063 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2068 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2070 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2076 /* Return a REG that occurs in ADDR with coefficient 1.
2077 ADDR can be effectively incremented by incrementing REG. */
2080 find_addr_reg (addr
)
2083 while (GET_CODE (addr
) == PLUS
)
2085 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2086 addr
= XEXP (addr
, 0);
2087 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2088 addr
= XEXP (addr
, 1);
2089 else if (CONSTANT_P (XEXP (addr
, 0)))
2090 addr
= XEXP (addr
, 1);
2091 else if (CONSTANT_P (XEXP (addr
, 1)))
2092 addr
= XEXP (addr
, 0);
2096 if (GET_CODE (addr
) == REG
)
2101 /* Output assembler code to perform a 32 bit 3 operand add. */
2104 output_addsi3 (operands
)
2107 if (! operands_match_p (operands
[0], operands
[1]))
2109 if (!ADDRESS_REG_P (operands
[1]))
2111 rtx tmp
= operands
[1];
2113 operands
[1] = operands
[2];
2117 /* These insns can result from reloads to access
2118 stack slots over 64k from the frame pointer. */
2119 if (GET_CODE (operands
[2]) == CONST_INT
2120 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2121 return "move%.l %2,%0\n\tadd%.l %1,%0";
2123 if (GET_CODE (operands
[2]) == REG
)
2124 return "lea 0(%1,%2.l),%0";
2126 return "lea %c2(%1),%0";
2129 if (GET_CODE (operands
[2]) == REG
)
2130 return "lea (%1,%2.l),%0";
2132 return "lea (%c2,%1),%0";
2133 #else /* not MOTOROLA (MIT syntax) */
2134 if (GET_CODE (operands
[2]) == REG
)
2135 return "lea %1@(0,%2:l),%0";
2137 return "lea %1@(%c2),%0";
2138 #endif /* not MOTOROLA */
2139 #endif /* not SGS */
2141 if (GET_CODE (operands
[2]) == CONST_INT
)
2144 if (INTVAL (operands
[2]) > 0
2145 && INTVAL (operands
[2]) <= 8)
2146 return "addq%.l %2,%0";
2147 if (INTVAL (operands
[2]) < 0
2148 && INTVAL (operands
[2]) >= -8)
2150 operands
[2] = GEN_INT (-INTVAL (operands
[2]));
2151 return "subq%.l %2,%0";
2153 /* On the CPU32 it is faster to use two addql instructions to
2154 add a small integer (8 < N <= 16) to a register.
2155 Likewise for subql. */
2156 if (TARGET_CPU32
&& REG_P (operands
[0]))
2158 if (INTVAL (operands
[2]) > 8
2159 && INTVAL (operands
[2]) <= 16)
2161 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
2162 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2164 if (INTVAL (operands
[2]) < -8
2165 && INTVAL (operands
[2]) >= -16)
2167 operands
[2] = GEN_INT (-INTVAL (operands
[2]) - 8);
2168 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2172 if (ADDRESS_REG_P (operands
[0])
2173 && INTVAL (operands
[2]) >= -0x8000
2174 && INTVAL (operands
[2]) < 0x8000)
2177 return "add%.w %2,%0";
2180 return "lea (%c2,%0),%0";
2182 return "lea %0@(%c2),%0";
2186 return "add%.l %2,%0";
2189 /* Store in cc_status the expressions that the condition codes will
2190 describe after execution of an instruction whose pattern is EXP.
2191 Do not alter them if the instruction would not alter the cc's. */
2193 /* On the 68000, all the insns to store in an address register fail to
2194 set the cc's. However, in some cases these instructions can make it
2195 possibly invalid to use the saved cc's. In those cases we clear out
2196 some or all of the saved cc's so they won't be used. */
2199 notice_update_cc (exp
, insn
)
2203 /* If the cc is being set from the fpa and the expression is not an
2204 explicit floating point test instruction (which has code to deal with
2205 this), reinit the CC. */
2206 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2207 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2208 && !(GET_CODE (exp
) == PARALLEL
2209 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2210 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2214 else if (GET_CODE (exp
) == SET
)
2216 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2220 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2222 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
2223 cc_status
.value1
= 0;
2224 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
2225 cc_status
.value2
= 0;
2227 else if (!FP_REG_P (SET_DEST (exp
))
2228 && SET_DEST (exp
) != cc0_rtx
2229 && (FP_REG_P (SET_SRC (exp
))
2230 || GET_CODE (SET_SRC (exp
)) == FIX
2231 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2232 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2236 /* A pair of move insns doesn't produce a useful overall cc. */
2237 else if (!FP_REG_P (SET_DEST (exp
))
2238 && !FP_REG_P (SET_SRC (exp
))
2239 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2240 && (GET_CODE (SET_SRC (exp
)) == REG
2241 || GET_CODE (SET_SRC (exp
)) == MEM
2242 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2246 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2250 else if (XEXP (exp
, 0) != pc_rtx
)
2252 cc_status
.flags
= 0;
2253 cc_status
.value1
= XEXP (exp
, 0);
2254 cc_status
.value2
= XEXP (exp
, 1);
2257 else if (GET_CODE (exp
) == PARALLEL
2258 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2260 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2262 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2264 cc_status
.flags
= 0;
2265 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2266 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2271 if (cc_status
.value2
!= 0
2272 && ADDRESS_REG_P (cc_status
.value2
)
2273 && GET_MODE (cc_status
.value2
) == QImode
)
2275 if (cc_status
.value2
!= 0
2276 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2277 switch (GET_CODE (cc_status
.value2
))
2279 case PLUS
: case MINUS
: case MULT
:
2280 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2281 #if 0 /* These instructions always clear the overflow bit */
2282 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2283 case ROTATE
: case ROTATERT
:
2285 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2286 cc_status
.flags
|= CC_NO_OVERFLOW
;
2289 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2290 ends with a move insn moving r2 in r2's mode.
2291 Thus, the cc's are set for r2.
2292 This can set N bit spuriously. */
2293 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2298 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2300 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2301 cc_status
.value2
= 0;
2302 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2303 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2304 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2305 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2306 cc_status
.flags
= CC_IN_68881
;
2310 output_move_const_double (operands
)
2313 #ifdef SUPPORT_SUN_FPA
2314 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2316 int code
= standard_sun_fpa_constant_p (operands
[1]);
2320 static char buf
[40];
2322 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2325 return "fpmove%.d %1,%0";
2330 int code
= standard_68881_constant_p (operands
[1]);
2334 static char buf
[40];
2336 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2339 return "fmove%.d %1,%0";
2344 output_move_const_single (operands
)
2347 #ifdef SUPPORT_SUN_FPA
2350 int code
= standard_sun_fpa_constant_p (operands
[1]);
2354 static char buf
[40];
2356 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2359 return "fpmove%.s %1,%0";
2362 #endif /* defined SUPPORT_SUN_FPA */
2364 int code
= standard_68881_constant_p (operands
[1]);
2368 static char buf
[40];
2370 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2373 return "fmove%.s %f1,%0";
2377 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2378 from the "fmovecr" instruction.
2379 The value, anded with 0xff, gives the code to use in fmovecr
2380 to get the desired constant. */
2382 /* This code has been fixed for cross-compilation. */
2384 static int inited_68881_table
= 0;
2386 char *strings_68881
[7] = {
2396 int codes_68881
[7] = {
2406 REAL_VALUE_TYPE values_68881
[7];
2408 /* Set up values_68881 array by converting the decimal values
2409 strings_68881 to binary. */
2416 enum machine_mode mode
;
2419 for (i
= 0; i
< 7; i
++)
2423 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2424 values_68881
[i
] = r
;
2426 inited_68881_table
= 1;
2430 standard_68881_constant_p (x
)
2436 #ifdef NO_ASM_FMOVECR
2440 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2441 used at all on those chips. */
2442 if (TARGET_68040
|| TARGET_68060
)
2445 #ifndef REAL_ARITHMETIC
2446 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2447 if (! flag_pretend_float
)
2452 if (! inited_68881_table
)
2453 init_68881_table ();
2455 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2457 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2459 for (i
= 0; i
< 6; i
++)
2461 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
2462 return (codes_68881
[i
]);
2465 if (GET_MODE (x
) == SFmode
)
2468 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2469 return (codes_68881
[6]);
2471 /* larger powers of ten in the constants ram are not used
2472 because they are not equal to a `double' C constant. */
2476 /* If X is a floating-point constant, return the logarithm of X base 2,
2477 or 0 if X is not a power of 2. */
2480 floating_exact_log2 (x
)
2483 REAL_VALUE_TYPE r
, r1
;
2486 #ifndef REAL_ARITHMETIC
2487 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2488 if (! flag_pretend_float
)
2493 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2495 if (REAL_VALUES_LESS (r
, dconst0
))
2500 while (REAL_VALUES_LESS (r1
, r
))
2502 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2503 if (REAL_VALUES_EQUAL (r1
, r
))
2510 #ifdef SUPPORT_SUN_FPA
2511 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2512 from the Sun FPA's constant RAM.
2513 The value returned, anded with 0x1ff, gives the code to use in fpmove
2514 to get the desired constant. */
2516 static int inited_FPA_table
= 0;
2518 char *strings_FPA
[38] = {
2519 /* small rationals */
2532 /* Decimal equivalents of double precision values */
2533 "2.718281828459045091", /* D_E */
2534 "6.283185307179586477", /* 2 pi */
2535 "3.141592653589793116", /* D_PI */
2536 "1.570796326794896619", /* pi/2 */
2537 "1.414213562373095145", /* D_SQRT2 */
2538 "0.7071067811865475244", /* 1/sqrt(2) */
2539 "-1.570796326794896619", /* -pi/2 */
2540 "1.442695040888963387", /* D_LOG2ofE */
2541 "3.321928024887362182", /* D_LOG2of10 */
2542 "0.6931471805599452862", /* D_LOGEof2 */
2543 "2.302585092994045901", /* D_LOGEof10 */
2544 "0.3010299956639811980", /* D_LOG10of2 */
2545 "0.4342944819032518167", /* D_LOG10ofE */
2546 /* Decimal equivalents of single precision values */
2547 "2.718281745910644531", /* S_E */
2548 "6.283185307179586477", /* 2 pi */
2549 "3.141592741012573242", /* S_PI */
2550 "1.570796326794896619", /* pi/2 */
2551 "1.414213538169860840", /* S_SQRT2 */
2552 "0.7071067811865475244", /* 1/sqrt(2) */
2553 "-1.570796326794896619", /* -pi/2 */
2554 "1.442695021629333496", /* S_LOG2ofE */
2555 "3.321928024291992188", /* S_LOG2of10 */
2556 "0.6931471824645996094", /* S_LOGEof2 */
2557 "2.302585124969482442", /* S_LOGEof10 */
2558 "0.3010300099849700928", /* S_LOG10of2 */
2559 "0.4342944920063018799", /* S_LOG10ofE */
2563 int codes_FPA
[38] = {
2564 /* small rationals */
2577 /* double precision */
2591 /* single precision */
2607 REAL_VALUE_TYPE values_FPA
[38];
2609 /* This code has been fixed for cross-compilation. */
2614 enum machine_mode mode
;
2619 for (i
= 0; i
< 38; i
++)
2623 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2626 inited_FPA_table
= 1;
2631 standard_sun_fpa_constant_p (x
)
2637 #ifndef REAL_ARITHMETIC
2638 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2639 if (! flag_pretend_float
)
2644 if (! inited_FPA_table
)
2647 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2649 for (i
=0; i
<12; i
++)
2651 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2652 return (codes_FPA
[i
]);
2655 if (GET_MODE (x
) == SFmode
)
2657 for (i
=25; i
<38; i
++)
2659 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2660 return (codes_FPA
[i
]);
2665 for (i
=12; i
<25; i
++)
2667 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2668 return (codes_FPA
[i
]);
2673 #endif /* define SUPPORT_SUN_FPA */
2675 /* A C compound statement to output to stdio stream STREAM the
2676 assembler syntax for an instruction operand X. X is an RTL
2679 CODE is a value that can be used to specify one of several ways
2680 of printing the operand. It is used when identical operands
2681 must be printed differently depending on the context. CODE
2682 comes from the `%' specification that was used to request
2683 printing of the operand. If the specification was just `%DIGIT'
2684 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2685 is the ASCII code for LTR.
2687 If X is a register, this macro should print the register's name.
2688 The names can be found in an array `reg_names' whose type is
2689 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2691 When the machine description has a specification `%PUNCT' (a `%'
2692 followed by a punctuation character), this macro is called with
2693 a null pointer for X and the punctuation character for CODE.
2695 The m68k specific codes are:
2697 '.' for dot needed in Motorola-style opcode names.
2698 '-' for an operand pushing on the stack:
2699 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2700 '+' for an operand pushing on the stack:
2701 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2702 '@' for a reference to the top word on the stack:
2703 sp@, (sp) or (%sp) depending on the style of syntax.
2704 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2705 but & in SGS syntax, $ in CRDS/UNOS syntax).
2706 '!' for the cc register (used in an `and to cc' insn).
2707 '$' for the letter `s' in an op code, but only on the 68040.
2708 '&' for the letter `d' in an op code, but only on the 68040.
2709 '/' for register prefix needed by longlong.h.
2711 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2712 'd' to force memory addressing to be absolute, not relative.
2713 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2714 'o' for operands to go directly to output_operand_address (bypassing
2715 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2716 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2717 than directly). Second part of 'y' below.
2718 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2719 or print pair of registers as rx:ry.
2720 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2721 CONST_DOUBLE's as SunFPA constant RAM registers if
2722 possible, so it should not be used except for the SunFPA.
2727 print_operand (file
, op
, letter
)
2728 FILE *file
; /* file to write to */
2729 rtx op
; /* operand to print */
2730 int letter
; /* %<letter> or 0 */
2732 #ifdef SUPPORT_SUN_FPA
2738 #if defined (MOTOROLA) && !defined (CRDS)
2739 asm_fprintf (file
, ".");
2742 else if (letter
== '#')
2744 asm_fprintf (file
, "%0I");
2746 else if (letter
== '-')
2749 asm_fprintf (file
, "-(%Rsp)");
2751 asm_fprintf (file
, "%Rsp@-");
2754 else if (letter
== '+')
2757 asm_fprintf (file
, "(%Rsp)+");
2759 asm_fprintf (file
, "%Rsp@+");
2762 else if (letter
== '@')
2765 asm_fprintf (file
, "(%Rsp)");
2767 asm_fprintf (file
, "%Rsp@");
2770 else if (letter
== '!')
2772 asm_fprintf (file
, "%Rfpcr");
2774 else if (letter
== '$')
2776 if (TARGET_68040_ONLY
)
2778 fprintf (file
, "s");
2781 else if (letter
== '&')
2783 if (TARGET_68040_ONLY
)
2785 fprintf (file
, "d");
2788 else if (letter
== '/')
2790 asm_fprintf (file
, "%R");
2792 else if (letter
== 'o')
2794 /* This is only for direct addresses with TARGET_PCREL */
2795 if (GET_CODE (op
) != MEM
|| GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
2798 output_addr_const (file
, XEXP (op
, 0));
2800 else if (GET_CODE (op
) == REG
)
2802 #ifdef SUPPORT_SUN_FPA
2804 && (letter
== 'y' || letter
== 'x')
2805 && GET_MODE (op
) == DFmode
)
2807 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2808 reg_names
[REGNO (op
)+1]);
2814 /* Print out the second register name of a register pair.
2815 I.e., R (6) => 7. */
2816 fputs (reg_names
[REGNO (op
) + 1], file
);
2818 fputs (reg_names
[REGNO (op
)], file
);
2821 else if (GET_CODE (op
) == MEM
)
2823 output_address (XEXP (op
, 0));
2824 if (letter
== 'd' && ! TARGET_68020
2825 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2826 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2827 && INTVAL (XEXP (op
, 0)) < 0x8000
2828 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2831 fprintf (file
, ".l");
2833 fprintf (file
, ":l");
2837 #ifdef SUPPORT_SUN_FPA
2838 else if ((letter
== 'y' || letter
== 'w')
2839 && GET_CODE (op
) == CONST_DOUBLE
2840 && (i
= standard_sun_fpa_constant_p (op
)))
2842 fprintf (file
, "%%%d", i
& 0x1ff);
2845 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2848 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2849 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2851 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2854 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2855 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2857 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2860 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2861 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2865 /* Use `print_operand_address' instead of `output_addr_const'
2866 to ensure that we print relevant PIC stuff. */
2867 asm_fprintf (file
, "%0I");
2869 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
2870 print_operand_address (file
, op
);
2872 output_addr_const (file
, op
);
2877 /* A C compound statement to output to stdio stream STREAM the
2878 assembler syntax for an instruction operand that is a memory
2879 reference whose address is ADDR. ADDR is an RTL expression.
2881 Note that this contains a kludge that knows that the only reason
2882 we have an address (plus (label_ref...) (reg...)) when not generating
2883 PIC code is in the insn before a tablejump, and we know that m68k.md
2884 generates a label LInnn: on such an insn.
2886 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2887 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2889 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2890 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2891 we want. This difference can be accommodated by using an assembler
2892 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2893 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2894 macro. See m68k/sgs.h for an example; for versions without the bug.
2895 Some assemblers refuse all the above solutions. The workaround is to
2896 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2899 They also do not like things like "pea 1.w", so we simple leave off
2900 the .w on small constants.
2902 This routine is responsible for distinguishing between -fpic and -fPIC
2903 style relocations in an address. When generating -fpic code the
2904 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2905 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2907 #ifndef ASM_OUTPUT_CASE_FETCH
2910 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2911 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2913 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2914 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2917 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2918 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2920 #endif /* ASM_OUTPUT_CASE_FETCH */
2923 print_operand_address (file
, addr
)
2927 register rtx reg1
, reg2
, breg
, ireg
;
2930 switch (GET_CODE (addr
))
2934 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2936 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2941 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2943 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2948 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2950 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2954 reg1
= reg2
= ireg
= breg
= offset
= 0;
2955 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2957 offset
= XEXP (addr
, 0);
2958 addr
= XEXP (addr
, 1);
2960 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2962 offset
= XEXP (addr
, 1);
2963 addr
= XEXP (addr
, 0);
2965 if (GET_CODE (addr
) != PLUS
)
2969 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2971 reg1
= XEXP (addr
, 0);
2972 addr
= XEXP (addr
, 1);
2974 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2976 reg1
= XEXP (addr
, 1);
2977 addr
= XEXP (addr
, 0);
2979 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2981 reg1
= XEXP (addr
, 0);
2982 addr
= XEXP (addr
, 1);
2984 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2986 reg1
= XEXP (addr
, 1);
2987 addr
= XEXP (addr
, 0);
2989 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2991 reg1
= XEXP (addr
, 0);
2992 addr
= XEXP (addr
, 1);
2994 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2996 reg1
= XEXP (addr
, 1);
2997 addr
= XEXP (addr
, 0);
2999 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
3000 || GET_CODE (addr
) == SIGN_EXTEND
)
3012 #if 0 /* for OLD_INDEXING */
3013 else if (GET_CODE (addr
) == PLUS
)
3015 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3017 reg2
= XEXP (addr
, 0);
3018 addr
= XEXP (addr
, 1);
3020 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
3022 reg2
= XEXP (addr
, 1);
3023 addr
= XEXP (addr
, 0);
3035 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
3036 || GET_CODE (reg1
) == MULT
))
3037 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
3042 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
3047 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
3048 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3051 if (GET_CODE (ireg
) == MULT
)
3053 scale
= INTVAL (XEXP (ireg
, 1));
3054 ireg
= XEXP (ireg
, 0);
3056 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3058 ASM_OUTPUT_CASE_FETCH (file
,
3059 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3060 reg_names
[REGNO (XEXP (ireg
, 0))]);
3061 fprintf (file
, "w");
3065 ASM_OUTPUT_CASE_FETCH (file
,
3066 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3067 reg_names
[REGNO (ireg
)]);
3068 fprintf (file
, "l");
3073 fprintf (file
, "*%d", scale
);
3075 fprintf (file
, ":%d", scale
);
3081 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3082 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3084 ASM_OUTPUT_CASE_FETCH (file
,
3085 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3086 reg_names
[REGNO (breg
)]);
3087 fprintf (file
, "l)");
3090 if (ireg
!= 0 || breg
!= 0)
3097 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3104 output_addr_const (file
, addr
);
3105 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3107 fprintf (file
, "@GOT");
3109 fprintf (file
, ".w");
3112 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3118 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3121 output_addr_const (file
, addr
);
3122 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3123 fprintf (file
, ":w");
3124 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3125 fprintf (file
, ":l");
3127 if (addr
!= 0 && ireg
!= 0)
3132 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3134 scale
= INTVAL (XEXP (ireg
, 1));
3135 ireg
= XEXP (ireg
, 0);
3137 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3140 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3142 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3148 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3150 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3156 fprintf (file
, "*%d", scale
);
3158 fprintf (file
, ":%d", scale
);
3164 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3165 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3167 ASM_OUTPUT_CASE_FETCH (file
,
3168 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3169 reg_names
[REGNO (reg1
)]);
3170 fprintf (file
, "l)");
3173 /* FALL-THROUGH (is this really what we want?) */
3175 if (GET_CODE (addr
) == CONST_INT
3176 && INTVAL (addr
) < 0x8000
3177 && INTVAL (addr
) >= -0x8000)
3181 /* Many SGS assemblers croak on size specifiers for constants. */
3182 fprintf (file
, "%d", INTVAL (addr
));
3184 fprintf (file
, "%d.w", INTVAL (addr
));
3187 fprintf (file
, "%d:w", INTVAL (addr
));
3190 else if (GET_CODE (addr
) == CONST_INT
)
3193 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
3200 else if (TARGET_PCREL
)
3203 output_addr_const (file
, addr
);
3205 asm_fprintf (file
, ":w,%Rpc)");
3207 asm_fprintf (file
, ":l,%Rpc)");
3211 /* Special case for SYMBOL_REF if the symbol name ends in
3212 `.<letter>', this can be mistaken as a size suffix. Put
3213 the name in parentheses. */
3214 if (GET_CODE (addr
) == SYMBOL_REF
3215 && strlen (XSTR (addr
, 0)) > 2
3216 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
3219 output_addr_const (file
, addr
);
3223 output_addr_const (file
, addr
);
3229 /* Check for cases where a clr insns can be omitted from code using
3230 strict_low_part sets. For example, the second clrl here is not needed:
3231 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3233 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3234 insn we are checking for redundancy. TARGET is the register set by the
3238 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3239 enum machine_mode mode
;
3245 p
= prev_nonnote_insn (first_insn
);
3249 /* If it isn't an insn, then give up. */
3250 if (GET_CODE (p
) != INSN
)
3253 if (reg_set_p (target
, p
))
3255 rtx set
= single_set (p
);
3258 /* If it isn't an easy to recognize insn, then give up. */
3262 dest
= SET_DEST (set
);
3264 /* If this sets the entire target register to zero, then our
3265 first_insn is redundant. */
3266 if (rtx_equal_p (dest
, target
)
3267 && SET_SRC (set
) == const0_rtx
)
3269 else if (GET_CODE (dest
) == STRICT_LOW_PART
3270 && GET_CODE (XEXP (dest
, 0)) == REG
3271 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3272 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3273 <= GET_MODE_SIZE (mode
)))
3274 /* This is a strict low part set which modifies less than
3275 we are using, so it is safe. */
3281 p
= prev_nonnote_insn (p
);
3288 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3289 range carefully since this predicate is used in DImode contexts. Also, we
3290 need some extra crud to make it work when hosted on 64-bit machines. */
3293 const_uint32_operand (op
, mode
)
3295 enum machine_mode mode ATTRIBUTE_UNUSED
;
3297 #if HOST_BITS_PER_WIDE_INT > 32
3298 /* All allowed constants will fit a CONST_INT. */
3299 return (GET_CODE (op
) == CONST_INT
3300 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3302 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3303 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3307 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3308 to check the range carefully since this predicate is used in DImode
3312 const_sint32_operand (op
, mode
)
3314 enum machine_mode mode ATTRIBUTE_UNUSED
;
3316 /* All allowed constants will fit a CONST_INT. */
3317 return (GET_CODE (op
) == CONST_INT
3318 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3321 /* Operand predicates for implementing asymmetric pc-relative addressing
3322 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3323 when used as a source operand, but not as a destintation operand.
3325 We model this by restricting the meaning of the basic predicates
3326 (general_operand, memory_operand, etc) to forbid the use of this
3327 addressing mode, and then define the following predicates that permit
3328 this addressing mode. These predicates can then be used for the
3329 source operands of the appropriate instructions.
3331 n.b. While it is theoretically possible to change all machine patterns
3332 to use this addressing more where permitted by the architecture,
3333 it has only been implemented for "common" cases: SImode, HImode, and
3334 QImode operands, and only for the principle operations that would
3335 require this addressing mode: data movement and simple integer operations.
3337 In parallel with these new predicates, two new constraint letters
3338 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3339 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3340 In the pcrel case 's' is only valid in combination with 'a' registers.
3341 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3342 of how these constraints are used.
3344 The use of these predicates is strictly optional, though patterns that
3345 don't will cause an extra reload register to be allocated where one
3348 lea (abc:w,%pc),%a0 ; need to reload address
3349 moveq &1,%d1 ; since write to pc-relative space
3350 movel %d1,%a0@ ; is not allowed
3352 lea (abc:w,%pc),%a1 ; no need to reload address here
3353 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3355 For more info, consult tiemann@cygnus.com.
3358 All of the ugliness with predicates and constraints is due to the
3359 simple fact that the m68k does not allow a pc-relative addressing
3360 mode as a destination. gcc does not distinguish between source and
3361 destination addresses. Hence, if we claim that pc-relative address
3362 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3363 end up with invalid code. To get around this problem, we left
3364 pc-relative modes as invalid addresses, and then added special
3365 predicates and constraints to accept them.
3367 A cleaner way to handle this is to modify gcc to distinguish
3368 between source and destination addresses. We can then say that
3369 pc-relative is a valid source address but not a valid destination
3370 address, and hopefully avoid a lot of the predicate and constraint
3371 hackery. Unfortunately, this would be a pretty big change. It would
3372 be a useful change for a number of ports, but there aren't any current
3373 plans to undertake this.
3375 ***************************************************************************/
3378 /* Special case of a general operand that's used as a source operand.
3379 Use this to permit reads from PC-relative memory when -mpcrel
3383 general_src_operand (op
, mode
)
3385 enum machine_mode mode
;
3388 && GET_CODE (op
) == MEM
3389 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3390 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3391 || GET_CODE (XEXP (op
, 0)) == CONST
))
3393 return general_operand (op
, mode
);
3396 /* Special case of a nonimmediate operand that's used as a source.
3397 Use this to permit reads from PC-relative memory when -mpcrel
3401 nonimmediate_src_operand (op
, mode
)
3403 enum machine_mode mode
;
3405 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3406 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3407 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3408 || GET_CODE (XEXP (op
, 0)) == CONST
))
3410 return nonimmediate_operand (op
, mode
);
3413 /* Special case of a memory operand that's used as a source.
3414 Use this to permit reads from PC-relative memory when -mpcrel
3418 memory_src_operand (op
, mode
)
3420 enum machine_mode mode
;
3422 if (TARGET_PCREL
&& GET_CODE (op
) == MEM
3423 && (GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
3424 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
3425 || GET_CODE (XEXP (op
, 0)) == CONST
))
3427 return memory_operand (op
, mode
);
3430 /* Predicate that accepts only a pc-relative address. This is needed
3431 because pc-relative addresses don't satisfy the predicate
3432 "general_src_operand". */
3435 pcrel_address (op
, mode
)
3437 enum machine_mode mode
;
3439 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
3440 || GET_CODE (op
) == CONST
);
3444 output_andsi3 (operands
)
3448 if (GET_CODE (operands
[2]) == CONST_INT
3449 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3450 && (DATA_REG_P (operands
[0])
3451 || offsettable_memref_p (operands
[0]))
3454 if (GET_CODE (operands
[0]) != REG
)
3455 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3456 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
3457 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3459 if (operands
[2] == const0_rtx
)
3461 return "and%.w %2,%0";
3463 if (GET_CODE (operands
[2]) == CONST_INT
3464 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3465 && (DATA_REG_P (operands
[0])
3466 || offsettable_memref_p (operands
[0])))
3468 if (DATA_REG_P (operands
[0]))
3470 operands
[1] = GEN_INT (logval
);
3474 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3475 operands
[1] = GEN_INT (logval
% 8);
3477 /* This does not set condition codes in a standard way. */
3479 return "bclr %1,%0";
3481 return "and%.l %2,%0";
3485 output_iorsi3 (operands
)
3488 register int logval
;
3489 if (GET_CODE (operands
[2]) == CONST_INT
3490 && INTVAL (operands
[2]) >> 16 == 0
3491 && (DATA_REG_P (operands
[0])
3492 || offsettable_memref_p (operands
[0]))
3495 if (GET_CODE (operands
[0]) != REG
)
3496 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3497 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3499 if (INTVAL (operands
[2]) == 0xffff)
3500 return "mov%.w %2,%0";
3501 return "or%.w %2,%0";
3503 if (GET_CODE (operands
[2]) == CONST_INT
3504 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3505 && (DATA_REG_P (operands
[0])
3506 || offsettable_memref_p (operands
[0])))
3508 if (DATA_REG_P (operands
[0]))
3510 operands
[1] = GEN_INT (logval
);
3514 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3515 operands
[1] = GEN_INT (logval
% 8);
3518 return "bset %1,%0";
3520 return "or%.l %2,%0";
3524 output_xorsi3 (operands
)
3527 register int logval
;
3528 if (GET_CODE (operands
[2]) == CONST_INT
3529 && INTVAL (operands
[2]) >> 16 == 0
3530 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3533 if (! DATA_REG_P (operands
[0]))
3534 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3535 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3537 if (INTVAL (operands
[2]) == 0xffff)
3539 return "eor%.w %2,%0";
3541 if (GET_CODE (operands
[2]) == CONST_INT
3542 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3543 && (DATA_REG_P (operands
[0])
3544 || offsettable_memref_p (operands
[0])))
3546 if (DATA_REG_P (operands
[0]))
3548 operands
[1] = GEN_INT (logval
);
3552 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3553 operands
[1] = GEN_INT (logval
% 8);
3556 return "bchg %1,%0";
3558 return "eor%.l %2,%0";